Display device

Abstract

There is provided a display device including: a substrate including a display area and a non-display area; the pixel driving circuit is located in the display area on the substrate; the insulating layer is located on the pixel driving circuit; a bank disposed in a plurality of sub-pixels including a first sub-pixel and a second sub-pixel on the insulating layer; a first electrode disposed on the bank and including a central region, an edge region, and a reflective region between the central region and the edge region; and a light emitting device electrically connected with the first electrode on the first electrode and overlapping the bank, in which a width of a reflective region of the first electrode in the first sub-pixel is different from a width of a reflective region of the first electrode in the second sub-pixel.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0118536, filed on September 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] Display devices are used in a variety of electronic devices such as TVs, mobile phones, laptops, and tablets.

[0005] Display devices include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0006] Recently, display devices including light-emitting diodes (LEDs) have attracted much attention as next-generation display devices. LEDs are made of inorganic materials rather than organic materials. Therefore, compared to liquid crystal displays or organic light-emitting displays, display devices including LEDs have faster light emission speeds, superior luminous efficiency, and can display images with high brightness.

[0007] In the case of display devices that include light-emitting devices, a process is required to transfer multiple light-emitting devices onto a substrate. However, during the transfer process, errors may occur due to various reasons, such as the light-emitting devices not being transferred to the correct position. Summary of the Invention

[0008] This disclosure was made in view of the above-mentioned problems, and one aspect of this disclosure is to provide a display device that can reduce errors that may occur during the transfer process of the light-emitting device.

[0009] According to one aspect of this disclosure, the above and other technical effects can be achieved by providing a display device comprising: a substrate including a display area and a non-display area; a pixel driving circuit located within the display area on the substrate; an insulating layer located on the pixel driving circuit; a dam disposed on the insulating layer among a plurality of sub-pixels including a first sub-pixel and a second sub-pixel; a first electrode disposed on the dam and including a central region, an edge region, and a reflective region between the central region and the edge region; and a light-emitting device disposed on and electrically connected to the first electrode, and overlapping the dam, wherein the width of the reflective region of the first electrode in the first sub-pixel is different from the width of the reflective region of the first electrode in the second sub-pixel.

[0010] Furthermore, according to one aspect of this disclosure, the above and other technical effects can be achieved by providing a display device comprising: a display area including a first display area, a second display area, and a third display area between the first and second display areas; a plurality of light-emitting devices disposed in a plurality of sub-pixels having a matrix structure within the display area; and a plurality of first electrodes electrically connected to the plurality of light-emitting devices in the plurality of sub-pixels and including a central region, an edge region, and a reflective region between the central and edge regions, wherein the widths of the reflective regions of the plurality of first electrodes in the plurality of sub-pixels within the third display area are different from each other.

[0011] Furthermore, according to one aspect of this disclosure, the above and other technical effects can be achieved by providing a display device comprising: a display area including a first display area, a second display area located to the right of the first display area, a third display area located between the first display area and the second display area, a fourth display area located to the left of the first display area, a fifth display area located below the fourth display area, and a sixth display area located between the fourth display area and the fifth display area; a plurality of light-emitting devices located in a plurality of sub-pixels having a matrix structure within the display area; and a plurality of first electrodes electrically connected to the plurality of light-emitting devices in the plurality of sub-pixels and including a central region, an edge region, and a reflective region between the central region and the edge region, wherein the width of the reflective region of the plurality of first electrodes in the plurality of sub-pixels in the third display area gradually increases or decreases with increasing column number of the matrix structure, and wherein the width of the reflective region of the plurality of first electrodes in the plurality of sub-pixels in the sixth display area gradually increases or decreases with increasing row number of the matrix structure.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0013] The accompanying drawings are included to provide a further understanding of this disclosure. The drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure. In the drawings:

[0014] Figure 1 This is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0015] Figure 2 This is a plan view of a display device according to an embodiment of the present disclosure.

[0016] Figure 3This is an enlarged view of a display device according to an embodiment of the present disclosure.

[0017] Figure 4 This is a view showing a circuit structure according to an embodiment of the present disclosure.

[0018] Figure 5 This is a plan view of a display device according to an embodiment of the present disclosure.

[0019] Figure 6 This is a plan view of a display device according to an embodiment of the present disclosure.

[0020] Figure 7 This is a plan view of a display device according to an embodiment of the present disclosure.

[0021] Figure 8 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0022] Figure 9 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0023] Figure 10A This is a plan view showing the transfer area of ​​a display device according to an embodiment of the present disclosure.

[0024] Figure 10B This is a plan view showing the transfer area of ​​a display device according to another embodiment of the present disclosure.

[0025] Figure 11A and Figure 11B These are cross-sectional and plan views of a subpixel according to an embodiment of the present disclosure.

[0026] Figure 12A and Figure 12B This is a cross-sectional view and a plan view of a subpixel according to another embodiment of the present disclosure.

[0027] Figure 13A and Figure 13B This is a cross-sectional view and a plan view of a subpixel according to another embodiment of the present disclosure.

[0028] Figure 14A and Figure 14B This is a cross-sectional view and a plan view of a subpixel according to another embodiment of the present disclosure.

[0029] Figure 15 An embodiment of the present disclosure is shown with configurations. Figure 10A Multiple sub-pixels within the X region (e.g., within the region near the first boundary line between the first and second transfer regions).

[0030] Figure 16A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the X region (e.g., in the region near the first boundary line between the first transfer region and the second transfer region).

[0031] Figure 17 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Y region (e.g., in the region near the second boundary line between the first and third transfer regions).

[0032] Figure 18 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Y region (e.g., in the region near the second boundary line between the first and third transfer regions).

[0033] Figure 19 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Z region (e.g., in the vicinity of the intersection of the first boundary line between the first and second transfer regions and the second boundary line between the first and third transfer regions).

[0034] Figure 20 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Z region (e.g., in the vicinity of the intersection of the first boundary line between the first and second transfer regions and the second boundary line between the first and third transfer regions).

[0035] Figures 21 to 24 This is a view of a device that uses a display apparatus according to an embodiment of the present disclosure.

[0036] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated, the same reference numerals should be understood to indicate the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and descriptions of these elements may be exaggerated. Detailed Implementation

[0037] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein, except that they must occur in a specific order, and can be varied as is known in the art. The names of the corresponding elements used in the following description may be chosen solely for convenience in writing the specification, and therefore may differ from the names used in actual products.

[0038] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be complete and fully convey its scope to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0039] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, similar reference numerals indicate similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the essence of this disclosure. Where terms such as “comprising,” “having,” and “including” are used in this disclosure, additional parts may be added unless “only…” is used. Singular terms may include plural forms unless the opposite is mentioned.

[0040] When interpreting components, they are interpreted as including the error range even if there is no separate explicit description of the error range.

[0041] When describing positional relationships, for example, when the positional relationship is described as "on," "above," "below," and "beside," one or more parts may be positioned between two other parts, unless "only" or "directly" is used. This document may use terms such as "below," "lower," "above," "upper," etc., to describe the relationships between the elements shown in the accompanying drawings. It should be understood that the terms are spatially relative and based on the orientation shown in the accompanying drawings.

[0042] The description of time relationships can include situations where time priority is described as "after", "following", or "before", and is not consecutive unless "immediately" or "directly" is used.

[0043] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical concept of this disclosure, the "first component" mentioned below can be the "second component."

[0044] It should be understood that although the terms “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0045] If a component is described as “connected,” “coupled,” “connected,” or “attached” to another component, then that component may be directly connected, coupled, connected, or attached to that other component. However, it should be understood that, without any specific description, other components may be inserted between components that may be indirectly connected, coupled, connected, or attached.

[0046] It should be understood that if a component or layer is described as "in contact" or "overlapping" with another component or layer, then that component or layer may be in direct contact or overlap with another component or layer, but other components may be interposed between various components that may be in indirect contact or overlap without a specific explicit description.

[0047] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0048] The terms “first direction,” “second direction,” “third direction,” “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted merely as geometrically perpendicular to each other, but can refer to the range of directions within which the configuration of this disclosure can function functionally, and the configuration of this disclosure has a wider range of directions.

[0049] Features of each embodiment in the various embodiments of this specification may be partially or completely coupled or combined with each other, may be technically interconnected and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0050] An embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0052] refer to Figure 1 According to one embodiment of the present disclosure, a display device 1000 may include a display panel 100, a polarizing layer 280, an adhesive layer 290, a cover member 120, a support substrate 190, a flexible circuit board 170, and a printed circuit board 160.

[0053] The display panel 100 can display information, videos, and / or images to the user.

[0054] A polarizing layer 280 can be disposed on the display panel 100. The polarizing layer 280 can prevent or reduce the light generated from external light sources from entering the display panel 100 and affecting the light-emitting elements, etc.

[0055] The adhesive layer 290 can attach the cover member 120 to the display panel 100. The adhesive layer 290 can be disposed between the polarizing layer 280 and the cover member 120 to attach the cover member 120 to the polarizing layer 280. The adhesive layer 290 may include optically clear adhesive (OCA), optically clear resin (OCR), pressure-sensitive adhesive (PSA), etc., but the embodiments disclosed herein are not limited thereto.

[0056] The cover member 120 may be disposed on the polarizing layer 280. The cover member 120 may be disposed on the adhesive layer 290. The cover member 120 may be a member for protecting the display panel 100. The cover member 120 may be formed of a transparent material.

[0057] A support substrate 190 may be disposed between the display panel 100 and the printed circuit board 160. The support substrate 190 may enhance the rigidity of the display panel 100. The support substrate 190 may be a back plate, but the embodiments disclosed herein are not limited thereto.

[0058] Flexible circuit board 170 and printed circuit board 160 may be disposed on the bottom of display panel 100. Flexible circuit board 170 and printed circuit board 160 may be disposed on at least one edge of display panel 100, but embodiments of the present disclosure are not limited thereto. One side of flexible circuit board 170 may be attached to display panel 100, and the other side of flexible circuit board 170 may be attached to printed circuit board 160, but embodiments of the present disclosure are not limited thereto. Flexible circuit board 170 may be a flexible film, but embodiments of the present disclosure are not limited thereto.

[0059] The printed circuit board 160 may include at least one hole 180, but embodiments of this disclosure are not limited thereto. An internal component for sensing ambient light or temperature, which can be provided to multiple sensors, may be disposed in the area corresponding to the at least one hole 180. For example, the internal component may include an ambient light sensor (ALS) or a temperature sensor, but embodiments of this disclosure are not limited thereto. For example, the hole 180 may be a through hole, etc., but embodiments of this disclosure are not limited thereto.

[0060] Figure 2 This is a plan view of a display device according to an embodiment of the present disclosure. Figure 3 This is an enlarged view of a display device according to an embodiment of the present disclosure.

[0061] refer to Figure 2 and Figure 3 The display device 1000 may include a display panel 100, a flexible circuit board 170, and a printed circuit board 160.

[0062] The display panel 100 may include a substrate 110. The substrate 110 may be a component supporting other components of the display device 1000. The substrate 110 may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. Furthermore, the substrate 110 may be made of a flexible material. For example, the substrate 110 may be made of a flexible plastic material such as polyimide (PI). However, the embodiments disclosed herein are not limited thereto.

[0063] For example, the display panel 100 may include a display area AA and a non-display area NA. For example, the substrate 110 may include a display area AA and a non-display area NA. The display area AA and the non-display area NA are not limited to the substrate 110, but can be described as being throughout the display device 1000.

[0064] The display area AA can be an area in which an image is displayed. The display area AA can include multiple pixels PX. Each of the multiple pixels PX can include multiple sub-pixels. Multiple light-emitting elements can be disposed in each of the multiple sub-pixels. The multiple light-emitting elements can be configured differently depending on the type of display device 1000. For example, when the display device 1000 is an inorganic light-emitting display device, the light-emitting elements can be light-emitting diodes (LEDs), micro-LEDs, or miniature light-emitting diodes (MLEDs), but the embodiments of this disclosure are not limited thereto.

[0065] The display area AA can be configured into various shapes according to the design of the display device 1000. For example, the display area AA can be configured as a rectangle with four rounded corners, but the configuration disclosed herein is not limited to this. As another example, the display area AA can be configured as a rectangle or a circle with four corners, but the configuration disclosed herein is not limited to this.

[0066] refer to Figure 3Multiple pixel driving circuits (PDs) can be disposed within the display area (AA). Each pixel driving circuit (PD) can be a circuit for driving light-emitting elements of multiple sub-pixels. Each of the multiple pixel driving circuits (PDs) can include multiple transistors comprising driving transistors and storage capacitors. Furthermore, each of the multiple pixel driving circuits (PDs) can control the light-emitting operation of the multiple light-emitting elements by providing control signals, power supplies, and driving currents to the light-emitting elements of the multiple sub-pixels. For example, the pixel driving circuit (PD) can include power lines and signal lines for controlling the light-emitting on / off and / or light-emitting time of the light-emitting elements. For example, the multiple pixel driving circuits (PDs) can be a driver manufactured on a semiconductor substrate using a metal-oxide-silicon (MOSFET) manufacturing process, but embodiments of this disclosure are not limited thereto. The driver includes multiple pixel driving circuits (PDs) and can drive multiple sub-pixels.

[0067] The non-display area NA can be an area in which no image is displayed. Various wirings, circuits, etc., for driving the multiple pixels PX of the display area AA can be arranged within the non-display area NA. For example, various wirings and driving circuits can be installed within the non-display area NA. Furthermore, pad portions PAD connected to integrated circuits, printed circuits, etc., can be provided within the non-display area NA, but embodiments of this disclosure are not limited thereto.

[0068] For example, the driving circuit may be a data driving circuit and / or a gate driving circuit, but embodiments of this disclosure are not limited thereto. Wiring for control signals supplied to control the driving circuit may be provided within the non-display area NA. For example, the control signals may include various timing signals including clock signals, input data enable signals, and synchronization signals, but embodiments of this disclosure are not limited thereto. The control signals may be received via pad portions PAD. For example, link lines LL for transmitting signals may be provided within the non-display area NA. For example, driving components such as flexible circuit board 170 and printed circuit board 160 may be connected to the pad portions PAD.

[0069] According to this disclosure, the non-display area NA may include a first non-display area NA1, a curved area BA, and a second non-display area NA2. For example, the first non-display area NA1 may be a region surrounding at least a portion of the display area AA. The curved area BA may be a region extending from at least one of the multiple sides of the first non-display area NA1, and may be a flexible region. The second non-display area NA2 is a region extending from the curved area BA, and may be provided with pad portions PAD. For example, the curved area BA may be curved, and the remaining area of ​​the substrate 110, excluding the curved area BA, may be flat. In this case, as the curved area BA bends, the second non-display area NA2 may be disposed on the back side of the display area AA. However, embodiments of this disclosure are not limited thereto.

[0070] Multiple link lines LL can be provided within the non-display area NA. These link lines LL can be wiring for transmitting various signals from one or more flexible circuit boards (or flexible films) 170 and printed circuit boards 160 to the display area AA. The link lines LL can extend from multiple pad electrodes PE of the second non-display area NA2 toward the curved area BA and the first non-display area NA1, and can be electrically connected to multiple drive lines VL of the display area AA. Multiple pixel drive circuits PD can be driven by receiving signals from one or more flexible circuit boards (or flexible films) 170 and printed circuit boards 160 via the drive lines VL located within the display area AA and the link lines LL located within the non-display area NA.

[0071] For example, multiple drive lines VL can be wiring for transmitting signals output from the flexible circuit board (or flexible film) 170 and the printed circuit board 160 to multiple pixel driving circuits PD having multiple link lines LL. The multiple drive lines VL can be disposed within the display area AA and electrically connected to each of the multiple pixel driving circuits PD. The multiple drive lines VL can extend from the display area AA towards the non-display area NA and can be electrically connected to the multiple link lines LL. Therefore, signals output from the flexible circuit board (or flexible film) 170 and the printed circuit board 160 can be transmitted to each of the multiple pixel driving circuits PD through the multiple link lines LL and the multiple drive lines VL.

[0072] As the bending region BA bends, a portion of the multiple link lines LL can also bend. Stress concentrates on the bent portion of the link lines LL, and therefore, cracks may appear in the link lines LL. Therefore, the multiple link lines LL can be formed of a conductive material with excellent ductility to reduce cracking when the bending region BA bends. For example, the multiple link lines LL can be formed of conductive materials with excellent ductility such as gold (Au), silver (Ag), aluminum (Al), etc., but embodiments of this disclosure are not limited thereto. Furthermore, the multiple link lines LL can be formed of one of various conductive materials used within the display region AA. For example, the multiple link lines LL can be formed of alloys of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), silver (Ag), and magnesium (Mg), etc., but embodiments of this disclosure are not limited thereto. The multiple link lines LL can be a multilayer structure comprising various conductive materials. For example, the multiple link lines LL can be a three-layer structure comprising titanium (Ti), aluminum (Al), and titanium (Ti), but embodiments of this disclosure are not limited thereto.

[0073] Multiple link lines LL can be configured in various shapes to reduce stress. At least a portion of the multiple link lines LL disposed on the curved region BA can extend in the same direction as the extension direction of the curved region BA, or can extend in a direction different from the extension direction of the curved region BA to reduce stress. For example, when the curved region BA extends from the first non-display region NA1 to the second non-display region NA2 in one direction, at least a portion of the link lines LL disposed on the curved region BA can extend in a direction inclined relative to that direction. As another example, at least a portion of the multiple link lines LL can include patterns of various shapes. For example, at least a portion of the multiple link lines LL disposed on the curved region BA can have a shape with a repeating arrangement of conductive patterns having at least one of diamond shape, rhombus shape, trapezoid shape, triangular wave shape, sawtooth wave shape, sine wave shape, circular shape, and omega (Ω) shape, but embodiments of the present disclosure are not limited thereto. Therefore, in order to minimize stress and corresponding cracks concentrated on the multiple link lines LL, the shape of the multiple link lines LL can be formed in various shapes including the above-described shapes, but embodiments of the present disclosure are not limited thereto.

[0074] According to this disclosure, the width of the second non-display area NA2, which is provided with multiple pad electrodes PE, can be wider than the width of the curved area BA, which is provided with only multiple link lines LL. Furthermore, the width of the display area AA, which is provided with multiple sub-pixels, can be wider than the width of the curved area BA, which is provided with only multiple link lines LL. Although the width of the curved area BA is shown as narrower than the width of other areas of the substrate 110, the shape of the substrate 110 including the curved area BA is exemplary, and embodiments of this disclosure are not limited thereto.

[0075] A pad portion PAD, comprising multiple pad electrodes PE, can be disposed within the second non-display area NA2. A driving assembly comprising one or more flexible circuit boards (or flexible films) 170 and printed circuit boards 160 can be attached to or bonded to the pad portion PAD. The multiple pad electrodes PE of the pad portion PAD are electrically connected to one or more flexible circuit boards (or flexible films) 170, and various signals (or power supplies) received from the printed circuit boards 160 and the flexible circuit boards (or flexible films) 170 can be transmitted to multiple pixel driving circuits PD of the display area AA.

[0076] The flexible circuit board (or flexible film) 170 can be a film on which various components are disposed on a flexible base film. For example, a driver IC, such as a gate driver IC or a data driver IC, can be disposed on the flexible circuit board (or flexible film), but embodiments of this disclosure are not limited thereto. The driver IC can be a component that processes data and drive signals for displaying images. Depending on the mounting method, the driver IC can be disposed by a chip-on-glass (COG) method, a chip-on-film (COF) method, or a tape-on-package (TCP) method, but embodiments of this disclosure are not limited thereto. The flexible circuit board (or flexible film) 170 can be attached to or bonded to multiple pad electrodes PE by a conductive adhesive layer, but embodiments of this disclosure are not limited thereto.

[0077] The printed circuit board 160 may be a component electrically connected to one or more flexible circuit boards (or flexible films) 170 and providing signals to the driver IC. The printed circuit board 160 may be disposed on one side of the flexible circuit board (or flexible film) 170 and may be electrically connected to the flexible circuit board (or flexible film). Various components for providing various signals to the driver IC may be disposed on the printed circuit board 160. For example, various components such as timing controllers, power supply units, memory, processors, etc., may be disposed on the printed circuit board 160. For example, the printed circuit board 160 may include a power management integrated circuit (PMIC), but the embodiments of this disclosure are not limited thereto.

[0078] Figure 4 This is a view showing a circuit structure according to an embodiment of the present disclosure.

[0079] Figure 4The diagram illustrates a single light-emitting diode (ED) connected to a micro-driver (μDriver), but is not limited to this. For example, eight EDs can be connected to a single μDriver. As another example, 16 EDs can be connected to a single μDriver, and 32 or 64 EDs can be simultaneously connected to a single μDriver. The EDs can be micro-LEDs (μLEDs).

[0080] A micro-driver (μDriver) may include a driving transistor T DR and light-emitting transistor T EM However, the embodiments disclosed herein are not limited thereto.

[0081] For example, a high-potential power supply voltage VDD can be applied to the driving transistor T. DR The first electrode, the light-emitting transistor T EM The first electrode can be connected to the driving transistor T DR The second electrode, the scan signal SC, can be applied to the driving transistor T. DR The gate of the driving transistor T is applied. DR The gate scan signal SC is a DC power supply, and a fixed reference voltage Vref can be applied to each frame, but the embodiments disclosed herein are not limited thereto.

[0082] Drive transistor T DR The second electrode can be connected to the light-emitting transistor T. EM The first electrode, the light-emitting device ED, can be connected to the light-emitting transistor T. EM The second electrode allows the light-emitting signal EM to be applied to the light-emitting transistor T. EM The gate of the light-emitting transistor T. EM The light emission signal EM of the gate can be a pulse width modulation signal that changes every frame, but the embodiments disclosed herein are not limited thereto.

[0083] The first electrode of the light-emitting device ED can be connected to the light-emitting transistor T. EM The second electrode of the light-emitting device (ED) can be grounded. For example, the first electrode of the ED can be the anode, and the second electrode of the ED can be the cathode, but the embodiments of this disclosure are not limited thereto.

[0084] Drive transistor T DR and light-emitting transistor T EM Each of them can be an n-type transistor or a p-type transistor.

[0085] Drive transistor T DRThe light-emitting transistor T can be turned on by the scan signal SC applied from the timing controller T-CON in the micro-driver (μDriver). EM It can be turned on by emitting a light signal EM. Therefore, by applying a signal to the driving transistor T... DR The high potential power supply voltage VDD of the first electrode drives the current through the driving transistor T. DR and light-emitting transistor T EM An energy is applied to the light-emitting device (ED), so the ED can emit light.

[0086] Figures 5 to 7 This is a plan view of a display device according to an embodiment of the present disclosure. For example, Figure 5 It is a magnified planar view of a display area that includes multiple pixels. For example, Figure 6 It is a magnified planar view of a display area including one pixel. For example, Figure 7 It is a magnified planar view of a display area that includes multiple pixels. Although Figure 5 and Figure 7 Multiple signal lines TL, multiple communication lines NL, multiple first electrodes CE1, multiple embankments BNK, and multiple light-emitting devices ED are shown, but the embodiments of this disclosure are not limited thereto. Figure 7 Multiple second electrodes CE2 are additionally set Figure 5 In the enlarged planar view, for convenience, the area overlapping with the second electrode CE2 is represented by a dashed line.

[0087] refer to Figures 5 to 7 Within the display area AA, multiple pixels PX, including multiple sub-pixels, can be provided. Each of the multiple sub-pixels includes a light-emitting device ED and can emit light independently. The multiple sub-pixels can be configured in multiple rows and columns, and can be arranged in a matrix, but the embodiments of this disclosure are not limited thereto.

[0088] The plurality of sub-pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel, another may be a green sub-pixel, and the remaining one may be a blue sub-pixel. The type of the plurality of sub-pixels is an example, and the embodiments of this disclosure are not limited thereto.

[0089] Each of a plurality of pixels PX may include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, a pixel PX may include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3. A pair of first sub-pixels SP1 may include first-1 sub-pixels SP1a and first-2 sub-pixels SP1b. A pair of second sub-pixels SP2 may include second-1 sub-pixels SP2a and second-2 sub-pixels SP2b. A pair of third sub-pixels SP3 may include third-1 sub-pixels SP3a and third-2 sub-pixels SP3b. For example, a pixel PX may include first-1 sub-pixels SP1a, first-2 sub-pixels SP1b, second-1 sub-pixels SP2a, second-2 sub-pixels SP2b, third-1 sub-pixels SP3a, and third-2 sub-pixels SP3b, but the embodiments of this disclosure are not limited thereto.

[0090] The multiple subpixels constituting a pixel PX can be arranged differently. For example, in a pixel PX, a pair of first subpixels SP1 can be arranged in the same column, a pair of second subpixels SP2 can be arranged in the same column, and a pair of third subpixels SP3 can be arranged in the same column. The first subpixels SP1, second subpixels SP2, and third subpixels SP3 can be arranged in the same row. The number and arrangement of the multiple subpixels constituting a pixel PX are examples, and the embodiments of this disclosure are not limited thereto.

[0091] Multiple signal lines TL can be set within a region between multiple sub-pixels. Multiple signal lines TL can extend in the column direction between multiple sub-pixels. Multiple signal lines TL can be derived from the pixel driving circuit PD (in... Figure 3 The anode voltage (as shown in the diagram) is transmitted to multiple sub-pixels via lines. For example, multiple signal lines TL can be electrically connected to multiple pixel drive circuits PD (in...). Figure 3 (shown in the image) and the first electrode CE1 of multiple sub-pixels. From the pixel driving circuit PD (in... Figure 3 (As shown in the diagram) The output anode voltage can be transmitted to the first electrode CE1 of multiple sub-pixels via multiple signal lines TL. For example, the first electrode CE1 can be the anode 134 electrically connected to the light-emitting device ED (in...). Figure 9 The electrode is shown in the figure. Therefore, the anode voltage from the signal line TL can be transmitted through the first electrode CE1 to the anode 134 of the light-emitting device ED (in the figure). Figure 9 (as shown in the image).

[0092] Therefore, instead of forming multiple transistors and storage capacitors in each of the multiple sub-pixels, it is possible to integrate multiple pixel circuits into a single pixel drive circuit (PD). Figure 3 The pixel driving circuit PD (shown in) is shown in the figure. Figure 3 (as shown in the diagram) to simplify the structure of the display device 1000. Furthermore, since the circuitry provided in each of the multiple sub-pixels is integrated into a single pixel drive circuit PD (as shown in the diagram), the structure of the display device 1000 is simplified. Figure 3 As shown in the figure, this allows for high-efficiency and low-power driving.

[0093] Multiple signal lines TL may include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. The first signal line TL1 and the second signal line TL2 can be electrically connected to corresponding sub-pixels in a pair of first sub-pixels SP1. The third signal line TL3 and the fourth signal line TL4 can be electrically connected to corresponding sub-pixels in a pair of second sub-pixels SP2. The fifth signal line TL5 and the sixth signal line TL6 can be electrically connected to corresponding sub-pixels in a pair of third sub-pixels SP3.

[0094] A first signal line TL1 can be disposed on one side of a pair of first sub-pixels SP1, and a second signal line TL2 can be disposed on the other side of the pair of first sub-pixels SP1. The first signal line TL1 can be electrically connected to one of the pair of first sub-pixels SP1, for example, the first electrode CE1 of the first sub-pixel SP1a. The second signal line TL2 can be electrically connected to the remaining first sub-pixels SP1 in the pair of first sub-pixels SP1, for example, the first electrode CE1 of the first sub-pixel SP1b.

[0095] The third signal line TL3 can be positioned on one side of a pair of second sub-pixels SP2, and the fourth signal line TL4 can be positioned on the other side of the pair of second sub-pixels SP2. For example, the third signal line TL3 can be positioned adjacent to the second signal line TL2. The third signal line TL3 can be electrically connected to one of the pair of second sub-pixels SP2, for example, the first electrode CE1 of the second-1st sub-pixel SP2a. The fourth signal line TL4 can be electrically connected to the remaining second sub-pixels SP2 in the pair of second sub-pixels SP2, for example, the first electrode CE1 of the second-2nd sub-pixel SP2b.

[0096] The fifth signal line TL5 can be positioned on one side of a pair of third sub-pixels SP3, and the sixth signal line TL6 can be positioned on the other side of the pair of third sub-pixels SP3. For example, the fifth signal line TL5 can be positioned adjacent to the fourth signal line TL4. The sixth signal line TL6 can be positioned adjacent to the first signal line TL1 connected to the adjacent pixel PX. The fifth signal line TL5 can be electrically connected to one of the pair of third sub-pixels SP3, for example, the first electrode CE1 of the 3-1st sub-pixel SP3a. The sixth signal line TL6 can be electrically connected to the remaining third sub-pixels SP3 in the pair of third sub-pixels SP3, for example, the first electrode CE1 of the 3-2nd sub-pixel SP3b.

[0097] Multiple signal lines TL can be formed of conductive materials. For example, multiple signal lines TL can be formed of conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto. As another example, multiple signal lines TL can be formed of a multilayer structure of conductive materials. For example, multiple signal lines TL can be formed of a multilayer structure stacked with titanium (Ti), aluminum (Al), titanium (Ti), and indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0098] Multiple communication lines NL can be disposed within a region between multiple pixels PX. Multiple communication lines NL can be configured to extend along a row direction within the region between multiple pixels PX. Multiple communication lines NL can be disposed within a region between multiple second electrodes CE2, and may not overlap with the multiple second electrodes CE2. For example, multiple communication lines NL can be wiring for short-range communication such as near-field communication (NFC). Multiple communication lines NL can be used as antennas. For example, multiple communication lines NL can be multiple connecting lines, etc., but embodiments of this disclosure are not limited thereto.

[0099] According to this disclosure, a dam section (BNK) can be disposed in each of a plurality of sub-pixels. The plurality of dam sections (BNK) can be a structure provided with a plurality of light-emitting devices (EDs). The plurality of dam sections (BNK) can guide the position of the plurality of light-emitting devices (EDs) during a transfer process. The plurality of light-emitting devices (EDs) can be transferred onto the plurality of dam sections (BNK) during the transfer process. The plurality of dam sections (BNK) can be a dam pattern or structure, but embodiments of this disclosure are not limited thereto.

[0100] The dam portions BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be set to be spaced apart from each other. Therefore, it is easy to identify which types of light-emitting devices (EDs) are transferred to the dam portions BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0101] The dam portion BNK of sub-pixel SP1a and the dam portion BNK of sub-pixel SP1b can be connected to each other or spaced apart. For example, considering design requirements such as those of a transfer process, the dam portion BNK of sub-pixel SP1a and the dam portion BNK of sub-pixel SP1b, which are provided with the same light-emitting device ED, can be connected, separated, or spaced apart. The dam portion BNK of sub-pixel SP2a and the dam portion BNK of sub-pixel SP2b can be connected to each other or spaced apart. The dam portion BNK of sub-pixel SP3a and the dam portion BNK of sub-pixel SP3b can be connected to each other or spaced apart. Therefore, the dam portion BNK of a pair of first sub-pixels SP1, the dam portion BNK of a pair of second sub-pixels SP2, and the dam portion BNK of a pair of third sub-pixels SP3 can be formed differently, and the embodiments of this disclosure are not limited thereto.

[0102] For example, multiple dammed BNKs can be formed of organic insulating materials. Multiple dammed BNKs can be formed of single-layer or multi-layer organic insulating materials. For example, multiple dammed BNKs can be formed of photoresist, polyimide (PI), acrylic-based materials, etc., but the embodiments of this disclosure are not limited thereto.

[0103] A first electrode CE1 may be disposed in each of a plurality of sub-pixels. The first electrode CE1 may be disposed on a dam BNK. The first electrode CE1 may be electrically connected to one of a plurality of signal lines TL. At least a portion of the first electrode CE1 may extend to the outside of the dam BNK to be electrically connected to the signal line TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of sub-pixel SP1a may extend to one side of sub-pixel SP1a to be electrically connected to the first signal line TL1, and a portion of the first electrode CE1 of sub-pixel SP1b may extend to the other side of sub-pixel SP1b to be electrically connected to the second signal line TL2. A portion of the first electrode CE1 of sub-pixel SP2a may extend to one side of sub-pixel SP2a to be electrically connected to the third signal line TL3, and a portion of the first electrode CE1 of sub-pixel SP2b may extend to the other side of sub-pixel SP2b to be electrically connected to the fourth signal line TL4. A portion of the first electrode CE1 of the 3-1 sub-pixel SP3a can extend to one side of the 3-1 sub-pixel SP3a to be electrically connected to the fifth signal line TL5, and a portion of the first electrode CE1 of the 3-2 sub-pixel SP3b can extend to the other side of the 3-2 sub-pixel SP3b to be electrically connected to the sixth signal line TL6.

[0104] The first electrode CE1 is electrically connected to the anode 134 of the light-emitting device ED (shown in Figure 14). This connection originates from the pixel driving circuit PD (in... Figure 3 The anode voltage (shown in the diagram) can be transmitted to the light-emitting device ED via signal line TL and first electrode CE1. Different voltages can be applied to the first electrode CE1 of each of the plurality of sub-pixels depending on the image being displayed. For example, different voltages can be applied to the first electrode CE1 of each of the plurality of sub-pixels. Therefore, the first electrode CE1 can be a pixel electrode, and the embodiments of this disclosure are not limited thereto.

[0105] The first electrode CE1 can be formed of a conductive material. For example, the first electrode CE1 can be integrally formed with multiple signal lines TL. For example, the first electrode CE1 can be formed of the same conductive material as the multiple signal lines TL, but the embodiments of this disclosure are not limited thereto. For example, the first electrode CE1 can be formed of conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto. As another example, the first electrode CE1 can be formed of a multilayer structure of conductive material. For example, multiple first electrodes CE1 can be formed of a multilayer structure stacked with titanium (Ti), aluminum (Al), titanium (Ti), and indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0106] The light-emitting device ED can be disposed in each of the plurality of sub-pixels. The plurality of light-emitting devices ED can be any of light-emitting diodes (LEDs) and micro LEDs, but embodiments of this disclosure are not limited thereto. The plurality of light-emitting devices ED can be disposed on the embankment BNK and the first electrode CE1. The plurality of light-emitting devices ED can be disposed on the first electrode CE1 and can be electrically connected to the first electrode CE1. Therefore, the light-emitting device ED can emit light by receiving an anode voltage from the pixel driving circuit PD via the signal line TL and the first electrode CE1.

[0107] Multiple light-emitting devices (EDs) may include a first light-emitting device 130, a second light-emitting device 140, and a third light-emitting device 150. The first light-emitting device 130 may be disposed in a first sub-pixel SP1. The second light-emitting device 140 may be disposed in a second sub-pixel SP2. The third light-emitting device 150 may be disposed in a third sub-pixel SP3. For example, one of the first light-emitting device 130, the second light-emitting device 140, and the third light-emitting device 150 may be a red light-emitting device, another may be a green light-emitting device, and the remaining one may be a blue light-emitting device, but the embodiments of this disclosure are not limited thereto. Therefore, various colors of light, including white, can be achieved by combining red, green, and blue light emitted from multiple light-emitting devices (EDs). The types of multiple light-emitting devices (EDs) are examples, and the embodiments of this disclosure are not limited thereto.

[0108] The first light-emitting device 130 may include a first-1 light-emitting device 130a disposed in the first-1 sub-pixel SP1a and a first-2 light-emitting device 130b disposed in the first-2 sub-pixel SP1b. The second light-emitting device 140 may include a second-1 light-emitting device 140a disposed in the second-1 sub-pixel SP2a and a second-2 light-emitting device 140b disposed in the second-2 sub-pixel SP2b. The third light-emitting device 150 may include a third-1 light-emitting device 150a disposed in the third-1 sub-pixel SP3a and a third-2 light-emitting device 150b disposed in the third-2 sub-pixel SP3b.

[0109] The second electrode CE2 can be disposed in each of multiple sub-pixels. The second electrode CE2 can be disposed on the light-emitting device ED. The second electrode CE2 can be electrically connected to the pixel driving circuit PD (in) via multiple contact electrodes CCE. Figure 3 (as shown in the image).

[0110] For example, the second electrode CE2 can be electrically connected to the cathode 135 of the light-emitting device ED (shown in Figure 14) to transmit light from the pixel driving circuit PD (in Figure 3 The cathode voltage (shown in the diagram) is transmitted to the light-emitting device ED. The same cathode voltage can be applied to the second electrode CE2 of each of the multiple sub-pixels. For example, the same voltage can be applied to the second electrode CE2 of each of the multiple sub-pixels and the cathode 135 of the light-emitting device ED (in the diagram). Figure 9 (As shown in the figure). Therefore, the second electrode CE2 can be a common electrode, but the embodiments of this disclosure are not limited thereto.

[0111] At least a portion of the sub-pixels in a plurality of sub-pixels may share a second electrode CE2. A portion of the second electrode CE2 of each of the plurality of sub-pixels may be integrally formed and electrically connected. When the same voltage is applied to the second electrode CE2, the second electrode CE2 of a portion of the sub-pixels may be shared and used. For example, the second electrodes CE2 of a portion of pixels PX arranged in the same row horizontally may be integrally formed and connected to each other. For example, a plurality of pixels PX may be provided with one second electrode CE2. One second electrode CE2 may be provided for every n sub-pixels.

[0112] For example, a portion of the second electrodes CE2 of each of the multiple sub-pixels may be spaced apart or separated from each other. For example, the second electrode CE2 connected to pixel PX in row n and the second electrode CE2 connected to pixel PX in row n+1 may be spaced apart from each other. For example, the multiple second electrodes CE2 may be spaced apart from each other with multiple communication lines NL extending along the row direction interposed between them. Therefore, the number of multiple sub-pixels may be greater than the number of multiple second electrodes CE2. As another example, all the second electrodes CE2 of the multiple sub-pixels may be integrally connected, so that only one second electrode CE2 may be provided on the substrate 110, and the embodiments of this disclosure are not limited thereto.

[0113] Multiple second electrodes CE2 can be formed of a transparent conductive material, but embodiments of this disclosure are not limited thereto. The multiple second electrodes CE2 can be formed of a transparent conductive material such that light emitted from the light-emitting device ED is guided to the upper part of the second electrodes CE2. For example, the second electrodes CE2 can be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but embodiments of this disclosure are not limited thereto.

[0114] Multiple contact electrodes CCE can be disposed on the substrate 110. For example, the multiple contact electrodes CCE can be spaced apart from multiple embankments BNK and multiple signal lines TL. Each of the multiple second electrodes CE2 can overlap with at least one contact electrode CCE. For example, one second electrode CE2 can overlap with multiple contact electrodes CCE.

[0115] For example, multiple contact electrodes CCE can be electrically connected to multiple second electrodes CE2. Multiple contact electrodes CCE can be disposed between the substrate 110 and the multiple second electrodes CE2 to receive signals from the pixel driving circuit PD (in... Figure 3 The cathode voltage (shown in the figure) is transmitted to the second electrode CE2.

[0116] For example, when miniature light-emitting diodes (LEDs) are used as light-emitting devices (EDs), multiple miniature LEDs can be formed in a wafer, and the miniature LEDs can be transferred onto a substrate 110 to manufacture a display panel 100. Various defects may occur during the process of transferring multiple LEDs with micro-sized dimensions from the wafer onto the substrate 110. For example, a non-transfer defect may occur in some sub-pixels, where an LED is not transferred, while a defect may occur in some sub-pixels where the LED is transferred out of position due to alignment errors. Furthermore, even if the transfer process proceeds normally, the transferred LED itself may have defects. Therefore, during the transfer process of multiple LEDs, considering defects, multiple identical LEDs may be transferred to a single sub-pixel. After performing illumination tests on multiple LEDs, only one LED that is ultimately determined to be functioning correctly can be used.

[0117] For example, first-1 light-emitting device 130a and first-2 light-emitting device 130b can be transferred to a pixel PX, and defects can be checked in first-1 light-emitting device 130a and first-2 light-emitting device 130b. If both first-1 light-emitting device 130a and first-2 light-emitting device 130b are determined to be normal, only first-1 light-emitting device 130a can be used, and first-2 light-emitting device 130b can be omitted. As another example, if only first-2 light-emitting device 130b is determined to be normal, first-1 light-emitting device 130a can be omitted, and only first-2 light-emitting device 130b can be used. Therefore, even if multiple identical light-emitting devices ED are transferred to a pixel PX, only one light-emitting device ED can ultimately be used.

[0118] Therefore, either one of a pair of light-emitting diodes (EDs) can be the primary ED, and the other ED can be a redundant ED. The redundant ED can be an additional ED transferred to address defects in the primary ED. When the primary ED is defective, the redundant ED can be used to replace it. Thus, the primary and redundant EDs are transferred to a single pixel (PX), minimizing display quality degradation caused by defects in both the primary and redundant EDs.

[0119] For example, the first-1 light-emitting device 130a, the second-1 light-emitting device 140a, and the third-1 light-emitting device 150a transferred to a pixel PX can be used as the main light-emitting device ED, and the first-2 light-emitting device 130b, the second-2 light-emitting device 140b, and the third-2 light-emitting device 150b can be used as redundant light-emitting devices ED.

[0120] Figure 8 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 9 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. For example, Figure 8 This is a cross-sectional view of the display area AA, the first non-display area NA1, the curved area BA, and the second non-display area NA2. Figure 9 It is a cross-sectional view of a portion of the display area AA.

[0121] refer to Figure 8 The first buffer layer 111a and the second buffer layer 111b can be disposed in the remaining areas of the substrate 110 except for the bending region BA.

[0122] The first buffer layer 111a and the second buffer layer 111b can be disposed within the display area AA, the first non-display area NA1, and the second non-display area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or impurities into the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be formed of an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can be formed of silicon oxide (SiO2). x ) or silicon nitride (SiN) x It can be formed in a single layer or multiple layers, but the embodiments disclosed herein are not limited thereto.

[0123] For example, a portion of the first buffer layer 111a and the second buffer layer 111b located in the bending region BA can be removed. The upper surface of the substrate 110 disposed within the bending region BA can be exposed by the first buffer layer 111a and the second buffer layer 111b. The first buffer layer 111a and the second buffer layer 111b, made of inorganic insulating material, can be removed from the bending region BA, thereby minimizing cracks in the first buffer layer 111a and the second buffer layer 111b that may occur during bending.

[0124] Multiple alignment keys MK can be disposed between the first buffer layer 111a and the second buffer layer 111b. The multiple alignment keys MK can identify the position of the pixel driving circuit PD during the manufacturing process of the display panel 100. For example, the multiple alignment keys MK can be aligned with the position of the pixel driving circuit PD transferred to the adhesive layer 112. Alternatively, the multiple alignment keys MK can be omitted.

[0125] The adhesive layer 112 may be disposed on the second buffer layer 111b. The adhesive layer 112 may be disposed within the display area AA, the first non-display area NA1, the curved area BA, and the second non-display area NA2. Alternatively, a portion of the adhesive layer 112 may be removed from the non-display area NA, which includes the curved area BA. For example, the adhesive layer 112 may be formed from any one of adhesive polymers, epoxy resins, UV-curable resins, polyimide resins, acrylate-based materials, polyurethane-based materials, and polydimethylsiloxane (PDMS), but the embodiments of this disclosure are not limited thereto.

[0126] Within the display area AA, a pixel driving circuit PD can be disposed on the adhesive layer 112. When the pixel driving circuit PD is implemented as a drive driver, the drive driver can be mounted on the adhesive layer 112 through a transfer process, but the embodiments of this disclosure are not limited thereto.

[0127] The first protective layer 113a and the second protective layer 113b may be disposed on the adhesive layer 112 and the pixel driving circuit PD. The first protective layer 113a and the second protective layer 113b may surround the side surface of the pixel driving circuit PD, but embodiments of this disclosure are not limited thereto. For example, the second protective layer 113b may cover at least a portion of the upper surface of the pixel driving circuit PD. For example, at least one of the first protective layer 113a and the second protective layer 113b disposed on the curved region BA may be omitted. For example, the first protective layer 113a may be completely disposed within the display area AA and the non-display area NA, and the second protective layer 113b may be partially disposed within the display area AA, the first non-display area NA1, and the second non-display area NA2, and may not be disposed within the curved region BA. For example, a portion of the second protective layer 113b within the curved region BA may be removed. However, embodiments of this disclosure are not limited thereto.

[0128] The first protective layer 113a and the second protective layer 113b may be formed of organic insulating materials, but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be formed of photoresist, polyimide (PI), photopropylene-based materials, etc., but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be an outer coating or an insulating layer, but the embodiments of this disclosure are not limited thereto.

[0129] According to this disclosure, multiple first connection lines 121 can be disposed on the second protective layer 113b within the display area AA. The multiple first connection lines 121 can be wiring for electrically connecting the pixel driving circuit PD to other components. For example, the pixel driving circuit PD can be electrically connected to multiple signal lines TL, multiple contact electrodes CCE, etc., via the multiple first connection lines 121. For example, the multiple first connection lines 121 may include multiple first-1 connection lines 121a, multiple first-2 connection lines 121b, multiple first-3 connection lines 121c, and multiple first-4 connection lines 121d, but the embodiments of this disclosure are not limited thereto.

[0130] For example, multiple first-1 connection lines 121a can be disposed on the second protective layer 113b. The multiple first-1 connection lines 121a can be electrically connected to the pixel driving circuit PD. The multiple first-1 connection lines 121a can transmit the voltage output from the pixel driving circuit PD to the first electrode CE1 or the second electrode CE2.

[0131] For example, a third protective layer 114 may be disposed on the second protective layer 113b. The third protective layer 114 may be disposed over the entire display area AA and the non-display area NA. Within the curved area BA, the third protective layer 114 may be disposed on the side surface of the second protective layer 113b and the upper surface of the first protective layer 113a, or cover the side surface of the second protective layer 113b and the upper surface of the first protective layer 113a. The third protective layer 114 may be formed of an organic insulating material. For example, the third protective layer 114 may be formed of photoresist, polyimide (PI), photopolymer-based materials, etc., but the embodiments of this disclosure are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 may be formed of the same material, but the embodiments of this disclosure are not limited thereto.

[0132] Multiple first-second connection lines 121b can be disposed on the third protective layer 114. These multiple first-second connection lines 121b can be connected to the pixel driving circuit PD via the first-first connection line 121a, or they can be directly connected to the pixel driving circuit PD. For example, a portion of the first-second connection lines 121b can be directly connected to the pixel driving circuit PD through contact holes in the third protective layer 114. Another portion of the first-second connection lines 121b can be electrically connected to the first-first connection line 121a through contact holes in the third protective layer 114. However, embodiments of this disclosure are not limited to this. For example, the voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 or the second electrode CE2 via connection lines different from the multiple first-second connection lines 121b.

[0133] The first insulating layer 115a can be disposed on multiple first-second connecting lines 121b. The first insulating layer 115a can be disposed throughout the entire display area AA and the non-display area NA, but embodiments of this disclosure are not limited thereto. The first insulating layer 115a can be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the first insulating layer 115a can be formed of photoresist, polyimide (PI), photopropylene-based materials, etc., but embodiments of this disclosure are not limited thereto.

[0134] Multiple first-to-third connecting wires 121c can be disposed on the first insulating layer 115a. Multiple first-to-third connecting wires 121c can be electrically connected to multiple first-to-second connecting wires 121b. For example, the first-to-third connecting wires 121c can be electrically connected to the first-to-second connecting wires 121b through contact holes in the first insulating layer 115a.

[0135] The second insulating layer 115b can be disposed on multiple first-to-third connecting lines 121c. The second insulating layer 115b can be disposed in areas other than the bending region BA, but embodiments of this disclosure are not limited thereto. The second insulating layer 115b can be disposed within the display region AA, the first non-display region NA1, and the second non-display region NA2, but embodiments of this disclosure are not limited thereto. For example, at least a portion of the second insulating layer 115b disposed within the bending region BA can be removed. The second insulating layer 115b can be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the second insulating layer 115b can be formed of photoresist, polyimide (PI), photopropylene-based materials, etc., but embodiments of this disclosure are not limited thereto.

[0136] Multiple first-to-fourth connecting wires 121d can be disposed on the second insulating layer 115b. Multiple first-to-fourth connecting wires 121d can be electrically connected to multiple first-to-third connecting wires 121c. For example, the first-to-fourth connecting wires 121d can be electrically connected to the first-to-third connecting wires 121c through contact holes in the second insulating layer 115b.

[0137] The first-to-fourth connection line 121d can be connected to the contact electrode CCE through the contact hole of the third insulating layer 115c. Therefore, the contact electrode CCE and the pixel driving circuit PD can be electrically connected to each other through the first connection line 121.

[0138] Although not shown, the first-fourth connection line 121d can be directly connected to the signal line TL through a contact hole provided in the third insulating layer 115c, or it can be electrically connected to the signal line TL through other additional lines or electrodes. Therefore, the signal line TL and the pixel driving circuit PD can be electrically connected through the first connection line 121.

[0139] According to this disclosure, multiple second connection lines 122 can be disposed on a second protective layer 113b within the non-display area NA. The multiple second connection lines 122 can be used to transfer data from a flexible circuit board (or flexible film) 170 (in...) Figure 2 (shown in) and printed circuit board 160 (in Figure 2 The wiring of the pixel drive circuit PD (shown in the figure) transmits the received signal to the display area AA.

[0140] For example, multiple second connection lines 122 can be electrically connected to multiple pad electrodes PE to connect from the flexible circuit board (or flexible film) 170 (in Figure 2 (shown in) and printed circuit board 160 (in Figure 2 (As shown in the image) Received signal.

[0141] For example, multiple second connection lines 122 can be connected from the pad portion PAD (in Figure 2 (As shown in the diagram) wiring extending to the display area AA to transmit signals to the display area AA. In this case, multiple second connection lines 122 can be used as link lines LL (in... Figure 3 (As shown in the figure). The plurality of second connection lines 122 may include second-1 connection line 122a, second-2 connection line 122b, second-3 connection line 122c and second-4 connection line 122d.

[0142] Multiple second-first connecting lines 122a can be disposed on the second protective layer 113b. The multiple second-first connecting lines 122a can extend from the second non-display area NA2 to the curved area BA and the first non-display area NA1. The multiple second-first connecting lines 122a can extend from the flexible circuit board (or flexible film) 170 (in... Figure 2 (shown in) and printed circuit board 160 (in Figure 2 The received signal (shown in the diagram) is transmitted to the pixel driving circuit PD of the display area AA. Therefore, multiple second-1 connection lines 122a can be electrically connected to the pad electrode PE and the pixel driving circuit PD, respectively.

[0143] For example, although not shown, the second-1 connection line 122a can extend to the display area AA to be directly connected to the pixel driving circuit PD within the display area AA, or it can be electrically connected to the pixel driving circuit PD via other additional lines or electrodes. Furthermore, the second-1 connection line 122a can be electrically connected to the pad electrode PE within the second non-display area NA2 via the second-2 connection line 122b, the second-3 connection line 122c, and the second-4 connection line 122d. Therefore, the pixel driving circuit PD and the pad electrode PE can be electrically connected to each other via the second connection line 122.

[0144] Multiple second-2 connecting lines 122b can be disposed on the third protective layer 114. Multiple second-2 connecting lines 122b can be disposed within the second non-display area NA2. The second-2 connecting lines 122b can be electrically connected to the second-1 connecting line 122a through contact holes in the third protective layer 114. Therefore, from the flexible circuit board (or flexible film) 170 (in... Figure 2 (shown in) and printed circuit board 160 (in Figure 2 The signal shown in the figure can be transmitted to the 2-1 connection line 122a through the 2-2 connection line 122b.

[0145] The second-third connecting line 122c can be disposed on the first insulating layer 115a. The second-third connecting line 122c can be disposed within the second non-display area NA2. The second-third connecting line 122c can be electrically connected to the second-second connecting line 122b through the contact hole of the first insulating layer 115a. Therefore, from the flexible circuit board (or flexible film) 170 (in Figure 2 (shown in) and printed circuit board 160 (in Figure 2 The signal shown in the figure can be transmitted to the 2-1 connection line 122a through the 2-3 connection line 122c and the 2-2 connection line 122b.

[0146] The second-fourth connection line 122d can be disposed on the second insulating layer 115b. The second-fourth connection line 122d can be disposed within the second non-display area NA2. The second-fourth connection line 122d can be electrically connected to the second-third connection line 122c through the contact hole of the second insulating layer 115b. The second-fourth connection line 122d can be electrically connected to the pad electrode PE through the contact hole of the third insulating layer 115c.

[0147] Therefore, from flexible circuit board (or flexible film) 170 (in Figure 2 (shown in) and printed circuit board 160 (in Figure 2 The signal shown in the figure can be transmitted to the 2-1 connection line 122a through the 2-4 connection line 122d, the 2-3 connection line 122c and the 2-2 connection line 122b.

[0148] The plurality of first connecting lines 121 and the plurality of second connecting lines 122 may be formed of a conductive material with excellent ductility or various conductive materials used within the display area AA. For example, the second connecting lines 122, which are partially disposed within the curved area BA, may be formed of a conductive material with excellent ductility, such as gold (Au), silver (Ag), or aluminum (Al), but embodiments of the present disclosure are not limited thereto. As another example, the plurality of first connecting lines 121 and the plurality of second connecting lines 122 may be formed of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), silver (Ag), and magnesium (Mg), or alloys thereof, but embodiments of the present disclosure are not limited thereto.

[0149] The third insulating layer 115c can be disposed on multiple first connecting lines 121 and multiple second connecting lines 122. The third insulating layer 115c can be disposed in the remaining areas except for the curved region BA, but embodiments of this disclosure are not limited thereto. The third insulating layer 115c can be disposed within the display region AA, the first non-display region NA1, and the second non-display region NA2. At least a portion of the third insulating layer 115c within the curved region BA can be removed. The third insulating layer 115c can be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. For example, the third insulating layer 115c can be formed of photoresist, polyimide (PI), photopropylene-based materials, etc., but embodiments of this disclosure are not limited thereto.

[0150] Multiple dam sections (BNK) can be disposed on the third insulating layer 115c within the display area AA. The multiple dam sections (BNK) can overlap with each of the multiple sub-pixels. The multiple dam sections (BNK) may not be disposed within the first non-display area NA1, the second non-display area NA2, and the curved area BA. One or more light-emitting devices (ED) of the same type can be disposed on top of each of the multiple dam sections (BNK).

[0151] Within the display area AA, multiple signal lines TL can be disposed on the third insulating layer 115c. These multiple signal lines TL can be disposed between multiple dikes BNK. For example, the multiple signal lines TL can be disposed adjacent to any one of the multiple dikes BNK. Each of the multiple signal lines TL can be electrically connected to a first connecting line 121, for example, connecting lines 1-4 121d.

[0152] In the display area AA, multiple contact electrodes CCE can be disposed on the third insulating layer 115c. The multiple contact electrodes CCE can supply the cathode voltage from the pixel driving circuit PD to the second electrode CE2. Each of the multiple contact electrodes CCE can be electrically connected to the first connection line 121, for example, the first to fourth connection lines 121d.

[0153] The first electrode CE1 can be disposed on the embankment BNK. For example, the first electrode CE1 can extend from the adjacent signal line TL to the upper part of the embankment BNK. The first electrode CE1 can be disposed on the upper surface and the side surface of the embankment BNK. For example, the first electrode CE1 can extend from the signal line TL on the upper surface of the third insulating layer 115c to the side surface and the upper surface of the embankment BNK. The first electrode CE1 can be integrally formed with the signal line TL.

[0154] refer to Figure 9 The first electrode CE1 may include multiple conductive layers. For example, the first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but the embodiments of this disclosure are not limited thereto.

[0155] The first conductive layer CE1a can be disposed on the embankment BNK. The second conductive layer CE1b can be disposed on the first conductive layer CE1a. The third conductive layer CE1c can be disposed on the second conductive layer CE1b, and the fourth conductive layer CE1d can be disposed on the third conductive layer CE1c. For example, the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be formed of titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto.

[0156] According to this disclosure, a portion of the conductive layers in the plurality of conductive layers included in the first electrode CE1, which has high reflectivity, may be composed of alignment bonds and / or reflectors for aligning the light-emitting device ED. For example, the second conductive layer CE1b in the plurality of conductive layers of the first electrode CE1 may contain a reflective material. For example, the second conductive layer CE1b may contain aluminum (Al), but embodiments of this disclosure are not limited thereto. Therefore, the second conductive layer CE1b can be used as a reflector. Furthermore, due to the high reflectivity of the second conductive layer CE1b, identification can be easily performed during manufacturing, and therefore the position or repositioning of the light-emitting device ED can be arranged with reference to the second conductive layer CE1b.

[0157] For example, to use the second conductive layer CE1b as a reflector, the third conductive layer CE1c and the fourth conductive layer CE1d covering the second conductive layer CE1b can be partially removed or etched. For example, a portion of the third conductive layer CE1c and the fourth conductive layer CE1d disposed on the embankment BNK can be removed or etched to expose the upper surface of the second conductive layer CE1b. For example, the central and edge portions of the third conductive layer CE1c and the fourth conductive layer CE1d with solder patterns SDP can be retained, and the remaining portions of the third conductive layer CE1c and the fourth conductive layer CE1d except for the central and edge portions can be removed. For example, the central and edge portions of each of the third conductive layer CE1c made of titanium (Ti) and the fourth conductive layer CE1d made of indium tin oxide (ITO) can be left unetched. Therefore, the other conductive layer of the first electrode CE1 can be prevented from being etched by the TMAH (tetramethylammonium hydroxide) solution used in the masking process of the first electrode CE1.

[0158] According to this disclosure, the first conductive layer CE1a and the third conductive layer CE1c may comprise titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b may comprise aluminum (Al). The fourth conductive layer CE1d may comprise a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) that has high adhesion to the solder pattern SDP and is resistant to corrosion and acid. However, embodiments of this disclosure are not limited thereto.

[0159] The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be deposited sequentially and then patterned by photolithography and etching processes, but the embodiments disclosed herein are not limited thereto.

[0160] like Figure 8 and Figure 9 As shown, according to this disclosure, the signal line TL, contact electrode CCE, and pad electrode PE disposed on the same layer as the first electrode CE1 can be formed of multilayer conductive materials, but the embodiments of this disclosure are not limited thereto. For example, the signal line TL, contact electrode CCE, and pad electrode PE can be formed of multilayers of indium tin oxide (ITO), titanium (Ti), aluminum (Al), and titanium (Ti), but the embodiments of this disclosure are not limited thereto.

[0161] According to this disclosure, a solder pattern SDP can be disposed on a first electrode CE1 in each of a plurality of sub-pixels. The solder pattern SDP can bond a light-emitting device ED to the first electrode CE1. The first electrode CE1 and the light-emitting device ED can be electrically connected to each other via eutectic bonding using the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, when the solder pattern SDP is formed of indium (In) and the anode 134 of the light-emitting device ED is formed of gold (Au), the solder pattern SDP and the anode 134 can be bonded to each other by applying heat and pressure during a transfer process of the light-emitting device ED. The light-emitting device ED can be bonded to the solder pattern SDP and the first electrode CE1 via eutectic bonding without a separate adhesive member. For example, the solder pattern SDP can be formed of indium (In), tin (Sn), or alloys thereof, but embodiments of this disclosure are not limited thereto. For example, the solder pattern SDP can be a bonding pad, a contact pad, etc., but embodiments of this disclosure are not limited thereto.

[0162] According to this disclosure, a passivation layer 116 can be provided on multiple signal lines TL, multiple first electrodes CE1, multiple contact electrodes CCE, and a third insulating layer 115c. For example, the passivation layer 116 can be provided within a display area AA, a first non-display area NA1, and a second non-display area NA2. A portion of the passivation layer 116 provided within the curved area BA can be removed. A portion of the passivation layer 116 covering multiple pad electrodes PE can be removed within the second non-display area NA2. A portion of the passivation layer 116 covering multiple contact electrodes CCE can be removed within the display area AA. The passivation layer 116 covering the solder pattern SDP can be removed within the display area AA.

[0163] Since the passivation layer 116 covers the remaining area while exposing a portion of the multiple pad electrodes (PE), a portion of the multiple contact electrodes (CCE), and a portion of the solder pattern (SDP), the penetration of moisture or impurities into the light-emitting device (ED) can be reduced. For example, the passivation layer 116 can be made of silicon oxide (SiO2). x ) or silicon nitride (SiN) x The passivation layer 116 may be formed in a single layer or multiple layers, but the embodiments of this disclosure are not limited thereto. For example, the passivation layer 116 may be a protective layer or an insulating layer, but the embodiments of this disclosure are not limited thereto. For example, the passivation layer 116 may include holes exposing the solder pattern SDP and holes exposing the contact electrode CCE.

[0164] In each of the plurality of sub-pixels, a light-emitting device ED can be disposed on a solder pattern SDP. A first light-emitting device 130 can be disposed in a first sub-pixel SP1. A second light-emitting device 140 can be disposed in a second sub-pixel SP2. A third light-emitting device 150 can be disposed in a third sub-pixel SP3.

[0165] Light-emitting devices (EDs) can be formed on silicon wafers using methods such as metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or sputtering, but the embodiments disclosed herein are not limited thereto.

[0166] refer to Figure 9 The first light-emitting device 130 may include an anode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode 135, and an encapsulation layer 136, but the embodiments disclosed herein are not limited thereto. For example, the encapsulation layer 136 may not be included in the first light-emitting device 130.

[0167] The first semiconductor layer 131 can be disposed on the solder pattern SDP. The second semiconductor layer 133 can be disposed on the first semiconductor layer 131.

[0168] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 may comprise a compound semiconductor such as a group III-V or group II-VI semiconductor, and may be doped with impurities (or dopants). For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 may be a semiconductor layer doped with n-type impurities, and the other may be a semiconductor layer doped with p-type impurities, but the embodiments of this disclosure are not limited thereto. For example, at least one of the first semiconductor layer 131 and the second semiconductor layer 133 may be a layer in which n-type or p-type impurities are doped into materials such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or materials such as gallium arsenide (GaAs), but the embodiments of this disclosure are not limited thereto. For example, n-type impurities can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), tin (Sn), etc., but the embodiments of this disclosure are not limited to these. For example, p-type impurities can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), beryllium (Be), etc., but the embodiments of this disclosure are not limited to these.

[0169] For example, each of the first semiconductor layer 131 and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities and a nitride semiconductor containing p-type impurities, but the embodiments of this disclosure are not limited thereto. For example, the first semiconductor layer 131 may be a nitride semiconductor containing p-type impurities, and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities, but the embodiments of this disclosure are not limited thereto.

[0170] An active layer 132 may be disposed between a first semiconductor layer 131 and a second semiconductor layer 133. The active layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. For example, the active layer 132 may be formed from one of a single-well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but the embodiments of this disclosure are not limited thereto. For example, the active layer 132 may be formed from indium gallium nitride (InGaN) or gallium nitride (GaN), but the embodiments of this disclosure are not limited thereto.

[0171] For example, the active layer 132 may include a multi-quantum well (MQW) structure having a well layer and a blocking layer with a higher bandgap than the well layer. For example, the active layer 132 may include InGaN as the well layer and may include an AlGaN layer as the blocking layer, but the embodiments disclosed herein are not limited thereto.

[0172] An anode 134 may be disposed between the first semiconductor layer 131 and the solder pattern SDP. For example, the anode 134 may electrically connect the first semiconductor layer 131 to the first electrode CE1. The anode voltage output from the pixel driving circuit PD may be applied to the first semiconductor layer 131 via the signal line TL, the first electrode CE1, and the anode 134. For example, the anode 134 may be formed of a conductive material capable of eutectic bonding with the solder pattern SDP, but embodiments of this disclosure are not limited thereto. For example, the anode 134 may be formed of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), copper (Cu), or alloys thereof, but embodiments of this disclosure are not limited thereto.

[0173] A cathode 135 may be disposed on the second semiconductor layer 133. For example, the cathode 135 may electrically connect the second semiconductor layer 133 to the second electrode CE2. The cathode voltage output from the pixel driving circuit PD may be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode 135. The cathode 135 may be formed of a transparent conductive material to guide light emitted from the light-emitting device ED to the upper part of the light-emitting device ED, but the embodiments of this disclosure are not limited thereto. For example, the cathode 135 may be formed of materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the embodiments of this disclosure are not limited thereto.

[0174] The encapsulation layer 136 may be disposed on at least a portion of each of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode 134, and the cathode 135. For example, the encapsulation layer 136 may surround at least a portion of each of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode 134, and the cathode 135.

[0175] For example, the encapsulation layer 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation layer 136 can be disposed on the side surface of the first semiconductor layer 131, the side surface of the active layer 132, and the side surface of the second semiconductor layer 133.

[0176] For example, the encapsulation layer 136 may be disposed on at least a portion of the anode 134 and the cathode 135, for example, on an edge portion (or one side) of the anode 134 and an edge portion (or one side) of the cathode 135. At least a portion of the anode 134 may be exposed by the encapsulation layer 136, and the anode 134 may be connected to a solder pattern SDP. For example, at least a portion of the cathode 135 may be exposed by the encapsulation layer 136, and the cathode 135 may be connected to a second electrode CE2. For example, the encapsulation layer 136 may be made of a material such as silicon nitride (SiN). x ) or silicon oxide (SiO) x The insulating material is formed, but the embodiments disclosed herein are not limited thereto.

[0177] For example, the encapsulation layer 136 may have a structure in which reflective material is distributed in the resin layer, but the embodiments of this disclosure are not limited thereto. For example, the encapsulation layer 136 may be manufactured as a reflector with various structures, but the embodiments of this disclosure are not limited thereto. Light emitted from the active layer 132 may be reflected upward by the encapsulation layer 136, thereby improving light extraction efficiency. For example, the encapsulation layer 136 may be a reflective layer, but the embodiments of this disclosure are not limited thereto.

[0178] According to this disclosure, the light-emitting device (ED) is described as having a vertical structure, but the embodiments of this disclosure are not limited thereto. For example, the ED may have a lateral structure or a flip-chip structure.

[0179] Although reference Figure 9 The first light-emitting device 130 has been described, but the second light-emitting device 140 and the third light-emitting device 150 may have a structure that is substantially the same as that of the first light-emitting device 130. For example, the second light-emitting device 140 and the third light-emitting device 150 may have a configuration that is substantially the same as that of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode 134, the cathode 135 and the encapsulation layer 136.

[0180] like Figure 8 and Figure 9 As shown, a first optical layer 117a may be disposed within the display area AA, surrounding multiple light-emitting devices ED. For example, the first optical layer 117a may cover the side surfaces of multiple light-emitting devices ED and multiple embankment BNK in multiple sub-pixels. For example, the first optical layer 117a may cover a portion of the passivation layer 116. For example, the first optical layer 117a may cover the second electrode CE2, a portion of the passivation layer 116, and the area between the multiple light-emitting devices ED. The first optical layer 117a may be disposed or cover the areas between the multiple light-emitting devices ED and the multiple embankment BNK contained in a pixel PX. For example, in a plan view, the first optical layer 117a may extend in a first direction X, and multiple first optical layers 117a may be spaced apart from each other in a second direction Y. For example, the first optical layer 117a may be disposed between the passivation layer 116 and the second electrode CE2 to surround the side surfaces of the light-emitting devices ED and the side surfaces of the embankment BNK, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a may be a diffusion layer, a sidewall diffusion layer, etc., but the embodiments of this disclosure are not limited thereto.

[0181] The first optical layer 117a may comprise an organic insulating material with distributed fine particles, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a may be formed of a siloxane with distributed fine metal particles such as titanium dioxide (TiO2) particles, but the embodiments of this disclosure are not limited thereto. Light from the multiple light-emitting devices (EDs) can be scattered and emitted to the outside of the display panel 100 by the fine particles distributed in the first optical layer 117a. Therefore, the first optical layer 117a can improve the extraction efficiency of light emitted from the multiple light-emitting devices (EDs).

[0182] For example, the first optical layer 117a may be disposed in each of the plurality of pixels PX, or it may be disposed in a subset of pixels PX arranged in the same row, but the embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a may be disposed in each of the plurality of pixels PX, or the plurality of pixels PX may share a single first optical layer 117a. As another example, each of the plurality of sub-pixels may individually include the first optical layer 117a, but the embodiments of this disclosure are not limited thereto.

[0183] According to this disclosure, the second optical layer 117b can be disposed on the passivation layer 116 within the display area AA. For example, the second optical layer 117b can surround the first optical layer 117a. For example, the second optical layer 117b can contact the side surface of the first optical layer 117a. For example, the second optical layer 117b can be disposed in the area between multiple pixels PX. However, the embodiments of this disclosure are not limited thereto. For example, the second optical layer 117b can be a diffusion layer, a window diffusion layer, etc., but the embodiments of this disclosure are not limited thereto.

[0184] The second optical layer 117b may be formed of an organic insulating material, but embodiments of this disclosure are not limited thereto. The second optical layer 117b may be formed of the same material as the first optical layer 117a, but embodiments of this disclosure are not limited thereto. For example, the first optical layer 117a may contain fine particles, while the second optical layer 117b may not contain fine particles. For example, the second optical layer 117b may be formed of a siloxane, but embodiments of this disclosure are not limited thereto.

[0185] For example, the thickness of the first optical layer 117a may be less than the thickness of the second optical layer 117b, but the embodiments of this disclosure are not limited thereto. Therefore, in a plan view, the area where the first optical layer 117a is disposed may include a recessed portion recessed from the upper surface of the second optical layer 117b.

[0186] According to this disclosure, the second electrode CE2 can be disposed on the first optical layer 117a and the second optical layer 117b. For example, the second electrode CE2 can be electrically connected to multiple contact electrodes CCE through contact holes in the second optical layer 117b. For example, the second electrode CE2 can be disposed on multiple light-emitting devices ED. For example, the second electrode CE2 can contain a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto. For example, the second electrode CE2 can contact the cathode 135. For example, the second electrode CE2 can overlap the entire first optical layer 117a and a portion of the second optical layer 117b.

[0187] The second electrode CE2 can extend continuously in a first direction of the substrate 110. Therefore, the second electrode CE2 can be connected to a plurality of pixels PX arranged along the first direction of the substrate 110. For example, the second electrode CE2 can be connected to a plurality of pixels PX.

[0188] According to this disclosure, the second electrode CE2 can extend continuously over the first optical layer 117a, the second optical layer 117b, and the light-emitting device ED. The region where the first optical layer 117a is disposed may include a recessed portion that is recessed from the upper surface of the second optical layer 117b. Therefore, since the first portion of the second electrode CE2 disposed on the first optical layer 117a is disposed along the recessed portion, the first portion can be disposed at a position lower than the second portion of the second electrode CE2 disposed on the second optical layer 117b.

[0189] The third optical layer 117c can be disposed on the second electrode CE2. The third optical layer 117c can overlap with the plurality of light-emitting devices ED and the first optical layer 117a. For example, the third optical layer 117c may not overlap with the second optical layer 117b. Since the third optical layer 117c is disposed on the second electrode CE2 and the plurality of light-emitting devices ED, it can improve the appearance of spots (or brightness inhomogeneities) that may occur in some of the plurality of light-emitting devices ED. For example, when the plurality of light-emitting devices ED are transferred to the substrate 110 of the display panel 100, areas with uneven spacing between the plurality of light-emitting devices ED may be formed due to process deviations, etc. When the spacing between the plurality of light-emitting devices ED is uneven, the light-emitting area of ​​each of the plurality of light-emitting devices ED may be unevenly set, and therefore the user may perceive spots (or brightness inhomogeneities). Therefore, since the third optical layer 117c is formed to uniformly diffuse light on the upper part of the plurality of light-emitting devices ED, the situation where light emitted from some of the light-emitting devices ED is perceived as spots (or brightness inhomogeneities) can be reduced. Therefore, since the light emitted from multiple light-emitting devices (EDs) is uniformly diffused by the third optical layer 117c and extracted to the outside of the display panel 100, the brightness uniformity of the display device can be improved.

[0190] The third optical layer 117c can be formed of an organic insulating material with finely distributed particles, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 117c can be formed of a siloxane with fine metal particles such as titanium dioxide (TiO2) particles distributed thereto, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 117c can be formed of the same material as the first optical layer 117a, but the embodiments of this disclosure are not limited thereto. For example, the third optical layer 117c can be a diffusion layer, an upper diffusion layer, etc., but the embodiments of this disclosure are not limited thereto.

[0191] According to this disclosure, light from multiple light-emitting devices (EDs) can be scattered and emitted to the outside of the display panel 100 by fine particles distributed in the third optical layer 117c. The third optical layer 117c can uniformly mix the light emitted from the multiple light-emitting devices (EDs) to further improve the brightness uniformity of the display device. In addition, the light extraction efficiency of the display device can be improved by the light scattered from the multiple fine particles, and therefore the display device can be driven with low power consumption.

[0192] Within the display area AA, a black matrix BM can be disposed on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c. For example, the black matrix BM can fill the contact hole of the second optical layer 117b. Since the black matrix BM can cover the display area AA, color mixing of light from multiple sub-pixels and reflection of external light can be reduced. For example, since the black matrix BM is disposed within the contact hole where the second electrode CE2 and the contact electrode CCE are connected, light leakage between multiple adjacent sub-pixels can be prevented.

[0193] For example, the black matrix BM can be formed from an opaque material, but the embodiments of this disclosure are not limited thereto. For example, the black matrix BM can be an organic insulating material with added black pigment or black dye, but the embodiments of this disclosure are not limited thereto.

[0194] refer to Figure 8 A cover layer 118 may be disposed on the black matrix BM within the display area AA. The cover layer 118 can protect the components beneath it. For example, the cover layer 118 may be formed of an organic insulating material, but the embodiments of this disclosure are not limited thereto. For example, the cover layer 118 may be formed of photoresist, polyimide (PI), photopropylene-based materials, etc., but the embodiments of this disclosure are not limited thereto. For example, the cover layer 118 may be an outer coating, an insulating layer, etc., but the embodiments of this disclosure are not limited thereto.

[0195] The polarizing layer 280 can be disposed on the cover layer 118 via the first adhesive layer 291. The cover member 120 can be disposed on the polarizing layer 280 via the second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 may comprise optically transparent adhesive (OCA), optically transparent resin (OCR), pressure-sensitive adhesive (PSA), etc., but the embodiments of this disclosure are not limited thereto.

[0196] According to this disclosure, a plurality of pad electrodes PE can be disposed on a third insulating layer 115c within a second non-display area NA2. For example, a portion of the plurality of pad electrodes PE can be exposed by a passivation layer 116. For example, the plurality of pad electrodes PE can be electrically connected to the second-fourth connection line 122d through contact holes in the third insulating layer 115c.

[0197] An adhesive film (ACF) can be disposed on multiple pad electrodes PE. The adhesive film ACF can be an adhesive layer in which conductive spheres are distributed in an insulating material, but embodiments of this disclosure are not limited thereto. When heat or pressure is applied to the adhesive film ACF, the conductive spheres can have conductive properties in the area where heat or pressure is applied. The adhesive film ACF can be disposed between the multiple pad electrodes PE and the flexible circuit board (or flexible film) 170, such that the flexible circuit board (or flexible film) 170 can be attached to or bonded to the multiple pad electrodes PE. For example, the adhesive film ACF can be an anisotropic conductive film (ACF), but embodiments of this disclosure are not limited thereto.

[0198] A flexible circuit board (or flexible film) 170 can be disposed on an adhesive film ACF. The flexible circuit board (or flexible film) 170 can be electrically connected to multiple pad electrodes PE via the adhesive film ACF. Therefore, signals output from the flexible circuit board (or flexible film) 170 and the printed circuit board 160 can be transmitted to the pixel driving circuit PD of the display area AA via the multiple pad electrodes PE, the second-fourth connection line 122d, the second-third connection line 122c, the second-second connection line 122b, and the second-first connection line 122a.

[0199] Figure 10A This is a plan view showing the transfer area of ​​a display device according to an embodiment of the present disclosure. Figure 10B This is a plan view showing the transfer area of ​​a display device according to another embodiment of the present disclosure.

[0200] refer to Figure 10A and Figure 10B Multiple light-emitting devices can be transferred to the display area AA of the display device through multiple transfer processes.

[0201] For example, such as Figure 10A As shown, multiple light-emitting devices can be transferred to the display area AA by performing six transfer processes on the first to sixth transfer areas using a transfer stamp capable of transferring multiple light-emitting devices. In this case, the first to sixth transfer areas can be divided by a first boundary line D1 in the vertical direction and a second and third boundary lines D2 and D3 in the horizontal direction, and multiple sub-pixels can be set in each of the first to sixth transfer areas.

[0202] Or, such as Figure 10BAs shown, multiple light-emitting devices can be transferred to the display area AA by performing nine transfer processes on the first to ninth transfer areas using a transfer stamp capable of transferring multiple light-emitting devices. In this case, the first to ninth transfer areas can be divided by a first boundary line D1 and a second boundary line D2 in the vertical direction, and a third boundary line D3 and a fourth boundary line D4 in the horizontal direction, and multiple sub-pixels can be set in each of the first to ninth transfer areas.

[0203] In execution according to Figure 10A and Figure 10B During the transfer process, transfer errors or deviations may occur between each transfer step using the transfer stamp.

[0204] For example, there may be no transfer error during the transfer process to the first transfer region, but a transfer error may occur during the transfer process to the second transfer region. Alternatively, although no transfer error occurs during the transfer processes to the first and second transfer regions, there may be a deviation between the light-emitting characteristics of the multiple light-emitting devices in the multiple sub-pixels transferred to the first transfer region and the light-emitting characteristics of the multiple light-emitting devices in the multiple sub-pixels transferred to the second transfer region.

[0205] In this way, if there are differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices among multiple transfer regions, differences in luminous intensity may occur between the multiple transfer regions. In this case, spots may appear near the boundary lines D1, D2, D3, and D4 between the multiple transfer regions, leading to a decrease in display quality.

[0206] The following section describes a display device that can reduce the problem of spots appearing near the boundary lines between multiple transfer areas.

[0207] Figure 11A and Figure 11B These are cross-sectional and plan views of a subpixel according to an embodiment of the present disclosure. Figure 12A and Figure 12B This is a cross-sectional view and a plan view of a subpixel according to another embodiment of the present disclosure. Figure 13A and Figure 13B This is a cross-sectional view and a plan view of a subpixel according to another embodiment of the present disclosure. Figure 14A and Figure 14B This is a cross-sectional view and a plan view of a subpixel according to another embodiment of the present disclosure.

[0208] Figure 11A , Figure 12A , Figure 13A and Figure 14A Only the above are shown respectively. Figure 9The embankment BNK and the first electrode CE1. Figure 11B It shows according to Figure 11A The view shows the state of the signal line TL connected to the first electrode CE1, based on an example. Figure 12B It shows according to Figure 12A The view shows the state of the signal line TL connected to the first electrode CE1, based on an example. Figure 13B It shows according to Figure 13A The view shows the state of the signal line TL connected to the first electrode CE1, based on an example. Figure 14B It shows according to Figure 14A The view shows the state of the signal line TL connected to the first electrode CE1, based on an example.

[0209] As can be seen from each of the accompanying figures, each sub-pixel includes a dam portion BNK and a first electrode CE1 disposed on the dam portion BNK. The first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d.

[0210] In this case, the first electrode CE1 set in each sub-pixel may include a central region CA, reflective regions RA1, RA2, RA3, RA4, and edge regions EA1, EA2, EA3, EA4.

[0211] The Central Area CA is configured as described above. Figure 9 SDP solder pattern with Figure 9 The solder pattern SDP contacts the area. The central region CA of the first electrode CE1 passes through... Figure 9 The solder pattern SDP is electrically connected to the light-emitting device ED. Within the central region CA, the upper surface of the first electrode CE1 can be formed by a fourth conductive layer CE1d. For example, it includes a layer with... Figure 9 The fourth conductive layer CE1d of the transparent conductive oxide layer with good adhesion of the solder pattern SDP and corrosion and acid resistance can form the upper surface of the first electrode CE1 within the central region CA.

[0212] In this case, according to Figure 11A , Figure 12A , Figure 13A and Figure 14A In various embodiments, the width of the central region CA can be the same across all sub-pixels.

[0213] like Figure 11B , Figure 12B , Figure 13B and Figure 14B As shown, the central region CA can have a rectangular structure, such as a square structure, but is not limited to this.

[0214] Reflective regions RA1, RA2, RA3, and RA4 are located between the central region CA and the edge regions EA1, EA2, EA3, and EA4. Reflective regions RA1, RA2, RA3, and RA4 may not be directly adjacent to each other. Figure 9 The solder pattern is SDP contact. Within the reflective regions RA1, RA2, RA3, and RA4, the upper surface of the first electrode CE1 can be formed by a second conductive layer CE1b. Since the third conductive layer CE1c and the fourth conductive layer CE1d constituting the first electrode CE1 are removed from the reflective regions RA1, RA2, RA3, and RA4, the second conductive layer CE1b, located below the third conductive layer CE1c and the fourth conductive layer CE1d, can be exposed on the upper surface of the reflective regions RA1, RA2, RA3, and RA4. For example, the second conductive layer CE1b, which has good reflection efficiency and can be used as a reflector, can form the upper surface of the first electrode CE1 within the reflective regions RA1, RA2, RA3, and RA4.

[0215] In this case, according to various embodiments, the widths of the reflective regions RA1, RA2, RA3, and RA4 can be configured to be different from each other in the sub-pixels. For example, according to... Figure 11A and Figure 11B In the embodiment, the width of the first reflective region RA1 of the sub-pixel is relatively minimal, according to Figure 12A and Figure 12B In another embodiment, the width of the second reflective region RA2 of the sub-pixel is greater than the width of the first reflective region RA1, according to Figure 13A and Figure 13B In another embodiment, the width of the third reflective region RA3 of the sub-pixel can be greater than the width of the second reflective region RA2, according to Figure 14A and Figure 14B In another embodiment, the width of the fourth reflective region RA4 of the sub-pixel can be greater than the width of the third reflective region RA3.

[0216] Therefore, according to Figure 12A and Figure 12B In another embodiment, the sub-pixels can have a higher density than those according to... Figure 11A and Figure 11B The embodiment has better sub-pixel reflection efficiency, according to Figure 13A and Figure 13B In another embodiment, the sub-pixels can have a higher density than those according to... Figure 12A and Figure 12B Another embodiment has better sub-pixel reflection efficiency, and according to Figure 14A and Figure 14B In another embodiment, the sub-pixels can have a higher density than those according to... Figure 13A and Figure 13B Another embodiment shows that the subpixels have better reflection efficiency.

[0217] like Figure 11B , Figure 12B , Figure 13B and Figure 14B As shown, the reflective regions RA1, RA2, RA3, and RA4 can have a rectangular frame structure while surrounding the central region CA, such as a square frame structure, but are not limited to this.

[0218] Refer to the above Figure 9 The reflective regions RA1, RA2, RA3, and RA4 can be covered by the passivation layer 116.

[0219] Edge regions EA1, EA2, EA3, and EA4 are areas located outside the reflection regions RA1, RA2, RA3, and RA4. Edge regions EA1, EA2, EA3, and EA4 may not be adjacent to... Figure 9 The solder pattern is an SDP contact. Within the edge regions EA1, EA2, EA3, and EA4, the upper surface of the first electrode CE1 can be formed by a fourth conductive layer CE1d. For example, the fourth conductive layer CE1d, comprising a transparent conductive oxide layer with corrosion and acid resistance, can form the upper surface of the first electrode CE1 within the edge regions EA1, EA2, EA3, and EA4. Within the edge regions EA1, EA2, EA3, and EA4, the upper surface of the first electrode CE1 can be formed by the same material layer (e.g., the same fourth conductive layer CE1d) as the upper surface of the first electrode CE1 within the central region CA.

[0220] In this case, the widths of edge regions EA1, EA2, EA3, and EA4 can be configured to be different from each other in the sub-pixels of various embodiments. The widths of edge regions EA1, EA2, EA3, and EA4 in the sub-pixels of various embodiments can be the opposite of the widths of reflective regions RA1, RA2, RA3, and RA4 in the sub-pixels of various embodiments. For example, according to... Figure 11A and Figure 11B In the embodiment, the width of the first edge region EA1 of the sub-pixel is relatively the largest, according to Figure 12A and Figure 12B In another embodiment, the width of the second edge region EA2 of the sub-pixel is smaller than the width of the first edge region EA1, according to Figure 13A and Figure 13B In another embodiment, the width of the third edge region EA3 of the sub-pixel is smaller than the width of the second edge region EA2, and according to Figure 14A and Figure 14B In another embodiment, the width of the fourth edge region EA4 of the sub-pixel can be smaller than the width of the third edge region EA3.

[0221] like Figure 11B , Figure 12B , Figure 13B and Figure 14B As shown, the edge regions EA1, EA2, EA3, and EA4 may include, but are not limited to, a rectangular frame structure surrounding the reflection regions RA1, RA2, RA3, and RA4.

[0222] The edge regions EA1, EA2, EA3, and EA4 of the first electrode CE1 can extend through the end of the embankment BNK to connect to the signal line TL. The signal line TL can be integrally formed with the edge regions EA1, EA2, EA3, and EA4 of the first electrode CE1. Therefore, the signal line TL may include, but is not limited to, a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d.

[0223] Refer to the above Figure 9 The edge regions EA1, EA2, EA3, and EA4 can be covered by the passivation layer 116.

[0224] Figure 15 An embodiment of the present disclosure is shown with configurations. Figure 10A Multiple sub-pixels within the X region (e.g., within the region near the first boundary line D1 between the first transfer region and the second transfer region).

[0225] from Figure 15 As can be seen, for example, based on the first boundary line D1 between the first transfer area and the second transfer area, the first display area AA1 is set on the left and the second display area AA2 is set on the right.

[0226] Furthermore, a third display area AA3 is disposed between the first display area AA1 and the second display area AA2. A portion of the third display area AA3 (e.g., the left side area) may be disposed to the left of the first boundary line D1, and the remaining portion of the third display area AA3 (e.g., the right side area) may be disposed to the right of the first boundary line D1.

[0227] Therefore, the first transfer process can transfer multiple light-emitting elements of multiple sub-pixels to a portion of the first display area AA1 and the third display area AA3 corresponding to the first transfer area. Furthermore, the second transfer process can transfer the remaining areas of the second display area AA2 and the third display area AA3 corresponding to the second transfer area.

[0228] For simplicity, a sub-pixel with a 4×8 matrix structure of first row R1 to fourth row R4 and first column C1 to eighth column C8 is shown. In this case, the first display area AA1 includes sub-pixels with a 4×2 matrix structure of first row R1 to fourth row R4 and first column C1 to second column C2, the second display area AA2 includes sub-pixels with a 4×2 matrix structure of first row R1 to fourth row R4 and seventh column C7 to eighth column C8, and the third display area AA3 includes sub-pixels with a 4×4 matrix structure of first row R1 to fourth row R4 and third column C3 to sixth column C6. In this case, the matrix structure of the sub-pixels constituting the third display area AA3 can be changed differently. For example, the number of columns C3 to C6 constituting the third display area AA3 can be changed differently.

[0229] A first electrode CE1 having a reflective area of ​​the same width can be disposed in all sub-pixels of a plurality of sub-pixels within the first display area AA1. For example, a first electrode CE1 having a reflective area of ​​the middle width among a plurality of widths applied to the entire display area can be disposed in a plurality of sub-pixels within the first display area AA1. For example, when the reflective area of ​​a plurality of widths applied to the entire display area is composed of the aforementioned first reflective area RA1, second reflective area RA2, third reflective area RA3, and fourth reflective area RA4, a first electrode CE1_RA3 having a third reflective area can be disposed in a plurality of sub-pixels within the first display area AA1. In some cases, a first electrode CE1_RA2 having a second reflective area can be disposed in a plurality of sub-pixels within the first display area AA1. For example, as shown in the accompanying drawings, a first electrode CE1_RA3 having a third reflective area can be disposed in all sub-pixels of a plurality of sub-pixels within the first display area AA1 having a 4×2 matrix structure of first row R1 to fourth row R4 and first column C1 to second column C2.

[0230] Similarly, a first electrode CE1 with a reflective area of ​​the same width can be provided in multiple sub-pixels within the second display area AA2. For example, similar to the first display area AA1, a first electrode CE1 with a reflective area of ​​the middle width among multiple widths applicable to the entire display area can be provided in multiple sub-pixels within the second display area AA2. For example, when the reflective area with multiple widths applicable to the entire display area is composed of the aforementioned first reflective area RA1, second reflective area RA2, third reflective area RA3, and fourth reflective area RA4, a first electrode CE1_RA3 with a third reflective area can be provided in multiple sub-pixels within the second display area AA2, as shown in the figure. In some cases, a first electrode CE1_RA2 with a second reflective area can be provided in multiple sub-pixels within the second display area AA2. For example, as shown in the figure, a first electrode CE1_RA3 with a third reflective area can be provided in all sub-pixels of multiple sub-pixels having a 4×2 matrix structure of first row R1 to fourth row R4 and seventh column C7 to eighth column C8.

[0231] First electrodes CE1 with reflective regions of different widths can be provided within multiple sub-pixels in the third display area AA3. For example, first electrodes CE1 with reflective regions of all widths applicable to the entire display area can be provided in multiple sub-pixels in the third display area AA3. Specifically, first electrodes CE1 with the smallest to the largest reflective regions can be provided in multiple sub-pixels in the third display area AA3. For example, when the reflective regions with multiple widths applicable to the entire display area are composed of the aforementioned first reflective region RA1, second reflective region RA2, third reflective region RA3, and fourth reflective region RA4, as shown in the figure, first electrodes CE1_RA1 with first reflective regions, first electrodes CE1_RA2 with second reflective regions, first electrodes CE1_RA3 with third reflective regions, and first electrodes CE1_RA4 with fourth reflective regions can be provided in multiple sub-pixels in the third display area AA3. Although not shown, the third display area AA3 may additionally include first electrodes with fifth reflective regions larger than the fourth reflective region RA4, first electrodes with sixth reflective regions larger than the fifth reflective region, etc.

[0232] In odd-numbered rows R1 and R3, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from column C3 to column C6, and in even-numbered rows R2 and R4, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from column C3 to column C6. For example, in odd-numbered rows R1 and R3, a first electrode CE1_RA1 having a first reflective region, a first electrode CE1_RA2 having a second reflective region, a first electrode CE1_RA3 having a third reflective region, and a first electrode CE1_RA4 having a fourth reflective region are sequentially disposed across multiple sub-pixels from column C3 to column C6. In even-numbered rows R2 and R4, a first electrode CE1_RA4 having a fourth reflective region, a first electrode CE1_RA3 having a third reflective region, a first electrode CE1_RA2 having a second reflective region, and a first electrode CE1_RA1 having a first reflective region can be sequentially disposed across multiple sub-pixels from column C3 to column C6.

[0233] In some cases, in odd-numbered rows R1 and R3, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from the third column C3 to the sixth column C6, and in even-numbered rows R2 and R4, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from the third column C3 to the sixth column C6.

[0234] On the other hand, the main light-emitting devices (EDs) are located in odd-numbered rows R1 and R3, and redundant EDs are located in even-numbered rows R2 and R4, so that a sub-pixel can be formed by a combination of the two rows. In this case, in the odd-numbered rows R1 and R3 where the main light-emitting devices (EDs) are located, the width of the reflective area gradually increases or decreases as the column number (C3 to C6) increases. Conversely, in the even-numbered rows R2 and R4 where redundant EDs are located, the first electrode can be configured such that the width of the reflective area gradually decreases or increases as the column number (C3 to C6) increases.

[0235] As described above, according to the configuration of this disclosure, within the third display area AA3 including the first boundary line D1 between the first transfer area and the second transfer area, the first electrode can be configured such that the width of the reflective area gradually increases in odd or even rows, and the first electrode can be configured such that the width of the reflective area gradually decreases in even or odd rows. Therefore, the reflectivity of the first electrode is distributed differently among the multiple sub-pixels within the third display area AA3. Even if there are differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices between the first and second transfer areas, the problem of spots appearing near the first boundary line D1 between the first and second transfer areas can be solved or reduced.

[0236] Figure 16 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the X region (e.g., in the region near the first boundary line D1 between the first transfer region and the second transfer region).

[0237] Based on the above Figure 15 Within the third display area AA3, which includes the first boundary line D1 between the first transfer area and the second transfer area, the first electrode is configured such that the width of the reflective area gradually increases in odd-numbered rows as the column number (C3 to C6) increases, and the width of the reflective area gradually decreases in even-numbered rows as the column number (C3 to C6) increases; or the first electrode is configured such that the width of the reflective area gradually decreases in odd-numbered rows as the column number (C3 to C6) increases, and the width of the reflective area gradually increases in even-numbered rows as the column number (C3 to C6) increases.

[0238] On the other hand, according to Figure 16 Within the third display area AA3, which includes the first boundary line D1 between the first and second transfer areas, the first electrode can be configured such that the width of the reflective area gradually increases with increasing column number (C3 to C6) in adjacent rows (e.g., in the first row R1 and the second row R2), and the first electrode can be configured such that the width of the reflective area gradually decreases with increasing column number (C3 to C6) in adjacent rows (e.g., in the third row R3 and the fourth row R4). Alternatively, within the third display area AA3, which includes the first boundary line D1 between the first and second transfer areas, the first electrode can be configured such that the width of the reflective area gradually decreases with increasing column number (C3 to C6) in adjacent rows (e.g., in the first row R1 and the second row R2), and the first electrode can be configured such that the width of the reflective area gradually increases with increasing column number (C3 to C6) in other adjacent rows (e.g., in the third row R3 and the fourth row R4).

[0239] The main light-emitting devices (EDs) are placed in the odd-numbered rows R1 and R3, and the redundant light-emitting devices (EDs) are placed in the even-numbered rows R2 and R4, so that a sub-pixel can be composed of a combination of two rows.

[0240] In this case, the first electrode can be configured such that the width of the reflective region gradually increases or decreases in the adjacent rows R1 and R2 where the main light-emitting device ED and the redundant light-emitting device ED are provided, as the column number (C3 to C6) increases, and the first electrode can be configured such that the width of the reflective region gradually decreases or increases in the other adjacent rows R3 and R4 where the main light-emitting device ED and the redundant light-emitting device ED are provided, as the column number (C3 to C6) increases.

[0241] As described above, according to another configuration of this disclosure, within the third display area AA3 including the first boundary line D1 between the first transfer area and the second transfer area, the first electrode can be configured such that the width of the reflective area gradually increases or decreases with increasing column number in adjacent rows, and the first electrode can be configured such that the width of the reflective area gradually decreases or increases with increasing column number in other adjacent rows. Therefore, the reflectivity of the first electrode is distributed differently among multiple sub-pixels within the third display area AA3, and even if there are differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices between the first transfer area and the second transfer area, the problem of spots appearing near the first boundary line D1 between the first transfer area and the second transfer area can be solved or reduced.

[0242] Figure 17 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Y region (e.g., in the region near the second boundary line D2 between the first and third transfer regions).

[0243] from Figure 17 As can be seen, for example, based on the second boundary line D2 between the first transfer area and the third transfer area, the fourth display area AA4 is set on the upper side, and the fifth display area AA5 is set on the lower side.

[0244] Furthermore, the sixth display area AA6 is located between the fourth display area AA4 and the fifth display area AA5. A portion of the sixth display area AA6 (e.g., the upper portion) may be located above the second boundary line D2, and the remaining portion of the sixth display area AA6 (e.g., the lower portion) may be located below the second boundary line D2.

[0245] Therefore, the first transfer process can transfer multiple light-emitting devices of multiple sub-pixels to a portion of the fourth display area AA4 and the sixth display area AA6, which correspond to the first transfer area. Furthermore, the third transfer process can transfer the remaining areas of the fifth display area AA5 and the sixth display area AA6, which correspond to the third transfer area.

[0246] For simplicity, a sub-pixel with an 8×4 matrix structure of first row R1 to eighth row R8 and first column C1 to fourth column C4 is shown. In this case, the fourth display area AA4 has a 2×4 matrix structure of sub-pixels of first row R1 to second row R2 and first column C1 to fourth column C4, the fifth display area AA5 has a 2×4 matrix structure of sub-pixels of seventh row R7 to eighth row R8 and first column C1 to fourth column C4, and the sixth display area AA6 has a 4×4 matrix structure of sub-pixels of third row R3 to sixth row R6 and first column C1 to fourth column C4. In this case, the matrix structure of the sub-pixels constituting the sixth display area AA6 can be changed differently. For example, the number of rows R3 to R6 constituting the sixth display area AA6 can be changed differently.

[0247] A first electrode CE1 with a reflective area of ​​equal width can be disposed in all sub-pixels of a plurality of sub-pixels within the fourth display area AA4. For example, a first electrode CE1 with a reflective area of ​​the middle width among a plurality of widths applied to the entire display area can be disposed in a plurality of sub-pixels within the fourth display area AA4. For example, when the reflective area of ​​a plurality of widths applied to the entire display area is composed of the aforementioned first reflective area RA1, second reflective area RA2, third reflective area RA3, and fourth reflective area RA4, a first electrode CE1_RA3 with a third reflective area can be disposed in a plurality of sub-pixels within the fourth display area AA4. In some cases, a first electrode CE1_RA2 with a second reflective area can be disposed in a plurality of sub-pixels within the fourth display area AA4. For example, as shown in the figure, a first electrode CE1_RA3 with a third reflective area can be disposed in all sub-pixels of a plurality of sub-pixels within the fourth display area AA4 having a 2×4 matrix structure of first row R1 to second row R2 and first column C1 to fourth column C4.

[0248] Similarly, a first electrode CE1 with a reflective area of ​​the same width can be disposed in multiple sub-pixels within the fifth display area AA5. For example, similar to the fourth display area AA4, a first electrode CE1 with a reflective area of ​​the middle width among multiple widths applicable to the entire display area can be disposed in multiple sub-pixels within the fifth display area AA5. For example, when the reflective area with multiple widths applicable to the entire display area is composed of the aforementioned first reflective area RA1, second reflective area RA2, third reflective area RA3, and fourth reflective area RA4, a first electrode CE1_RA3 with a third reflective area can be disposed in multiple sub-pixels within the fifth display area AA5, as shown in the figure. In some cases, a first electrode CE1_RA2 with a second reflective area can be disposed in multiple sub-pixels within the fifth display area AA5. For example, as shown in the figure, a first electrode CE1_RA3 with a third reflective area can be disposed in all sub-pixels of multiple sub-pixels having a 2×4 matrix structure with seventh row R7 to eighth row R8 and first column C1 to fourth column C4.

[0249] First electrodes CE1 with reflective regions of different widths can be disposed in multiple sub-pixels within the sixth display area AA6. For example, first electrodes CE1 with reflective regions of all widths applicable to the entire display area can be disposed in multiple sub-pixels within the sixth display area AA6. Specifically, first electrodes CE1 with the smallest reflective region to the first electrode CE1 with the largest reflective region can be disposed in multiple sub-pixels within the sixth display area AA6. For example, when the reflective regions with multiple widths applicable to the entire display area are composed of the aforementioned first reflective region RA1, second reflective region RA2, third reflective region RA3, and fourth reflective region RA4, as shown in the figure, first electrodes CE1_RA1 with the first reflective region, first electrodes CE1_RA2 with the second reflective region, first electrodes CE1_RA3 with the third reflective region, and first electrodes CE1_RA4 with the fourth reflective region can be disposed in multiple sub-pixels within the sixth display area AA6. Although not shown, the sixth display area AA6 may additionally include first electrodes with a fifth reflective region larger than the fourth reflective region RA4, first electrodes with a sixth reflective region larger than the fifth reflective region, etc.

[0250] In odd-numbered columns C1 and C3, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from the third row R3 to the sixth row R6, and in even-numbered columns C2 and C4, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from the third row R3 to the sixth row R6. For example, in odd-numbered columns C1 and C3, the first electrode CE1_RA4 with a fourth reflective region, the first electrode CE1_RA3 with a third reflective region, the first electrode CE1_RA2 with a second reflective region, and the first electrode CE1_RA1 with a first reflective region are sequentially disposed across multiple sub-pixels from the third row R3 to the sixth row R6. In even-numbered columns C2 and C4, the first electrode CE1_RA1 with a first reflective region, the first electrode CE1_RA2 with a second reflective region, the first electrode CE1_RA3 with a third reflective region, and the first electrode CE1_RA4 with a fourth reflective region can be sequentially disposed across multiple sub-pixels from the third row R3 to the sixth row R6.

[0251] In some cases, in odd-numbered columns C1 and C3, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from the third row R3 to the sixth row R6, and in even-numbered columns C2 and C4, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from the third row R3 to the sixth row R6.

[0252] As described above, according to the configuration of this specification, within the sixth display area AA6, which includes the second boundary line D2 between the first and third transfer areas, in odd or even columns, the first electrode can be configured such that the width of the reflective area gradually increases with the row number (R3 to R6), and in even or odd columns, the width of the reflective area gradually decreases with the row number (R3 to R6). Therefore, the reflectivity of the first electrode is distributed differently among the multiple sub-pixels within the sixth display area AA6. Even if there are differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices between the first and third transfer areas, the problem of spots appearing near the second boundary line D2 between the first and third transfer areas can be solved or reduced.

[0253] Figure 18 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Y region (e.g., within the region near the second boundary line between the first and third transfer regions).

[0254] According to the above Figure 17Within the sixth display area AA6, which includes the second boundary line D2 between the first and third transfer areas, the first electrode is configured such that the width of the reflective area gradually increases in odd-numbered columns as the row number increases, or the first electrode is configured such that the width of the reflective area gradually decreases in even-numbered columns as the row number increases, or the first electrode is configured such that the width of the reflective area gradually decreases in odd-numbered columns as the row number increases, and the width of the reflective area gradually increases in even-numbered columns as the row number increases.

[0255] On the other hand, according to Figure 18 Within the sixth display area AA6, which includes the second boundary line D2 between the first and third transfer areas, the first electrode can be configured such that the width of the reflective area gradually decreases in adjacent columns (e.g., in the first column C1 and the second column C2) as the row number (R3 to R6) increases, and the first electrode can also be configured such that the width of the reflective area gradually increases in adjacent columns (e.g., in the third column C3 and the fourth column C4) as the row number (R3 to R6) increases. Alternatively, within the sixth display area AA6, which includes the second boundary line D2 between the first and third transfer areas, the first electrode can be configured such that the width of the reflective area gradually increases in adjacent columns (e.g., in the first column C1 and the second column C2) as the row number (R3 to R6) increases, and the first electrode can also be configured such that the width of the reflective area gradually decreases in other adjacent columns (e.g., in the third column C3 and the fourth column C4) as the row number (R3 to R6) increases.

[0256] As described above, according to another configuration of this disclosure, within the sixth display area AA6, which includes the second boundary line D2 between the first and third transfer areas, the first electrode can be configured such that the width of the reflective area gradually increases or decreases with increasing row number in adjacent columns, and the first electrode can also be configured such that the width of the reflective area gradually decreases or increases with increasing row number in other adjacent columns. Therefore, the reflectivity of the first electrode is distributed differently among the multiple sub-pixels within the sixth display area AA6. Even if there are differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices between the first and third transfer areas, the problem of spots appearing near the second boundary line D2 between the first and third transfer areas can be solved or reduced.

[0257] Figure 19 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Z region (e.g., in the vicinity of the intersection of the first boundary line D1 between the first and second transfer regions and the second boundary line D2 between the first and third transfer regions).

[0258] from Figure 19 As can be seen, for example, based on the first boundary line D1 between the first and second transfer areas and between the third and fourth transfer areas, the seventh display area AA7 is located on the left, and the eighth display area AA8 is located on the right. In this case, a portion of the seventh display area AA7 (e.g., the upper portion) can be located within the first transfer area, and the remaining portion of the seventh display area AA7 (e.g., the lower portion) can be located within the third transfer area. Similarly, a portion of the eighth display area AA8 (e.g., the upper portion) can be located within the second transfer area, and the remaining portion of the eighth display area AA8 (e.g., the lower portion) can be located within the fourth transfer area.

[0259] Furthermore, the ninth display area AA9 is positioned between the seventh display area AA7 and the eighth display area AA8. A portion of the ninth display area AA9 (e.g., the left side) can be positioned to the left of the first boundary line D1, and the remaining portion (e.g., the right side) can be positioned to the right of the first boundary line D1. In this case, the upper left portion of the ninth display area AA9 is positioned within the first transfer area, the upper right portion within the ninth display area AA9 is positioned within the second transfer area, the lower left portion of the ninth display area AA9 can be positioned within the third transfer area, and the lower right portion of the ninth display area AA9 can be positioned within the fourth transfer area.

[0260] Therefore, through the first transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the upper region of the seventh display area AA7 and the upper left region of the ninth display area AA9, which correspond to the first transfer area. Furthermore, through the second transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the upper region of the eighth display area AA8 and the upper right region of the ninth display area AA9, which correspond to the second transfer area. Furthermore, through the third transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the lower region of the seventh display area AA7 and the lower left region of the ninth display area AA9, which correspond to the third transfer area. Furthermore, through the fourth transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the lower region of the eighth display area AA8 and the lower right region of the ninth display area AA9, which correspond to the fourth transfer area.

[0261] For simplicity, a sub-pixel with an 8×8 matrix structure of first row R1 to eighth row R8 and first column C1 to eighth column C8 is shown. In this case, the seventh display area AA7 may include sub-pixels with an 8×2 matrix structure of first row R1 to eighth row R8 and first column C1 to second column C2, the eighth display area AA8 may include sub-pixels with an 8×2 matrix structure of first row R1 to eighth row R8 and seventh column C7 to eighth column C8, and the ninth display area AA9 may include sub-pixels with an 8×4 matrix structure of first row R1 to eighth row R8 and third column C3 to sixth column C6. In this case, the matrix structure of the sub-pixels constituting the ninth display area AA9 can be changed differently. For example, the number of columns C3 to C6 constituting the ninth display area AA9 can be changed differently.

[0262] A first electrode CE1 having a reflective area of ​​the same width can be disposed in all sub-pixels of a plurality of sub-pixels within the seventh display area AA7. For example, a first electrode CE1 having a reflective area of ​​the middle width among a plurality of widths applied to the entire display area can be disposed in a plurality of sub-pixels within the seventh display area AA7. For example, when the reflective area of ​​a plurality of widths applied to the entire display area is composed of the aforementioned first reflective area RA1, second reflective area RA2, third reflective area RA3, and fourth reflective area RA4, a first electrode CE1_RA3 having a third reflective area can be disposed in a plurality of sub-pixels within the seventh display area AA7. In some cases, a first electrode CE1_RA2 having a second reflective area can be disposed in a plurality of sub-pixels within the seventh display area AA7. For example, as shown in the accompanying drawings, a first electrode CE1_RA3 having a third reflective area can be disposed in all sub-pixels of a plurality of sub-pixels within the seventh display area AA7 having an 8×2 matrix structure of first row R1 to eighth row R8 and first column C1 to second column C2.

[0263] Similarly, a first electrode CE1 having a reflective area of ​​the same width can be disposed in multiple sub-pixels within the eighth display area AA8. For example, similar to the seventh display area AA7, a first electrode CE1 having a reflective area of ​​the middle width among multiple widths applicable to the entire display area can be disposed in multiple sub-pixels within the eighth display area AA8. For example, when the reflective area having multiple widths applicable to the entire display area is composed of the aforementioned first reflective area RA1, second reflective area RA2, third reflective area RA3, and fourth reflective area RA4, a first electrode CE1_RA3 having a third reflective area can be disposed in multiple sub-pixels within the eighth display area AA8, as shown in the attached figure. In some cases, a first electrode CE1_RA2 having a second reflective area can be disposed in multiple sub-pixels within the eighth display area AA8. For example, as shown in the attached figure, a first electrode CE1_RA3 having a third reflective area can be disposed in all sub-pixels of multiple sub-pixels having an 8×2 matrix structure of first row R1 to eighth row R8 and seventh column C7 to eighth column C8.

[0264] First electrodes CE1 with different widths of reflective regions can be disposed in multiple sub-pixels within the ninth display area AA9. For example, first electrodes CE1 with reflective regions of all sizes across multiple widths applied to the entire display area can be disposed in multiple sub-pixels within the ninth display area AA9. Specifically, first electrodes CE1 with the smallest to the largest reflective regions can be disposed in multiple sub-pixels within the ninth display area AA9. For example, when the reflective regions with multiple widths applied to the entire display area are composed of the aforementioned first reflective region RA1, second reflective region RA2, third reflective region RA3, and fourth reflective region RA4, as shown in the accompanying drawings, first electrodes CE1_RA1 with first reflective regions, first electrodes CE1_RA2 with second reflective regions, first electrodes CE1_RA3 with third reflective regions, and first electrodes CE1_RA4 with fourth reflective regions can be disposed in multiple sub-pixels within the ninth display area AA9. Although not shown, the ninth display area AA9 may additionally include first electrodes with fifth reflective regions larger than the fourth reflective region RA4, first electrodes with sixth reflective regions larger than the fifth reflective region, etc.

[0265] In odd-numbered rows R1, R3, R5, and R7, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from column C3 to column C6, and in even-numbered rows R2, R4, R6, and R8, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from column C3 to column C6. For example, in odd-numbered rows R1, R3, R5, and R7, a first electrode CE1_RA1 having a first reflective region, a first electrode CE1_RA2 having a second reflective region, a first electrode CE1_RA3 having a third reflective region, and a first electrode CE1_RA4 having a fourth reflective region are sequentially disposed across multiple sub-pixels from column C3 to column C6. In even-numbered rows R2, R4, R6, and R8, the first electrode CE1_RA4 with a fourth reflective region, the first electrode CE1_RA3 with a third reflective region, the first electrode CE1_RA2 with a second reflective region, and the first electrode CE1_RA1 with a first reflective region can be sequentially set in multiple sub-pixels from the third column C3 to the sixth column C6.

[0266] In some cases, in odd-numbered rows R1, R3, R5, and R7, the first electrode can be configured such that the width of the reflective region gradually decreases among multiple sub-pixels from the third column C3 to the sixth column C6, and in even-numbered rows R2, R4, R6, and R8, the first electrode can be configured such that the width of the reflective region gradually increases among multiple sub-pixels from the third column C3 to the sixth column C6.

[0267] On the other hand, the main light-emitting devices (EDs) are arranged in odd-numbered rows R1, R3, R5, and R7, and the redundant light-emitting devices (EDs) are arranged in even-numbered rows R2, R4, R6, and R8, so that a sub-pixel can be composed of a combination of two rows. In this case, in the odd-numbered rows R1, R3, R5, and R7 where the main light-emitting devices (EDs) are arranged, the first electrode can be configured such that the width of the reflective area gradually increases or decreases as the column number (C3 to C6) increases. Conversely, in the even-numbered rows R2, R4, R6, and R8 where the redundant light-emitting devices (EDs) are arranged, the width of the reflective area gradually decreases or increases as the column number (C3 to C6) increases.

[0268] As described above, according to another configuration of this disclosure, within the ninth display area AA9, including the region where the first boundary line D1 intersects with the second boundary line D2, the first electrode can be configured such that the width of the reflective area gradually increases with increasing column number in odd or even rows, and the first electrode can be configured such that the width of the reflective area gradually decreases with increasing column number in even or odd rows. Therefore, the reflectivity of the first electrode is distributed differently among the multiple sub-pixels within the ninth display area AA9, and even if differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices occur between the first transfer area and the fourth transfer area, the problem of spots appearing near the first boundary line D1 and the second boundary line D2 can be solved or reduced.

[0269] Figure 20 A setting according to another embodiment of the present disclosure is shown. Figure 10A Multiple sub-pixels within the Z region (e.g., in the vicinity of the intersection of the first boundary line between the first and second transfer regions and the second boundary line between the first and third transfer regions).

[0270] from Figure 20 As can be seen, for example, based on the second boundary line D2 between the first and third transfer areas and between the second and fourth transfer areas, the seventh display area AA7 is positioned on the upper side, and the eighth display area AA8 is positioned on the lower side. In this case, a portion of the seventh display area AA7 (e.g., the left side) can be positioned within the first transfer area, and the remaining portion of the seventh display area AA7 (e.g., the right side) can be positioned within the second transfer area. Similarly, a portion of the eighth display area AA8 (e.g., the left side) can be positioned within the third transfer area, and the remaining portion of the eighth display area AA8 (e.g., the right side) can be positioned within the fourth transfer area.

[0271] Furthermore, the ninth display area AA9 is positioned between the seventh display area AA7 and the eighth display area AA8. A portion of the ninth display area AA9 (e.g., the upper region) may be positioned above the second boundary line D2, and the remaining portion (e.g., the lower region) may be positioned below the second boundary line D2. In this case, the upper left region of the ninth display area AA9 is positioned within the first transfer area, the upper right region of the ninth display area AA9 is positioned within the second transfer area, the lower left region of the ninth display area AA9 may be positioned within the third transfer area, and the lower right region of the ninth display area AA9 may be positioned within the fourth transfer area.

[0272] Therefore, through the first transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the left side of the seventh display area AA7 and the upper left side of the ninth display area AA9, corresponding to the first transfer area. Furthermore, through the second transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the right side of the seventh display area AA7 and the upper right side of the ninth display area AA9, corresponding to the second transfer area. Furthermore, through the third transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the left side of the eighth display area AA8 and the lower left side of the ninth display area AA9, corresponding to the third transfer area. Furthermore, through the fourth transfer process, multiple light-emitting devices of multiple sub-pixels are transferred to the right side of the eighth display area AA8 and the lower right side of the ninth display area AA9, corresponding to the fourth transfer area.

[0273] For simplicity, a sub-pixel with an 8×8 matrix structure of first row R1 to eighth row R8 and first column C1 to eighth column C8 is shown. In this case, the seventh display area AA7 has a 2×8 matrix structure of first row R1 to second row R2 and first column C1 to eighth column C8, the eighth display area AA8 includes a 2×8 matrix structure of seventh row R7 to eighth row R8 and first column C1 to eighth column C8, and the ninth display area AA9 includes a 4×8 matrix structure of third row R3 to sixth row R6 and first column C1 to eighth column C8. In this case, the matrix structure of the sub-pixels constituting the ninth display area AA9 can be changed differently. For example, the number of rows R3 to R6 constituting the ninth display area AA9 can be changed differently.

[0274] A first electrode CE1 having a reflective area of ​​the same width can be disposed in all sub-pixels of a plurality of sub-pixels within the seventh display area AA7. For example, a first electrode CE1 having a reflective area of ​​the middle width among a plurality of widths applied to the entire display area can be disposed in a plurality of sub-pixels within the seventh display area AA7. For example, a first electrode CE1_RA3 having a third reflective area or a first electrode CE1_RA2 having a second reflective area can be disposed in a plurality of sub-pixels within the seventh display area AA7. For example, as shown in the figure, a first electrode CE1_RA3 having a third reflective area can be disposed in all sub-pixels of a plurality of sub-pixels within the seventh display area AA7 having a 2×8 matrix structure of first row R1 to second row R2 and first column C1 to eighth column C8.

[0275] Similarly, a first electrode CE1 having a reflective area of ​​the same width can be disposed in multiple sub-pixels within the eighth display area AA8. For example, similar to the seventh display area AA7, a first electrode CE1 having a reflective area of ​​intermediate width among multiple widths applied to the entire display area can be disposed in multiple sub-pixels within the eighth display area AA8. For example, a first electrode CE1_RA3 having a third reflective area or a first electrode CE1_RA2 having a second reflective area can be disposed in multiple sub-pixels within the eighth display area AA8. For example, as shown in the accompanying drawings, a first electrode CE1_RA3 having a third reflective area can be disposed in all sub-pixels within multiple sub-pixels of the eighth display area AA8 having a 2×8 matrix structure of seventh row R7 to eighth row R8 and first column C1 to eighth column C8.

[0276] First electrodes CE1 with reflective regions of different widths can be disposed in multiple sub-pixels within the ninth display area AA9. For example, first electrodes CE1 with reflective regions of all widths across multiple widths applied to the entire display area can be disposed in multiple sub-pixels within the ninth display area AA9. Specifically, first electrodes CE1 with the smallest to the largest reflective regions can be disposed in multiple sub-pixels within the ninth display area AA9. For example, first electrodes CE1_RA1 with a first reflective region, CE1_RA2 with a second reflective region, CE1_RA3 with a third reflective region, and CE1_RA4 with a fourth reflective region can be disposed in multiple sub-pixels within the ninth display area AA9.

[0277] In odd-numbered columns C1, C3, C5, and C7, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from the third row R3 to the sixth row R6, and in even-numbered columns C2, C4, C6, and C8, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from the third row R3 to the sixth row R6. For example, in odd-numbered columns C1, C3, C5, and C7, a first electrode CE1_RA4 with a fourth reflective region, a first electrode CE1_RA3 with a third reflective region, a first electrode CE1_RA2 with a second reflective region, and a first electrode CE1_RA1 with a first reflective region are sequentially disposed across multiple sub-pixels from the third row R3 to the sixth row R6. In even-numbered columns C2, C4, C6, and C8, a first electrode CE1_RA1 having a first reflective region, a first electrode CE1_RA2 having a second reflective region, a first electrode CE1_RA3 having a third reflective region, and a first electrode CE1_RA4 having a fourth reflective region can be sequentially set in multiple sub-pixels from the third row R3 to the sixth row R6.

[0278] In some cases, in odd-numbered columns C1, C3, C5, and C7, the first electrode can be configured such that the width of the reflective region gradually increases across multiple sub-pixels from the third row R3 to the sixth row R6, and in even-numbered columns C2, C4, C6, and C8, the first electrode can be configured such that the width of the reflective region gradually decreases across multiple sub-pixels from the third row R3 to the sixth row R6.

[0279] As described above, according to another configuration of this disclosure, within the ninth display area AA9, including the region where the first boundary line D1 intersects with the second boundary line D2, the first electrode can be configured such that the width of the reflective region gradually increases with increasing row number in either odd or even columns, and the width of the reflective region gradually decreases with increasing row number in either even or odd columns. Therefore, the reflectivity of the first electrode is distributed differently among the multiple sub-pixels within the ninth display area AA9. Even if differences in the presence or absence of transfer errors or differences in the characteristics of the light-emitting devices occur between the first transfer area and the fourth transfer area, the problem of spots appearing near the first boundary line D1 and the second boundary line D2 can be solved or reduced.

[0280] Figures 21 to 24 This is a view of a device that uses a display apparatus according to an embodiment of the present disclosure.

[0281] refer to Figures 21 to 24 The display device according to embodiments of this disclosure can be included in various devices or electronic devices. For example, various electronic devices may include, Figure 21 The wearable device 1100 shown is, for example Figure 22 The mobile device 1200 shown is, for example Figure 23 The laptop computer 1300 shown, and as shown Figure 24 The monitor or TV 1400 shown is an example, but the embodiments disclosed herein are not limited thereto.

[0282] Each of the wearable device 1100, mobile device 1200, laptop computer 1300, and monitor or TV 1400 may include housing units 1005, 1010, 1015, 1020, and display panel 100 and display device 1000 according to the above embodiments of the present disclosure.

[0283] For example, a display device according to one embodiment of this disclosure includes a mobile device, a video phone, a smartwatch, a phone watch, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a bending device, a sliding device, a variable device, an electronic notebook, an e-book, a portable multimedia player (PMP), a PDA (personal digital assistant), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation system, a vehicle display, a cinema display, a television, a wallpaper device, a signage device, a gaming device, a laptop computer, a monitor, a camera, a camcorder, or a home appliance.

[0284] It will be apparent to those skilled in the art that the present disclosure described above is not limited to the embodiments and drawings described herein, and that various substitutions, modifications, and variations can be made to the present disclosure without departing from the spirit or scope thereof. Therefore, the scope of the present disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the present disclosure.

Claims

1. A display device comprising: a substrate including a display area and a non-display area; a pixel driving circuit located within the display area on the substrate; an insulating layer located on the pixel driving circuit; a bank provided on the insulating layer in a plurality of sub-pixels including a first sub-pixel and a second sub-pixel; a first electrode provided on the bank and including a central area, a peripheral area, and a reflection area between the central area and the peripheral area; and a light emitting device provided on the first electrode and electrically connected to the first electrode, and overlapping the bank, wherein a width of the reflection area of the first electrode in the first sub-pixel is different from a width of the reflection area of the first electrode in the second sub-pixel. a width of the central area of the first electrode in the first sub-pixel is the same as a width of the central area of the first electrode in the second sub-pixel, 2. The display device according to claim 1, wherein wherein the width of the reflection area of the first electrode in the first sub-pixel is greater than the width of the reflection area of the first electrode in the second sub-pixel, and wherein a width of the peripheral area of the first electrode in the first sub-pixel is less than a width of the peripheral area of the first electrode in the second sub-pixel. the first electrode includes a plurality of conductive layers including a first conductive layer and a second conductive layer different from the first conductive layer, 3. The display device according to claim 1, wherein wherein upper surfaces of the central area and the peripheral area of the first electrode are formed by the same first conductive layer, and wherein an upper surface of the reflection area of the first electrode is formed by the second conductive layer. the first conductive layer is made of a transparent conductive oxide, and the second conductive layer is provided above the first conductive layer and made of a reflective material.

4. The display device according to claim 3, wherein the first electrode and the light emitting device are electrically connected to each other by a solder pattern, 5. The display device according to claim 1, wherein wherein the central area of the first electrode overlaps the solder pattern, and wherein the reflection area and the peripheral area of the first electrode do not overlap the solder pattern. the reflection area of the first electrode surrounds the central area of the first electrode, and the peripheral area of the first electrode surrounds the reflection area of the first electrode.

6. The display device according to claim 1, wherein 7.The display device of claim 1, further comprising a signal line provided on the insulating layer and electrically connecting the first electrode with the pixel driving circuit, and the peripheral area of the first electrode extends to the signal line and is connected to the signal line. wherein, 8.The display device of claim 1, further comprising a passivation layer on the first electrode, and the passivation layer covers the reflection area and the peripheral area of the first electrode. wherein 9.The display device of claim 1, further comprising: a second electrode provided on the light emitting device and electrically connected to the light emitting device; ​ a first optical layer provided below the second electrode and covering side surfaces of the light-emitting device and side surfaces of the bank; and a second optical layer in contact with side surfaces of the first optical layer.

10. The display device according to claim 9, further comprising: a black matrix over the second electrode; and and a third optical layer between the second electrode and the black matrix.

11. A display device comprising: a display region including a first display region, a second display region, and a third display region between the first display region and the second display region; a plurality of light-emitting devices provided in a plurality of subpixels having a matrix structure within the display region; and a plurality of first electrodes electrically connected to the plurality of light-emitting devices in the plurality of subpixels and including a central region, an edge region, and a reflection region between the central region and the edge region, wherein in the plurality of subpixels within the third display region, widths of the reflection regions of the plurality of first electrodes are different from each other.

12. The display device of claim 11, wherein, The widths of the reflection regions of the plurality of first electrodes in the plurality of subpixels within the first display region and the second display region are the same as each other.

13. The display device of claim 11, wherein, The plurality of first electrodes in the plurality of subpixels within the third display region include first electrodes of the reflection regions of all size widths from a first electrode of the reflection region of the smallest width to a first electrode of the reflection region of the largest width, which are applied to the plurality of widths of the entire display region.

14. The display device of claim 11, wherein, The widths of the reflection regions of the plurality of first electrodes in the plurality of subpixels within the third display region gradually increase or decrease as a row number or a column number of the matrix structure increases.

15. The display device of claim 14, wherein, The widths of the reflection regions of the plurality of first electrodes in the plurality of subpixels within the third display region gradually increase as the column number increases in odd-numbered rows and gradually decrease as the column number increases in even-numbered rows.

16. The display device of claim 14, wherein, The widths of the reflection regions of the plurality of first electrodes in the plurality of subpixels within the third display region gradually increase as the column number increases in two adjacent rows and gradually decrease as the column number increases in another two adjacent rows.

17. The display device of claim 14, wherein, The widths of the reflection regions of the plurality of first electrodes in the plurality of subpixels within the third display region gradually increase as the row number increases in odd-numbered columns and gradually decrease as the row number increases in even-numbered columns.

18. The display device of claim 14, wherein, The widths of the reflection regions of the plurality of first electrodes in the plurality of subpixels within the third display region gradually increase as the row number increases in two adjacent columns and gradually decrease as the row number increases in another two adjacent columns.

19. A display device comprising: a display area including a first display area, a second display area located right of the first display area, a third display area located between the first display area and the second display area, a fourth display area located left of the first display area, a fifth display area located below the fourth display area, and a sixth display area located between the fourth display area and the fifth display area; a plurality of light emitting devices located in a plurality of subpixels having a matrix structure within the display area; and a plurality of first electrodes electrically connected to the plurality of light emitting devices in the plurality of subpixels and including a central area, an edge area, and a reflection area between the central area and the edge area, wherein a width of the reflection area of the plurality of first electrodes in the plurality of subpixels within the third display area gradually increases or decreases as a column number of the matrix structure increases, and wherein a width of the reflection area of the plurality of first electrodes in the plurality of subpixels within the sixth display area gradually increases or decreases as a row number of the matrix structure increases.

20. The display device of claim 19, wherein, The width of the reflection area of the plurality of first electrodes in the plurality of subpixels within the first display area, the second display area, the fourth display area, and the fifth display area is the same.

Images