Display device

Abstract

A display apparatus is provided. The display device includes: a substrate in which a plurality of pixels including a plurality of sub-pixels are defined; a plurality of transistors disposed on the substrate; an insulating layer disposed on the substrate; an adhesive layer disposed on the insulating layer; and a plurality of light emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, in which the insulating layer includes a plurality of holes disposed in each of the plurality of pixels, the plurality of holes including a plurality of first holes disposed to overlap the plurality of light emitting diodes, a plurality of second holes disposed to overlap the plurality of light emitting diodes, and a plurality of third holes disposed to overlap the plurality of light emitting diodes. The plurality of second holes are disposed to surround the plurality of first holes on a plane, and the plurality of third holes include a hole disposed at the outermost periphery in the first direction among the plurality of holes.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0122679, filed on September 9, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more particularly to display devices using light-emitting diodes (LEDs). Background Technology

[0004] Display devices used for computer monitors, televisions, cellular phones, etc. include organic light-emitting display (OLED) devices that are self-emissive devices and liquid crystal display (LCD) devices that require a separate light source.

[0005] The applications of display devices are diversified, ranging from personal digital assistants to computer monitors and televisions, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Furthermore, display devices, including those using light-emitting diodes (LEDs), have recently attracted attention as next-generation display devices. Because LEDs are formed from inorganic materials rather than organic materials, they offer superior reliability, resulting in a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs feature fast illumination speed, excellent luminous efficiency, and strong shock resistance, leading to excellent stability and the ability to display high-brightness images. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display device having a reduced thickness deviation in the adhesive layer to which the light-emitting diodes are attached.

[0008] Another objective of this disclosure is to provide a display device in which the problem of over-transfer during the transfer process is improved to reduce manufacturing costs.

[0009] Another objective of this disclosure is to provide a display device in which the selectivity of light-emitting diode switching and non-switching is improved.

[0010] The purpose of this disclosure is not limited to the purposes mentioned above, and other purposes not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0011] According to an aspect of the disclosure, a display apparatus is provided. The display apparatus includes a substrate in which a plurality of pixels including a plurality of sub-pixels are defined, a plurality of transistors disposed on the substrate, an insulating layer disposed on the substrate, an adhesive layer disposed on the insulating layer, and a plurality of light emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes a plurality of holes disposed in each of the plurality of pixels, the plurality of holes including a plurality of first holes, a plurality of second holes, and a plurality of third holes, the plurality of first holes are disposed to overlap the plurality of light emitting diodes, the plurality of second holes are disposed to surround the plurality of first holes in a planar view, and the plurality of third holes include holes disposed at an outermost periphery among the plurality of holes in a first direction.

[0012] According to another aspect of the disclosure, a display apparatus is provided. The display apparatus includes a substrate in which a pixel including a plurality of sub-pixels is defined, an insulating layer disposed on the substrate, a plurality of reflective electrodes disposed on the insulating layer, an adhesive layer disposed on the plurality of reflective electrodes, and a plurality of light emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes a plurality of first holes overlapping the plurality of reflective electrodes, a plurality of second holes overlapping the plurality of reflective electrodes, and a plurality of third holes not overlapping the plurality of reflective electrodes.

[0013] Further details of example embodiments include those described in the detailed description and drawings.

[0014] According to the disclosure, the thickness of the adhesive layer is uniformized to optimize processing.

[0015] According to the disclosure, the pressure of the non-transfer region is reduced to suppress excessive transfer.

[0016] According to the disclosure, the selectivity of the transfer and non-transfer of the light emitting diodes is improved to reduce processing costs and product costs.

[0017] Effects according to the disclosure are not limited to those exemplified above, and more diverse effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other aspects, features, and other advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic view of a display apparatus according to an example embodiment of the disclosure;

[0020] Figure 2A is a partial cross-sectional view of a display apparatus according to an example embodiment of the disclosure;

[0021] Figure 2B is a perspective view of a tiled display apparatus according to an exemplary embodiment of the present disclosure;

[0022] Figure 3 is an enlarged plan view of a display apparatus according to an exemplary embodiment of the present disclosure;

[0023] Figure 4 is an enlarged plan view of a display apparatus according to an exemplary embodiment of the present disclosure;

[0024] Figure 5 is a cross-sectional view of the display apparatus taken along Figure 3 A-A' of FIG. 1;

[0025] Figure 6 is a cross-sectional view of the display apparatus taken along Figure 4 B-B' of FIG. 1;

[0026] Figure 7 is a cross-sectional view of the display apparatus taken along Figure 4 C-C' of FIG. 1;

[0027] Figures 8A to 8D is a process diagram for explaining a manufacturing method of a display apparatus according to an exemplary embodiment of the present disclosure; and

[0028] Figure 9 is an enlarged plan view of a display apparatus according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and a method for achieving the advantages and features will be apparent based on the exemplary embodiments described below in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein and will be implemented in various forms. The exemplary embodiments are provided by way of example only, so that one skilled in the art can fully understand the disclosure and the scope of the present disclosure.

[0030] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples and the present disclosure is not limited thereto. Throughout the specification, like drawing reference numerals generally refer to like elements. Furthermore, in the following description of the present disclosure, detailed descriptions of known related technologies can be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Unless the terms such as "include" and "have" are used together with the term "only" or the like, these terms are generally intended to allow addition of other components. Unless explicitly stated otherwise, any reference to a singular can include a plural.

[0031] Components are to be interpreted in their broadest reasonable manner, even if not explicitly stated.

[0032] When a positional relationship between two parts is described using terms such as "on", "above", "below", and "next to", unless the terms are used together with the term "immediately" or "directly", one or more parts can be located between the two parts.

[0033] When an element or layer is disposed "on" another element or layer, the other layer or element can be directly disposed on the other element or layer or disposed therebetween.

[0034] Although the terms "first", "second", and the like are used to describe various components, the components are not limited by these terms. The terms are used only to distinguish one component from another component. Thus, a first component mentioned below can be a second component in the technical idea of the disclosure.

[0035] Throughout the specification, like reference numerals generally refer to like elements.

[0036] The size and thickness of each component shown in the drawings are shown for the purpose of facilitating description, and the disclosure is not limited to the size and thickness of the components shown.

[0037] The features of various embodiments of the disclosure can be partially or wholly combined or combined with each other and can interact and operate in technically different ways, and the embodiments can be executed independently of or in association with each other.

[0038] Hereinafter, a display apparatus according to exemplary embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a schematic view of a display apparatus according to exemplary embodiments of the disclosure. In Figure 1 In the display apparatus 100, only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC among various components of the display apparatus 100 are shown for the purpose of facilitating description.

[0040] Referring to Figure 1 , the display apparatus 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0041] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Although in Figure 1In the drawing, a gate driver GD is shown to be disposed apart from one side of the display panel PN, but the number of gate drivers GD and their placement are not limited thereto.

[0042] The data driver DD converts image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD can supply the converted data voltages to a plurality of data lines DL.

[0043] The timing controller TC aligns image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals such as dot clock signals, data enable signals, and horizontal / vertical synchronization signals input from the outside. The timing controller TC supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0044] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and the plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, even though not shown in the drawing, each of the plurality of sub-pixels SP is connected to a high-potential power line, a low-potential power line, and a reference line.

[0045] In the display panel PN, an active area AA and a non-active area NA surrounding the active area AA can be defined.

[0046] The active area AA is an area in which an image is displayed in the display apparatus 100. In the active area AA, a plurality of sub-pixels SP in which a plurality of pixels PX are configured and a circuit for driving the plurality of sub-pixels SP can be disposed. The plurality of sub-pixels SP is a minimum unit in which the active area AA is configured, and n sub-pixels SP form one pixel PX. In each of the plurality of sub-pixels SP, a light emitting diode and a thin film transistor for driving the light emitting diode can be disposed. According to the type of the display panel PN, the plurality of light emitting diodes can be defined in different ways. For example, when the display panel PN is an inorganic light emitting display panel, the light emitting diode can be a light emitting diode (LED) or a micro light emitting diode (micro LED).

[0047] In the active area AA, a plurality of signal lines that transmit various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines include a plurality of data lines DL that supply a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines SL that supply a gate voltage to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low-potential power line and a high-potential power line can also be provided, but are not limited thereto.

[0048] The non-active area NA is an area in which an image is not displayed, such that the non-active area NA can be defined as an area extending from the active area AA. In the non-active area NA, a link line, a pad electrode, or a driving IC, such as a gate driver IC or a data driver IC, that transmits a signal to the sub-pixel SP of the active area AA can be provided. The non-active area NA can be located on a rear surface of the display panel PN, that is, a surface on which the sub-pixel SP is not provided or can be omitted, and is not limited to that shown in the drawing.

[0049] Meanwhile, the drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-active area NA in a gate-in-panel (GIP) manner, or between the plurality of sub-pixels SP in the active area AA in a gate-in-array (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and a printed circuit board, and are electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to the pad electrode formed in the non-active area NA of the display panel PN. If the gate driver GD is mounted in a GIP manner, and the data driver DD and the timing controller TC transmit a signal to the display panel PN through the pad electrode of the non-active area NA, an area of the non-active area NA for providing the gate driver GD and the pad electrode needs to be secured. As such, the bezel increases.

[0050] In contrast, when the gate driver GD is mounted in the active area AA in a GIA manner and a side line SRL that connects a signal line on a front surface of the display panel PN to a pad electrode on a rear surface of the display panel PN is formed by bonding the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero bezel without a bezel can be substantially achieved, which will be described with reference to Figure 2A and Figure 2BTo describe in more detail.

[0051] Figure 2A This is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B This is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure.

[0052] In the non-active area NA of the display panel PN, multiple pad electrodes are provided for transmitting various signals to multiple sub-pixels SP. For example, in the non-active area NA on the front surface of the display panel PN, a first pad electrode PAD1 is provided for transmitting signals to multiple sub-pixels SP. In the non-active area NA on the rear surface of the display panel PN, a second pad electrode PAD2 is provided, which is electrically connected to driving components such as flexible films and printed circuit boards.

[0053] In this case, even though not shown in the figure, various signal lines such as scan lines SL or data lines DL connected to multiple sub-pixels SP extend from the active region AA to the non-active region NA to be electrically connected to the first pad electrode PAD1.

[0054] A side line SRL is disposed along the side surface of the display panel PN. The side line SRL is electrically connected to a first pad electrode PAD1 on the front surface of the display panel PN and a second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving components on the rear surface of the display panel PN are transmitted to multiple sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Thus, a signal transmission path is formed from the front surface to the side and rear surfaces of the display panel PN to minimize the area of ​​the non-active region NA of the display panel PN.

[0055] Reference Figure 2B A large-screen tiled display device TD can be achieved by connecting multiple display devices 100. At this time, when... Figure 2A When a tiled display device TD is implemented using a display device 100 with a minimized bezel, the seam area between the display devices 100 where no image is displayed is minimized, thereby improving display quality.

[0056] For example, multiple subpixels SP form a pixel PX, and the distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another display device 100 adjacent to this display device 100 can be implemented as equal to the distance D1 between pixels PX in one display device 100. Therefore, the spacing of pixels PX between display devices 100 is constantly configured to minimize the seam area.

[0057] However, Figure 2A and Figure 2BThis is illustrative, and therefore the display device 100 according to the exemplary embodiments of this disclosure may be a conventional display device with a bezel, but is not limited thereto.

[0058] Figure 3 This is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 4 This is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 3 and Figure 4 This is an enlarged plan view of a pixel PX of a display device 100 according to an exemplary embodiment of the present disclosure. Figure 3 The image shows only multiple reflective electrodes (REs) and multiple light-emitting diodes (LEDs). Figure 4 The image shows only multiple reflective electrodes RE, multiple light-emitting diodes (LEDs), and multiple holes H in the insulating layer. Figure 4 In the diagram, for ease of description, multiple reflective electrodes RE are represented by solid lines, and multiple holes H are represented by dashed lines.

[0059] Reference Figure 3 and Figure 4 The display panel PN comprises multiple pixels PX formed by multiple sub-pixels SP. Each of the multiple sub-pixels SP includes a light-emitting diode (LED) and pixel circuitry to emit light independently. A pixel PX includes one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. The first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, but they are not limited to these.

[0060] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the multiple sub-pixels SP are set along the first direction DR1.

[0061] Each of the multiple pixels PX includes a first region A1 and a second region A2.

[0062] The first region A1 includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, the first region A1 may be a region that overlaps with multiple reflective electrodes RE.

[0063] The second region A2 is located in the outer edge region of pixel PX extending outward from the first region A1. For example, the second region A2 is located on both sides of the first region A1. For example, in a plurality of sub-pixels SP, the second region A2 is set to be adjacent to the first sub-pixel SP1 and the third sub-pixel SP3. Therefore, the second region A2 is set to be spaced apart from the second sub-pixel SP2, wherein the first sub-pixel SP1 is located between the second region A2 and the second sub-pixel SP2, and the second region A2 is set to be spaced apart from the second sub-pixel SP2, wherein the third sub-pixel SP3 is located between the second region A2 and the second sub-pixel SP2.

[0064] The second region A2 can be a region that does not overlap with the plurality of reflective electrodes RE. When the plurality of reflective electrodes RE are arranged to be spaced apart from each other along the first direction DR1 and extend along the second direction DR2, which is different from the first direction DR1, the second region A2 extends along the second direction DR2 and is disposed on both sides of the plurality of reflective electrodes RE along the first direction DR1. The second direction DR2 can be perpendicular to the first direction.

[0065] Reference Figure 3 and Figure 4 Multiple reflective electrodes RE are disposed in the region corresponding to pixel PX. The reflective electrodes RE are configured to reflect light emitted from multiple light-emitting diodes (LEDs) onto the top of substrate 110, and are formed with a shape corresponding to each of the multiple sub-pixels SP. The multiple reflective electrodes RE are configured to cover a large portion of the area of ​​a sub-pixel SP. The multiple reflective electrodes RE reflect light emitted from the LEDs and also serve as electrodes for electrically connecting the LEDs and pixel circuitry.

[0066] For example, multiple reflective electrodes RE include reflective electrodes RE corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0067] In addition, the plurality of reflective electrodes RE include reflective electrodes RE electrically connected to the driving transistors of each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3, and reflective electrodes RE connected to the power lines of each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3.

[0068] Meanwhile, each of the plurality of reflective electrodes RE extends in the second direction DR2 and overlaps with a plurality of sub-pixels SP arranged along the second direction DR2.

[0069] Multiple light-emitting diodes (LEDs) are disposed in multiple sub-pixels SP. The multiple LEDs include a first LED (LED1), a second LED (LED2), and a third LED (LED3). The first LED (LED1) is disposed in the first sub-pixel SP1, the second LED (LED2) is disposed in the second sub-pixel SP2, and the third LED (LED3) is disposed in the third sub-pixel SP3. The first LED (LED1) is a red LED, the second LED (LED2) is a green LED, and the third LED (LED3) is a blue LED; however, this disclosure is not limited to this.

[0070] Multiple light-emitting diodes (LEDs) are arranged along a first direction DR1. For example, a first LED (LED1), a second LED (LED2), and a third LED (LED3) are arranged along the first direction DR1.

[0071] A pair of LEDs emitting the same color can be placed in a sub-pixel SP. For example, a pair of first LEDs LED1 can be placed in the first sub-pixel SP1. The pair of first LEDs LED1 is positioned along the second direction DR2. A pair of second LEDs LED2 can be placed in the second sub-pixel SP2. The pair of second LEDs LED2 is positioned along the second direction DR2. A pair of third LEDs LED3 can be placed in the third sub-pixel SP3. The pair of third LEDs LED3 is positioned along the second direction DR2.

[0072] Meanwhile, each of the plurality of light-emitting diodes (LEDs) has a long side in the second direction DR2. For example, when the LED has a structure in which a first electrode and a second electrode are included at both ends, the LED has a long side along the direction in which the first electrode and the second electrode are disposed, but is not limited thereto.

[0073] An insulating layer is disposed on multiple reflective electrodes RE in each of the multiple pixels PX. The insulating layer includes multiple holes H. For example, the multiple holes H expose one surface of the multiple reflective electrodes RE disposed thereunder. (Refer to below) Figures 5 to 7 Describe the insulation layer in detail.

[0074] Each of the plurality of holes H has a short side in the first direction DR1 and a long side in the second direction DR2. For example, each of the plurality of holes H has a long side and a short side corresponding to the size of the plurality of light-emitting diodes (LEDs), but is not limited thereto.

[0075] The plurality of holes H includes a plurality of first holes H1, a plurality of second holes H2, and a plurality of third holes H3. The plurality of first holes H1 and the plurality of second holes H2 are disposed in a first region A1, and the plurality of third holes H3 are disposed in a second region A2.

[0076] In the first region A1, a plurality of first holes H1 are provided. A plurality of light-emitting diodes (LEDs) are provided in each of the plurality of first holes H1. Furthermore, the plurality of first holes H1 are arranged to overlap with a plurality of reflective electrodes RE.

[0077] In the first region A1, a plurality of second holes H2 are provided. The plurality of second holes H2 are configured to surround a light-emitting diode (LED). The plurality of second holes H2 are configured to surround a first hole H1. For example, the plurality of second holes H2 can be provided along the outer periphery of the first hole H1. As another example, the plurality of second holes H2 can be provided in regions corresponding to the edges and vertices of each first hole H1. That is, the plurality of second holes H2 are provided on both sides of the plurality of first holes H1 in the first direction DR1, and on both sides of the plurality of first holes H1 in the second direction DR2. Furthermore, the second holes H2 are provided on both sides of the plurality of first holes H1 in a diagonal direction.

[0078] At this time, when multiple light-emitting diodes (LEDs) are arranged in a pixel PX, the second hole H2 and the first hole H1 are arranged alternately. For example, when LEDs emitting different colors of light are arranged in a pixel PX and / or when LEDs emitting the same color of light are arranged in a pixel PX, the second hole H2 and the first hole H1 are arranged alternately.

[0079] Simultaneously, multiple second holes H2 can be continuously arranged along the first direction DR1 and / or the second direction DR2. For example, multiple second holes H2 disposed on the outermost edge of a pixel PX can be continuously arranged along the first direction DR1 and / or the second direction DR2. For example, the second holes H2 are continuously arranged in the first column, and the first holes H1 and second holes H2 are alternately arranged in the second column, and the second holes H2 are continuously arranged in the third column. Furthermore, the second holes H2 are continuously arranged in the first row, and the first holes H1 and second holes H2 are alternately arranged in the second row, and the second holes H2 are continuously arranged in the third row.

[0080] Therefore, multiple second holes H2 can be set in the peripheral region of a pixel PX extending outward from multiple first holes H1. For example, the multiple second holes H2 set in the outermost part of a pixel PX are configured to surround all the multiple first holes H1.

[0081] Multiple second holes H2 are configured not to overlap with multiple light-emitting diodes (LEDs). Multiple second holes H2 are configured to overlap with multiple reflective electrodes (REs).

[0082] Meanwhile, the plurality of second holes H2 include all holes H in the plurality of holes H disposed in the first region A1 except for the hole H disposed with a light-emitting diode (LED).

[0083] In the second region A2, a plurality of third holes H3 are provided. The plurality of third holes H3 are located on the outer periphery of pixel PX, extending outward from the plurality of second holes H2. The plurality of third holes H3 are located on the outermost periphery of each of the plurality of pixels PX, extending outward from the plurality of second holes H2. As another example, the plurality of third holes H3 are located on the outermost periphery of each pixel PX in the first direction DR1.

[0084] Multiple third holes H3 are positioned adjacent to the long side between the long and short sides of multiple second holes H2. (Refer to...) Figure 4 Multiple third holes H3 are disposed on the outermost periphery of each pixel PX in the first direction DR1. Therefore, in the first direction DR1, the third hole H3, the second hole H2, and the first hole H1 are sequentially disposed from the outermost periphery of the pixel PX along the center direction of the pixel PX.

[0085] Meanwhile, the multiple third holes H3 may not be located on the outermost edge of each pixel PX in the second direction DR2. For example, among the multiple holes H, only multiple second holes H2 and multiple first holes H1 are located along the second direction DR2. Specifically, multiple second holes H2 are located on the outermost edge of each pixel PX. Therefore, in the second direction DR2, the second holes H2 and the first holes H1 are sequentially located from the outermost edge of the pixel PX along the center direction of the pixel PX, or only multiple second holes H2 are located.

[0086] Multiple third apertures H3 are configured not to overlap with multiple light-emitting diodes (LEDs). Multiple third apertures H3 are configured not to overlap with multiple reflective electrodes (REs). For example, in a pixel PX, multiple third apertures H3 are configured to be spaced apart from each other, with multiple reflective electrodes REs located between them.

[0087] at the same time, Figure 4 The diagram shows multiple holes H spaced apart from each other at equal intervals along a first direction DR1 and multiple holes H spaced apart from each other at equal intervals along a second direction DR2, but the present disclosure is not limited thereto. For example, the interval between the multiple holes H can vary depending on the placement of the pixel PX and the signal lines and connection lines of the pixel PX disposed on the substrate 110.

[0088] Reference Figure 4 Multiple holes H have the same size. However, this is not a limitation, and the multiple holes H can have different sizes. For example, multiple first holes H1, multiple second holes H2, and multiple third holes H3 can have different sizes. Furthermore, the multiple second holes H2 include second holes H2 with different sizes. For example, some of the multiple second holes H2 extend longer than another second hole H2 and include contact holes through which multiple reflective electrodes RE and multiple light-emitting diodes LED are connected.

[0089] Figure 5 It is alongFigure 3 A cross-sectional view of the display device taken by AA′. Figure 6 It is along Figure 4 A cross-sectional view of the display device taken by BB′. Figure 7 It is along Figure 4 A cross-sectional view of the display device taken at CC'. (Refer to...) Figures 5 to 7 In each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to an exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, an adhesive layer 116, a second planarization layer 117, a third planarization layer 118, an insulating layer 119, a dam BB, a protective layer 190, an optical film MF, a driving transistor DT, a light-emitting diode LED, a plurality of reflective electrodes RE, a plurality of connecting electrodes CE, a light-shielding layer LS, and an auxiliary electrode LE are provided.

[0090] First, the substrate 110 is a component used to support various parts included in the display device 100, and can be formed of an insulating material. For example, the substrate 110 can be formed of glass or resin. Furthermore, the substrate 110 can be configured to include polymers or plastics, or can be formed of a flexible material.

[0091] A light-shielding layer LS is provided in each of the plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light from incident from the bottom of the substrate 110 onto the active layer ACT of the driving transistor DT, which will be described below. The light incident onto the active layer ACT of the driving transistor DT is blocked by the light-shielding layer LS to minimize leakage current. For example, the light-shielding layer LS may be formed of molybdenum (Mo), which has high reflectivity, but is not limited thereto.

[0092] A buffer layer 111 is provided on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be configured as a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0093] A driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0094] An active layer ACT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0095] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE, and may be configured as a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0096] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or alloys thereof, but is not limited thereto.

[0097] A first interlayer insulating layer 113 is formed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113, through which the source electrode SE and drain electrode DE are connected to the active layer ACT. The first interlayer insulating layer 113 is an insulating layer protecting the components below it, and can be configured as a single or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0098] A capacitor electrode C2 is disposed on the first interlayer insulating layer 113. The capacitor electrode C2 is configured to overlap with the gate electrode GE, wherein the first interlayer insulating layer 113 is located between the capacitor electrode C2 and the gate electrode GE.

[0099] A second interlayer insulating layer 114 is formed on the capacitor electrode C2. Contact holes are formed in the second interlayer insulating layer 114, through which the source electrode SE and drain electrode DE are connected to the active layer ACT. The second interlayer insulating layer 114 is an insulating layer protecting the components below it, and can be configured as a single layer or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0100] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE can be configured with conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. For example, the source electrode SE and the drain electrode DE can be formed with a structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo), but are not limited thereto.

[0101] Meanwhile, the thickness of the source electrode SE and the drain electrode DE can be greater than the thickness of the light-shielding layer LS. The light-shielding layer LS is positioned adjacent to the substrate 110, making it difficult to form a light-shielding layer with a large thickness. In contrast, the source electrode SE and the drain electrode DE are disposed above the substrate 110 beyond the light-shielding layer LS. Therefore, the thickness of each of the source electrode SE and the drain electrode DE can be greater than the thickness of the light-shielding layer LS, but is not limited thereto.

[0102] This specification describes the provision of a first interlayer insulating layer 113 and a second interlayer insulating layer 114, i.e., multiple insulating layers, between the gate electrode GE and the source electrode SE and drain electrode DE. However, it is possible to provide only one insulating layer between the gate electrode GE and the source electrode SE and drain electrode DE, but it is not limited to this.

[0103] As shown in the figure, when multiple insulating layers, such as a first interlayer insulating layer 113 and a second interlayer insulating layer 114, are provided between the gate electrode GE and the source electrode SE and the drain electrode DE, an electrode can also be formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode can form a capacitor with other configurations provided below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0104] An auxiliary electrode LE is provided on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to either the source electrode SE or the drain electrode DE via the auxiliary electrode LE to prevent it from operating as a floating gate. Therefore, the threshold voltage fluctuation of the driving transistor DT caused by the floating light-shielding layer LS can be minimized. Although the light-shielding layer LS is shown connected to the source electrode SE in the figure, the light-shielding layer LS can also be connected to the drain electrode DE, but is not limited thereto.

[0105] A first planarization layer 115 is disposed on the driving transistor DT. The first planarization layer 115 can planarize the upper part of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 115 can be configured as a single layer or a double layer, and can be formed, for example, by a photoresist or an acrylic organic material, but is not limited thereto.

[0106] A plurality of reflective electrodes RE are spaced apart from each other on the first planarization layer 115. The plurality of reflective electrodes RE electrically connect the light-emitting diode (LED) to a plurality of power lines and a driving transistor DT, and act as reflectors that reflect light emitted from the LED to the top of the LED. The plurality of reflective electrodes RE are formed of a conductive material with excellent reflective properties to reflect light emitted from the LED toward the top of the LED.

[0107] For example, multiple reflective electrodes RE can be configured from conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. Simultaneously, the multiple reflective electrodes RE can be formed in a structure of indium tin oxide (ITO), aluminum (Al), and molybdenum (Mo) layers, but are not limited thereto.

[0108] The thickness of the plurality of reflective electrodes RE can be greater than the thickness of the light-shielding layer LS. The light-shielding layer LS is disposed adjacent to the substrate 110, making it difficult to form a light-shielding layer with a large thickness. In contrast, each of the plurality of reflective electrodes RE can be disposed above the substrate 110 beyond the light-shielding layer LS. Therefore, the thickness of each of the plurality of reflective electrodes RE can be greater than the thickness of the light-shielding layer LS.

[0109] Multiple reflective electrodes RE can be formed of aluminum.

[0110] The plurality of reflective electrodes RE includes a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 is electrically connected to the driving transistor DT and the light-emitting diode LED. The first reflective electrode RE1 is connected to the source electrode SE or drain electrode DE of the driving transistor DT through a contact hole formed in the first planarization layer 115. The first reflective electrode RE1 can be electrically connected to the first electrode 124 of the light-emitting diode LED via a first connection electrode CE1 described below. For example, refer to... Figure 5 The first reflective electrode RE1 is connected to the source electrode SE of the driving transistor DT. The first reflective electrode RE1 can be electrically connected to the first electrode 124 of the first light-emitting diode LED1 via the first connection electrode CE1 described below.

[0111] The second reflective electrode RE2 can be electrically connected to the second electrode 125 of a plurality of light-emitting diodes (LEDs) via the second connection electrode CE2 described below. For example, refer to Figure 5 The second reflective electrode RE2 can be electrically connected to the second electrode 125 of the first light-emitting diode LED1 via the second connection electrode CE2 described below. For example, refer to... Figure 6 The second reflective electrode RE2 can be electrically connected to the second electrode 125 of the third light-emitting diode LED3 by means of the second connecting electrode CE2 described below.

[0112] An insulating layer 119 is disposed on the first planarization layer 115 and the plurality of reflective electrodes RE. The first planarization layer 115 may be configured as a single layer or a double layer, and may be formed, for example, by a photoresist or an acrylic organic material, but is not limited thereto.

[0113] As described above, the insulating layer 119 includes a plurality of holes H. The plurality of holes H are disposed in each of the plurality of pixels PX. The plurality of holes H expose the top surface of the plurality of reflective electrodes RE and / or the first planarization layer 115 disposed thereunder.

[0114] The multiple holes H include multiple first holes H1, multiple second holes H2, and multiple third holes H3.

[0115] Reference Figure 6 and Figure 7The third light-emitting diode LED3 can be disposed in the first hole H1. In addition, multiple first holes H1 are configured to overlap with the first reflective electrode RE1 and the second reflective electrode RE2.

[0116] Multiple second holes H2 are disposed on one side and the other side of multiple first holes H1. For example, refer to Figure 6 Multiple holes H2 are disposed in a region adjacent to multiple first holes H1 in the second direction DR2, and refer to Figure 7 Multiple second holes H2 are disposed in a region that is also adjacent to multiple first holes H1 in the first direction DR1.

[0117] Multiple second holes H2 are disposed in the region that overlaps with multiple reflective electrodes RE, and are configured not to overlap with multiple light-emitting diodes LED.

[0118] Multiple third holes H3 are positioned on the outer periphery of pixel PX, extending outwards from multiple second holes H2. (See reference...) Figure 7 Multiple third holes H3 are disposed on one side of the second hole H2 in the first direction DR1.

[0119] Multiple third holes H3 are disposed in areas that do not overlap with multiple reflective electrodes RE, and are configured not to overlap with multiple light-emitting diodes (LEDs). An adhesive layer 116 is disposed on the multiple reflective electrodes RE and the insulating layer 119.

[0120] An adhesive layer 116 is coated on the front surface of the substrate 110 to fix a light-emitting diode (LED) disposed on the adhesive layer 116. For example, the adhesive layer 116 may be selected from any one of adhesive polymers, epoxy resins, UV resins, polyimides, acrylates, polyurethanes, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0121] The adhesive layer 116 can fill the plurality of holes H. Therefore, the thickness of the adhesive layer 116 in the plurality of holes H is greater than the thickness of the adhesive layer 116 on the insulating layer 119.

[0122] The adhesive layer 116 can cover the top surfaces of the plurality of reflective electrodes RE and the top surface of the first planarization layer 115. Furthermore, the adhesive layer extends from the top surface of the insulating layer 119 to cover the side surfaces of the insulating layer 119 disposed in the plurality of holes H. Simultaneously, when the ends of the plurality of reflective electrodes RE are disposed in the plurality of holes H, the adhesive layer 116 can also cover the ends of the plurality of reflective electrodes RE.

[0123] The adhesive layer 116 is formed by covering and curing a liquid organic insulating material onto the insulating layer 119. Therefore, due to the stepped structure of the insulating layer 119, which includes multiple holes H, the fluid organic insulating material flows towards the multiple holes H before the curing process. For example, the organic insulating material moves from the top surface of the insulating layer 119, where no holes H are provided, to the center direction of the pixel PX where multiple holes H are provided. Therefore, the thickness of the organic insulating material in the holes H in the peripheral region of a pixel PX can be greater than the thickness of the organic insulating material in the holes H in the central portion. Therefore, when the adhesive layer 116 is formed with the organic insulating material by performing a curing process, the adhesive layer 116 can have a thickness that varies at each location of the holes H. The thickness of the adhesive layer 116 in the holes H in the peripheral region of a pixel PX can be greater than the thickness of the adhesive layer 116 in the holes H in the central portion. Therefore, the thickness of the adhesive layer 116 in the holes H in the second region A2 is greater than the thickness of the adhesive layer 116 in the holes H in the first region A1. (Refer to...) Figure 7 The thickness of the portion of the adhesive layer 116 overlapping with the plurality of first holes H1 and the plurality of second holes H2 may be different from the thickness of the portion overlapping with the plurality of third holes H3. Specifically, the thickness of the portion of the adhesive layer 116 overlapping with the plurality of third holes H3 may be greater than the thickness of the portion overlapping with the plurality of first holes H1 and the plurality of second holes H2. Furthermore, the thickness of the portion of the adhesive layer 116 overlapping with the plurality of first holes H1 may be different from the thickness of the portion overlapping with the plurality of second holes H2.

[0124] Furthermore, in each of the plurality of holes H, the adhesive layer 116 may be formed with an uneven shape. For example, in each of the plurality of holes H, there may be a thickness variation in the adhesive layer 116. Specifically, in each of the plurality of holes H, the thickness of the adhesive layer 116 increases toward the periphery of the pixel PX. (Refer to...) Figure 7 The closer the adhesive layer 116 is to the second hole H2, the greater its thickness; conversely, the farther away from the second hole H2, the greater its thickness in the third hole H3. The organic insulating material used to form the adhesive layer 116 flows from the periphery of the pixel PX towards its center. At this time, the organic insulating material can flow along the side surface of the insulating layer 119 disposed in the hole H. Therefore, since the organic insulating material is adjacent to the side surface of the insulating layer 119 disposed in the peripheral region of the pixel PX, the organic insulating material is configured to have a large thickness. Therefore, a thickness deviation of the adhesive layer 116 may exist in one hole H.

[0125] The thickness deviation of the adhesive layer 116 can vary depending on the shape of the plurality of holes H. For example, the adhesive layer 116 can flow along the side surface of the insulating layer 119 provided in the plurality of holes H. Therefore, the amount of adhesive layer 116 filling the plurality of holes H can vary depending on the area of ​​the side surface of the insulating layer 119. For example, the amount of adhesive layer 116 flowing along the long side surface of the insulating layer 119 provided with the plurality of holes H is greater than the amount of adhesive layer 116 flowing along the short side surface of the insulating layer 119 provided with the plurality of holes H. Therefore, the amount of adhesive layer 116 flowing from the long side surface of the insulating layer 119 provided with the plurality of holes H along the first direction DR1 is greater than the amount of adhesive layer 116 flowing from the short side surface of the insulating layer 119 provided with the plurality of holes H along the second direction DR2. Therefore, referring to Figure 6 The thickness deviation of the adhesive layer 116 in the second direction DR2 will not occur, but reference Figure 7 Thickness deviation of adhesive layer 116 in the first direction DR1 may occur.

[0126] The adhesive layer 116 may include contact holes that expose a plurality of reflective electrodes RE. In this case, a plurality of connection electrodes CE, a plurality of light-emitting diodes (LEDs), and a plurality of reflective electrodes RE are electrically connected through the contact holes of the adhesive layer 116. The contact holes of the adhesive layer 116 may be located in areas overlapping with the plurality of holes H. For example, refer to… Figure 5 and Figure 6 In the region overlapping with the plurality of second holes H2, the adhesive layer 116 includes contact holes that expose the plurality of reflective electrodes RE. In the plurality of second holes H2, a plurality of light-emitting diodes (LEDs) and a plurality of reflective electrodes RE are electrically connected.

[0127] In each of the plurality of sub-pixels SP, a plurality of light-emitting diodes (LEDs) are disposed on the adhesive layer 116. For example, a plurality of LEDs are disposed in a plurality of first holes H1. In this case, the bottom surface of the plurality of LEDs in the plurality of first holes H1 can be disposed below the top surface of the insulating layer 119.

[0128] Multiple light-emitting diodes (LEDs) are light-emitting elements that emit light through an electric current, and may include LEDs that emit red, green, and blue light, and can be combined to achieve various colors of light, including white. For example, multiple LEDs can be light-emitting diodes (LEDs) or micro LEDs, but are not limited to these.

[0129] Each of the plurality of light-emitting diodes (LEDs) includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0130] Reference Figures 5 to 7A first semiconductor layer 121 for a light-emitting diode (LED) is disposed on an adhesive layer 116, and a second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 can be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 can be layers doped with n-type and p-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurities can be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurities can be silicon (Si), germanium, and tin (Sn), but are not limited thereto.

[0131] A light-emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The light-emitting layer 122 may be formed of a single-layer or multiple quantum well (MQW) structure, and may be formed, for example, of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0132] A first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or alloys thereof, but is not limited thereto.

[0133] A second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 is disposed on the top surface of the second semiconductor layer 123. The second electrode 125 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or alloys thereof, but is not limited thereto.

[0134] Next, an encapsulation film 126 is formed surrounding the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is formed of an insulating material to protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Contact holes are formed in the encapsulation film 126 to expose the first electrode 124 and the second electrode 125, so as to electrically connect the first connecting electrode CE1 and the second connecting electrode CE2 to the first electrode 124 and the second electrode 125.

[0135] If the light-emitting diode (LED) has a lateral or flip-chip structure, it can be positioned along one direction of the first electrode 124 and the second electrode 125. Therefore, each of the plurality of LEDs can have a long side in the direction in which the first electrode 124 and the second electrode 125 are positioned. For example, refer to... Figure 6 The third light-emitting diode, LED3, has a long side in the second direction, DR2. For example, refer to... Figure 7 The third light-emitting diode LED3 has a short side in the first direction DR1. However, it is not limited to this, and all light-emitting diodes LED can be formed to have the same side.

[0136] A second planarization layer 117 and a third planarization layer 118 are disposed on the adhesive layer 116. The second planarization layer 117 overlaps with a portion of the side surface of the plurality of light-emitting diodes (LEDs) to fix and protect the plurality of LEDs. Specifically, even when Figures 5 to 7 The diagram shows an encapsulation film 126 surrounding all side surfaces of the first semiconductor layer 121, but a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126. The light-emitting diode (LED) fabricated on the wafer is separated from the wafer for transfer to the display panel PN. However, during the process of separating the LED from the wafer, a portion of the encapsulation film 126 may be torn. For example, during the process of separating the LED from the wafer, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the LED may be torn. Therefore, a portion of the lower side surface of the first semiconductor layer 121 may be exposed. However, even if the lower portion of the LED is exposed from the encapsulation film 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after the formation of the second planarization layer 117 covering the side surface of the first semiconductor layer 121. Therefore, short-circuit defects can be minimized.

[0137] Furthermore, a third planarization layer 118 is formed to cover the second planarization layer 117 and the upper portion of the light-emitting diode (LED), and contact holes can be formed to expose the first electrode 124 and the second electrode 125 of the LED. The first electrode 124 and the second electrode 125 of the LED are exposed from the third planarization layer 118, and the third planarization layer 118 is partially disposed in the region between the first electrode 124 and the second electrode 125 to minimize short-circuit defects.

[0138] The second planarization layer 117 and the third planarization layer 118 can be configured as a single layer or a double layer, and can be formed, for example, by a photoresist or an acrylic organic material, but are not limited thereto. Even though the provision of the second planarization layer 117 and the third planarization layer 118 is described in the specification, the planarization layer can also be formed as a single layer, but is not limited thereto.

[0139] Multiple connection electrodes CE are disposed on the third planarization layer 118. The multiple connection electrodes CE include multiple first connection electrodes CE1 and multiple second connection electrodes CE2.

[0140] The first connection electrode CE1 is disposed in each of the plurality of sub-pixels SP to electrically connect the light-emitting diode (LED) and the driving transistor DT. The first connection electrode CE1 is connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Therefore, the first connection electrode CE1 is electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the first reflective electrode RE1. The first connection electrode CE1 is connected to the first electrode 124 of the plurality of LEDs through contact holes formed in the third planarization layer 118. Therefore, the first connection electrode CE1 electrically connects the driving transistor DT to the first electrode 124 of the plurality of LEDs and the first semiconductor layer 121.

[0141] The second connecting electrode CE2 is connected to the second reflective electrode RE2 through contact holes formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. The second connecting electrode CE2 is connected to the second electrode 125 of the plurality of light-emitting diodes (LEDs) through contact holes formed in the third planarization layer 118.

[0142] Even in Figure 7 The diagram shows multiple connecting electrodes CE configured not to overlap with the third hole H3, but the present disclosure is not limited thereto, and multiple connecting electrodes CE are configured to overlap with the third hole H3.

[0143] A dam BB is formed on the third planarization layer 118. The dam BB can be set at a predetermined interval from the light-emitting diode (LED).

[0144] The BB can be formed of an opaque material to reduce color mixing between multiple sub-pixels SP, and for example, it can be formed of black resin, but is not limited to this.

[0145] The dam BB has an opening region in the area corresponding to the light-emitting diode (LED). Therefore, referring to... Figures 5 to 7 In the multiple holes H, the dam BB is configured not to overlap with the first hole H1 which is provided with multiple light-emitting diodes (LEDs), and is configured to overlap with the second hole H2 and the third hole H3.

[0146] A protective layer 190 is disposed on the third planarization layer 118 and the embankment BB. The protective layer 190 is a layer for protecting the structure beneath it, and for example, covers at least a portion of the light-emitting diode (LED). The protective layer 190 may be configured as a single or double layer of transparent epoxy resin, silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0147] An optical film MF is disposed on the protective layer 190. The optical film MF can be a functional film that achieves higher quality images while protecting the display device 100. For example, the optical film MF may include, but is not limited to, an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, or a polarizer.

[0148] An adhesive layer may be additionally disposed between the optical film MF and the protective layer 190. Alternatively, the optical film MF may also be defined as including an adhesive layer disposed thereunder.

[0149] Meanwhile, a first connection electrode CE1 is separately provided in each of the multiple sub-pixels SP to connect the driving transistor DT and the light-emitting diode LED provided in each of the multiple sub-pixels SP.

[0150] Simultaneously, multiple light-emitting diodes (LEDs) can be connected to multiple power lines. For example, each of the multiple LEDs is connected to multiple power lines via multiple first connection electrodes CE1 and multiple second connection electrodes CE2.

[0151] Figures 8A to 8D This is a processing diagram used to illustrate a method for manufacturing a display device according to an exemplary embodiment of the present disclosure. Figures 8A to 8D This is a view used to illustrate the process of transferring multiple light-emitting diodes (LEDs) onto a display panel PN using a donor.

[0152] Reference Figure 8A A display panel PN is prepared by sequentially stacking multiple reflective electrodes RE, an insulating layer 119 including multiple holes H, and an adhesive layer 116 thereon. At this time, in the multiple holes H, the top surface of the adhesive layer 116 is formed to be lower than the top surface of the adhesive layer 116 above the insulating layer 119.

[0153] To perform the transfer process, light is selectively irradiated only in a portion of the display panel PN to alter the adhesive strength of the insulating layer 119. For example, light is irradiated to correspond to the second hole H2, thereby curing the surface of the adhesive layer 116 disposed in the second hole H2. Thus, the adhesive layer 116 disposed in the first hole H1 maintains its initial adhesive strength, but the adhesive layer 116 disposed in the second hole H2 may have a weaker adhesive strength than its initial adhesive strength.

[0154] Reference Figure 8B A plurality of light-emitting diodes (LEDs) are attached to a donor on a display panel PN. The LEDs are attached to the donor via an adhesive component PDMS. The adhesive component PDMS can be formed of a ductile material.

[0155] Simultaneously, multiple light-emitting diodes (LEDs) can be aligned to correspond to the positions of multiple holes H. For example, LEDs emitting the same color of light can be attached to correspond to each of the multiple first holes H1. Furthermore, LEDs emitting the same color of light can be attached to correspond to each of the multiple second holes H2. However, the LEDs configured to correspond to the first holes H1 and the LEDs configured to correspond to the second holes H2 can be LEDs emitting different colors of light.

[0156] In addition, Figure 8B In the adhesive layer 116 disposed in the second hole H2, surface curing is performed such that the adhesive strength is weaker than the initial adhesive strength, and the surface of the adhesive layer 116 where the adhesive strength changes is shown by dashed lines.

[0157] Reference Figure 8C After the donor is placed on the display panel PN, pressure is applied. At this time, multiple light-emitting diodes (LEDs) attached to the donor come into contact with the top surface of the adhesive layer 116 of the display panel PN.

[0158] Simultaneously, during the transfer process, pressure arises between the donor and the display panel PN, altering the shape of the adhesive component PDMS. At this time, the multiple holes H minimize the shape change of the adhesive component PDMS, suppressing over-transfer issues. Multiple light-emitting diodes (LEDs) attached to the donor are positioned below the top surface of the insulating layer 119 in the region overlapping with the multiple holes H. Therefore, compared to the case where the insulating layer does not contain multiple holes, the shape change of the adhesive component PDMS is minimized in the region corresponding to the multiple holes H. Consequently, the pressure between the LEDs and the adhesive component PDMS is reduced. Therefore, the pressure between the donor and the display panel PN is reduced, and over-transfer issues can be suppressed.

[0159] Reference Figure 8DThe donor separates from the display panel PN. Some of the multiple light-emitting diodes (LEDs) are attached to the adhesive layer 116 to transfer to the display panel PN, and some of the LEDs attached to the donor separate from the adhesive layer 116 while remaining attached to the donor. For example, the adhesive layer 116 in the first hole H1 is in a state that maintains its initial adhesive strength. Therefore, the LEDs attached to the top surface of the adhesive layer 116 in the first hole H1 are attached to the adhesive layer 116 with strong adhesive strength to separate from the donor. In contrast, the adhesive layer 116 in the second hole H2 may be in a state where the adhesive strength is less than the initial adhesive strength. Therefore, the LEDs attached to the top surface of the adhesive layer 116 in the second hole H2 are in contact with the top surface of the adhesive layer 116 with weaker adhesive strength, and then separate from the display panel PN together with the donor when the donor separates from the display panel PN.

[0160] In the next transfer process, only some of the LEDs attached to the multiple LEDs are brought into contact with the display panel PN again. Thus, the LEDs attached to the donors are transferred to the display panel PN through multiple transfer processes. For example, LEDs emitting different colors of light are attached to multiple donors, and in one transfer process, only LEDs emitting the same color of light are transferred to the display panel PN.

[0161] The adhesive layer is formed by curing a liquid organic insulating material, which may result in thickness variations in the areas where steps are formed. For example, when the insulating layer beneath the adhesive layer includes multiple holes, the thickness of the outermost hole in each of the pixels is greater than the thickness of the hole in the center of each pixel. Furthermore, as the thickness of the adhesive layer increases, over-transfer problems may occur during the transfer process. For example, as the thickness of the adhesive layer increases, the pressure generated between the donor and the display panel may increase. Therefore, even if the LED comes into contact with the adhesive layer with weak adhesive strength during the transfer process, the LED can still be transferred to the display panel. Thus, an over-transfer problem may occur where the LED that needs to be transferred in the next process is transferred to the display panel. Therefore, when the adhesive layer is formed thickly in the outermost hole in each of the pixels, over-transfer problems may occur in the area corresponding to the periphery of the pixel.

[0162] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, a dummy third hole H3 is formed in the outermost periphery of each of the plurality of pixels PX. Thus, the plurality of third holes H3 act as traps and suppress the flow of an appropriate amount or more of uncured adhesive layer 116 to the first hole H1 and the second hole H2 in the region having a high peripheral step. Therefore, the plurality of third holes H3 minimizes the thickness deviation of the adhesive layer 116 in the first hole H1 and the second hole H2.

[0163] Simultaneously, when there is no thickness deviation in the adhesive layer 116 in the first hole H1 and the second hole H2, the pressure generated between the donor and the plurality of light-emitting diodes (LEDs) during the transfer process can be reduced. Therefore, the problem of over-transferring of LEDs in the second hole H2 that need to be transferred in the next transfer process among the plurality of LEDs attached to the donor is suppressed. Therefore, in the display device 100 according to the exemplary embodiment of this disclosure, the transfer / non-transfer selectivity of the LEDs is increased during the manufacturing process of the display device 100. Furthermore, even when the transfer process is performed multiple times using a donor with a large area, the transfer success rate of the LEDs is increased, thereby reducing processing costs and product costs.

[0164] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of third holes H3 are arranged adjacent to the surface on which a plurality of first holes H1 and a plurality of second holes H2 are provided. The amount of adhesive layer 116 flowing along the side surface of the insulating layer 119 on which a plurality of holes H are provided is greater than the amount of adhesive layer 116 flowing along the side surface of the insulating layer 119 on which a plurality of holes H are provided. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of third holes H3 are provided on the surface on which a plurality of first holes H1 and a plurality of second holes H2 are provided. Therefore, the overflow of an appropriate amount or more of adhesive layer 116 into the first holes H1 and the second holes H2 is effectively suppressed. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the transfer success rate of the light-emitting diode (LED) is increased, thereby reducing processing costs and product costs.

[0165] Furthermore, in the display device 100 according to an exemplary embodiment of this disclosure, the plurality of third holes H3 may have the same size as the plurality of first holes H1 and the plurality of second holes H2. If the plurality of third holes has a larger size than the plurality of first holes and the plurality of second holes, all the adhesive layer flowing in the peripheral region of the pixel can fill the plurality of third holes. Therefore, the adhesive layer may not flow in the plurality of first holes and the plurality of second holes. In contrast, when the size of the plurality of third holes is smaller than the size of the plurality of first holes and the plurality of second holes, the adhesive layer flows from the plurality of third holes to the plurality of first holes and the plurality of second holes. Therefore, thickness deviations may exist in the plurality of first holes and the plurality of second holes. Therefore, in the display device 100 according to an exemplary embodiment of this disclosure, the plurality of third holes H3 are set to have the same size as the plurality of first holes H1 and the plurality of second holes H2 to suppress thickness deviations of the adhesive layer 116. In addition, the transfer success rate is increased, thereby reducing processing costs and product costs.

[0166] Furthermore, in the display device 100 according to an exemplary embodiment of this disclosure, a plurality of third holes H3 are disposed in a region that does not overlap with the reflective electrode RE to improve reliability. For example, during the process of connecting a plurality of wirings and a plurality of reflective electrodes disposed on a display panel, a dry etching process is performed on the plurality of reflective electrodes. At this time, when the reflective electrodes are exposed from the plurality of third holes, an arcing phenomenon may occur in the reflective electrodes, thereby degrading the reliability of the reflective electrodes. Therefore, a plurality of third holes H are disposed in a region that does not overlap with the reflective electrode RE to improve the reliability of the display device 100.

[0167] Figure 9 This is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 9 Display device 900 and Figures 1 to 7 The only difference between the display devices 100 is the multiple third holes H3, but the other configurations are basically the same, so redundant descriptions will be omitted.

[0168] Reference Figure 9 In each of the multiple pixels PX, an insulating layer including multiple holes H is provided on multiple reflective electrodes RE.

[0169] The plurality of holes H includes a plurality of first holes H1, a plurality of second holes H2, and a plurality of third holes H3. The plurality of first holes H1 and the plurality of second holes H2 can be disposed in the first region A1. At the same time, the plurality of third holes H3 are disposed on the outer periphery of the pixel PX extending outward from the plurality of second holes H2.

[0170] Multiple third holes H3 are disposed on the outermost periphery of each pixel PX in the first direction DR1. For example, multiple third holes H3 are disposed in the second region A2. Therefore, in the first direction DR1, the third holes H3, the second holes H2, and the first holes H1 are disposed sequentially from the outermost periphery of the pixel PX along the center direction of the pixel PX, or the multiple third holes H3 are disposed such that multiple second holes H2 are located therebetween.

[0171] In addition, the multiple third holes H3 in the second region A2 are configured not to overlap with the multiple reflective electrodes RE.

[0172] Furthermore, multiple third holes H3 can be disposed on the outermost periphery of each pixel PX in the second direction DR2. For example, in the first region A1, multiple third holes H3 are disposed on the outermost periphery of pixel PX extending outward from multiple second holes H2. Therefore, in the second direction DR2, the third holes H3, second holes H2, and first holes H1 are sequentially disposed from the outermost periphery of pixel PX along the center direction of pixel PX, or the multiple third holes H3 are disposed such that the multiple second holes H2 are located in between.

[0173] In addition, the multiple third holes H3 in the first region A1 are configured to overlap with the multiple reflective electrodes RE.

[0174] Meanwhile, multiple third holes H3 can be continuously arranged along the first direction DR1 and / or the second direction DR2. For example, in a pixel PX, multiple third holes H3 can be continuously arranged along the first direction DR1 and / or the second direction DR2 to surround multiple second holes H2 and multiple first holes H1.

[0175] Therefore, in a display device 900 according to another exemplary embodiment of the present disclosure, a dummy third hole H3 is formed in the outermost periphery of each of the plurality of pixels PX. Thus, the plurality of third holes H3 act as traps, and the thickness deviation of the adhesive layer 116 in the first hole H1 and the second hole H2 is minimized. Therefore, the problem of excessive transfer of the light-emitting diode (LED) onto the second hole H2 is suppressed, and the transfer success rate of the LED is increased, thereby reducing processing costs and product costs.

[0176] In another exemplary embodiment of the display device 900 according to this disclosure, a plurality of third holes H3 are configured to be adjacent to the long side of a surface provided with a plurality of first holes H1 and a plurality of second holes H2. Therefore, an appropriate amount or more of the adhesive layer 116 is effectively suppressed from overflowing into the first holes H1 and the second holes H2, thereby increasing the transfer success rate of the light-emitting diode (LED) and reducing processing and product costs.

[0177] Furthermore, in another exemplary embodiment of the display device 900 according to this disclosure, the plurality of third holes H3 may have the same dimensions as the plurality of first holes H1 and the plurality of second holes H2. Therefore, thickness deviations in the adhesive layer 116 are suppressed, and the transfer success rate of the light-emitting diodes (LEDs) is increased, thereby reducing processing costs and product costs.

[0178] Furthermore, in another exemplary embodiment of the display device 900 according to this disclosure, a plurality of third holes H3 are configured to be adjacent to the surface of the short side where a plurality of first holes H1 and a plurality of second holes H2 are provided. Therefore, overflow of the adhesive layer 116 along the side surface of the insulating layer 119 where the plurality of holes H are provided is suppressed, and overflow of an appropriate amount or more to the first holes H1 and the second holes H2 is effectively suppressed. Therefore, in the display device 900 according to another exemplary embodiment of this disclosure, the transfer success rate of the light-emitting diode (LED) is increased, thereby reducing processing costs and product costs.

[0179] Exemplary embodiments of this disclosure can also be described as follows:

[0180] According to one aspect of this disclosure, a display device is provided. The display device includes: a substrate defining a plurality of pixels, including a plurality of sub-pixels; a plurality of transistors disposed on the substrate; an insulating layer disposed on the substrate; an adhesive layer disposed on the insulating layer; and a plurality of light-emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes a plurality of holes disposed in each of the plurality of pixels, the plurality of holes including a plurality of first holes, a plurality of second holes, and a plurality of third holes, the plurality of first holes being configured to overlap with the plurality of light-emitting diodes, the plurality of second holes being configured to surround the plurality of first holes in a plane, and the plurality of third holes including the outermost hole disposed in a first direction.

[0181] Each of the plurality of holes may have a short side in a first direction and a long side in a second direction.

[0182] Each of the multiple light-emitting diodes can have a long side in the second direction.

[0183] The display device may also include a plurality of reflective electrodes disposed between the substrate and the insulating layer, wherein a plurality of first holes and a plurality of second holes may overlap with the plurality of reflective electrodes, and a plurality of third holes do not overlap with the plurality of reflective electrodes.

[0184] In the region overlapping with the multiple second holes, the adhesive layer may include holes that expose multiple reflective electrodes, and in these holes, the multiple reflective electrodes and multiple light-emitting diodes may be electrically connected.

[0185] The thickness of the portion of the adhesive layer that overlaps with the plurality of first holes and the plurality of second holes may be different from the thickness of the portion that overlaps with the plurality of third holes.

[0186] The thickness of the portion of the adhesive layer that overlaps with the multiple third holes can be greater than the thickness of the portion that overlaps with the multiple first holes and the multiple second holes.

[0187] The thickness of the portion of the adhesive layer that overlaps with the plurality of first holes may be different from the thickness of the portion that overlaps with the plurality of second holes.

[0188] The display device may also include a dam disposed above a plurality of light-emitting diodes, wherein a plurality of first holes may not overlap with the dam, and a plurality of second holes and a plurality of third holes may overlap with the dam.

[0189] Multiple third holes may also include holes located on the outermost periphery in the second direction.

[0190] According to another aspect of this disclosure, a display device is provided. The display device includes: a substrate defining pixels comprising a plurality of sub-pixels; an insulating layer disposed on the substrate; a plurality of reflective electrodes disposed on the insulating layer; an adhesive layer disposed on the plurality of reflective electrodes; and a plurality of light-emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes: a plurality of first holes overlapping the plurality of reflective electrodes; a plurality of second holes overlapping the plurality of reflective electrodes; and a plurality of third holes not overlapping the plurality of reflective electrodes.

[0191] The thickness of the adhesive layer overlapping with the multiple third holes can be greater than the thickness of the adhesive layer overlapping with the multiple first holes and the multiple second holes.

[0192] Multiple first holes can overlap with multiple light-emitting diodes, while multiple second holes and multiple third holes can not overlap with multiple light-emitting diodes.

[0193] Multiple third holes can be set on the outermost periphery of each of the multiple pixels in the first direction.

[0194] Multiple second holes can be configured to surround one of the multiple first holes, and multiple third holes can be configured on the outermost periphery of each of the multiple pixels, extending outward from the multiple second holes.

[0195] Although exemplary embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of this disclosure. Therefore, the exemplary embodiments of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit this disclosure. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of this disclosure.

Claims

1. A display device, comprising: a substrate in which a plurality of pixels including a plurality of sub-pixels are defined; a plurality of transistors disposed on the substrate; an insulating layer disposed on the substrate; an adhesive layer disposed on the insulating layer; and a plurality of light emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes a plurality of holes disposed in each of the plurality of pixels, the plurality of holes including a plurality of first holes, a plurality of second holes, and a plurality of third holes, the plurality of first holes being disposed to overlap the plurality of light emitting diodes, the plurality of second holes being disposed to surround the plurality of first holes in a planar view, and the plurality of third holes including holes that are disposed outermost in a first direction among the plurality of holes. each of the plurality of holes has a short side in the first direction and a long side in a second direction different from the first direction.

2. The display device of claim 1, wherein, each of the plurality of light emitting diodes has a long side in the second direction.

3. The display device of claim 2, wherein, 4.The display device of claim 1, further comprising: a plurality of reflective electrodes disposed between the substrate and the insulating layer, wherein the plurality of first holes and the plurality of second holes overlap the plurality of reflective electrodes, and the plurality of third holes do not overlap the plurality of reflective electrodes. in a region overlapping the plurality of second holes, the adhesive layer includes contact holes exposing the plurality of reflective electrodes, and in the contact holes, the plurality of reflective electrodes and the plurality of light emitting diodes are electrically connected.

5. The display device of claim 4, wherein, a thickness of a portion of the adhesive layer overlapping the plurality of first holes and the plurality of second holes is different from a thickness of a portion overlapping the plurality of third holes.

6. The display device of claim 1, wherein, a thickness of the portion of the adhesive layer overlapping the plurality of third holes is greater than the thickness of the portion overlapping the plurality of first holes and the plurality of second holes.

7. The display device of claim 6, wherein, a thickness of a portion of the adhesive layer overlapping the plurality of first holes is different from a thickness of a portion overlapping the plurality of second holes.

8. The display device of claim 7, wherein, 9.The display device of claim 1, further comprising: a bank disposed above the plurality of light emitting diodes, wherein the plurality of first holes do not overlap the bank, and the plurality of second holes and the plurality of third holes overlap the bank. the plurality of third holes further include holes disposed outermost in a second direction.

10. The display device of claim 1, wherein, in the first direction, the plurality of third holes, the plurality of second holes, and the plurality of first holes are configured to be sequentially disposed from an outermost periphery of each of the plurality of pixels in a direction of a center of each of the plurality of pixels.

11. The display device of claim 1, wherein, the plurality of third holes have the same size as the plurality of first holes and the plurality of second holes.

12. The display device of claim 1, wherein, 13.A display device, comprising: a substrate in which a plurality of pixels including a plurality of sub-pixels are defined; an insulating layer disposed on the substrate; a plurality of reflective electrodes disposed on the insulating layer; an adhesive layer disposed on the plurality of reflective electrodes; and a plurality of light emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes: a plurality of first holes overlapping the plurality of reflective electrodes; and a plurality of second holes overlapping the plurality of first holes and the plurality of light emitting diodes. ​ a plurality of second holes overlapping the plurality of reflective electrodes; and a plurality of third holes not overlapping the plurality of reflective electrodes.

14. The display device of claim 13, wherein, A thickness of a portion of the adhesive layer overlapping the plurality of third holes is greater than a thickness of a portion of the adhesive layer overlapping the plurality of first holes and the plurality of second holes.

15. The display device of claim 13, wherein, The plurality of first holes overlap the plurality of light emitting diodes, and the plurality of second holes and the plurality of third holes do not overlap the plurality of light emitting diodes.

16. The display device of claim 13, wherein, The plurality of third holes are disposed at an outermost periphery of each of the plurality of pixels in a first direction.

17. The display device of claim 13, wherein, The plurality of second holes are disposed to surround one of the plurality of first holes, and the plurality of third holes are disposed at an outermost periphery of each of the plurality of pixels outward from the plurality of second holes.

18. A display apparatus, comprising: a substrate defining a plurality of pixels including a plurality of sub-pixels therein; an insulating layer disposed on the substrate; a plurality of reflective electrodes disposed on the insulating layer; an adhesive layer disposed on the plurality of reflective electrodes; and a plurality of light emitting diodes disposed on the adhesive layer in each of the plurality of sub-pixels, wherein the insulating layer includes: a plurality of first holes overlapping the plurality of reflective electrodes; a plurality of second holes overlapping the plurality of reflective electrodes; and a plurality of third holes formed in an outermost periphery of each of the plurality of pixels.

19. The display device of claim 18, wherein, In a first direction, the plurality of third holes, the plurality of second holes, and the plurality of first holes are sequentially disposed from an outermost periphery of each of the plurality of pixels in a direction of a center of each of the plurality of pixels.

20. The display device of claim 19, wherein, In a second direction different from the first direction, the plurality of third holes, the plurality of second holes, and the plurality of first holes are sequentially disposed from an outermost periphery of each of the plurality of pixels in a direction of a center of each of the plurality of pixels.

Images