Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes: a substrate including a display area and a peripheral area; sub-pixels in the display area, each of the sub-pixels including a light emitting device, a first transistor electrically connected to the light emitting device, and a conductive layer electrically connecting the light emitting device and the first transistor; and a first voltage line and a second voltage line extending in parallel in the first direction and each applying a first voltage to two adjacent rows of sub-pixels among the plurality of sub-pixels, where the two adjacent rows of sub-pixels are located between the first voltage line and the second voltage line, the conductive layer of the sub-pixel connected to the first voltage line extends toward the second voltage line in the second direction, and the conductive layer of the sub-pixel connected to the second voltage line extends toward the first voltage line in the second direction.

Description

TECHNICAL FIELD

[0001] One or more embodiments of the present disclosure relate to a display device and an electronic device including the same. BACKGROUND

[0002] Recently, various flat panel display devices have been developed, which are light in weight and compact. The flat panel display devices include a liquid crystal display (LCD) device, a field emission display (FED) device, a plasma display panel (PDP) device, and an organic light emitting display device.

[0003] Among the flat panel display devices, the organic light emitting display device displays an image using an organic light emitting diode that emits light by recombination of electrons and holes. These organic light emitting display devices are attracting attention as next-generation displays due to their fast response speed and low power consumption. SUMMARY

[0004] One or more embodiments of the present disclosure provide a display device having improved integration and higher resolution and an electronic device including the same.

[0005] According to an embodiment of the present disclosure, a display device is provided, the display device including: a substrate including a display area and a peripheral area adjacent to the display area; a plurality of sub-pixels located in the display area, each of the plurality of sub-pixels including a light emitting device, a first transistor electrically connected to the light emitting device, and a conductive layer electrically connecting the light emitting device and the first transistor; and a first voltage line and a second voltage line extending in parallel in a first direction and each applying a first voltage to sub-pixels of two adjacent rows among the plurality of sub-pixels, wherein the sub-pixels of the two adjacent rows are located between the first voltage line and the second voltage line, the conductive layer of the sub-pixel connected to the first voltage line extends toward the second voltage line in a second direction perpendicular to the first direction, and the conductive layer of the sub-pixel connected to the second voltage line extends toward the first voltage line in the second direction.

[0006] The light emitting device includes a pixel electrode, a common electrode, and an intermediate layer located between the pixel electrode and the common electrode, wherein the light emitting device includes an organic material, and the pixel electrode is electrically connected to the conductive layer.

[0007] The display device further includes: a pixel definition layer covering a portion of the pixel electrode, the pixel definition layer defining an opening.

[0008] The plurality of sub-pixels include a first sub-pixel for emitting green light, a second sub-pixel for emitting blue light, and a third sub-pixel for emitting red light.

[0009] The first sub-pixel is arranged in the first column parallel to the second direction, the second sub-pixel is arranged in the second column parallel to the second direction, and the third sub-pixel is arranged in the third column parallel to the second direction.

[0010] The first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a repeating order of the first column, the second column, and the third column.

[0011] The shape of the opening of each first sub-pixel is symmetrical about a first virtual line that passes through the center of the opening of the first sub-pixel and extends in a first direction, and is asymmetrical about a second virtual line that passes through the center of the opening of the first sub-pixel and extends in a second direction.

[0012] The shape of the opening of each second sub-pixel is obtained by rotating the opening of each first sub-pixel by 180°.

[0013] The ratio of the area of ​​the opening of the third sub-pixel to the area of ​​the opening of the first sub-pixel is approximately 0.3 to approximately 0.7.

[0014] The shape of the opening of the third sub-pixel is symmetrical about a first virtual line that passes through the center of the opening of the third sub-pixel and extends in a second direction, and is also symmetrical about a second virtual line that passes through the center of the opening of the third sub-pixel and extends in a first direction.

[0015] According to embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area and a peripheral area adjacent to the display area; and a plurality of sub-pixels located in the display area, each of the plurality of sub-pixels including an organic light-emitting device and a first transistor electrically connected to the organic light-emitting device, wherein the plurality of sub-pixels includes a first sub-pixel for emitting green light, a second sub-pixel for emitting blue light, and a third sub-pixel for emitting red light, and wherein the shape of the light-emitting area of ​​each of the first sub-pixels is symmetrical about a first virtual line extending in a first direction through the center of the light-emitting area of ​​the first sub-pixel, and asymmetrical about a second virtual line extending in a second direction perpendicular to the first direction through the center of the light-emitting area of ​​the first sub-pixel.

[0016] The shape of the light-emitting area of ​​each second sub-pixel is obtained by rotating the light-emitting area of ​​each first sub-pixel by 180°.

[0017] The shape of the light-emitting region of each third sub-pixel is symmetrical about a third virtual line that passes through the center of the light-emitting region of the third sub-pixel and extends in a first direction, and is also symmetrical about a fourth virtual line that passes through the center of the light-emitting region of the third sub-pixel and extends in a second direction.

[0018] The ratio of the size of the light-emitting region of the third sub-pixel to the size of the light-emitting region of the first sub-pixel is approximately 0.3 to approximately 0.7.

[0019] Each of the plurality of sub-pixels further includes: a conductive layer located between the organic light-emitting device and the first transistor and electrically connecting the organic light-emitting device and the first transistor to each other, and the display device further includes: a first voltage line and a second voltage line extending parallel in a first direction and each applying a first voltage to two adjacent rows of sub-pixels among the plurality of sub-pixels, wherein the two adjacent rows of sub-pixels are located between the first voltage line and the second voltage line.

[0020] The conductive layer of the sub-pixel electrically connected to the first voltage line extends toward the second voltage line in a second direction perpendicular to the first direction, and the conductive layer of the sub-pixel electrically connected to the second voltage line extends toward the first voltage line in the second direction.

[0021] Each of the multiple sub-pixels further includes: a second transistor and a third transistor, located in the same layer between the first transistor and the organic light-emitting device.

[0022] The first transistor is the driving transistor, the second transistor is the switching transistor, and the third transistor is the initialization transistor.

[0023] The first sub-pixel is arranged in the first column parallel to the second direction, the second sub-pixel is arranged in the second column parallel to the second direction, and the third sub-pixel is arranged in the third column parallel to the second direction.

[0024] The first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a repeating order of the first column, the second column, and the third column.

[0025] According to embodiments of the present disclosure, an electronic device is provided, the electronic device comprising: a display device, wherein the display device includes: a substrate including a display area and a peripheral area located outside the display area; a plurality of sub-pixels located in the display area, each of the plurality of sub-pixels including a light-emitting device, a first transistor electrically connected to the light-emitting device, and a conductive layer electrically connecting the light-emitting device and the first transistor to each other; and a first voltage line and a second voltage line extending parallel in a first direction and each applying a first voltage to two adjacent rows of sub-pixels among the plurality of sub-pixels, wherein the two adjacent rows of sub-pixels are located between the first voltage line and the second voltage line, the conductive layer of the sub-pixel electrically connected to the first voltage line extends toward the second voltage line in a second direction perpendicular to the first direction, and the conductive layer of the sub-pixel electrically connected to the second voltage line extends toward the first voltage line in the second direction. Attached Figure Description

[0026] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0027] Figure 2 It is a schematic diagram. Figure 1 The diagram shows a block diagram of the structure of the display device.

[0028] Figure 3 yes Figure 1 The equivalent circuit diagram of a sub-pixel of the display device is shown in the figure.

[0029] Figure 4 It is a schematic diagram. Figure 1 The layout of the thin-film transistors and capacitors in the sub-pixels of the display device is shown.

[0030] Figure 5 It is a schematic diagram. Figure 1 A cross-sectional view of a portion of the display device shown in the figure.

[0031] Figure 6 It is a schematic diagram. Figure 1 The diagram shows an example plan view of the openings of multiple sub-pixels in a display device.

[0032] Figure 7 It is a schematic diagram. Figure 1 The diagram shows a plan view of an example opening of the first sub-pixel of a display device.

[0033] Figure 8 It is a schematic diagram. Figure 1 The diagram shows an example of an opening in the third sub-pixel of a display device.

[0034] Figure 9 It is a schematic diagram. Figure 1 The diagram shows a plan view of an example of two adjacent sub-pixels of a display device.

[0035] Figure 10 This is a schematic view illustrating an example of an electronic device including a display device implemented as a head-mounted display according to an embodiment. Detailed Implementation

[0036] Referring now to various embodiments illustrated in the accompanying drawings, in which the same reference numerals consistently indicate the same elements. It should be noted that these embodiments may take different forms and are not limited to the description provided herein. Accordingly, the embodiments described below with reference to the accompanying drawings are merely for illustrative purposes. In this context, the term "and / or" includes any and all combinations of one or more of the listed items. When a statement such as "at least one of..." follows a list of elements, it applies to the entire list as a whole, not to individual elements of the list.

[0037] In the following embodiments, terms such as “first” and “second” are used only to distinguish one component from another and should not be construed as implying any particular order or limitation.

[0038] In the following embodiments, unless the context explicitly indicates otherwise, singular terms include plural terms.

[0039] In the following embodiments, terms such as "comprising" or "having" indicate the presence of features or components described in the specification. These terms do not preclude the possibility of adding one or more additional features or components.

[0040] In the following embodiments, when a membrane, region, component, or similar element is described as being "on" or "above" another element, this includes cases where it is directly on or above the other element and cases where another membrane, region, component, or similar element is inserted therebetween.

[0041] In the accompanying drawings, components may be exaggerated or reduced in size for ease of illustration. For example, the dimensions and thicknesses of each component depicted are shown arbitrarily for convenience and should not be construed as limiting the scope of this disclosure.

[0042] This disclosure relates to a display device designed to improve integration and resolution by utilizing an innovative arrangement of subpixels and voltage lines. The display device includes a substrate having a display area comprising subpixels, each equipped with a light-emitting device, a transistor, and a conductive layer connecting these elements. The subpixels are arranged such that their conductive layers extend alternately toward adjacent voltage lines, thereby improving electrical connectivity and preventing short circuits.

[0043] Furthermore, to improve aperture ratio, the subpixels are optimized using both asymmetrical and symmetrical aperture designs, which allows for a larger light-emitting area density. This construction not only improves resolution and integration but also reduces current density, resulting in lower power consumption and extended lifespan for the subpixels. This design is particularly suitable for devices like organic light-emitting display devices and is applicable to a wide range of applications, including head-mounted displays, smartphones, and other electronic devices.

[0044] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present disclosure. Figure 2 It is a schematic diagram. Figure 1 The block diagram of the structure of the display device shown in the figure is as follows. Figure 3 yes Figure 1 The equivalent circuit diagram of the sub-pixels of the display device shown in the figure is as follows: Figure 4 It is a schematic diagram. Figure 1 The layout of the thin-film transistors and capacitors in the sub-pixels of the display device is shown.

[0045] First, refer to Figure 1 and Figure 2 According to an embodiment, the display device 10 may include a substrate 100, which has a display area DA for displaying an image and a peripheral area PA located outside the display area DA.

[0046] Multiple scan lines SL1, ..., SLn extending in the first direction x, multiple data lines DL1, ..., DLm extending in the second direction y perpendicular to the first direction x, and multiple sub-pixels PX can be arranged in the display area DA. Here, m and n can each be a natural number greater than 0.

[0047] The wiring that applies electrical signals to multiple sub-pixels PX may include multiple scan lines SL1, ..., SLn, multiple data lines DL1, ..., DLm, etc. In an example embodiment, the multiple scan lines SL1, ..., SLn may be arranged in multiple rows extending along a first direction x to transmit scan signals to the sub-pixels PX, and the multiple data lines DL1, ..., DLm may be arranged in multiple columns extending along a second direction y to transmit data signals to the sub-pixels PX. The multiple sub-pixels PX may be located at the intersection (e.g., junction) of the multiple scan lines SL1, ..., SLn and the multiple data lines DL1, ..., DLm.

[0048] Each sub-pixel PX may include a light-emitting device and emit red, green, blue, or white light. In an example embodiment, each sub-pixel PX may include an organic light-emitting diode as the light-emitting device.

[0049] A data driver 130 for providing data signals to the display area DA, a scan driver 150 for providing scan signals to the display area DA, a voltage controller 170 for controlling the voltage applied to the display area DA, and a control unit 190 for controlling the data driver 130, the scan driver 150, and the voltage controller 170 can be arranged in the peripheral area PA.

[0050] The voltage controller 170 can generate and control the first voltage ELVDD, the common voltage ELVSS, and the initialization voltage VINT applied to the display area DA.

[0051] Therefore, the first voltage ELVDD, the common voltage ELVSS, and the initialization voltage VINT can be applied to multiple sub-pixels PX. In the example embodiment, the first voltage ELVDD can be a positive voltage, and the common voltage ELVSS can be a negative voltage or a ground voltage. In other words, the common voltage ELVSS can have a lower level than the first voltage ELVDD.

[0052] The control unit 190 can receive image signals RGB and control signals CS from an external source (e.g., a system board). The control unit 190 can convert the data format of the image signals RGB to conform to the interface specifications of the data driver 130, thereby generating image data. The control unit 190 can then provide the image data to the data driver 130 after converting the RGB data format.

[0053] The control unit 190 can generate and output a first control signal CS1 and a second control signal CS2 in response to a control signal CS provided from an external source. The first control signal CS1 can be a scan control signal, and the second control signal CS2 can be a data control signal. The first control signal CS1 can be provided to the scan driver 150. The second control signal CS2 can be provided to the data driver 130.

[0054] The scan driver 150 can generate multiple scan signals in response to the first control signal CS1. The multiple scan signals can be applied to multiple sub-pixels PX through multiple scan lines SL1, ..., SLn.

[0055] The data driver 130 can generate multiple data voltages corresponding to image data in response to the second control signal CS2. These multiple data voltages can be applied to multiple sub-pixels PX via data lines DL1, ..., DLm. The data driver 130 can simultaneously provide the data voltages generated for each sub-pixel row to the data lines DL1, ..., DLm, thereby simultaneously providing data voltages to multiple sub-pixels PX.

[0056] Multiple sub-pixels (PXs) can receive multiple data voltages in response to multiple scan signals. Multiple sub-pixels (PXs) can display an image by emitting light with brightness corresponding to the multiple data voltages. Multiple sub-pixels (PXs) can display an image by emitting light sequentially or simultaneously.

[0057] Reference Figures 1 to 3 Each of the multiple sub-pixels PX may include a first transistor T1, a second transistor T2, a third transistor T3, and a light-emitting device OLED electrically connected to the first transistor T1.

[0058] Among multiple sub-pixels PX, the sub-pixel PX connected to the i-th scan line 155 of multiple scan lines SL1, ..., SLn and the j-th data line 131 of multiple data lines DL1, ..., DLm can be called the n-th sub-pixel PXn. In this respect, i and j can be natural numbers greater than 0.

[0059] The i-th scan line may include a first scan line 151 and a second scan line 152. The first scan line 151 and the second scan line 152 may respectively transmit scan signals GWi and GC to the n-th sub-pixel PXn.

[0060] The j-th data line 131 can transmit the data voltage VDATA to the n-th sub-pixel PXn. The data voltage VDATA can have a voltage level corresponding to the image signal RGB input to the display device 10.

[0061] The first voltage line 173 can transmit the first voltage ELVDD to the nth sub-pixel PXn, the common voltage line 177 can transmit the common voltage ELVSS to the nth sub-pixel PXn, and the initialization voltage line 174 can transmit the initialization voltage VINT to the nth sub-pixel PXn.

[0062] In this embodiment, the first transistor T1 may be a P-type transistor comprising a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, this is merely an example, and the first transistor T1 may also be an N-type transistor.

[0063] The second transistor T2 and the third transistor T3 can each be a P-type transistor with an oxide semiconductor layer. However, this is merely an example, and the second transistor T2 and / or the third transistor T3 can be N-type transistors.

[0064] The first transistor T1 may include a first gate electrode, a first driving electrode, and a second driving electrode. The first gate electrode of the first transistor T1 may be connected to a first node N1, the first driving electrode of the first transistor T1 may be connected to a first voltage line 173, and the second driving electrode of the first transistor T1 may be connected to a second node N2. The first transistor T1 may be referred to as a driving transistor.

[0065] The second transistor T2 may include a second gate electrode or a second sub-gate electrode, a first switching electrode, and a second switching electrode. The second gate electrode or the second sub-gate electrode of the second transistor T2 may be connected to the first scan line 151, the first switching electrode of the second transistor T2 may be connected to the first node N1, and the second switching electrode of the second transistor T2 may be connected to the third node N3. The second transistor T2 may be referred to as a switching transistor, a scanning transistor, etc.

[0066] The third transistor T3 may include a third gate electrode or a third sub-gate electrode, a first initialization electrode, and a second initialization electrode. The third gate electrode or the third sub-gate electrode of the third transistor T3 may be connected to the second scan line 152, the first initialization electrode of the third transistor T3 may be connected to the third node N3, and the second initialization electrode of the third transistor T3 may be connected to the second node N2. The third transistor T3 may be referred to as an initialization transistor.

[0067] In an embodiment, each of the plurality of sub-pixels PX may further include a first capacitor Cst and a second capacitor Cpr.

[0068] The first electrode of the first capacitor Cst can be connected to the first node N1, and the second electrode of the first capacitor Cst can be connected to the initialization voltage line 174. The first capacitor Cst can be referred to as a storage capacitor.

[0069] The first capacitor Cst can store the voltage between the first node N1 and the initialization voltage line 174. The drive current flowing through the first transistor T1 can be determined by the voltage stored in the first capacitor Cst. The light-emitting device OLED can emit light based on the drive current.

[0070] The first electrode of the second capacitor Cpr can be connected to the third node N3, and the second electrode of the second capacitor Cpr can be connected to the j-th data line 131.

[0071] The second capacitor Cpr can store the voltage between the third node N3 and the j-th data line 131. In some embodiments, the second capacitor Cpr can also initialize the first voltage ELVDD through the second node N2 and the third transistor T3. For example, the second capacitor Cpr can stabilize and initialize the voltage of the second node N2 by coupling its stored charge. As a result, the voltage of the second node N2 can be matched with the first voltage ELVDD.

[0072] The first electrode of the OLED can be connected to the second node N2, and the second electrode of the OLED can be connected to the common voltage line 177. The first electrode of the OLED can be referred to as the anode electrode or pixel electrode, and the second electrode of the OLED can be referred to as the cathode electrode or common electrode.

[0073] Reference Figure 4 The nth sub-pixel PXn may include a first voltage line 173, a first scan line 151, a second scan line 152, and an initialization voltage line 174 extending in the first direction x.

[0074] In some embodiments, the second gate electrode or second sub-gate electrode of the second transistor T2 of the nth sub-pixel PXn can be connected to the first scan line 151 of the i-th scan line 155, the third gate electrode or third sub-gate electrode of the third transistor T3 of the nth sub-pixel PXn can be connected to the second scan line 152 of the i-th scan line 155, and the first driving electrode of the first transistor T1 of the nth sub-pixel PXn can be connected to the first voltage line 173 to which the first voltage ELVDD is applied.

[0075] The second electrode of the first capacitor Cst of the nth sub-pixel PXn can be connected to the initialization voltage line 174 to which the initialization voltage VINT is applied, and the second electrode of the second capacitor Cpr of the nth sub-pixel PXn can be connected to the jth data line 131 to which the data voltage VDATA is applied.

[0076] In an embodiment, the i-th scan signal GWi transmitted to the n-th sub-pixel PXn via the first scan line 151 can be sequentially generated in the scan driver 150.

[0077] In some embodiments, the i-th scan signal GC transmitted to the nth sub-pixel PXn via the second scan line 152 may be a global gate signal used to synchronize multiple sub-pixels PX. However, this is not limited to this, and in another embodiment, the i-th scan signal GC transmitted via the second scan line 152 may be generated sequentially in the scan driver 150.

[0078] In an embodiment, the longitudinal direction of the first scan line 151, the second scan line 152, the first voltage line 173, and the initialization voltage line 174 connected to the nth sub-pixel PXn can be parallel to the first direction x.

[0079] In some embodiments, the j-th data line 131 for applying the data voltage VDATA to the n-th sub-pixel PXn can extend in a second direction y perpendicular to the first direction x.

[0080] Figure 5 It is a schematic diagram. Figure 1 A cross-sectional view of a portion of the display device is shown. For example, Figure 5 It can be shown Figures 1 to 4 An example of a subpixel PX shown in the diagram.

[0081] Reference Figure 5 Together Figures 2 to 4 According to the embodiment, the sub-pixel PX may include a substrate 100, a first transistor T1 on the substrate 100, a second transistor T2 and a third transistor T3 on the first transistor T1, a light-emitting device 400 located on the second transistor T2 and the third transistor T3 and electrically connected to the first transistor T1, a first capacitor Cst, and a second capacitor Cpr. The second transistor T2 and the third transistor T3 may be located on the same layer.

[0082] More specifically, substrate 100 may be made of a transparent glass material containing silicon dioxide (SiO2) as a main component. However, it is not limited to this, and substrate 100 may include a transparent plastic material. The transparent plastic material may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide, polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc.

[0083] The first semiconductor layer 510 may be formed on the substrate 100. The first semiconductor layer 510 may include a first source region 511, a first drain region 513, and a first channel region 512 between the first source region 511 and the first drain region 513.

[0084] In some embodiments, the first semiconductor layer 510 may include a first source region 511 and a first drain region 513 formed by doping impurities on both sides of the first channel region 512. In embodiments, the impurities may vary depending on the type of the first transistor T1 and may include N-type or P-type impurities. In other words, the first channel region 512, the first source region 511 located on a first side of the first channel region 512, and the first drain region 513 located on a second side of the first channel region 512 are referred to as the first semiconductor layer 510.

[0085] In some cases, the first source region 511 and the first drain region 513, which are doped with impurities, can be interpreted as the source electrode (or the first driving electrode) and the drain electrode (or the second driving electrode) of the first transistor T1, respectively. In some embodiments, the positions of the first source region 511 and the first drain region 513 can be interchanged depending on the type of impurities doped into the first semiconductor layer 510.

[0086] The first semiconductor layer 510 may include polysilicon. For example, the first semiconductor layer 510 may include low-temperature polysilicon (LTPS), but is not limited thereto, and the first semiconductor layer 510 may include semiconductor oxide.

[0087] In an alternative embodiment, a buffer layer may be located between the substrate 100 and the first semiconductor layer 510. The buffer layer can prevent impurity diffusion during the crystallization process used to form polycrystalline silicon, thereby improving its properties, and can also provide a flat surface.

[0088] A first insulating layer I1 may be formed on the first semiconductor layer 510 to cover the first semiconductor layer 510. A first conductive layer including a first gate electrode 520 may be formed on the first insulating layer I1. In a plan view, the area of ​​the first gate electrode 520 may be larger than the area of ​​the first channel region 512 of the first transistor T1.

[0089] The first gate electrode 520, together with the first semiconductor layer 510, can form a first transistor T1. The first transistor T1 can receive a first voltage ELVDD in the first source region 511 to provide a drive current to the light-emitting device 400.

[0090] In some embodiments, the first gate electrode 520 may function as the first electrode 520 of the first capacitor Cst. Accordingly, increasing the integration level of the display device 10 allows the first capacitor Cst and the first transistor T1 to have larger areas, thereby enabling the provision of high-quality images. However, this disclosure is not limited thereto. In another embodiment, the first electrode 520 of the first capacitor Cst may be a separate component independent of the first gate electrode 520 of the first transistor T1.

[0091] A second insulating layer I2 may be formed on the first conductive layer to cover the first conductive layer. A second conductive layer, including the second electrode 530 of the first capacitor Cst, may be formed on the second insulating layer I2. The second electrode 530 and the first electrode 520 of the first capacitor Cst may be formed together to form the first capacitor Cst.

[0092] A third insulating layer I3 may be formed on the second conductive layer to cover the second conductive layer. A third conductive layer, including the first scan line 151 and the second scan line 152 to which scan signals GWi and GC are respectively applied, may be formed on the third insulating layer I3.

[0093] A fourth insulating layer I4 may be formed on the third conductive layer to cover the third conductive layer. A second semiconductor layer 550 may be formed on the fourth insulating layer I4. The second semiconductor layer 550 may include a second source region 551, a second channel region 552, a second drain region 553, a third source region 553, a third channel region 554, and a third drain region 555.

[0094] The second channel region 552 may be located between the second source region 551 and the second drain region 553, and the third channel region 554 may be located between the third source region 553 and the third drain region 555. In some embodiments, the second drain region 553 and the third source region 553 may refer to the same region.

[0095] Depending on the impurities doped into the second semiconductor layer 550, the positions of the second source region 551 and the second drain region 553 can be interchanged. Similarly, the positions of the third source region 553 and the third drain region 555 can also be interchanged based on the impurities doped into the second semiconductor layer 550.

[0096] The second semiconductor layer 550 may be a layer comprising a semiconductor oxide, but is not limited thereto, and the second semiconductor layer 550 may also be a layer comprising, for example, low-temperature polycrystalline silicon (LTPS).

[0097] A fifth insulating layer I5 may be formed on the second semiconductor layer 550 to cover the second semiconductor layer 550. A fourth conductive layer may be formed on the fifth insulating layer I5 to include a plurality of contacts CNT1, CNT2, CNT3 and CNT4, a second gate electrode 571 and a third gate electrode 572.

[0098] The second gate electrode 571 and the third gate electrode 572 may overlap with the second channel region 552 and the third channel region 554, respectively. The second gate electrode 571 may form a second transistor T2 together with the second source region 551, the second channel region 552, and the second drain region 553. In some embodiments, the third gate electrode 572 may form a third transistor T3 located on the same layer as the second transistor T2 together with the third source region 553, the third channel region 554, and the third drain region 555.

[0099] In an embodiment, the first scan line 151 and the second scan line 152 located on the third insulating layer I3 between the first transistor T1 and the second transistor T2 and disposed on the same layer can be referred to as the second sub-gate electrode 151 and the third sub-gate electrode 152, respectively.

[0100] The second sub-gate electrode 151 and the second gate electrode 571, along with the third sub-gate electrode 152 and the third gate electrode 572, can respectively form the dual gate of the second transistor T2 and the dual gate of the third transistor T3. As a result, scan signals GWi and GC can be applied to the second transistor T2 and the third transistor T3, respectively.

[0101] In a plan view, the second sub-gate electrode 151 may overlap with the second gate electrode 571, and the area of ​​the second sub-gate electrode 151 may be larger than the area of ​​the second gate electrode 571. In some embodiments, in a plan view, the third sub-gate electrode 152 may overlap with the third gate electrode 572, and the area of ​​the third sub-gate electrode 152 may be larger than the area of ​​the third gate electrode 572.

[0102] When the second transistor T2 and the third transistor T3 include dual gates, the current flowing through these transistors can be controlled more precisely, and their switching speed can be improved due to the interaction of the dual gates. This allows the second transistor T2 and the third transistor T3 to operate with lower power consumption.

[0103] A sixth insulating layer I6 may be formed on the fourth conductive layer to cover the fourth conductive layer. A fifth conductive layer, including multiple contacts CNT5 and CNT6 and the first electrode 581 of the second capacitor Cpr, may be formed on the sixth insulating layer I6.

[0104] The first electrode 581 of the second capacitor Cpr can be electrically connected between the second channel region 552 and the third channel region 554 of the second semiconductor layer 550 through a contact hole. The contact hole can expose at least a portion of the region between the second channel region 552 and the third channel region 554.

[0105] In other words, the first electrode 581 of the second capacitor Cpr can be connected to the second transistor T2 and the third transistor T3 through a single contact hole, instead of being electrically connected through two different contact holes, in order to improve the integration of the display device 10.

[0106] The fifth contact CNT5 can be electrically connected to the first gate electrode 520 via the third contact CNT3 on the fifth insulating layer I5. In some embodiments, the fifth contact CNT5 can be electrically connected to the second source region 551 of the second transistor T2. Accordingly, the fifth contact CNT5, the first gate electrode 520, and the second source region 551 can be electrically connected to each other. For example, the fifth contact CNT5 can be... Figure 3 The first node N1 is shown in the figure.

[0107] A seventh insulating layer I7 may be formed on the fifth conductive layer to cover the fifth conductive layer. A sixth conductive layer, including the second electrode 590 of the second capacitor Cpr, may be formed on the seventh insulating layer I7.

[0108] The second electrode 590 of the second capacitor Cpr may overlap with the first electrode 581 of the second capacitor Cpr. In some embodiments, the second electrode 590 of the second capacitor Cpr may form the second capacitor Cpr together with the first electrode 581 of the second capacitor Cpr.

[0109] In some embodiments, the second electrode 590 of the second capacitor Cpr may include a data line 131 to which a data voltage VDATA is applied.

[0110] An eighth insulating layer I8 may be formed on the sixth conductive layer to cover the sixth conductive layer. A seventh conductive layer, including a first voltage line 173 to which a first voltage ELVDD is applied, an initialization voltage line 174 to which an initialization voltage VINT is applied, and a seventh contact CNT7, may be formed on the eighth insulating layer I8.

[0111] The first voltage line 173 can be connected to the first source region 511 of the first transistor T1 via the first contact CNT1 on the fifth insulating layer I5. Accordingly, the first voltage ELVDD can be applied to the first source region 511 of the first transistor T1.

[0112] The initialization voltage line 174 can be connected to the second electrode 530 of the first capacitor Cst via the second contact CNT2 on the fifth insulating layer l5. Accordingly, the first capacitor Cst can store the initialization voltage VINT.

[0113] Each of the first insulating layer I1, the second insulating layer I2, the third insulating layer I3, the fourth insulating layer I4, the fifth insulating layer I5, the sixth insulating layer I6, the seventh insulating layer I7, and the eighth insulating layer I8 may include silicon nitride and / or silicon oxide.

[0114] The ninth insulating layer I9 may be formed on the seventh conductive layer to cover the seventh conductive layer. The eighth conductive layer, including the eighth contact CNT8, may be formed on the ninth insulating layer I9.

[0115] The eighth contact CNT8 can be electrically connected to the seventh contact CNT7 located on the eighth insulating layer I8. The seventh contact CNT7 can be electrically connected to the sixth contact CNT6 located on the sixth insulating layer I6. In some embodiments, the sixth contact CNT6 can be electrically connected to the third drain region 555 of the third transistor T3, and the sixth contact CNT6 can be electrically connected to the first drain region 513 of the first transistor T1 via the fourth contact CNT4 located on the fifth insulating layer I5. In some embodiments, the eighth contact CNT8 can be electrically connected to the pixel electrode 410 of the light-emitting device 400.

[0116] In other words, the pixel electrode 410 of the light-emitting device 400 can be electrically connected to the first drain region 513 of the first transistor T1 and the third drain region 555 of the third transistor T3 via the eighth contact CNT8. For example, the eighth contact CNT8 can be... Figure 3 The second node N2 is shown in the diagram.

[0117] The tenth insulating layer I10 can be formed on the eighth conductive layer to cover the eighth conductive layer. A light-emitting device 400, including a pixel electrode 410, a common electrode 430, and an intermediate layer 420 having an emission layer disposed between the pixel electrode 410 and the common electrode 430, can be located on the tenth insulating layer I10. The light-emitting device 400 can be, for example, an organic light-emitting diode comprising organic materials.

[0118] In one embodiment, the pixel electrode 410 may be the anode of an organic light-emitting diode (OLED), and the common electrode 430 may be the cathode of an OLED. However, this disclosure is not limited thereto, and depending on the driving method of the display device 10, the pixel electrode 410 may be the cathode of an OLED, and the common electrode 430 may be the anode of an OLED. Holes and electrons are injected into the intermediate layer 420 from the pixel electrode 410 and the common electrode 430, respectively. The injected holes and electrons recombine to form excitons, which transition from the excited state to the ground state, thereby emitting light in the process.

[0119] The ninth insulating layer I9 and the tenth insulating layer I10 may each comprise organic materials such as imide polymers, general polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having phenol groups, acrylic polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers and blends thereof, or may comprise stacked layers of organic and inorganic materials.

[0120] The first to eighth conductive layers may each include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0121] In embodiments, the pixel electrode 410 may be a (semi-)transparent electrode or a reflective electrode. When the pixel electrode 410 is a (semi-)transparent electrode, it may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). When the pixel electrode 410 is a reflective electrode, it may include a reflective layer comprising one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and their compounds, as well as a layer comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). However, this disclosure is not limited thereto, and the pixel electrode 410 may include various materials, and its structure may be modified in various ways, such as single-layer structures and multi-layer structures.

[0122] A pixel defining layer 350 covering the peripheral portion of pixel electrode 410 may be disposed on a tenth insulating layer I10. The pixel defining layer 350 may have an opening corresponding to each pixel and exposing at least a portion of pixel electrode 410 therethrough, thereby defining the pixel. In embodiments, the opening may be a light-emitting region. In some embodiments, the pixel defining layer 350 may increase the distance between the common electrode 430 and the peripheral portion of pixel electrode 410 to prevent arcing therebetween. The pixel defining layer 350 may comprise organic materials such as polyimide and hexamethyldisiloxane (HMDSO).

[0123] Intermediate layer 420 can be formed on the portion of pixel electrode 410 exposed through the opening of pixel defining layer 350. Intermediate layer 420 can include low molecular weight or high molecular weight materials. When including low molecular weight materials, intermediate layer 420 can have a single structure or a composite structure of stacked hole injection layer (HIL), hole transport layer (HTL), emitter layer (EML), electron transport layer (ETL), and electron injection layer (EIL), and can include various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), and aluminum tri-8-hydroxyquinoline (Alq3). These layers can be formed by vacuum deposition processes.

[0124] When high molecular weight materials are included, the intermediate layer 420 may have a structure comprising a hole transport layer (HTL) and an emitter layer (EML). In embodiments, the hole transport layer may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the emitter layer may comprise polymeric materials such as polyphenylene acetylene (PPV) and polyfluorene. The structure of the intermediate layer 420 is not limited thereto, and the intermediate layer 420 may have various structures. For example, the intermediate layer 420 may comprise an integral layer across a plurality of pixel electrodes 410 or a patterned layer corresponding to each of the plurality of pixel electrodes 410.

[0125] A common voltage ELVSS can be applied to a common electrode 430, and the common electrode 430 can cover the entire display area. Figure 1The common electrode 430 can be integrally formed to cover multiple intermediate layers 420. The common electrode 430 can be a (semi-)transparent electrode or a reflective electrode. When it is a (semi-)transparent electrode, the common electrode 430 can include a material layer with a small work function, such as lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg) and their compounds (e.g., lithium fluoride (LiF)) or a material having a multilayer structure such as lithium fluoride (LiF) / calcium (Ca) or lithium fluoride (LiF) / aluminum (Al), and a (semi-)transparent conductive layer comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), etc. When it is a reflective electrode, the common electrode 430 may comprise a layer of material containing lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg) and their compounds (e.g., lithium fluoride (LiF)) or having a multilayer structure such as lithium fluoride (LiF) / calcium (Ca) or lithium fluoride (LiF) / aluminum (Al). However, the composition and materials of the common electrode 430 are not limited thereto, and various modifications are possible.

[0126] Figure 6 It is a schematic diagram. Figure 1 A plan view showing an example of openings for multiple sub-pixels in a display device. Figure 7 It is a schematic diagram. Figure 1 The plan view shows an example of the opening of the first sub-pixel of the display device, and Figure 8 It is a schematic diagram. Figure 1 The diagram shows an example of an opening in the third sub-pixel of a display device.

[0127] Reference Figures 6 to 8 Multiple sub-pixels PX may include a first sub-pixel P1 that emits green light, a second sub-pixel P2 that emits blue light, and a third sub-pixel P3 that emits red light.

[0128] The first sub-pixel P1 can be arranged in the first column C1 parallel to the second direction y, the second sub-pixel P2 can be arranged in the second column C2 parallel to the second direction y, and the third sub-pixel P3 can be arranged in the third column C3 parallel to the second direction y.

[0129] In one embodiment, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be arranged in a repeating order along the first column C1, the second column C2, and the third column C3. In other words, the first sub-pixel P1 in the first column C1, the second sub-pixel P2 in the second column C2, and the third sub-pixel P3 in the third column C3 can be arranged sequentially in the first direction x. This arrangement can then be repeated sequentially along the first direction x. However, this is merely an example and does not limit the arrangement order of the sub-pixels PX. In another embodiment, the second sub-pixel P2, the first sub-pixel P1, and the third sub-pixel P3 can be arranged sequentially in the first direction x.

[0130] Typically, the aperture ratio is defined as the ratio of the area of ​​the aperture OP of a sub-pixel PX in a planar diagram to the total area of ​​a single pixel. A single pixel may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3, thereby representing the smallest repeating unit in the display area DA.

[0131] When the aperture OP of a sub-pixel PX is shaped as a regular hexagon, the combined aperture ratio of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 within a single pixel can be approximately 0.2 to approximately 0.3. However, if the aperture OP is not shaped as a regular hexagon, the pixel density can be increased, resulting in a combined aperture ratio of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 within a single pixel of approximately 0.35 to approximately 0.5. Accordingly, the light-emitting regions of the multiple sub-pixels PX form a dense structure, thereby improving the integration level and resolution of the display device 10.

[0132] As the sum of the aperture ratios of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 in a single pixel increases, the current density required to emit light of the same intensity from the sub-pixel PX decreases. Therefore, the electrical energy consumed by the sub-pixel PX is reduced, resulting in an extended lifespan for the sub-pixel PX. For example, when the apertures OP of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are not formed into regular hexagons, the lifespan of the display device can be more than doubled compared to when the apertures OP of all sub-pixels PX are regular hexagons.

[0133] When the openings OP of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are not formed into regular hexagons, the aperture ratio of the first sub-pixel P1 can be approximately 0.1 to approximately 0.2, the aperture ratio of the second sub-pixel P2 can be approximately 0.1 to approximately 0.2, and the aperture ratio of the third sub-pixel P3 can be approximately 0.05 to approximately 0.1. In some embodiments, the ratio of the area of ​​the opening OP of the third sub-pixel P3 to the area of ​​the opening OP of the first sub-pixel P1 can be approximately 0.3 to approximately 0.7.

[0134] The shape of the opening OP of the first sub-pixel P1 does not have to be a regular hexagon. In an embodiment, the opening OP of the first sub-pixel P1 may have a shape that is symmetrical about a virtual line il1 that passes through the center O1 of the opening OP and extends in a first direction x, but asymmetrical about a virtual line il2 that passes through the center O1 and extends in a second direction y perpendicular to the first direction x.

[0135] In some embodiments, the angles between two adjacent sides of the opening OP of the first sub-pixel P1 on one side of the virtual line il1 extending in the first direction x are represented as θ1, θ2, and θ3 in clockwise order. In this configuration, angles θ2 and θ3 are substantially the same, while angle θ1 is different from angle θ2. In other words, the opening OP of the first sub-pixel P1 may have a shape in which a portion of a regular hexagon is removed along one side parallel to the second direction y.

[0136] However, this disclosure is not limited to this construction. Angles θ1, θ2, and θ3 can be different from each other, and the aperture OP of the first sub-pixel P1 can take other shapes as long as the aperture ratio is higher than that of a regular hexagonal shape. This allows for improved density of sub-pixels PX.

[0137] In another embodiment, the shape of the opening OP of the first sub-pixel P1 may be symmetrical about a virtual line il2 that passes through the center O1 of the opening OP and extends in the second direction y, but asymmetrical about a virtual line il1 that passes through the center O1 and extends in the first direction x perpendicular to the second direction y.

[0138] In another embodiment, the shape of the opening OP of the first sub-pixel P1 may be asymmetrical with respect to a virtual line il1 that passes through the center O1 of the opening OP and extends in a first direction x, and also asymmetrical with respect to a virtual line il2 that passes through the center O1 and extends in a second direction y perpendicular to the first direction x.

[0139] The aperture OP of the second sub-pixel P2 may not have a regular hexagonal shape. In an embodiment, the shape of the aperture OP of the second sub-pixel P2 is the same as the shape of the aperture OP of the first sub-pixel P1, but rotated 180° clockwise. However, this disclosure is not limited thereto. For example, the aperture OP of the second sub-pixel P2 can take any shape as long as its aperture ratio is higher than that of a regular hexagonal shape, thereby improving the density of sub-pixel PX. In another embodiment, the shape of the aperture OP of the second sub-pixel P1 may be independent of the shape of the first sub-pixel P1.

[0140] The shape of the opening OP of the third sub-pixel P3 does not have to be a regular hexagon. In an embodiment, the shape of the opening OP of the third sub-pixel P3 can be symmetrical about a virtual line il3 that passes through the center O2 of the opening OP of the third sub-pixel P3 and extends in the first direction x, and about a virtual line il4 that passes through the center O2 of the opening OP of the third sub-pixel P3 and extends in the second direction y perpendicular to the first direction x. However, this disclosure is not limited thereto. For example, the opening OP of the third sub-pixel P3 can take any shape as long as the aperture ratio of the opening OP of the third sub-pixel P3 is higher than that of a regular hexagonal shape, thereby increasing the density of the sub-pixel PX. Specifically, the opening OP of the third sub-pixel P3 can have a shape in which a regular hexagon is stretched in the second direction y.

[0141] In another embodiment, the shape of the opening OP of the third sub-pixel P3 may be asymmetrical about a virtual line il3 that passes through the center O2 of the opening OP of the third sub-pixel P3 and extends in the first direction x, and also asymmetrical about a virtual line il4 that passes through the center O2 of the opening OP of the third sub-pixel P3 and extends in the second direction y perpendicular to the first direction x.

[0142] Figure 9 It is a schematic diagram. Figure 1 The diagram shows a plan view of an example of two adjacent sub-pixels of a display device.

[0143] Reference Figure 9 Together Figure 5 The first voltage line 173 to which the first voltage ELVDD is applied can be parallel to the second voltage line 173a to which the first voltage ELVDD is applied. In an embodiment, the first voltage line 173 and the second voltage line 173a can be repeatedly arranged in the second direction y. Accordingly, the first voltage line 173 and the second voltage line 173a can respectively apply the first voltage ELVDD to two adjacent rows of sub-pixels PX located between the first voltage line 173 and the second voltage line 173a.

[0144] In some embodiments, the extension direction of the eighth conductive layer, including the eighth contact CNT8 for electrically connecting the light-emitting device 400 to the first transistor T1, may be opposite to each other in two adjacent rows of sub-pixels PX among a plurality of sub-pixels PX.

[0145] In some embodiments, the eighth conductive layer of the sub-pixel PX electrically connected to the first voltage line 173 may extend toward the second voltage line 173a in a second direction y perpendicular to the first direction x, and the eighth conductive layer of the sub-pixel PX electrically connected to the second voltage line 173a may extend toward the first voltage line 173 in the second direction y.

[0146] As described above, when the aperture OP of a sub-pixel PX is not a regular hexagon, the aperture ratio can be increased, and correspondingly, the degree of integration of a single pixel can be increased. However, if multiple sub-pixels PX do not include an eighth conductive layer extending in different directions, and the seventh contact CNT7, which is located on the same layer as the first voltage line 173 and the second voltage line 173a, is directly connected to the pixel electrode 410 through a contact hole, then the seventh contact CNT7, the first voltage line 173, and the second voltage line 173a may come into contact with each other and become electrically short-circuited due to the high pixel density.

[0147] In some embodiments, with Figure 9 The structure shown in the diagram is different. When the eighth conductive layer of the sub-pixel PX, which is electrically connected to the first voltage line 173, does not extend toward the second voltage line 173a in the second direction y, but extends toward the first voltage line 173, the seventh contact CNT7 connected to the eighth contact CNT8 can become electrically short-circuited by contacting the first voltage line 173, which is located on the same layer as the seventh contact CNT7.

[0148] Accordingly, when the eighth contact CNT8 extends in different directions in adjacent pixel rows, the aforementioned electrical short circuit can be prevented. Simultaneously, due to the denser structure of the light-emitting regions in the multiple sub-pixels PX, the integration level and resolution of the display device 10 can be improved.

[0149] Figure 10 This is a schematic view illustrating an example of an electronic device including a display apparatus according to an embodiment, implemented as a head-mounted display.

[0150] Reference Figure 10 The electronic device according to the embodiment may include a display device and may be implemented as a head-mounted display (HMD) 800. The HMD 800 may include a display unit 810, a main unit 820, and a mounting unit 830.

[0151] In an embodiment, the display unit 810 may include components for implementing a screen, according to... Figures 1 to 9 The display device 10 of the embodiment. The main unit 820 may include a controller, a touch sensor, an acoustic sensor, etc., for applying scan signals and data signals to the display unit 810. The HMD 800 can be mounted on a user via the mounting unit 830.

[0152] However, this is for illustrative purposes, and the electronic device is not limited to the HMD 800. For example, the electronic device can be any device with a combined display such as a virtual reality (VR) device, mobile phone, smartphone, digital TV, 3D TV, personal computer (PC) (e.g., tablet computer, laptop computer), home electronics, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation device, etc.

[0153] According to the embodiments, since the light-emitting areas of the sub-pixels form a denser structure, the integration level and resolution of the display device can be improved.

[0154] However, the effects achievable through this disclosure are not limited to those described above, and those skilled in the art will readily understand from the provided description other technical effects not explicitly mentioned.

[0155] Although this disclosure has been described with reference to specific embodiments and accompanying drawings, it is not limited thereto. As will be apparent to those skilled in the art, various modifications and variations can be made within the scope of the technical concept of this disclosure and within the equivalents of the outlined claims.

Claims

1. A display device comprising: a substrate including a display region and a peripheral region adjacent to the display region; a plurality of subpixels located in the display region, each of the plurality of subpixels including a light emitting device, a first transistor electrically connected to the light emitting device, and a conductive layer electrically connecting the light emitting device and the first transistor; and a first voltage line and a second voltage line extending in parallel in a first direction and each applying a first voltage to subpixels of two adjacent rows among the plurality of subpixels, wherein the subpixels of the two adjacent rows are located between the first voltage line and the second voltage line, the conductive layer of the subpixels connected to the first voltage line extends toward the second voltage line in a second direction perpendicular to the first direction, and the conductive layer of the subpixels connected to the second voltage line extends toward the first voltage line in the second direction.

2. The display device according to claim 1, wherein the light emitting device includes a pixel electrode, a common electrode, and an intermediate layer located between the pixel electrode and the common electrode, wherein the light emitting device includes an organic material, and the pixel electrode is electrically connected to the conductive layer.

3. The display device according to claim 2, further comprising: a pixel defining layer covering a portion of the pixel electrode, the pixel defining layer defining an opening.

4. The display device according to claim 3, wherein the plurality of subpixels include first subpixels for emitting green light, second subpixels for emitting blue light, and third subpixels for emitting red light.

5. The display device according to claim 4, wherein the first subpixels are arranged in a first column parallel to the second direction, the second subpixels are arranged in a second column parallel to the second direction, and the third subpixels are arranged in a third column parallel to the second direction.

6. The display device according to claim 5, wherein the first subpixels, the second subpixels, and the third subpixels are arranged in a repeating order of the first column, the second column, and the third column.

7. The display device according to claim 4, wherein a shape of the opening of each of the first subpixels is symmetrical about a first virtual line passing through a center of the opening of the first subpixel and extending in the first direction, and asymmetrical about a second virtual line passing through the center of the opening of the first subpixel and extending in the second direction.

8. The display device according to claim 7, wherein a shape of the opening of each of the second subpixels is obtained by rotating the opening of each of the first subpixels by 180°.

9. The display device according to claim 4, wherein a ratio of an area of the opening of the third subpixel to an area of the opening of the first subpixel is 0.3 to 0.

7.

10. The display device according to claim 4, wherein ​ A shape of the opening of the third sub-pixel is symmetrical with respect to a first virtual line passing through a center of the opening of the third sub-pixel and extending in the second direction, and symmetrical with respect to a second virtual line passing through the center of the opening of the third sub-pixel and extending in the first direction. 11.A display device comprising: a substrate including a display area and a peripheral area adjacent to the display area; and a plurality of sub-pixels located in the display area, each of the plurality of sub-pixels including an organic light emitting device and a first transistor electrically connected to the organic light emitting device, wherein the plurality of sub-pixels include first sub-pixels for emitting green light, second sub-pixels for emitting blue light, and third sub-pixels for emitting red light, and wherein a shape of a light emitting area of each of the first sub-pixels is symmetrical with respect to a first virtual line passing through a center of the light emitting area of the first sub-pixel and extending in a first direction, and asymmetrical with respect to a second virtual line passing through the center of the light emitting area of the first sub-pixel and extending in a second direction perpendicular to the first direction. 12.The display device of claim 11, wherein a shape of a light emitting area of each of the second sub-pixels is obtained by rotating the light emitting area of each of the first sub-pixels by 180°. 13.The display device of claim 11, wherein a shape of a light emitting area of each of the third sub-pixels is symmetrical with respect to a third virtual line passing through a center of the light emitting area of the third sub-pixel and extending in the first direction, and symmetrical with respect to a fourth virtual line passing through the center of the light emitting area of the third sub-pixel and extending in the second direction. 14.The display device of claim 11, wherein a ratio of a size of the light emitting area of the third sub-pixel to a size of the light emitting area of the first sub-pixel is 0.3 to 0.

7. 15.The display device of claim 11, wherein each of the plurality of sub-pixels further includes a conductive layer located between the organic light emitting device and the first transistor and electrically connecting the organic light emitting device and the first transistor to each other, and the display device further includes first and second voltage lines extending in parallel in the first direction and each applying a first voltage to sub-pixels of two adjacent rows among the plurality of sub-pixels, wherein the sub-pixels of the two adjacent rows are located between the first voltage line and the second voltage line. 16.The display device of claim 15, wherein the conductive layer of the sub-pixel electrically connected to the first voltage line extends toward the second voltage line in the second direction perpendicular to the first direction, and the conductive layer of the sub-pixel electrically connected to the second voltage line extends toward the first voltage line in the second direction. 17.The display device of claim 15, each of the plurality of sub-pixels further includes: A second transistor and a third transistor are located in the same layer between the first transistor and the organic light-emitting device.

18. The display device according to claim 17, wherein The first transistor is a driver transistor, the second transistor is a switch transistor, and the third transistor is an initialization transistor.

19. The display device according to claim 11, wherein The first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a repeating order of the first column, the second column, and the third column.

20. An electronic device comprising the display device according to any one of claims 1 to 19.

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