Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a first active layer disposed on a substrate and including a first driving channel portion and a second driving channel portion spaced apart from the first driving channel portion; a first gate pattern disposed on the first active layer, overlapping each of the first driving channel portion and the second driving channel portion in a plan view, and exposing a portion of the first active layer disposed between the first driving channel portion and the second driving channel portion; a second gate pattern disposed on the first gate pattern, overlapping the first gate pattern in a plan view, and exposing a portion of the first gate pattern; and a light emitting element disposed on the second gate pattern.

Description

TECHNICAL FIELD

[0001] Embodiments relate to display apparatuses and electronic apparatuses. More particularly, embodiments relate to display apparatuses and electronic apparatuses that provide visual information. BACKGROUND

[0002] A display apparatus can include a plurality of pixels. Each of the plurality of pixels can include a plurality of transistors including a driving transistor, a capacitor, and a light emitting element, etc. The driving transistor included in each pixel can generate a driving current, and the light emitting element included in each pixel can emit light with a luminance corresponding to a magnitude of the driving current. A voltage-current characteristic of the driving transistor can have a hysteresis characteristic that varies depending on an operating state of the driving transistor in a previous display frame. Since the hysteresis characteristic is related to a problem of a residual image remaining on a screen of the display apparatus, research is currently being conducted to improve the hysteresis characteristic of the display apparatus (e.g., the driving transistor). SUMMARY

[0003] Embodiments provide display apparatuses with improved display quality.

[0004] A display apparatus according to an embodiment includes a first active layer disposed on a substrate and including a first driving channel portion and a second driving channel portion spaced apart from the first driving channel portion, a first gate pattern disposed on the first active layer, overlapping each of the first driving channel portion and the second driving channel portion in a plan view, and exposing a portion of the first active layer disposed between the first driving channel portion and the second driving channel portion, a second gate pattern disposed on the first gate pattern, overlapping the first gate pattern in the plan view, and exposing a portion of the first gate pattern, and a light emitting element disposed on the second gate pattern.

[0005] In an embodiment, the display apparatus can further include a bottom metal layer disposed between the substrate and the first active layer in a cross-sectional view, and overlapping each of the first driving channel portion and the second driving channel portion in the plan view.

[0006] In an embodiment, the bottom metal layer can expose at least a portion of a back surface of the portion of the first active layer disposed between the first driving channel portion and the second driving channel portion.

[0007] In an embodiment, an area of the bottom metal layer can be greater than an area of the first gate pattern.

[0008] In an embodiment, the bottom metal layer can overlap the entire first gate pattern in the plan view.

[0009] In an embodiment, an area of the bottom metal layer can be substantially equal to an area of the first gate pattern.

[0010] In an embodiment, a shape of the first gate pattern can be substantially the same as a shape of the bottom metal layer in the plan view.

[0011] In an embodiment, the display device can further include first and second electrodes disposed on the second gate pattern and electrically connected to the first active layer, and the first active layer, the first gate pattern, the first electrode, and the second electrode can together define a drive transistor.

[0012] In an embodiment, the drive transistor can include a first sub-transistor including the first drive channel portion, and a second sub-transistor including the second drive channel portion.

[0013] In an embodiment, the display device can further include a second active layer disposed on the second gate pattern, a third gate pattern disposed on the second active layer, and third and fourth electrodes disposed on the third gate pattern, and the third and fourth electrodes are disposed in the same layer as the first and second electrodes, and the second active layer, the third gate pattern, the third electrode, and the fourth electrode can define a compensation transistor or an initialization transistor.

[0014] In an embodiment, the first active layer can include a silicon semiconductor, and the second active layer can include an oxide semiconductor.

[0015] In an embodiment, a length of the first drive channel portion can be greater than a length of the second drive channel portion.

[0016] In an embodiment, a length of the first drive channel portion can be substantially equal to a length of the second drive channel portion.

[0017] In an embodiment, the first and second drive channel portions can be symmetrical with respect to an imaginary line passing through a center disposed between the first and second drive channel portions of the first active layer in the plan view.

[0018] In an embodiment, the portion of the first gate pattern exposed by the second gate pattern can overlap the first drive channel portion in the plan view.

[0019] In an embodiment, the portion of the first gate pattern exposed by the second gate pattern can overlap the second drive channel portion in the plan view.

[0020] A display device according to an embodiment includes a data write transistor configured to transfer a data voltage to a first node in response to a write signal; a drive transistor configured to generate a drive current corresponding to the data voltage and including a first sub-transistor including a first terminal connected to the first node, a second terminal opposite the first terminal, and a gate terminal connected to a second node, and a second sub-transistor including a first terminal connected to the second terminal of the first sub-transistor, a second terminal connected to a third node, and a gate terminal connected to the second node; a storage capacitor configured to store the data voltage and including a first terminal connected to the second node and a second terminal configured to receive a drive voltage; and a light emitting element emitting light at a luminance corresponding to a magnitude of the drive current.

[0021] In an embodiment, the first sub-transistor and the second sub-transistor can be connected in series between the first node and the third node.

[0022] In an embodiment, the display device can further include a compensation transistor including a first terminal connected to the third node, a second terminal connected to a fourth node, and a gate terminal configured to receive a compensation signal, and an initialization transistor including a first terminal connected to the fourth node, a second terminal configured to receive an initialization voltage, and a gate terminal configured to receive an initialization signal.

[0023] In an embodiment, each of the compensation transistor and the initialization transistor can be an NMOS transistor.

[0024] In an embodiment, each of the compensation transistor and the initialization transistor can be a PMOS transistor.

[0025] In an embodiment, the display device can further include a first active layer including a first drive channel portion and a second drive channel portion, the first drive channel portion defining a channel of the first sub-transistor, and the second drive channel portion defining a channel of the second sub-transistor, and a first gate pattern disposed on the first active layer and defining the gate terminal of the first sub-transistor and the gate terminal of the second sub-transistor.

[0026] In an embodiment, the first gate pattern can expose a portion of the first active layer disposed between the first drive channel portion and the second drive channel portion.

[0027] In an embodiment, the display device may further include: a second gate pattern disposed on the first gate pattern and defining the second terminal of the storage capacitor, and the second gate pattern may expose a portion of the first gate pattern.

[0028] In an embodiment, the display device may further include: a bottom metal layer disposed between the substrate and the first active layer in a cross-sectional view, and overlapping each of the first drive channel portion and the second drive channel portion in a plan view, wherein the bottom metal layer exposes at least a portion of the rear surface of the portion of the first active layer disposed between the first drive channel portion and the second drive channel portion.

[0029] In an embodiment, each of the first sub-transistor and the second sub-transistor may further include a bottom gate terminal, and the bottom metal layer may define the bottom gate terminal of the first sub-transistor and the bottom gate terminal of the second sub-transistor.

[0030] In a display device according to an embodiment of the present disclosure, the display device may include: a first active layer including a first driving channel portion and a second driving channel portion; a first gate pattern disposed on the first active layer; a second gate pattern disposed on the first gate pattern; and a bottom metal layer disposed below the first active layer. Therefore, since the driving transistors included in the display device can have a dual-gate transistor structure including two driving channels, the driving channel length is relatively reduced compared to the case where the driving transistors have only one driving channel, and thus the hysteresis characteristics of the display device can be improved.

[0031] Furthermore, the first gate pattern can expose the upper surface of the portion of the first active layer between the first driving channel portion and the second driving channel portion, the second gate pattern can expose the upper surface of the first gate pattern, and the bottom metal layer can expose the rear surface of the first active layer. Therefore, hydrogen ions (H+) emitted from the first active layer and diffused into the upper portion of the second gate pattern... + The movement path of the light can be shortened, thereby promoting the emission of hydrogen ions from the first active layer. Furthermore, light introduced from the lower portion of the bottom metal layer can be directed towards the periphery of the first and second drive channel portions. Therefore, the reduction in the driving range of the drive transistor and the swing width of the data voltage can be minimized. Thus, when alternating black and white images are displayed on the screen of a display device, the phenomenon of afterimages or stains temporarily visible on the screen can be effectively prevented. Attached Figure Description

[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0034] Figure 2 It is shown Figure 1 A circuit diagram of an example of pixels included in a display device.

[0035] Figure 3 It is shown Figure 1 A circuit diagram of another example of pixels included in a display device.

[0036] Figure 4 It is shown Figure 1 A circuit diagram of yet another example of pixels included in a display device.

[0037] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 It is shown Figure 1 The layout diagram of pixels included in the display device.

[0038] Figure 17 It shows along Figure 1 A cross-sectional view of the section intercepted by the XY line.

[0039] Figure 18 This is a layout diagram showing the first transistor according to an embodiment.

[0040] Figure 19 It shows along Figure 18 A cross-sectional view of the section cut by line I-I'.

[0041] Figure 20 It is used to illustrate the passage Figure 19 A view showing light inflow (or light incident) into the bottom metal layer and hydrogen emission from the first active layer.

[0042] Figure 21 This is a layout diagram showing a first transistor according to another embodiment.

[0043] Figure 22 It shows along Figure 21A cross-sectional view of the section cut by line II-II'.

[0044] Figure 23 This is a layout diagram showing a first transistor according to yet another embodiment.

[0045] Figure 24 It shows along Figure 23 A cross-sectional view of the section cut by line III-III'.

[0046] Figure 25 This is a layout diagram showing a first transistor according to another embodiment.

[0047] Figure 26 This is a layout diagram showing a first transistor according to yet another embodiment.

[0048] Figure 27 This is a layout diagram showing a first transistor according to another embodiment.

[0049] Figure 28 This is a block diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0050] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be an intermediary element between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, “a,” “an,” “the,” and “at least one” do not imply a limitation on quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises and / or comprising” or “includes and / or including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0052] It will be understood that although the terms “first,” “second,” “third,” “first-first,” “first-second,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second part.”

[0053] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, “about” or “substantially equal to” includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, “substantially equal to” could mean within one or more standard deviations, or within ±10%, ±5%, or ±2% of the stated value.

[0054] In the following description, the display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0055] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0056] In this specification, a "plan view" can be defined as a view in the thickness direction (third direction DR3) of the display device DD. The third direction DR3 may be perpendicular to the plane defined by the mutually perpendicular first direction DR1 and second direction DR2.

[0057] Reference Figure 1 According to embodiments of the present disclosure, a display device DD may include a display area DA and a peripheral area PA. The display area DA may be defined as the area that generates light or displays an image by adjusting the transmittance of light provided from an external light source.

[0058] Multiple pixels (PX) can be set within the display area (DA). For example, each of the multiple pixels (PX) may include a driving element (e.g., Figure 2 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) and the light-emitting element (e.g., Figure 2The light-emitting element EE). Pixel PX can be arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, pixel PX can be arranged in a matrix form along the first direction DR1 and the second direction DR2.

[0059] The peripheral region PA can be defined as an area where no image is displayed. Furthermore, the peripheral region PA can surround at least a portion of the display region DA. For example, the peripheral region PA can surround the entire display region DA.

[0060] A driver electrically connected to pixel PX can be disposed in peripheral region PA. For example, the driver may include a data driver and a gate driver. The data driver transmits a data signal to pixel PX, and the gate driver transmits a gate signal to pixel PX. Specifically, pixel PX can be connected to a data line electrically connected to the data driver and extending along a second direction DR2, and a gate line electrically connected to the gate driver and extending along a first direction DR1. Therefore, pixel PX can emit light corresponding to each of the data signal and the gate signal. However, the direction in which each of the data line and the gate line extends according to embodiments of this disclosure is not limited to this.

[0061] Figure 2 It is shown Figure 1 A circuit diagram of an example of pixels included in a display device.

[0062] Reference Figure 2 Pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a light-emitting element EE. The first transistor T1 may include a first sub-transistor T1-1 and a second sub-transistor T1-2.

[0063] The first sub-transistor T1-1 may include a first terminal connected to the first node N1, a second terminal opposite to the first terminal, and a gate terminal connected to the second node N2. The second sub-transistor T1-2 may include a first terminal connected to the second terminal of the first sub-transistor T1-1, a second terminal connected to the third node N3, and a gate terminal connected to the second node N2. In an embodiment, the first sub-transistor T1-1 and the second sub-transistor T1-2 may be connected in series between the first node N1 and the third node N3.

[0064] The first terminal of the first sub-transistor T1-1 can be connected to the data voltage line, and the second terminal of the second sub-transistor T1-2 can be connected to the light-emitting element EE. Therefore, the first transistor T1 can receive the data voltage DATA from the data voltage line and generate a drive current corresponding to the data voltage DATA. This drive current can be supplied to the light-emitting element EE. In this specification, the first transistor T1 may be referred to as the "drive transistor".

[0065] The second transistor T2 may include a first terminal connected to a data voltage line, a second terminal connected to a first node N1, and a gate terminal providing a write signal GW. Therefore, the second transistor T2 can be turned on or off by the write signal GW. During the period when the second transistor T2 is on, it can provide a data voltage DATA to the first transistor T1. In other words, the second transistor T2 can transfer the data voltage DATA to the first node N1 in response to the write signal GW. For example, in this specification, the second transistor T2 may be referred to as a "data write transistor".

[0066] The third transistor T3 may include a first terminal connected to the third node N3, a second terminal connected to the fourth node N4, and a gate terminal provided with a compensation signal GC. Therefore, the third transistor T3 can be turned on or off by the compensation signal GC. During the period when the third transistor T3 is on, the third transistor T3 can compensate for the threshold voltage of the first transistor T1 by diode-connecting the first transistor T1. In this specification, the third transistor T3 may be referred to as a "compensation transistor".

[0067] The fourth transistor T4 may include a first terminal connected to the fourth node N4, a second terminal connected to the first initialization voltage line, and a gate terminal provided with the first initialization signal GI. Therefore, the fourth transistor T4 can be turned on or off by the first initialization signal GI. During the period when the fourth transistor T4 is turned on, the fourth transistor T4 can provide the first initialization voltage VINT provided by the first initialization voltage line to the gate terminal of the first transistor T1. In this specification, the fourth transistor T4 may be referred to as the "initialization transistor".

[0068] The fifth transistor T5 may include a first terminal connected to a first power voltage line, a second terminal connected to a first node N1, and a gate terminal connected to a light-emitting control line. The light-emitting control line can provide a light-emitting control signal EM to the gate terminal of the fifth transistor T5. Therefore, the fifth transistor T5 can be turned on or off by the light-emitting control signal EM. During the period when the fifth transistor T5 is on, the fifth transistor T5 can provide a first power voltage ELVDD provided by the first power voltage line to the first transistor T1.

[0069] In an embodiment, the first power voltage ELVDD provided by the first power voltage line and the second power voltage ELVSS provided by the second power voltage line connected to the light-emitting element EE can each be a constant voltage. In an embodiment, the first power voltage ELVDD and the second power voltage ELVSS can have different voltage levels. In this specification, the first power voltage ELVDD can be referred to as the "driving voltage".

[0070] The sixth transistor T6 may include a first terminal connected to the third node N3, a second terminal connected to the fifth node N5, and a gate terminal connected to the light-emitting control line. Therefore, the sixth transistor T6 can be turned on or off by the light-emitting control signal EM. During the period when the sixth transistor T6 is on, it can provide drive current to the light-emitting element EE.

[0071] The seventh transistor T7 may include a first terminal connected to the second initialization voltage line, a second terminal connected to the fifth node N5, and a gate terminal provided with a bypass signal EB. Therefore, the seventh transistor T7 can be turned on or off via the bypass signal EB. During the period when the seventh transistor T7 is on, it can provide the second initialization voltage AINT, provided by the second initialization voltage line, to the light-emitting element EE.

[0072] The storage capacitor CST may include a first terminal connected to the second node N2 and a second terminal connected to the first power voltage line. The storage capacitor CST may maintain the voltage level of each of the gate terminals of the first sub-transistor T1-1 and the second sub-transistor T1-2 during the disabled period of the write signal GW.

[0073] The light-emitting element EE may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal), and the first terminal of the light-emitting element EE is connected to a sixth transistor T6 and a seventh transistor T7, and the second terminal can receive a second power voltage ELVSS. The light-emitting element EE can generate light with a brightness corresponding to the magnitude of the drive current.

[0074] In this embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS transistor. In this embodiment, the third transistor T3 may be an NMOS transistor. In this embodiment, the fourth transistor T4 may be an NMOS transistor. Therefore, the active pattern of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include cation-doped silicon semiconductor, and the active pattern of each of the third transistor T3 and the fourth transistor T4 may include oxide semiconductor.

[0075] Furthermore, the corresponding one of the write signal GW, the light emission control signal EM, and the bypass signal EB used to turn on each of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may have a negative voltage level, and the corresponding one of the compensation signal GC and the first initialization signal GI used to turn on each of the third transistor T3 and the fourth transistor T4 may have a positive voltage level. However, the type of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the voltage level of the signal applied to each gate terminal, according to embodiments of this disclosure, are not limited to these.

[0076] Figure 3 It is shown Figure 1 A circuit diagram of another example of pixels included in a display device.

[0077] Apart from the respective configurations and connections of the first transistor T1 and the eighth transistor T8, Figure 3 The pixel PX can have the same characteristics as the reference. Figure 2 The described structures are essentially the same. In the following text, omissions or simplifications will be made in relation to the references. Figure 2 The description of the structure of pixel PX repeats any content.

[0078] Reference Figure 3 Pixel PX may include an eighth transistor T8. The eighth transistor T8 may include a first terminal connected to the first node N1, a second terminal connected to the bias voltage line to which the bias voltage VBIAS is applied, and a gate terminal providing a bypass signal EB. Therefore, the eighth transistor T8 can be turned on or off by the bypass signal EB. During the period when the eighth transistor T8 is on, the eighth transistor T8 can provide the bias voltage VBIAS to the first transistor T1.

[0079] Each of the first sub-transistor T1-1 and the second sub-transistor T1-2 may be a dual-gate transistor. For example, each of the first sub-transistor T1-1 and the second sub-transistor T1-2 may include a bottom gate terminal. The bottom gate terminal of the first sub-transistor T1-1 and the bottom gate terminal of the second sub-transistor T1-2 may each be connected to a first power voltage line.

[0080] In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a PMOS transistor. In an embodiment, each of the third transistor T3 and the fourth transistor T4 may be an NMOS transistor. However, the types of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 according to embodiments of this disclosure are not limited to these.

[0081] Figure 4 It is shown Figure 1 A circuit diagram of yet another example of pixels included in a display device.

[0082] Besides the types of the third transistor T3 and the fourth transistor T4, Figure 4 The pixel PX can be compared with the reference Figure 2 The described pixels PX have essentially the same structure. In the following text, references will be omitted or simplified. Figure 2 The description of the structure of pixel PX repeats any content.

[0083] Reference Figure 4 In this embodiment, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS transistor. The active pattern of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include cation-doped silicon semiconductor. Furthermore, the compensation signal GC and the first initialization signal GI used to turn on the third transistor T3 and the fourth transistor T4, respectively, may have negative voltage levels. However, the type of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the voltage level of the signal applied to each gate terminal, according to embodiments of this disclosure, are not limited to these.

[0084] However, despite reference Figure 2 , Figure 3 and Figure 4Each of the third transistor T3 and the fourth transistor T4 included in a pixel PX described may be shown as one, but the structure of the third transistor T3 and the fourth transistor T4 according to embodiments of this disclosure is not limited thereto. For example, each of the third transistor T3 and the fourth transistor T4 may be a transistor with a dual-gate structure. In embodiments, the gate terminals of each of the third transistor T3 and the fourth transistor T4 may include a bottom gate terminal and a top gate terminal, and the bottom gate terminal and the top gate terminal may be electrically connected.

[0085] In addition, refer to Figure 2 and Figure 4 The types (e.g., PMOS and NMOS) of each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 described, and referenced Figure 3 The type of each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 described may be exemplary, and the type of each of the plurality of transistors included in one of the plurality of pixels PX according to embodiments of the present disclosure may not be limited thereto. Furthermore, refer to... Figure 2 , Figure 3 and Figure 4 The number of transistors included in one of the multiple pixel PXs described may not be limited to this, and one of the multiple pixel PXs may include 6 or fewer transistors or 9 or more transistors.

[0086] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 It is shown Figure 1 The layout diagram of pixels included in the display device. Figure 17 It shows along Figure 1 A cross-sectional view of the section intercepted by the XY line. For example, Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 ,Figure 15 , Figure 16 and Figure 17 It shows having Figure 2 A view of one of the multiple pixels PX in a circuit diagram.

[0087] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 The pixel PX may include a substrate SUB, a bottom metal layer BML, a barrier layer BAR, a buffer layer BUF, a first active layer ACT1, a first gate insulating layer GIL1, a first conductive layer 1000, a second gate insulating layer GIL2, a second conductive layer 2000, a first interlayer insulating layer ISL1, a second active layer ACT2, a third gate insulating layer GIL3, a third conductive layer 3000, a second interlayer insulating layer ISL2, a fourth conductive layer 4000, a first via insulating layer VIA1, a fifth conductive layer 5000, a second via insulating layer VIA2, a pixel electrode PXE, a pixel defining layer PDL, a light emitting layer EML, and a common electrode CE.

[0088] The substrate SUB can be used as the substrate of the pixel PX. The substrate SUB can be an insulating substrate including glass, quartz, and plastic. In embodiments, the substrate SUB can include an organic insulating material such as polyimide (PI). A bottom metal layer BML can be disposed on the substrate SUB. The bottom metal layer BML can include a conductive material. For example, conductive materials can include molybdenum (Mo), copper (Cu), aluminum (Al), and titanium (Ti). These materials can be used alone or in combination with each other. In embodiments, the bottom metal layer BML can define a first groove RP1. For example, the bottom metal layer BML can have a concave shape in a plan view. Specifically, the bottom metal layer BML can have a curved shape defining the first groove RP1 in a plan view. However, the shape of the bottom metal layer BML in a plan view according to embodiments of the present disclosure is not limited to this.

[0089] A barrier layer (BAR) can be disposed on a substrate SUB. The barrier layer BAR can prevent impurities such as oxygen and moisture from diffusing through the substrate SUB to the various components and layers located above the substrate SUB. Furthermore, the barrier layer BAR can provide a flat upper surface on the upper portion of the substrate SUB. In embodiments, the barrier layer BAR may include an inorganic insulating material. For example, the inorganic insulating material may include silicon nitride, silicon oxide, and silicon oxynitride. These materials can be used alone or in combination with each other.

[0090] A buffer layer (BUF) can be disposed on the barrier layer (BAR). The buffer layer (BUF) can prevent impurities such as oxygen and moisture from diffusing through the substrate (SUB) to the various components and layers located above the substrate (SUB). Furthermore, the buffer layer (BUF) can provide a flat upper surface on the upper portion of the substrate (SUB). The buffer layer (BUF) may include an inorganic insulating material.

[0091] The first active layer ACT1 can be disposed on the buffer layer BUF. The first active layer ACT1 may include a first-first channel portion C1-1, a first-second channel portion C1-2, a second channel portion C2, a fifth channel portion C5, a sixth channel portion C6, and a seventh channel portion C7. The first-first channel portion C1-1, the first-second channel portion C1-2, the second channel portion C2, the fifth channel portion C5, the sixth channel portion C6, and the seventh channel portion C7 may be spaced apart from each other in a plan view. In this specification, the first-first channel portion C1-1 and the first-second channel portion C1-2 may be referred to as the "first drive channel portion" and the "second drive channel portion," respectively.

[0092] In an embodiment, the first active layer ACT1 may include a silicon semiconductor. However, the materials included in the first active layer ACT1 according to embodiments of the present disclosure are not limited to this, and the first active layer ACT1 may include various materials, such as amorphous silicon, oxide semiconductors, and organic semiconductors.

[0093] In an embodiment, the shape of the first active layer ACT1 can be arranged repeatedly or symmetrically along the first direction DR1 in a plan view. The shape of the first active layer ACT1 can be arranged repeatedly along the second direction DR2 in a plan view.

[0094] The first-first-channel portion C1-1 and the first-second-channel portion C1-2 can correspond to the first sub-transistor T1-1 and the second sub-transistor T1-2, respectively. In an embodiment, the shape of the portion of the first active layer ACT1 corresponding to the first sub-transistor T1-1 and the second sub-transistor T1-2 can have a curved shape (e.g., a "U" shape or an "Ω" shape) in a planar view. Specifically, the shape of the portion of the first active layer ACT1 connecting the first-first-channel portion C1-1 to the first-second-channel portion C1-2 can have a "U" shape or an "Ω" shape in a planar view. However, the shape of the first active layer ACT1 according to embodiments of the present disclosure is not limited to this, and the shape of the portion of the first active layer ACT1 corresponding to the first sub-transistor T1-1 and the second sub-transistor T1-2 in a planar view is not limited to this, and can have various shapes (such as straight lines and "S" shapes, etc.) in a planar view.

[0095] The first active layer ACT1 can overlap with the bottom metal layer BML in a planar view. For example, the first-first channel portion C1-1 and the first-second channel portion C1-2 of the first active layer ACT1 can each overlap with the bottom metal layer BML in a planar view.

[0096] In an embodiment, the bottom metal layer BML may expose a portion of the first active layer ACT1. For example, the bottom metal layer BML may expose at least a portion of the rear surface (or lower surface) of the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2. Specifically, the first groove RP1 of the bottom metal layer BML may expose the rear surface of the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2. In other words, the first groove RP1 of the bottom metal layer BML may overlap with the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2 in a plan view.

[0097] A first gate insulating layer GIL1 may be disposed on the first active layer ACT1. In one embodiment, the first gate insulating layer GIL1 may have a uniform thickness along the contour of the first active layer ACT1. In another embodiment, the first gate insulating layer GIL1 may have a substantially flat upper surface without creating a step around the first active layer ACT1. In another embodiment, the first gate insulating layer GIL1 may comprise an inorganic insulating material.

[0098] A first conductive layer 1000 may be disposed on a first gate insulating layer GIL1. The first conductive layer 1000 may include a light-emitting control line 1100, a first gate pattern 1200, and a first gate voltage line 1300. In an embodiment, the first conductive layer 1000 may include a conductive material. The light-emitting control line 1100 may extend along a first direction DR1. The light-emitting control line 1100 may overlap with the first active layer ACT1 in a planar view. For example, the light-emitting control line 1100 may include a first portion overlapping with the fifth channel portion C5 of the first active layer ACT1 in a planar view and a second portion overlapping with the sixth channel portion C6 of the first active layer ACT1 in a planar view. Specifically, the first portion of the light-emitting control line 1100 may correspond to the gate terminal of the fifth transistor T5. Furthermore, the second portion of the light-emitting control line 1100 may correspond to the gate terminal of the sixth transistor T6.

[0099] The first gate pattern 1200 may be spaced apart from the light-emitting control line 1100 in the second direction DR2. The first gate pattern 1200 may overlap with the first active layer ACT1 in a planar view. For example, the first gate pattern 1200 may include a first portion overlapping with the first-first channel portion C1-1 of the first active layer ACT1 in a planar view and a second portion overlapping with the first-second channel portion C1-2 of the first active layer ACT1 in a planar view. Specifically, the first portion of the first gate pattern 1200 may correspond to the gate terminal of the first sub-transistor T1-1. Furthermore, the second portion of the first gate pattern 1200 may correspond to the gate terminal of the second sub-transistor T1-2.

[0100] In an embodiment, the first gate pattern 1200 may define a second recess RP2. For example, the first gate pattern 1200 may have a concave shape in a plan view. Specifically, the first gate pattern 1200 may have a curved shape in a plan view defining the second recess RP2. However, the shape of the first gate pattern 1200 in a plan view according to embodiments of the present disclosure is not limited to this, and the first gate pattern 1200 may have various shapes that overlap with the first-first channel portion C1-1 and the first-second channel portion C1-2 in a plan view and do not partially overlap with the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2.

[0101] In an embodiment, the first gate pattern 1200 may expose a portion of the first active layer ACT1. For example, the first gate pattern 1200 may expose the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2. Specifically, the second recess RP2 of the first gate pattern 1200 may expose the upper surface of the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2. In other words, the second recess RP2 of the first gate pattern 1200 may overlap with the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2 in a plan view.

[0102] In one embodiment, the entire bottom metal layer BML may overlap with the first gate pattern 1200 in a plan view. In another embodiment, the first gate pattern 1200 may have a shape substantially the same as the bottom metal layer BML in a plan view. The overlap relationship between the bottom metal layer BML and the first gate pattern 1200 according to embodiments of this disclosure is not limited to this. For example, the first gate pattern 1200 may have a shape different from the bottom metal layer BML in a plan view.

[0103] In one embodiment, the area of ​​the bottom metal layer BML can be larger than the area of ​​the first gate pattern 1200. When the area of ​​the bottom metal layer BML is larger than the area of ​​the first gate pattern 1200, the edge of the bottom metal layer BML can completely surround the edge of the first gate pattern 1200 in a planar view. However, the area relationship between each of the bottom metal layer BML and the first gate pattern 1200 according to embodiments of the present disclosure is not limited to this, and in another embodiment, the area of ​​the bottom metal layer BML can be substantially equal to the area of ​​the first gate pattern 1200. In other words, the area of ​​the bottom metal layer BML in a planar view can be equal to or greater than the area of ​​the first gate pattern 1200 in a planar view.

[0104] In one embodiment, the first gate pattern 1200 may overlap with the bottom metal layer BML in a planar view. In another embodiment, the first recess RP1 and the second recess RP2 may overlap each other in a planar view. In yet another embodiment, the area of ​​the rear surface of the portion of the first active layer ACT1 exposed by the first recess RP1 may be smaller than the area of ​​the upper surface of the portion of the first active layer ACT1 exposed by the second recess RP2. However, the area of ​​the first active layer ACT1 exposed by each of the first recess RP1 and the second recess RP2 according to embodiments of the present disclosure may not be limited thereto, and in another embodiment, the area of ​​the rear surface of the portion of the first active layer ACT1 exposed by the first recess RP1 may be substantially equal to the area of ​​the upper surface of the portion of the first active layer ACT1 exposed by the second recess RP2. In other words, in a planar view, the area of ​​the rear surface of the portion of the first active layer ACT1 exposed by the first recess RP1 may be less than or equal to the area of ​​the upper surface of the portion of the first active layer ACT1 exposed by the second recess RP2.

[0105] The first gate voltage line 1300 may extend along a first direction DR1. The first gate voltage line 1300 may be spaced apart from the light-emitting control line 1100 in a second direction DR2. The first gate voltage line 1300 may overlap with the first active layer ACT1 in a planar view. For example, the first gate voltage line 1300 may include a first portion overlapping with the second channel portion C2 of the first active layer ACT1 in a planar view and a second portion overlapping with the seventh channel portion C7 of the first active layer ACT1 in a planar view. Specifically, the first portion of the first gate voltage line 1300 may correspond to the gate terminal of the second transistor T2. Furthermore, the second portion of the first gate voltage line 1300 may correspond to the gate terminal of the seventh transistor T7. In an embodiment, when pixel PX is included in the Nth pixel row, the second portion of the first gate voltage line 1300 may correspond to the gate terminal of the seventh transistor T7 of the pixel included in the (N+1)th pixel row, where N is a positive integer.

[0106] A second gate insulating layer GIL2 may be disposed on the first conductive layer 1000. In one embodiment, the second gate insulating layer GIL2 may have a uniform thickness along the contour of the first conductive layer 1000. In another embodiment, the second gate insulating layer GIL2 may have a substantially flat upper surface without creating steps around the first conductive layer 1000. In another embodiment, the second gate insulating layer GIL2 may comprise an inorganic insulating material.

[0107] The second conductive layer 2000 may be disposed on the second gate insulating layer GIL2. The second conductive layer 2000 may include a first initialization voltage line 2100, a second gate pattern 2200, a second gate voltage line 2300, and a third gate voltage line 2400. In an embodiment, the second conductive layer 2000 may include a conductive material.

[0108] The first initialization voltage line 2100 may extend along the first direction DR1. The first initialization voltage line 2100 may overlap with the first active layer ACT1 in a plan view. Specifically, the first initialization voltage line 2100 may overlap with the portion of the first active layer ACT1 that extends from the sixth channel portion C6 in a direction opposite to the second direction DR2 and bends in a plan view.

[0109] The second gate pattern 2200 may be spaced apart from the first initialization voltage line 2100 in the second direction DR2. The second gate pattern 2200 may overlap with the first gate pattern 1200 in a planar view. For example, the first gate pattern 1200 and the second gate pattern 2200 may overlap each other in a planar view to define a storage capacitor CST. Specifically, the first gate pattern 1200 may define a first terminal of the storage capacitor CST, and the second gate pattern 2200 may define a second terminal of the storage capacitor CST.

[0110] The second gate pattern 2200 may overlap with the first gate pattern 1200 in a planar view. The second gate pattern 2200 may overlap with the bottom metal layer BML in a planar view. The second gate pattern 2200 may expose a portion of the first gate pattern 1200. Furthermore, the second gate pattern 2200 may expose a portion of the bottom metal layer BML.

[0111] In an embodiment, the second gate pattern 2200 may define a third recess RP3. For example, the second gate pattern 2200 may have a concave shape in a plan view. Specifically, the second gate pattern 2200 may have a curved shape in a plan view defining the third recess RP3. However, the shape of the second gate pattern 2200 in a plan view according to embodiments of the present disclosure is not limited to this, and the second gate pattern 2200 may have various shapes in a plan view exposing the upper surface of the first gate pattern 1200.

[0112] The second gate pattern 2200 may overlap with the first active layer ACT1 in a planar view. For example, the second gate pattern 2200 may overlap with the first-first channel portion C1-1 in a planar view. In an embodiment, the second gate pattern 2200 may overlap with a portion of the first active layer ACT1 that does not overlap with the first gate pattern 1200 in a planar view. For example, the second gate pattern 2200 may overlap with a portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2 in a planar view.

[0113] In an embodiment, the second gate pattern 2200 may not overlap with the first-second channel portion C1-2 of the first active layer ACT1 in a plan view. For example, a third recess RP3 may expose the portion of the first gate pattern 1200 that overlaps with the first-second channel portion C1-2. The third recess RP3 may be spaced apart from each of the first recess RP1 and the second recess RP2 in a direction opposite to the second direction DR2 in a plan view. The third recess RP3 may be positioned in a plan view closer to the sixth channel portion C6 than the fifth channel portion C5. However, the position of the third recess RP3 of the second gate pattern 2200 according to embodiments of the present disclosure is not limited to this.

[0114] In one embodiment, the area of ​​the second gate pattern 2200 may be larger than the area of ​​the first gate pattern 1200. In another embodiment, the area of ​​the second gate pattern 2200 may be larger than the area of ​​the bottom metal layer.

[0115] The second gate voltage line 2300 may extend along the first direction DR1. Furthermore, the second gate voltage line 2300 may be spaced apart from the first initialization voltage line 2100 and the second gate pattern 2200 in the second direction DR2. The second gate voltage line 2300 may overlap with the first active layer ACT1 in a planar view. For example, the second gate voltage line 2300 may overlap with a portion of the first active layer ACT1 adjacent to the second channel portion C2 in a direction opposite to the second direction DR2 in a planar view.

[0116] The third gate voltage line 2400 may extend along the first direction DR1. Furthermore, the third gate voltage line 2400 may be spaced apart from the second gate voltage line 2300 in the second direction DR2. The third gate voltage line 2400 may overlap with the first active layer ACT1 in a planar view. For example, the third gate voltage line 2400 may overlap with a portion of the first active layer ACT1 in the second direction DR2 adjacent to the seventh channel portion C7 in a planar view.

[0117] A first interlayer insulating layer ISL1 may be disposed on the second conductive layer 2000. In one embodiment, the first interlayer insulating layer ISL1 may have a uniform thickness along the contour of the second conductive layer 2000. In another embodiment, the first interlayer insulating layer ISL1 may have a substantially flat upper surface without creating a step around the second conductive layer 2000. In another embodiment, the first interlayer insulating layer ISL1 may comprise an inorganic insulating material.

[0118] The second active layer ACT2 may be disposed on the first interlayer insulating layer ISL1. The second active layer ACT2 may not overlap with the first active layer ACT1 in a planar view. In embodiments, the first active layer ACT1 and the second active layer ACT2 may comprise different materials. In embodiments, the first active layer ACT1 may comprise a silicon semiconductor, and the second active layer ACT2 may comprise an oxide semiconductor. However, the materials comprised in each of the first active layer ACT1 and the second active layer ACT2 according to embodiments of this disclosure are not limited thereto.

[0119] The second active layer ACT2 may include a third channel portion C3 and a fourth channel portion C4. The third channel portion C3 and the fourth channel portion C4 may be spaced apart from each other in a planar view. For example, the third channel portion C3 may be spaced apart from the fourth channel portion C4 in a direction opposite to the second direction DR2 in a planar view. The third channel portion C3 of the second active layer ACT2 may overlap with the second gate voltage line 2300 in a planar view. The fourth channel portion C4 of the second active layer ACT2 may overlap with the third gate voltage line 2400 in a planar view.

[0120] A third gate insulating layer GIL3 may be disposed on the second active layer ACT2. In one embodiment, the third gate insulating layer GIL3 may have a uniform thickness along the contour of the second active layer ACT2. In another embodiment, the third gate insulating layer GIL3 may have a substantially flat upper surface without creating a step around the second active layer ACT2. In another embodiment, the third gate insulating layer GIL3 may comprise an inorganic insulating material.

[0121] The third conductive layer 3000 may be disposed on the third gate insulating layer GIL3. The third conductive layer 3000 may include a fourth gate voltage line 3100 and a fifth gate voltage line 3200. In an embodiment, the third conductive layer 3000 may include a conductive material.

[0122] The fourth gate voltage line 3100 may extend along the first direction DR1. The fourth gate voltage line 3100 may overlap with the second gate voltage line 2300 in a planar view. The fourth gate voltage line 3100 may overlap with the second active layer ACT2 in a planar view. For example, the fourth gate voltage line 3100 may overlap with the third channel portion C3 of the second active layer ACT2 in a planar view. Specifically, the portion of the fourth gate voltage line 3100 that overlaps with the third channel portion C3 in a planar view may correspond to the gate terminal of the third transistor T3.

[0123] Furthermore, when the third transistor T3 has a dual-gate structure, the portion of the fourth gate voltage line 3100 that overlaps with the third channel portion C3 in the plan view can correspond to the top gate terminal of the third transistor T3, and the portion of the second gate voltage line 2300 that overlaps with the third channel portion C3 in the plan view can correspond to the bottom gate terminal of the third transistor T3.

[0124] The fifth gate voltage line 3200 may extend along the first direction DR1. The fifth gate voltage line 3200 may be spaced apart from the fourth gate voltage line 3100 in the second direction DR2. The fifth gate voltage line 3200 may overlap with the third gate voltage line 2400 in a planar view. The fifth gate voltage line 3200 may overlap with the second active layer ACT2 in a planar view. For example, the fifth gate voltage line 3200 may overlap with the fourth channel portion C4 of the second active layer ACT2 in a planar view. Specifically, the portion of the fifth gate voltage line 3200 that overlaps with the fourth channel portion C4 in a planar view may correspond to the gate terminal of the fourth transistor T4.

[0125] Furthermore, when the fourth transistor T4 has a dual-gate structure, the portion of the fifth gate voltage line 3200 that overlaps with the fourth channel portion C4 in the plan view can correspond to the top gate terminal of the fourth transistor T4, and the portion of the third gate voltage line 2400 that overlaps with the fourth channel portion C4 in the plan view can correspond to the bottom gate terminal of the fourth transistor T4.

[0126] The second interlayer insulating layer ISL2 may be disposed on the third conductive layer 3000. In one embodiment, the second interlayer insulating layer ISL2 may have a uniform thickness along the contour of the third conductive layer 3000. In another embodiment, the second interlayer insulating layer ISL2 may have a substantially flat upper surface without creating a step around the third conductive layer 3000. In another embodiment, the second interlayer insulating layer ISL2 may comprise an inorganic insulating material.

[0127] A fourth conductive layer 4000 may be disposed on the second interlayer insulating layer ISL2. The fourth conductive layer 4000 may include a first connection electrode 4100, a second connection electrode 4200, a third connection electrode 4300, a fourth connection electrode 4400, a fifth connection electrode 4500, a sixth connection electrode 4600, and a second initialization voltage line 4700. In an embodiment, the fourth conductive layer 4000 may include a conductive material. At least one of the plurality of insulating layers disposed below the fourth conductive layer 4000 (e.g., a first gate insulating layer GIL1, a second gate insulating layer GIL2, and a third gate insulating layer GIL3, a first interlayer insulating layer ISL1, and a second interlayer insulating layer ISL2) may have a contact hole, defined as a means to contact the fourth conductive layer 4000 with the bottom metal layer BML, the first active layer ACT1, and the second active layer ACT2 between the first conductive layer 1000, the second conductive layer 2000, and the third conductive layer 3000.

[0128] The first connection electrode 4100 may overlap with the first gate pattern 1200 and the second active layer ACT2 in a planar view. The first connection electrode 4100 may be electrically connected to the first gate pattern 1200 and the second active layer ACT2, respectively. For example, the first connection electrode 4100 may contact the first gate pattern 1200 and the second active layer ACT2 through multiple contact holes. Therefore, the gate terminal of the first sub-transistor T1-1, the gate terminal of the second sub-transistor T1-2, the second terminal of the third transistor T3, and the first terminal of the fourth transistor T4 may be electrically connected to each other through the first connection electrode 4100.

[0129] The second connection electrode 4200 may be spaced apart from the first connection electrode 4100 in the first direction DR1. The second connection electrode 4200 may overlap with the first active layer ACT1 and the second active layer ACT2 in a planar view. The second connection electrode 4200 may be electrically connected to the first active layer ACT1 and the second active layer ACT2, respectively. For example, the second connection electrode 4200 may contact each of the first active layer ACT1 and the second active layer ACT2 through a contact hole. Therefore, the second terminal of the second sub-transistor T1-2, the first terminal of the third transistor T3, and the first terminal of the sixth transistor T6 may be electrically connected to each other through the second connection electrode 4200.

[0130] The third connecting electrode 4300 may be spaced apart from the second connecting electrode 4200 in the opposite direction to the second direction DR2. The third connecting electrode 4300 may overlap with the first active layer ACT1 in a plan view. The third connecting electrode 4300 may be electrically connected to the first active layer ACT1. For example, the third connecting electrode 4300 may contact the first active layer ACT1 through a contact hole. Therefore, the third connecting electrode 4300 may be connected to the second terminal of the sixth transistor T6.

[0131] The fourth connection electrode 4400 may be spaced apart from the third connection electrode 4300 in the opposite direction to the second direction DR2. The fourth connection electrode 4400 may overlap with the second active layer ACT2 in a plan view. The fourth connection electrode 4400 may be electrically connected to the second active layer ACT2. For example, the fourth connection electrode 4400 may contact the second active layer ACT2 through a contact hole. Therefore, the fourth connection electrode 4400 may be connected to the second terminal of the fourth transistor T4.

[0132] The fifth connection electrode 4500 may be spaced apart from the third connection electrode 4300 in the opposite direction to the first direction DR1. The fifth connection electrode 4500 may overlap with the first active layer ACT1 and the second gate pattern 2200 in a planar view. The fifth connection electrode 4500 may be electrically connected to each of the first active layer ACT1 and the second gate pattern 2200. For example, the fifth connection electrode 4500 may contact each of the first active layer ACT1 and the second gate pattern 2200 through a contact hole. Therefore, the first terminal of the fifth transistor T5 and the second terminal of the storage capacitor CST may be electrically connected to each other through the fifth connection electrode 4500.

[0133] The sixth connection electrode 4600 may be spaced apart from the fifth connection electrode 4500 in the second direction DR2. The sixth connection electrode 4600 may overlap with the first active layer ACT1 in a plan view. The sixth connection electrode 4600 may be electrically connected to the first active layer ACT1. For example, the sixth connection electrode 4600 may contact the first active layer ACT1 through a contact hole. Therefore, the sixth connection electrode 4600 may be connected to the first terminal of the second transistor T2.

[0134] The second initialization voltage line 4700 may extend along the first direction DR1. The second initialization voltage line 4700 may be spaced apart from the sixth connecting electrode 4600 in the opposite direction to the second direction DR2. The second initialization voltage line 4700 may overlap with the first active layer ACT1 in a plan view. The second initialization voltage line 4700 may be electrically connected to the first active layer ACT1. For example, the second initialization voltage line 4700 may contact the first active layer ACT1 through a contact hole. Therefore, the second initialization voltage line 4700 may be connected to the first terminal of the seventh transistor T7.

[0135] A first via insulating layer VIA1 may be disposed on the fourth conductive layer 4000. The first via insulating layer VIA1 may have a substantially flat upper surface. In embodiments, the first via insulating layer VIA1 may comprise an organic insulating material and / or an inorganic insulating material. For example, the organic insulating material may comprise polyimide.

[0136] A fifth conductive layer 5000 may be disposed on a first via insulating layer VIA1. The fifth conductive layer 5000 may include a data voltage line 5100, a power voltage line 5200, and a seventh connection electrode 5300. In an embodiment, the fifth conductive layer 5000 may include a conductive material. Contact holes for contacting the fifth conductive layer 5000 with the first conductive layer 1000, the second conductive layer 2000, the third conductive layer 3000, the fourth conductive layer 4000, the first active layer ACT1, and the second active layer ACT2 may be defined in at least one of a plurality of insulating layers disposed below the fifth conductive layer 5000 (e.g., a first gate insulating layer GIL1, a second gate insulating layer GIL2, and a third gate insulating layer GIL3, a first interlayer insulating layer ISL1, a second interlayer insulating layer ISL2, and a first via insulating layer VIA1).

[0137] Data voltage line 5100 may extend along the second direction DR2. Data voltage line 5100 may overlap with the sixth connection electrode 4600 in a plan view. Data voltage line 5100 may be electrically connected to the sixth connection electrode 4600. For example, data voltage line 5100 may contact the sixth connection electrode 4600 through a contact hole. Therefore, data voltage line 5100 may be connected to the first terminal of the second transistor T2.

[0138] The power voltage line 5200 may be spaced apart from the data voltage line 5100 in the first direction DR1. The power voltage line 5200 may extend along the second direction DR2. The power voltage line 5200 may overlap with the fifth connection electrode 4500 in a plan view. The power voltage line 5200 may be electrically connected to the fifth connection electrode 4500. For example, the power voltage line 5200 may contact the fifth connection electrode 4500 through a contact hole. Therefore, the power voltage line 5200 may be connected to each of the first terminal of the fifth transistor T5 and the second terminal of the storage capacitor CST.

[0139] In reference Figure 18 , Figure 19 , Figure 20 , Figure 19 , Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9In the described display device DD, the contact holes connecting the power voltage line 5200 and the bottom metal layer BML may not be shown; however, this disclosure is not limited to this, and the power voltage line 5200 can be electrically connected to the bottom metal layer BML through the contact holes. When the power voltage line 5200 is electrically connected to the bottom metal layer BML through the contact holes, the bottom metal layer BML can overlap with the first-first channel portion C1-1 to define the bottom gate terminal of the first sub-transistor T1-1. Furthermore, when the power voltage line 5200 is electrically connected to the bottom metal layer BML through the contact holes, the bottom metal layer BML can overlap with the first-second channel portion C1-2 to define the bottom gate terminal of the second sub-transistor T1-2.

[0140] The seventh connecting electrode 5300 may be spaced apart from the power voltage line 5200 in the first direction DR1. The seventh connecting electrode 5300 may overlap with the third connecting electrode 4300 in a plan view. The seventh connecting electrode 5300 may be electrically connected to the third connecting electrode 4300. For example, the seventh connecting electrode 5300 may contact the third connecting electrode 4300 through a contact hole.

[0141] A second via insulating layer VIA2 may be disposed on the fifth conductive layer 5000. The second via insulating layer VIA2 may have a substantially flat upper surface. A contact hole may be defined in the second via insulating layer VIA2, extending through the third-direction DR3 and exposing the upper surface of the seventh connection electrode 5300. In embodiments, the second via insulating layer VIA2 may comprise an organic insulating material and / or an inorganic insulating material.

[0142] The pixel electrode PXE can be disposed on the second via insulating layer VIA2. The pixel electrode PXE can be electrically connected to the seventh connection electrode 5300 through the contact hole of the second via insulating layer VIA2. Therefore, the pixel electrode PXE can be electrically connected to the second terminal of the sixth transistor T6 through the third connection electrode 4300 and the seventh connection electrode 5300.

[0143] In embodiments, the pixel electrode PXE may include conductive materials such as metals, alloys, and transparent conductive oxides. For example, the pixel electrode PXE may include silver (Ag) and indium tin oxide (ITO). In embodiments, the pixel electrode PXE may have a multilayer structure including an indium tin oxide layer, a silver layer, and an indium tin oxide layer stacked on a third-direction DR3. However, the structure of the pixel electrode PXE according to embodiments of this disclosure is not limited to this.

[0144] A pixel defining layer (PDL) may be disposed on a pixel electrode (PXE). The PDL may partially cover the pixel electrode (PXE). Furthermore, an opening may be defined in the PDL to expose at least a portion of the pixel electrode (PXE). For example, the opening in the PDL may expose the center of the pixel electrode (PXE), and the PDL may cover the edge of the pixel electrode (PXE). The PDL may comprise an organic insulating material such as polyimide.

[0145] The emissive layer (EML) can be disposed on the pixel electrode (PXE). The EML can be disposed on the pixel electrode (PXE) exposed by an opening in the pixel defining layer (PDL). The EML can include organic light-emitting materials or quantum dots, etc.

[0146] The common electrode CE can be disposed on the light-emitting layer EML and the pixel-defining layer PDL. The common electrode CE can include materials such as aluminum, platinum (Pt), silver, magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), and titanium. These materials can be used alone or in combination.

[0147] Pixel electrode PXE, emissive layer EML, and common electrode CE can define light-emitting element EE. Furthermore, first active layer ACT1, light-emitting control line 1100, second connecting electrode 4200, and third connecting electrode 4300 can define sixth transistor T6. Furthermore, second active layer ACT2, fourth gate voltage line 3100, first connecting electrode 4100, and second connecting electrode 4200 can define third transistor T3. Moreover, although in Figure 10 Although not shown in the diagram, the second active layer ACT2, the fifth gate voltage line 3200, the first connection electrode 4100, and the fourth connection electrode 4400 may define the fourth transistor T4. Furthermore, the first active layer ACT1, the first gate pattern 1200, the second connection electrode 4200, and the sixth connection electrode 4600 may define the first transistor T1.

[0148] In this specification, the second connecting electrode 4200 and the sixth connecting electrode 4600 may be referred to as the "first electrode" and the "second electrode," respectively. Furthermore, the first connecting electrode 4100 and the second connecting electrode 4200 may be referred to as the "third electrode" and the "fourth electrode," respectively. Alternatively, the first connecting electrode 4100 and the fourth connecting electrode 4400 may be referred to as the "third electrode" and the "fourth electrode," respectively. In embodiments, the third and fourth electrodes may be disposed in the same layer as the first and second electrodes.

[0149] Figure 11 This is a layout diagram showing the first transistor according to an embodiment. Figure 12 yes Figure 13 An enlarged view of region A in the image. Figure 14It shows along Figure 15 A cross-sectional view of the section cut by line I-I'.

[0150] Reference Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 21 , Figure 21 , Figure 18 , Figure 21 , Figure 22 , Figure 18 , Figure 19 , Figure 18 , Figure 19 , Figure 21 , Figure 22 and Figure 6 The first-first-channel portion C1-1 overlapping with the first gate pattern 1200 can be the channel of the first sub-transistor T1-1. Furthermore, the first-second-channel portion C1-2 overlapping with the first gate pattern 1200 can be the channel of the second sub-transistor T1-2. The first channel length CH1 of the first-first-channel portion C1-1 can be defined along the contour of the first active layer ACT1 in a plan view. Furthermore, the second channel length CH2 of the first-second-channel portion C1-2 can be defined along the contour of the first active layer ACT1 in a plan view. Specifically, the first gate pattern 1200 can include a first portion overlapping the first-first-channel portion C1-1 and a second portion overlapping the first-second-channel portion C1-2. In a cross-sectional view, the length of the first-first-channel portion C1-1 overlapping the first portion can be defined as the first channel length CH1, and the length of the first-second-channel portion C1-2 overlapping the second portion can be defined as the second channel length CH2.

[0151] The curved portion (bent shape) of the first-first channel portion C1-1 extending to the first-second channel portion C1-2 of the first active layer ACT1 can be symmetrical in a plan view with respect to an imaginary line SML passing through the center of the curved portion and parallel to the second direction DR2. However, the shape of the portion of the first active layer ACT1 corresponding to the first sub-transistor T1-1 and the second sub-transistor T1-2 in a plan view according to embodiments of the present disclosure is not limited to this, and the shape of the portion of the first active layer ACT1 corresponding to the first sub-transistor T1-1 and the second sub-transistor T1-2 in a plan view can be asymmetrical in a plan view with respect to the imaginary line SML.

[0152] In an embodiment, the shape of the first gate pattern 1200 may be asymmetrical with respect to the imaginary line SML in a planar view. Therefore, the first-first channel portion C1-1 and the first-second channel portion C1-2 may be asymmetrical with respect to the imaginary line SML. Consequently, the first channel length CH1 and the second channel length CH2 may be different from each other.

[0153] In an embodiment, the first channel length CH1 may be greater than the second channel length CH2. In an embodiment, the first channel length CH1 may be from about 10 micrometers (μm) to about 14 μm. Preferably, the first channel length CH1 may be about 12 μm. In an embodiment, the second channel length CH2 may be from about 3 μm to about 5 μm. Preferably, the second channel length CH2 may be about 4 μm. In an embodiment, the sum of the first channel length CH1 and the second channel length CH2 may be about 20 μm or less (e.g., from about 13 μm to about 19 μm). Preferably, the sum of the first channel length CH1 and the second channel length CH2 may be about 16 μm. However, the value or sum of each of the first channel length CH1 and the second channel length CH2 according to embodiments of this disclosure may not be limited thereto.

[0154] In one embodiment, the shape of the bottom metal layer BML may be asymmetrical with respect to the imaginary line SML in a planar view. In another embodiment, the shape of the second gate pattern 2200 may be asymmetrical with respect to the imaginary line SML in a planar view. The first recess RP1, the second recess RP2, and the third recess RP3 may be disposed on the first direction DR1 with respect to the imaginary line SML.

[0155] Figure 6 It is used to illustrate the passage Figure 21 A view of light flowing into the bottom metal layer and hydrogen emissions from the first active layer.

[0156] Reference Figure 18 , Figure 23 , Figure 24 , Figure 23 , Figure 23 , Figure 18 , Figure 23 , Figure 24 , Figure 18 , Figure 19 , Figure 18 , Figure 19 , Figure 23 , Figure 24 , Figure 25 , Figure 25 , Figure 18 , Figure 25 , Figure 18 and Figure 18As described above, the display device DD according to embodiments of the present disclosure may include a first active layer ACT1 comprising a first driving channel portion (e.g., a first-first channel portion C1-1) and a second driving channel portion (e.g., a first-second channel portion C1-2), a first gate pattern 1200 disposed on the first active layer ACT1, a second gate pattern 2200 disposed on the first gate pattern 1200, and a bottom metal layer BML disposed below the first active layer ACT1. Therefore, the driving transistor (e.g., the first transistor T1) included in the display device DD has a dual-gate transistor structure comprising two driving channels (first-first channel portion C1-1 and first-second channel portion C1-2), such that the total channel length is relatively reduced compared to the case where the driving transistor has only one driving channel, and thereby the hysteresis characteristics of the display device DD can be effectively improved.

[0157] Meanwhile, when the channel length of the driving transistor included in a conventional display device decreases, the driving range of the driving transistor and the swing width of the data voltage decrease respectively, and when the screen of the display device alternately displays black and white images, a phenomenon occurs in which afterimages or color spots are temporarily visible on the screen.

[0158] Meanwhile, in the display device DD according to an embodiment of the present disclosure, the second recess RP2 defined by the first gate pattern 1200 can expose the upper surface of the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1 and the first-second channel portion C1-2, the third recess RP3 defined by the second gate pattern 2200 can expose the upper surface of the first gate pattern 1200, and the first recess RP1 defined by the bottom metal layer BML can expose the rear surface of the first active layer ACT1. Therefore, hydrogen ions (H+) released from the first active layer ACT1 and diffused into the upper portion of the second gate pattern 2200 can be... + The movement path of the light can be shortened, thereby promoting the release of hydrogen ions in the first active layer ACT1. Furthermore, light flowing in from the lower part of the bottom metal layer BML can flow to the periphery of the first and second driving channel portions. Therefore, the driving range of the driving transistor and the swing width of the data voltage can be reduced respectively. Thus, when alternating black and white images are displayed on the screen of the display device DD, the phenomenon of afterimages or color spots temporarily appearing on the screen can be effectively prevented.

[0159] Here, hysteresis can refer to the difference between the threshold voltage of the first transistor T1 during the forward swing and the threshold voltage of the first transistor T1 during the reverse swing. The swing width of the data voltage can refer to the difference between the driving range of the first transistor T1 during the forward swing and the driving range of the first transistor T1 during the reverse swing.

[0160] Figure 19 This is a layout diagram showing a first transistor according to another embodiment. Figure 25 It shows along Figure 25 A cross-sectional view of the section intercepted by line II-II'. For example, Figure 23 It corresponds to Figure 25 The view.

[0161] In addition to the shape of the second gate pattern 2200a, refer to Figure 23 and Figure 25 The described display device DDa can be compared with the reference Figure 23 and Figure 26 The described display device DD is substantially the same as or similar to the one referenced. Therefore, omissions or simplifications will be made in accordance with the reference. Figure 26 and Figure 18 The content described is repetitive.

[0162] Reference Figure 26 and Figure 18 The display device DDa may include a second gate pattern 2200a defining a third recess RP3a. In an embodiment, the third recess RP3a may overlap with the first-first channel portion C1-1 in a plan view. Specifically, the third recess RP3a of the second gate pattern 2200a may expose the portion of the upper surface of the first gate pattern 1200 that overlaps with the first-first channel portion C1-1.

[0163] The third groove RP3a can be spaced apart from the first groove RP1 in an oblique direction opposite to the oblique direction between the first direction DR1 and the second direction DR2. Furthermore, the third groove RP3a can be spaced apart from the second groove RP2 in an oblique direction opposite to the oblique direction between the first direction DR1 and the second direction DR2. Therefore, the third groove RP3a can be compared to... Figure 18 The sixth channel section C6 is close to Figure 26 The fifth channel section C5 is set.

[0164] The third groove RP3a can be positioned in the opposite direction to the first direction DR1, relative to the center of the curved shape passing through the first active layer ACT1 and parallel to the imaginary line SML in the second direction DR2. That is, Figure 27 The shape of the second gate pattern 2200a can be relative to the imaginary line SML in the planar diagram. Figure 27 The second gate pattern 2200 has a symmetrical shape.

[0165] Figure 26 This is a layout diagram showing a first transistor according to yet another embodiment. Figure 27 It shows along Figure 26 A cross-sectional view of the section intercepted by line III-III'. For example,Figure 26 It corresponds to Figure 27 The view.

[0166] Apart from the shape of each of the bottom metal layer BMLb, the first gate pattern 1200b, and the second gate pattern 2200b, refer to Figure 28 and Figure 28 The described display device DDb can be compared with the reference Figure 1 and ​ The described display devices DD are substantially the same or similar. Therefore, references will be omitted or simplified. ​ and ​ The description contains repeated content.

[0167] Reference ​ and ​ The display device DDb may include a bottom metal layer BMLb defining a first recess RP1b, a first gate pattern 1200b defining a second recess RP2b, and a second gate pattern 2200b defining an opening OP. The first recess RP1b of the bottom metal layer BMLb may expose the rear surface of the first active layer ACT1. The second recess RP2b of the first gate pattern 1200b may expose the upper surface of the first active layer ACT1. The opening OP of the second gate pattern 2200b may expose the upper surface of the first gate pattern 1200b.

[0168] The first recess RP1b and the second recess RP2b can be defined as having concave shapes for the bottom metal layer BMLb and the first gate pattern 1200b, respectively. Furthermore, the opening OP can be defined as the shape of a hole whose boundary is surrounded by the second gate pattern 2200b.

[0169] The first groove RP1b and the second groove RP2b may overlap each other in the plan view. The opening OP may be spaced apart from the first groove RP1b and the second groove RP2b in the plan view in a direction opposite to the second direction DR2.

[0170] The shape of each of the bottom metal layer BMLb, the first gate pattern 1200b, and the second gate pattern 2200b in a plan view may be symmetrical with respect to an imaginary line SML that passes through the center of the curved shape of the first active layer ACT1 and is parallel to the second direction DR2. In an embodiment, the imaginary line SML may pass through the center of each of the first recess RP1b, the second recess RP2b, and the opening OP. In an embodiment, each of the first recess RP1b, the second recess RP2b, and the opening OP may be symmetrical with respect to the imaginary line SML.

[0171] In an embodiment, the opening OP may have a rectangular shape in a plan view. However, the shape of the opening OP in a plan view according to embodiments of the present disclosure is not limited to this, and may have various shapes in a plan view that can expose the upper surface of the first gate pattern 1200b. Furthermore, depending on the shape of the opening OP, the second gate pattern 2200b may have a shape asymmetrical with respect to the imaginary line SML in a plan view.

[0172] In an embodiment, the bottom metal layer BMLb may have a shape substantially the same as that of the first gate pattern 1200b in a plan view (e.g., a "C" shape). Specifically, the bottom metal layer BMLb may have a "C" shape in a plan view that is symmetrical with respect to the imaginary line SML while completely surrounding the outer edge (or outer boundary) of the first gate pattern 1200b. However, the shape of each of the bottom metal layer BMLb and the first gate pattern 1200b in a plan view according to embodiments of the present disclosure may not be limited to this.

[0173] The second gate pattern 2200b may overlap with the portion of the first active layer ACT1 extending from the first-first channel portion C1-1b to the first-second channel portion C1-2b in a plan view. The opening OP may be spaced apart from the first recess RP1b in a direction opposite to the second direction DR2. In an embodiment, the opening OP may not overlap with the first active layer ACT1 in a plan view. Specifically, the opening OP may expose the upper surface of the portion of the first gate pattern 1200b that does not overlap with the first active layer ACT1. However, the location of the opening OP according to embodiments of this disclosure is not limited to this, and the opening OP may overlap with the first active layer ACT1 in a plan view.

[0174] In an embodiment, the areas of the first-first-channel portion C1-1b and the first-second-channel portion C1-2b, which are the portions of the first active layer ACT1 that overlap with the first gate pattern 1200b, can be substantially equal to each other. Therefore, the first channel length CH1b of the first-first-channel portion C1-1b and the second channel length CH2b of the first-second-channel portion C1-2b can be substantially equal to each other.

[0175] In an embodiment, the first channel length CH1b and the second channel length CH2b can each be about 6.5 μm to about 9.5 μm. Preferably, the first channel length CH1b and the second channel length CH2b can be about 8 μm. However, the values ​​of the first channel length CH1b and the second channel length CH2b according to embodiments of the present disclosure are not limited to these.

[0176] ​ This is a layout diagram showing a first transistor according to another embodiment. For example, ​It corresponds to ​ The view.

[0177] Apart from the shape of each of the bottom metal layer BMLc and the first gate pattern 1200c, refer to ​ The described display device DDc can be compared with the reference ​ The described display device DD is substantially the same as or similar to the one referenced. Therefore, omissions or simplifications will be made in accordance with the reference. ​ and ​ The content described is repetitive.

[0178] Reference ​ The display device DDc may include a bottom metal layer BMLc defining a recess RPc, a first gate pattern 1200c, and a second gate pattern 2200. The bottom metal layer BMLc may expose at least a portion of the rear surface of the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1c and the first-second channel portion C1-2c. The first gate pattern 1200c may expose the upper surface of the portion of the first active layer ACT1 disposed between the first-first channel portion C1-1c and the first-second channel portion C1-2c.

[0179] Each of the bottom metal layer BMLc and the first gate pattern 1200c may be symmetrical with respect to an imaginary line SML that passes through the center of the curved shape of the first active layer ACT1 and is parallel to the second direction DR2. In an embodiment, each of the bottom metal layer BMLc and the first gate pattern 1200c may have a rectangular shape in a plan view. However, the shape of the first gate pattern 1200c in a plan view according to embodiments of the present disclosure is not limited to this.

[0180] In an embodiment, the shape of the second gate pattern 2200 may be asymmetrical with respect to the imaginary line SML. The recess RPc of the second gate pattern 2200 may expose the upper surface of the portion of the first gate pattern 1200c that overlaps with the first-second channel portions C1-2c. However, the position of the recess RPc of the second gate pattern 2200 according to embodiments of the present disclosure is not limited to this, and in another embodiment, the recess RPc may expose the upper surface of the portion of the first gate pattern 1200c that overlaps with the first-first channel portion C1-1c, or it may expose the upper surface of the portion of the first gate pattern 1200c that does not overlap with the first active layer ACT1. Furthermore, depending on the position of the recess RPc, the second gate pattern 2200 may have a shape symmetrical with respect to the imaginary line SML in a plan view.

[0181] ​ The first gate pattern 1200c shown in the figure and ​The first gate pattern 1200b shown can have a shape symmetrical with respect to the imaginary line SML in a planar view, but ​ The area of ​​the portion of the first gate pattern 1200c that overlaps with the first active layer ACT1 shown in the figure can be smaller than 1 / 2. ​ The area of ​​the portion of the first gate pattern 1200b that overlaps with the first active layer ACT1 is shown in the diagram. Therefore, it has ​ The sum of the lengths of the first-first channel and the first-second channel of the display device DDc shown in the diagram can be less than the length of the first-first channel. ​ The structure shown in the figure represents the sum of the first-first channel length CH1b and the first-second channel length CH2b of the display device DDb.

[0182] ​ This is a layout diagram showing a first transistor according to yet another embodiment. For example, ​ It corresponds to ​ The view.

[0183] Except for the shape of each of the bottom metal layer BMLd, the first active layer ACT1d, the first gate pattern 1200d, and the second gate pattern 2200d, refer to ​ The described display device DDd can be compared with the reference ​ The described display device DD is substantially the same as or similar to the one referenced. Therefore, omissions or simplifications will be made in accordance with the reference. ​ The content described is repetitive.

[0184] Reference ​ The display device DDd may include a bottom metal layer BMLd defining a first opening OP1d, a first active layer ACT1d, a first gate pattern 1200d defining a second opening OP2d, and a second gate pattern 2200d defining a third opening OP3d. The first opening OP1d may expose the rear surface of the portion of the first active layer ACT1d disposed between the first-first channel portion C1-1d and the first-second channel portion C1-2d. The second opening OP2d may expose the upper surface of the portion of the first active layer ACT1d disposed between the first-first channel portion C1-1d and the first-second channel portion C1-2d. The third opening OP3d may expose a portion of the upper surface of the first gate pattern 1200d. In an embodiment, the third opening OP3d may expose the upper surface of the portion of the first gate pattern 1200d that overlaps with the first-first channel portion C1-1d. However, the location of the third opening OP3d according to the embodiments of the present disclosure is not limited to this, and the third opening OP3d may expose the upper surface of the portion of the first gate pattern 1200d that overlaps with the first-second channel portion C1-2d.

[0185] The first opening OP1d, the second opening OP2d, and the third opening OP3d can be defined as the shape of a hole whose boundaries are surrounded by a bottom metal layer BMLd, a first gate pattern 1200d, and a second gate pattern 2200d, respectively.

[0186] The first opening OP1d and the second opening OP2d may overlap each other in a planar view. The third opening OP3d may be spaced apart from each of the first opening OP1d and the second opening OP2d in the opposite direction to the first direction DR1. In an embodiment, the bottom metal layer BMLd, the first gate pattern 1200d, and the second gate pattern 2200d may have substantially the same shape in a planar view. For example, each of the bottom metal layer BMLd, the first gate pattern 1200d, and the second gate pattern 2200d may have a rectangular shape in a planar view, comprising a hole defined therein. In an embodiment, the first active layer ACT1d may extend along and parallel to the second direction DR2. However, the shape of each of the first gate pattern 1200d, the second gate pattern 2200d, the bottom metal layer BMLd, and the first active layer ACT1d may not be limited to this and may have various shapes in a planar view.

[0187] In an embodiment, the shape of each of the first gate pattern 1200d, the second gate pattern 2200d, and the bottom metal layer BMLd can be asymmetrical in a planar view with respect to an imaginary line SML extending through the center of the first active layer ACT1d and in a direction parallel to the second direction DR2. Because the first gate pattern 1200d has an asymmetrical shape with respect to the imaginary line SML, the first channel length CH1d and the second channel length CH2d can be different from each other in a planar view. For example, the first channel length CH1d can be greater than the second channel length CH2d.

[0188] In one embodiment, the first opening OP1d and the second opening OP2d may be positioned relative to the imaginary line SML in the first direction DR1. In another embodiment, the third opening OP3d may be positioned relative to the imaginary line SML in a direction opposite to the first direction DR1.

[0189] ​ This is a layout diagram showing a first transistor according to another embodiment. For example, ​ It corresponds to ​ The view.

[0190] In addition to the shape of each of the bottom metal layer BMLe and the first gate pattern 1200e, refer to ​ The described display device DDe can be compared with the reference ​The described display device DDd is substantially the same as or similar to the one referenced. Therefore, omissions or simplifications will be made in accordance with the reference. ​ The content described is repetitive.

[0191] Reference ​ The display device DDe may include a bottom metal layer BMLe defining a first opening OP1e, a first active layer ACT1e, a first gate pattern 1200e defining a second opening OP2e, and a second gate pattern 2200e defining a third opening OP3e.

[0192] In one embodiment, the shape of each of the bottom metal layer BMLe and the first gate pattern 1200e can be symmetrical in a planar view with respect to an imaginary line SML extending through the center of the first active layer ACT1e and in a direction parallel to the second direction DR2. Since the first gate pattern 1200e has a shape symmetrical with respect to the imaginary line SML in the planar view, the first channel length CH1e and the second channel length CH2e can be substantially equal to each other. In another embodiment, the first channel length CH1e can be greater than the second channel length CH2e. The imaginary line SML may not intersect with the third opening OP3e in the planar view.

[0193] ​ This is a block diagram illustrating an electronic device according to an embodiment.

[0194] Reference ​ In an embodiment, the electronic device ED may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may correspond to... ​ The display device DD. The electronic device ED may also include multiple ports for communicating with video cards, sound cards, memory cards, or Universal Serial Bus (“USB”) devices. In one embodiment, the electronic device ED may be implemented as a television set. In another embodiment, the electronic device ED may be implemented as a smartphone. However, the embodiments are not limited thereto; in another embodiment, the electronic device ED may be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC (“PC”), car navigation system, computer monitor, laptop computer, or head-mounted display (e.g., head-mounted display (“HMD”)).

[0195] Processor 1010 can perform various computing functions. In embodiments, processor 1010 may be a microprocessor, a central processing unit (“CPU”), or an application processor (“AP”), etc. Processor 1010 may be coupled to other components via address buses, control buses, or data buses, etc. In embodiments, processor 1010 may be coupled to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0196] The memory device 1020 can store data for the operation of the electronic device ED. In embodiments, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PCRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, or a ferroelectric random access memory (“FRAM”) device and / or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, or a mobile DRAM device.

[0197] In an embodiment, storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, or an optical disc read-only memory (“CD-ROM”) device, etc. In an embodiment, I / O device 1040 may include input devices such as a keyboard, keypad, mouse device, touchpad, or touch screen, and output devices such as a printer or speaker.

[0198] Power supply 1050 can provide power for the operation of electronic device ED. Power supply 1050 can also provide power to display device 1060. Display device 1060 can be coupled to other components via a bus or other communication link. In an embodiment, display device 1060 may be included in I / O device 1040.

[0199] Although the apparatus according to embodiments has been described with reference to the accompanying drawings, the embodiments shown are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims.

Claims

1. A display device, wherein, The display device includes: a first active layer provided over a substrate and including a first drive channel portion and a second drive channel portion spaced apart from the first drive channel portion; a first gate pattern provided over the first active layer, overlapping each of the first drive channel portion and the second drive channel portion in a plan view, and exposing a portion of the first active layer provided between the first drive channel portion and the second drive channel portion; a second gate pattern provided over the first gate pattern, overlapping the first gate pattern in the plan view, and exposing a portion of the first gate pattern; and a light emitting element provided over the second gate pattern.

2. The display device according to claim 1, wherein The display device further includes: a bottom metal layer provided between the substrate and the first active layer in a cross-sectional view, and overlapping each of the first drive channel portion and the second drive channel portion in the plan view.

3. The display device of claim 2, wherein, The bottom metal layer exposes at least a portion of a back surface of the portion of the first active layer provided between the first drive channel portion and the second drive channel portion.

4. The display device according to claim 2, wherein An area of the bottom metal layer is greater than an area of the first gate pattern.

5. The display device according to claim 1, wherein The display device further includes: a first electrode and a second electrode provided over the second gate pattern and electrically connected to the first active layer, wherein the first active layer, the first gate pattern, the first electrode, and the second electrode together define a drive transistor.

6. The display device of claim 5, wherein, The drive transistor includes: a first sub-transistor including the first drive channel portion; and a second sub-transistor including the second drive channel portion.

7. The display device according to claim 5, wherein The display device further includes: a second active layer provided over the second gate pattern; a third gate pattern provided over the second active layer; and a third electrode and a fourth electrode provided over the third gate pattern, and the third electrode and the fourth electrode are provided in the same layer as the first electrode and the second electrode, wherein the second active layer, the third gate pattern, the third electrode, and the fourth electrode define a compensation transistor or an initialization transistor.

8. The display device of claim 7, wherein, The first active layer includes a silicon semiconductor, and The second active layer includes an oxide semiconductor.

9. The display device according to claim 1, wherein The first drive channel portion and the second drive channel portion are symmetrical with respect to an imaginary line passing through a center of the first active layer provided between the first drive channel portion and the second drive channel portion in the plan view.

10. The display device according to claim 1, wherein The portion of the first gate pattern exposed by the second gate pattern overlaps the first drive channel portion in the plan view.

11. The display device according to claim 1, wherein The portion of the first gate pattern exposed by the second gate pattern overlaps the second drive channel portion in the plan view.

12. A display device, wherein, The display device includes: a data write transistor configured to transmit a data voltage to a first node in response to a write signal; a driving transistor configured to generate a driving current corresponding to the data voltage and including: a first sub-transistor including a first terminal connected to the first node, a second terminal opposite to the first terminal, and a gate terminal connected to a second node; and a second sub-transistor including a first terminal connected to the second terminal of the first sub-transistor, a second terminal connected to a third node, and a gate terminal connected to the second node; a storage capacitor configured to store the data voltage and including a first terminal connected to the second node and a second terminal configured to receive a driving voltage; and a light emitting element emitting light with a luminance corresponding to a magnitude of the driving current.

13. The display device of claim 12, wherein, The first sub-transistor and the second sub-transistor are connected in series between the first node and the third node.

14. The display device of claim 12, wherein, The display device further includes: a compensation transistor including a first terminal connected to the third node, a second terminal connected to a fourth node, and a gate terminal configured to receive a compensation signal; and an initialization transistor including a first terminal connected to the fourth node, a second terminal configured to receive an initialization voltage, and a gate terminal configured to receive an initialization signal.

15. The display device of claim 12, wherein, The display device further includes: a first active layer including a first driving channel portion and a second driving channel portion, the first driving channel portion defining a channel of the first sub-transistor, the second driving channel portion defining a channel of the second sub-transistor; and a first gate pattern disposed on the first active layer and defining the gate terminal of the first sub-transistor and the gate terminal of the second sub-transistor.

16. The display device of claim 15, wherein, The first gate pattern exposes a portion of the first active layer disposed between the first driving channel portion and the second driving channel portion.

17. The display device of claim 16, wherein, The display device further includes: a second gate pattern disposed on the first gate pattern and defining the second terminal of the storage capacitor, wherein the second gate pattern exposes a portion of the first gate pattern.

18. The display device of claim 17, wherein, The display device further includes: a bottom metal layer disposed between a substrate and the first active layer in a cross-sectional view and overlapping each of the first driving channel portion and the second driving channel portion in a plan view, wherein the bottom metal layer exposes at least a portion of a back surface of the portion of the first active layer disposed between the first driving channel portion and the second driving channel portion.

19. The display device of claim 18, wherein, Each of the first sub-transistor and the second sub-transistor further includes a bottom gate terminal, and the bottom metal layer defines the bottom gate terminal of the first sub-transistor and the bottom gate terminal of the second sub-transistor.

20. An electronic device, comprising: The electronic device includes: a display device; and a power supply configured to supply power to the display device, wherein the display device includes: a first active layer disposed on a substrate and including a first driving channel portion and a second driving channel portion, the second driving channel portion being spaced apart from the first driving channel portion; a first gate pattern disposed on the first active layer and defining a gate terminal of a first sub-transistor and a gate terminal of a second sub-transistor, the first sub-transistor and the second sub-transistor being connected in series between a first node and a third node, the first node being connected to the first driving channel portion, the third node being connected to the second driving channel portion, the first gate pattern exposing a portion of the first active layer disposed between the first driving channel portion and the second driving channel portion; and a storage capacitor including a first terminal connected to the second node and a second terminal configured to receive a driving voltage, the second terminal being disposed on the first gate pattern. a first gate pattern provided on the first active layer, overlapping each of the first drive channel portion and the second drive channel portion in a plan view, and exposing a portion of the first active layer provided between the first drive channel portion and the second drive channel portion; a second gate pattern provided on the first gate pattern, overlapping the first gate pattern in the plan view, and exposing a portion of the first gate pattern; and a light emitting element provided on the second gate pattern.

Images