Thin film transistor, method of manufacturing the same, and display device including the same

Abstract

Disclosed are a thin film transistor, a method of manufacturing the same, and a display device including the same. One embodiment of the present disclosure provides a thin film transistor including: a seed layer having an inclined surface; an active layer contacting the seed layer and including a channel portion; and a gate electrode overlapping at least a portion of the active layer, in which the channel portion has a crystal structure, in which the channel portion is disposed on and contacts the inclined surface, and in which at least a portion of the gate electrode is disposed to face the inclined surface, the active layer being interposed between the at least a portion of the gate electrode and the inclined surface. In addition, another embodiment of the present disclosure provides a method of manufacturing a thin film transistor and a display device including the thin film transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a thin film transistor having a seed layer, a method for manufacturing a thin film transistor, and a display device including the thin film transistor. BACKGROUND

[0002] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin film transistors can be manufactured on a glass or plastic substrate, thin film transistors are widely used as switching devices in display devices such as liquid crystal display devices or organic light emitting devices.

[0003] Thin film transistors can be classified into amorphous silicon thin film transistors in which amorphous silicon is used as an active layer, poly-silicon thin film transistors in which poly-silicon is used as an active layer, and oxide semiconductor thin film transistors in which an oxide semiconductor is used as an active layer, based on the material constituting the active layer.

[0004] Since amorphous silicon can be deposited in a short time to form an active layer, amorphous silicon thin film transistors (a-Si TFTs) have the advantages of a short manufacturing process time and low production costs. On the other hand, amorphous silicon thin film transistors have the disadvantage of being limited in use in active matrix organic light emitting diodes (AMOLEDs) due to low mobility, poor current driving capability, and threshold voltage variation.

[0005] Poly-silicon thin film transistors (poly-Si TFTs) are made by crystallizing amorphous silicon after the amorphous silicon has been deposited. Poly-silicon thin film transistors have the advantages of high electron mobility, excellent stability, thin thickness, high resolution, and high power efficiency. Examples of such poly-silicon thin film transistors include low temperature poly-silicon (LTPS) thin film transistors or poly-silicon thin film transistors. Since the manufacturing process of poly-silicon thin film transistors requires a process of crystallizing amorphous silicon, the number of processes increases, which increases manufacturing costs, and crystallization must be performed at a high process temperature.

[0006] Oxide semiconductor thin film transistors, which have high mobility and large resistance variation depending on the oxygen content, have the advantage of being able to easily obtain desired properties. In addition, since the oxide constituting the active layer can be formed at a relatively low temperature in the manufacturing process of oxide semiconductor thin film transistors, manufacturing costs are low. Since oxide semiconductors are transparent due to the properties of the oxide, they are also advantageous in realizing transparent displays.

[0007] However, the performance of oxide semiconductor thin-film transistors (OSTs) can degrade, and their on-state voltage can become unstable due to hydrogen. In particular, hydrogen-induced performance degradation or instability can become severe when OSTs are used in environments containing large amounts of hydrogen or at high temperatures. Therefore, to prevent degradation and improve the stability of OSTs, it is necessary to protect them from the effects of hydrogen.

[0008] Furthermore, electronic products have recently become more highly integrated. Additionally, the demand for high-resolution display devices is increasing. To achieve high integration and high resolution, the size and area of ​​thin-film transistors (TFTs) need to be reduced. Therefore, it is necessary to manufacture TFTs in narrow areas.

[0009] The descriptions provided in the background section should not be construed as prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0010] One embodiment of this disclosure provides a thin-film transistor including a seed layer having a tilted surface and a gate disposed facing the tilted surface of the seed layer. Another embodiment of this disclosure provides a thin-film transistor with a vertical structure including a channel portion disposed on the tilted surface of the seed layer.

[0011] One embodiment of this disclosure is to provide a thin-film transistor having a vertical structure that ensures channel length even within a limited area.

[0012] One embodiment of this disclosure is to provide a thin-film transistor with a narrow area.

[0013] One embodiment of this disclosure is to provide a thin-film transistor having a crystalline channel and excellent hydrogen resistance.

[0014] Another embodiment of this disclosure provides a method for fabricating a thin-film transistor with a vertical structure by using an oxide semiconductor material having conductive properties and a seed layer.

[0015] Another embodiment of this disclosure provides a display device with excellent reliability, which includes the thin-film transistor as described above.

[0016] One embodiment of the present disclosure for achieving the above-described technical subject matter provides a thin-film transistor, the thin-film transistor comprising: a seed layer having a tilted surface; an active layer contacting the seed layer and including a channel portion; and a gate overlapping at least a portion of the active layer, wherein the channel portion has a crystal structure, wherein the channel portion is disposed on and in contact with the tilted surface, and wherein at least a portion of the gate is disposed facing the tilted surface, and the active layer is interposed between at least a portion of the gate and the tilted surface.

[0017] The active layer may further include a first connection portion connected to one side of the channel portion and a second connection portion connected to the other side of the channel portion, and both the first connection portion and the second connection portion may have an amorphous structure.

[0018] The first and second connecting parts do not contact the seed crystal layer.

[0019] In the plan view, in the portion where the gate is located, the width of the seed layer is greater than the width of the active layer. Here, the widths of the seed layer and the active layer are measured in a direction perpendicular to the line connecting the first and second connection portions.

[0020] The aforementioned seed crystal layer can have an amorphous structure.

[0021] The seed layer is an amorphous layer in which the sum of the areas of crystals with a grain size of 1 nm or larger in the cross-section of the seed layer is 10% or less of the total cross-sectional area.

[0022] The seed layer can have a lower carrier concentration than the channel.

[0023] The seed layer can have a size of 1.0 × 10⁻⁶. 16 ea / cm 3 Or even lower carrier concentration.

[0024] The seed layer may include at least one oxide semiconductor material selected from IZO (InZnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, and GO (GaO)-based oxide semiconductor material.

[0025] The active layer may include at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, GO (GaO) based oxide semiconductor material, TO (SnO) based oxide semiconductor material, ITO (InSnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, ZO (ZnO) based oxide semiconductor material, InO (InO) based oxide semiconductor material, and FIZO (FeInZnO) based oxide semiconductor material.

[0026] The active layer may also include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr).

[0027] The seed layer and the active layer may include at least one common metallic element.

[0028] In the cross-section of the channel, the sum of the areas of crystals with a grain size of 1 nm or larger is 50% or greater than the total cross-sectional area.

[0029] The channel portion may include at least one of the following: (400) crystal plane, (222) crystal plane, (220) crystal plane, (311) crystal plane, and (001) crystal plane.

[0030] The thin-film transistor also includes a source and a drain spaced apart from each other, wherein the source can contact the seed layer and the first connection portion, and wherein the drain can contact the seed layer and the second connection portion.

[0031] The seed layer may have a recess, wherein the recess may be defined by an inclined surface and a bottom surface, and wherein the active layer may be disposed on the inclined surface and the bottom surface of the recess.

[0032] The bottom surface can be part of the seed layer, and the channel can extend from the inclined surface to the bottom surface.

[0033] The thin-film transistor may further include a metal layer disposed on the bottom surface of the recess, wherein the active layer may further include a third connection portion in contact with the metal layer.

[0034] The third connecting part can have an amorphous structure.

[0035] Another embodiment of this disclosure provides a display device including the thin-film transistors described above.

[0036] Another embodiment of this disclosure provides a method for manufacturing a thin-film transistor, the method comprising the following steps: forming a seed material layer on a substrate; forming a seed layer having a tilted surface by patterning the seed material layer; forming an active layer that contacts the tilted surface of the seed layer; heat-treating the active layer to crystallize a portion of the active layer that contacts the tilted surface; and forming a gate on the active layer, wherein at least a portion of the gate may be configured to face the tilted surface, and the active layer is interposed between at least a portion of the gate and the tilted surface.

[0037] Before heat treatment, the active layer can have an amorphous structure.

[0038] The heat treatment temperature can be in the range of 300℃ to 500℃.

[0039] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0040] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0041] Figure 1 This is a plan view of a thin-film transistor according to one embodiment of the present disclosure.

[0042] Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0043] Figure 3 It is along Figure 1 The cross-sectional view taken from line II-II'.

[0044] Figure 4 This is a plan view of a thin-film transistor according to another embodiment of the present disclosure.

[0045] Figure 5 It is along Figure 4 The cross-sectional view taken from line III-III'.

[0046] Figure 6 This is a plan view of a thin-film transistor according to another embodiment of the present disclosure.

[0047] Figure 7 It is along Figure 6 A cross-sectional view taken from line IV-IV'.

[0048] Figure 8 This is a plan view of a thin-film transistor according to another embodiment of the present disclosure.

[0049] Figure 9 It is along Figure 8 A cross-sectional view taken from line V-V'.

[0050] Figures 10A to 101 This is a cross-sectional view showing a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure.

[0051] Figure 11 This is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0052] Figure 12 yes Figure 11 A circuit diagram for one pixel.

[0053] Figure 13 yes Figure 12 A planar image of pixels.

[0054] Figure 14 It is along Figure 13 The cross-sectional view taken from line VI-VI'. Detailed Implementation

[0055] The advantages and features of this disclosure, as well as the methods for implementing them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various other forms. These embodiments are provided to ensure that the disclosure is complete and to enable those skilled in the art to readily understand it.

[0056] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to illustrate embodiments of this disclosure are exemplary, and this disclosure is not limited to what is shown in the drawings. Throughout the specification, the same components may be represented by the same reference numerals. Furthermore, in describing this disclosure, detailed descriptions of related known technologies are omitted if it is determined that such detailed descriptions may unnecessarily obscure the main points of this disclosure.

[0057] In this specification, when the words “comprising,” “having,” and “consisting of” are used, other components may be added unless the expression “only” is used. When a component is represented in the singular, the plural is included unless otherwise expressly stated.

[0058] When describing a component, even if there is no separate explicit description, it is interpreted as including the tolerance range.

[0059] When describing positional relationships, for example, when the positional relationship between two parts is described as "on top of", "above", "below", "next to", etc., one or more other parts may be located between the two parts unless the expressions "exactly" or "directly" are used.

[0060] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used to readily describe the relationship between one element or component and another, as shown in the accompanying drawings. Spatial relative terms should be understood to include not only the orientation depicted in the drawings but also different orientations of the elements during use or operation. For example, if the elements shown in the drawings are flipped, an element described as “below” or “under” another element may ultimately be positioned “above” another element. Thus, the exemplary term “below” can include both above and below directions. Similarly, the exemplary term “above” can include both above and below directions.

[0061] When describing temporal relationships, such as those described as “after,” “next,” “next,” or “before,” it can also include cases where there is no continuity, as long as the expressions “immediately” or “directly” are not used.

[0062] Although the terms "first," "second," "third," and "fourth" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be a second component within the technical concept of this disclosure.

[0063] At least one term should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of "at least one of the first, second, and third items" can refer not only to each of the first, second, or third items, but also to all combinations that can be presented from two or more of the first, second, and third items.

[0064] The various features of the various embodiments of this disclosure can be combined in part or in whole, or combined with each other, and can be technically linked and driven in various ways, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship.

[0065] Any implementation described as an "example" in this document is not necessarily to be construed as preferred or superior to other implementations.

[0066] Furthermore, when a component or layer is “connected,” “joined,” or “adhered” to another component or layer, unless otherwise stated, the component or layer may not only be directly connected or adhered to the other component or layer, but also indirectly connected or adhered to the other component or layer, with one or more intermediate components or layers “set” or “intercalated” between the components or layers. This should be understood to mean that components may be arranged to be in direct contact with each other, or may be arranged to be in direct contact with each other.

[0067] The terms “first element,” “second element,” and / or “third element” should be understood as one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0068] Unless otherwise defined, all terms used herein (including technical and scientific terms) should be interpreted as having the same meaning as those defined in common dictionaries as those in exemplary embodiments, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the functions described herein as would be understood by one of ordinary skill in the art.

[0069] Instead, these implementations may be provided to make this disclosure thorough and complete enough to help those skilled in the art to fully understand the scope of this disclosure.

[0070] In the following, a thin-film transistor and a display device including the thin-film transistor according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components may be given the same numerals as much as possible, even if they are shown in different drawings.

[0071] In embodiments of this disclosure, the source and drain are different, but they can be interchanged. For example, the source according to one embodiment can become the drain in another embodiment, and the drain according to one embodiment can become the source in another embodiment.

[0072] In the embodiments of this disclosure, for ease of explanation, a distinction is made between the source region and the source, and between the drain region and the drain, but the embodiments of this disclosure are not limited thereto. The source region can be the source, and the drain region can be the drain. Alternatively, the source region can be the drain, and the drain region can be the source.

[0073] Figure 1 This is a plan view of a thin-film transistor 100 according to one embodiment of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken from line I-I'. Figure 3 It is along Figure 1 The cross-sectional view taken from line II-II'.

[0074] A thin-film transistor 100 according to one embodiment of the present disclosure includes a seed layer 120 having a tilted surface 120s, an active layer 130 contacting the seed layer 120, and a gate 150 at least partially overlapping the active layer 130. The active layer 130 includes a channel portion 130n. The channel portion 130n has a crystal structure.

[0075] The channel portion 130n is disposed on and contacts the inclined surface 120s of the seed layer 120. At least a portion of the gate 150 is disposed facing the inclined surface 120s of the seed layer 120, and the active layer 130 is interposed between at least a portion of the gate 150 and the inclined surface 120s of the seed layer 120.

[0076] Reference Figure 2 and Figure 3 The thin-film transistor 100 can be disposed on the substrate 110. Anything supporting the thin-film transistor 100 can be referred to as the substrate 110 without limitation.

[0077] Glass or plastic can be used as substrate 110. Transparent plastic with flexible properties can be used as substrate 110. In plastics, for example, when polyimide is used as substrate 110, heat-resistant polyimide that can withstand high temperatures can be used, taking into account the high-temperature deposition process performed on substrate 110.

[0078] A buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may be made of an insulating material. For example, the buffer layer 115 may include at least one of insulating materials such as silicon oxide, silicon nitride, and metal oxides. The buffer layer 115 may have a single-film structure or a multi-film structure. The buffer layer 115 can protect the active layer 130 by blocking air and moisture. The buffer layer 115 can make the upper surface of the substrate 110 uniform.

[0079] Buffer layer 115 can be omitted.

[0080] The source electrode 161 can be disposed on the buffer layer 115. The source electrode 161 can also be directly disposed on the substrate 110. However, one embodiment of this disclosure is not limited to this, and the source electrode 161 can also be disposed on the seed layer 120.

[0081] The seed layer 120 can be disposed on the source electrode 161. However, one embodiment of this disclosure is not limited to this, and the seed layer 120 can be directly disposed on the substrate 110. The seed layer 120 can also be disposed on the buffer layer 115.

[0082] The seed layer 120 selectively crystallizes the portion of the active layer 130 that is in contact with the seed layer 120. The seed layer 120 serves as a seed for crystal growth. Selected portions of the active layer 130 can be crystallized through the seed layer 120. As a result, a portion of the active layer 130 can be crystalline.

[0083] According to one embodiment of this disclosure, the seed layer 120 may include an oxide semiconductor material.

[0084] For example, the seed layer 120 may include at least one of IZO (InZnO) based oxide semiconductor material, IGZO (InGaZnO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material and GO (GaO) based oxide semiconductor material.

[0085] According to one embodiment of this disclosure, the seed layer 120 may have a basic composition made of an oxide semiconductor material, but includes a large amount of oxygen. As a result, the seed layer 120 may have the characteristics of an insulating layer in terms of electrical properties. The seed layer 120 selectively crystallizes the active layer 130 and does not affect the electrical properties of the active layer 130.

[0086] In detail, the seed layer 120 can be formed of an oxide semiconductor material having a low carrier concentration and a high oxygen concentration. According to one embodiment of this disclosure, the seed layer 120 can have a high resistivity. The seed layer 120 with high resistivity has electrical properties similar to an insulator and does not participate in carrier migration of the active layer 130. According to one embodiment of this disclosure, the seed layer 120 can have a lower carrier concentration than the channel portion 130n of the active layer 130.

[0087] According to one embodiment of this disclosure, the seed layer 120 may have a density of 1.0 × 10⁻⁶. 16 ea / cm 3 Or even lower carrier concentrations. When the carrier concentration of the seed layer 120 is 1.0 × 10⁻⁶. 16 ea / cm 3 When the seed layer 120 is smaller, it can have electrical properties close to those of an insulating layer.

[0088] According to one embodiment of this disclosure, the seed layer 120 may have a density of 1.0 × 10⁻⁶. 16 ea / cm 3 The seed layer 120 has a low carrier concentration, or even lower, and therefore has insulating properties. Thus, the seed layer 120 can remain unaffected by the conduction current characteristics of the thin-film transistor 100.

[0089] The seed layer 120 may have an amorphous structure. According to one embodiment of the present disclosure, the seed layer 120 may be an amorphous layer.

[0090] According to one embodiment of this disclosure, when the sum of the areas of crystals with a grain size of 1 nm or larger is 10% or less relative to the total cross-sectional area based on the cross-section of the layer, the layer is referred to as an amorphous layer. Specifically, based on a transmission electron microscope (TEM) image of the cross-section of the layer to be measured, when the sum of the areas of crystals with a grain size of 1 nm or larger is 10% or less relative to the total cross-sectional area, the layer is referred to as an amorphous layer.

[0091] According to one embodiment of this disclosure, the seed layer 120 may be an amorphous layer, wherein, based on the cross-section, the sum of the areas of crystals with a grain size of 1 nm or larger is 10% or less relative to the total cross-sectional area.

[0092] On the other hand, if the sum of the areas of crystals with a grain size of 1 nm or larger is 50% or greater of the total cross-sectional area based on the layer's cross-section, then the layer is called a crystalline layer. Specifically, based on a transmission electron microscope (TEM) image of the cross-section of the layer to be measured, if the sum of the areas of crystals with a grain size of 1 nm or larger is 50% or greater of the total cross-sectional area, then the layer is called a crystalline layer.

[0093] Reference Figure 2 The seed layer 120 may have a tilted surface 120s. After a seed material layer is formed by means of a material used to form the seed layer 120, the seed material layer may be patterned, thereby forming a seed layer 120 with a tilted surface 120s.

[0094] The inclined surface 120s of the seed layer 120 can have a predetermined inclination angle θ based on the upper surface of the substrate 110. According to one embodiment of this disclosure, the angle between the upper surface of the substrate 110 and the inclined surface 120s of the seed layer 120 is referred to as the inclination angle θ. When the upper surface of the source 161 and the upper surface of the substrate 110 are parallel to each other, such as... Figure 2 As shown, the angle between the upper surface of the source 161 and the inclined surface 120s of the seed layer 120 can be called the tilt angle θ.

[0095] Drain 162 may be disposed on seed layer 120. In one embodiment of this disclosure, source 161 and drain 162 are distinguished only for ease of illustration, and source 161 and drain 162 are not limited to... Figure 2 .exist Figure 2 In this configuration, the positions of source 161 and drain 162 can be interchanged.

[0096] Both source 161 and drain 162 may comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. Source 161 and drain 162 may each be formed as a single layer of metal or metal alloy, or may be formed as a multilayer of two or more layers.

[0097] According to one embodiment of this disclosure, an active layer 130 may be disposed on a seed layer 120. At least a portion of the active layer 130 may contact the seed layer 120.

[0098] Reference Figure 2 and Figure 3 The active layer 130 can be disposed on the source 161, drain 162, and seed layer 120. The active layer 130 is disposed on the inclined surface 120s of the seed layer 120. At least a portion of the active layer 130 can contact the inclined surface 120s of the seed layer 120.

[0099] According to one embodiment of the present disclosure, the active layer 130 includes a channel portion 130n. Furthermore, the active layer 130 includes a first connecting portion 130a connected to one side of the channel portion 130n and a second connecting portion 130b connected to the other side of the channel portion 130n.

[0100] According to one embodiment of this disclosure, the channel portion 130n may have a crystalline structure. The first connecting portion 130a and the second connecting portion 130b may each have an amorphous structure.

[0101] According to one embodiment of this disclosure, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material. The active layer 130 may include, for example, an oxide semiconductor layer.

[0102] exist Figures 1 to 3 The image shows, as an example, a thin-film transistor 100 in which the active layer 130 is an oxide semiconductor layer.

[0103] According to one embodiment of this disclosure, the active layer 130 may be formed of an oxide semiconductor material having a high mobility similar to that of a conductor. For example, the active layer 130 may be formed of a material with a carrier concentration of 1.0 × 10⁻⁶. 19 ea / cm 3 Alternatively, a larger amorphous oxide semiconductor material may be formed. On the other hand, the seed layer 120 may be formed of an amorphous oxide semiconductor material having a carrier concentration lower than that of the active layer 130.

[0104] The active layer 130 may include at least one of the following: IGZO (InGaZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, GO (GaO) based oxide semiconductor material, TO (SnO) based oxide semiconductor material, ITO (InSnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, IZO (InZnO) based oxide semiconductor material, ZO (ZnO) based oxide semiconductor material, and InO (InO) based oxide semiconductor material. It may also include FIZO (FeInZnO) based oxide semiconductor material. However, one embodiment of this disclosure is not limited to this, and other known oxide semiconductor materials with high mobility may be applied to the active layer 130 according to one embodiment of this disclosure.

[0105] According to one embodiment of this disclosure, an indium-based oxide semiconductor material with an indium (In) content of 50 atomic percent (at%) or more, based on the number of atoms in all metal elements, can be used as the oxide semiconductor material for forming the active layer 130. The active layer 130 may include at least one of, for example, IZO (InZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, ITO (InSnO)-based oxide semiconductor materials, and IGZTO (InGaZnSnO)-based oxide semiconductor materials, wherein the indium (In) content is 50 atomic percent (at%) or more based on the number of atoms in all metal elements.

[0106] In detail, the active layer 130 may include an IZO-based oxide semiconductor material having an indium (In) content of 50 at% or more relative to the total content of indium (In) and zinc (Zn), an IGO-based oxide semiconductor material having an indium (In) content of 70 at% or more relative to the total content of indium (In) and gallium (Ga), an IGZO-based oxide semiconductor material having an indium (In) content of 50 at% or more relative to the total content of indium (In), gallium (Ga) and zinc (Zn), an ITO-based oxide semiconductor material having an indium (In) content of 80 at% or more relative to the total content of indium (In) and tin (Sn), and an IGZTO-type oxide semiconductor material having a mixed content of indium (In) and tin (Sn) of 50 at% or more relative to the total content of indium (In), gallium (Ga), zinc (Zn) and tin (Sn).

[0107] According to one embodiment of this disclosure, the active layer 130 may have a low oxygen concentration. When the active layer 130 comprises a high concentration of indium (In) and a low concentration of oxygen, the active layer 130 may have high mobility characteristics and excellent conductivity.

[0108] According to one embodiment of this disclosure, the active layer 130 may include at least one selected from beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr). These elements may be dispersed in an oxide semiconductor material.

[0109] According to one embodiment of this disclosure, beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr) can be referred to as crystallization control elements.

[0110] The crystallization control element is an element that has a strong binding force with oxygen and can delay the crystallization rate of the active layer 130. The active layer 130 can be formed by deposition and patterning, and the crystallization control element prevents the active layer 130 from crystallizing during the deposition process, thereby preventing or reducing the degradation of the patterning performance of the active layer 130.

[0111] On the other hand, crystallization control cannot completely prevent the crystallization of the active layer 130. As a result, if heat treatment is performed while the active layer 130 can contact the seed layer 120, the portion of the active layer 130 in contact with the seed layer 120 can crystallize.

[0112] According to one embodiment of this disclosure, the crystallization control element may have a content of 0.1 atomic% (at%) to 6 atomic% (at%) relative to the total atoms (excluding oxygen) of the active layer 130. When the content of the crystallization control element is less than 0.1 atomic% (at%) relative to the total atoms (excluding oxygen) of the active layer 130, the crystallization prevention effect may not be fully realized during the deposition process. As a result, difficulties may arise during the patterning process following the deposition of the oxide semiconductor material used to form the active layer 130.

[0113] On the other hand, if the content of the crystallization control element exceeds 6 atomic % at% relative to the total atoms other than oxygen in the active layer 130, a selected portion of the active layer 130 may not crystallize or the crystallization rate may be reduced due to the excessive amount of crystallization control element.

[0114] According to one embodiment of this disclosure, the active layer 130 and the seed layer 120 may include at least one common metal element. When the active layer 130 and the seed layer 120 include the same element, the bonding strength between the active layer 130 and the seed layer 120 can be improved.

[0115] According to one embodiment of the present disclosure, after an active layer 130 can be formed by an amorphous oxide semiconductor material, the region of the active layer 130 that is in contact with the seed layer 120 is crystallized to form a channel portion 130n.

[0116] According to one embodiment of this disclosure, the transformation of a portion having an amorphous structure into a crystalline structure is referred to as "crystallization". Furthermore, crystallizing only a specific portion of the active layer 130 is referred to as "selective crystallization".

[0117] According to one embodiment of this disclosure, the channel portion 130n may be a portion of the active layer 130 that is crystallized through the seed layer 120. Alternatively, the channel portion 130n may be a portion that is selectively crystallized through the seed layer 120.

[0118] For example, selective crystallization of the active layer 130 can occur when oxygen contained in the seed layer 120 diffuses to the active layer 130 in contact with the seed layer 120. The seed layer 120 serves as a seed for crystallization. Using the seed layer 120 as a seed, crystallization can occur from the portion of the active layer 130 in contact with the seed layer 120.

[0119] During the process of crystallizing the active layer 130 of the seed layer 120 to form the channel portion 130n, oxygen (O) migration may occur. Oxygen can migrate from the seed layer 120 to the channel portion 130n. As a result, the channel portion 130n may have a higher oxygen concentration than the first connection portion 130a and the second connection portion 130b. However, the oxygen concentration of the channel portion 130n will not become higher than the oxygen concentration of the seed layer 120.

[0120] According to one embodiment of this disclosure, the channel portion 130n may have a lower oxygen concentration than the seed layer 120. The oxygen concentration can be expressed as atomic percentage (at%).

[0121] According to one embodiment of this disclosure, in the cross-section of the channel portion 130n, the ratio of the sum of the areas of crystals with a grain size of 1 nm or larger to the total area of ​​the cross-section can be 50% or larger. Specifically, based on a transmission electron microscope (TEM) image of the cross-section of the channel portion 130n, the ratio of the sum of the areas of crystals with a grain size of 1 nm or larger to the total area of ​​the cross-section can be 50% or larger.

[0122] According to one embodiment of this disclosure, the channel portion 130n may include at least one crystal structure selected from, for example, cubic crystal structure, ferromanganese crystal structure, cubic ferromanganese crystal structure, spinel crystal structure, hexagonal crystal structure and wurtzite crystal structure.

[0123] According to one embodiment of this disclosure, the channel portion 130n may have crystal planes. The channel portion 130n may include at least one of, for example, a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (001) crystal plane. The crystal planes can be identified or measured from X-ray diffraction analysis (XRD) of the channel portion 130n of the active layer 130.

[0124] The channel portion 130n, having a crystalline structure, can exhibit excellent physical and chemical stability. As a result, damage to the channel portion 130n or deformation of its physical properties during the manufacturing and usage processes of the thin-film transistor 100 can be suppressed or prevented. Furthermore, since the channel portion 130n has a crystalline structure, it can exhibit excellent hydrogen resistance. Consequently, the channel portion 130n can exhibit excellent stability. According to one embodiment of this disclosure, due to the excellent stability of the channel portion 130n, the thin-film transistor 100 can exhibit excellent operational stability.

[0125] According to one embodiment of this disclosure, the first connecting portion 130a and the second connecting portion 130b are non-crystalline portions. The first connecting portion 130a and the second connecting portion 130b can have excellent electrical conductivity similar to that of metals.

[0126] The channel portion 130n has a lower carrier concentration than the first connection portion 130a and the second connection portion 130b. Additionally, the channel portion 130n may have a lower mobility than the first connection portion 130a and the second connection portion 130b.

[0127] Reference Figure 2 The first connecting portion 130a and the second connecting portion 130b do not contact the seed layer 120. The portion of the active layer 130 that contacts the seed layer 120 and its surrounding area can be crystallized to form a channel portion 130n, and the portion that does not contact the seed layer 120 can form the first connecting portion 130a and the second connecting portion 130b. The amorphous portion of the active layer 130 can form the first connecting portion 130a and the second connecting portion 130b.

[0128] The first connecting portion 130a and the second connecting portion 130b, which are non-crystalline and exist in an amorphous state, can have excellent electrical conductivity. According to one embodiment of this disclosure, the first connecting portion 130a and the second connecting portion 130b can each have a conductivity of 1.0 × 10⁻⁶. 19 ea / cm 3Or a higher carrier concentration. Specifically, the first connector 130a and the second connector 130b may each have a carrier concentration of 1.0 × 10⁻⁶. 21 ea / cm 3 Or a higher carrier concentration.

[0129] Furthermore, the first connecting portion 130a and the second connecting portion 130b may each have 10 3 A thin-film resistance of Ω / □ or less. Specifically, the first connecting portion 130a and the second connecting portion 130b may each have a resistance of 10 Ω / □ or less. 2 Thin-film resistance of Ω / □ or less.

[0130] The first connection portion 130a and the second connection portion 130b, which have high carrier concentration and low surface resistance, can have electrical properties similar to those of a conductor without requiring a separate conductorization process.

[0131] According to one embodiment of this disclosure, the first connection portion 130a and the second connection portion 130b can be formed without performing a conductor-enhancing process on the active layer 130. As a result, it is possible to prevent the conductor-enhanced region from diffusing into the channel portion 130n during the conductor-enhancing process. In one embodiment of this disclosure, the conductor-enhancing process may be referred to as a process of providing conductivity or improving conductivity to selected portions of the semiconductor layer or selected portions of the active layer 130.

[0132] According to one embodiment of this disclosure, the first connection portion 130a may contact the source electrode 161. The source electrode 161 is electrically connected to the first connection portion 130a of the active layer 130. The drain electrode 162 is spaced apart from the source electrode 161 and contacts the second connection portion 130b. The drain electrode 162 is electrically connected to the second connection portion 130b of the active layer 130.

[0133] According to one embodiment of this disclosure, the first connection portion 130a may be a source region, and the second connection portion 130b may be a drain region. According to one embodiment of this disclosure, the first connection portion 130a may be used as a source, and the second connection portion 130b may be used as a drain. The first connection portion 130a and the second connection portion 130b may be interchanged.

[0134] Furthermore, according to one embodiment of this disclosure, the active layer 130 may have a multilayer structure. For example, the active layer 130 may include a first oxide semiconductor layer and a second oxide semiconductor layer disposed on the first oxide semiconductor layer. Additionally, the active layer 130 may also include a third oxide semiconductor layer disposed on the second oxide semiconductor layer.

[0135] like Figure 1 and Figure 2As shown, a thin-film transistor according to one embodiment of the present disclosure may include a source 161 and a drain 162 spaced apart from each other. The source 161 may contact the seed layer 120 and the first connection portion 130a. The drain 162 may contact the seed layer 120 and the second connection portion 130b.

[0136] Reference Figure 2 and Figure 3 A gate insulating layer 140 may be disposed on the active layer 130. The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating layer 140 may have a single-layer or multi-layer structure. The gate insulating layer 140 may protect the channel portion 130n.

[0137] Reference Figure 2 The gate insulating layer 140 can be disposed on the channel portion 130n, which is disposed on the inclined surface 120s of the seed layer 120. The channel portion 130n of the active layer 130 and the gate 150 can be spaced apart from each other by the gate insulating layer 140.

[0138] Additionally, the gate insulating layer 140 may be formed over the entire upper portion of the substrate 110. For example, the gate insulating layer 140 may cover the entire channel portion 130n, the first connection portion 130a, and the second connection portion 130b, excluding the contact area.

[0139] However, one embodiment of this disclosure is not limited thereto, and the gate insulating layer 140 may be patterned. For example, the gate insulating layer 140 may be patterned into a shape corresponding to the gate 150.

[0140] The gate 150 can be disposed on the gate insulating layer 140.

[0141] The gate 150 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate 150 may also have a multilayer structure comprising at least two conductive layers with different physical properties.

[0142] The gate 150 may overlap with the channel portion 130n of the active layer 130. In addition, the seed layer 120 may overlap with the gate 150.

[0143] According to one embodiment of this disclosure, an active layer 130 is disposed between a seed layer 120 and a gate 150. Furthermore, a channel portion 130n may be disposed between the seed layer 120 and the gate 150.

[0144] The channel portion 130n of the active layer 130 can have semiconductor characteristics and can be conductive when a voltage is applied to the gate 150. For driving the thin-film transistor 100, the channel portion 130n is typically disposed in a region where an electric field generated by the gate 150 is applied. According to one embodiment of this disclosure, the channel portion 130n, as a crystalline portion of the active layer 130, can be disposed in the region defined by the gate 150.

[0145] Reference Figure 1 and Figure 3 In the region where it overlaps with the gate 150 in a planar manner, the width w1 of the seed layer 120 is greater than the width w2 of the active layer. According to one embodiment of this disclosure, the width is measured in a direction perpendicular to the line connecting the first connection portion 130a and the second connection portion 130b.

[0146] If a portion of the active layer 130 does not overlap with the seed layer 120 in the width direction, an electrical short circuit may occur. Specifically, the portion of the active layer 130 that does not overlap with the seed layer 120 will not crystallize and will have a high carrier concentration, low resistance, and high conductivity. Therefore, if the portion of the active layer 130 that does not overlap with the seed layer 120 extends along the width direction (the directions of w1, w2) from the first connection portion 130a to the second connection portion 130b to form a connection, current will flow through the connection, regardless of the on / off state of the thin-film transistor 100. As a result, a short circuit or leakage current may occur between the first connection portion 130a and the second connection portion 130b, and the thin-film transistor 100 may fail to perform its switching function.

[0147] To prevent such short circuits or leakage currents, according to one embodiment of this disclosure, the width w1 of the seed layer 120 in the region overlapping with the gate 150 in the plane is designed to be greater than the width w2 of the active layer.

[0148] Furthermore, the thin-film transistor 100 according to one embodiment of the present disclosure may have a vertical structure, which includes a channel portion 130n disposed on the inclined surface 120s of the seed layer 120. According to one embodiment of the present disclosure, since the thin-film transistor 100 can have a vertical structure, the length of the channel portion 130n can be ensured even in a narrow region. In addition, the thin-film transistor 100 occupies a small area, and the thin-film transistor 100 can be formed in a narrow region.

[0149] Figure 4 This is a plan view of a thin-film transistor 200 according to another embodiment of the present disclosure. Figure 5 It is along Figure 4 The cross-sectional view taken from line III-III'.

[0150] Reference Figure 4 andFigure 5 The seed layer 120 may have a recess 125. The recess 125 of the seed layer 120 may have an inclined surface 120s and a bottom surface 120b. The recess 125 may be defined by the inclined surface 120s and the bottom surface 120b. According to another embodiment of the present disclosure, the space surrounded by the inclined surface 120s and the bottom surface 120b may be referred to as the recess 125.

[0151] Reference Figure 5 The bottom surface 120b of the recess 125 may be a part of the seed layer 120. More specifically, according to another embodiment of this disclosure, the bottom surface 120b of the recess 125 may be a part of the surface of the seed layer 120. Additionally, the inclined surface 120s of the recess 125 may also be another part of the surface of the seed layer 120.

[0152] The active layer 130 can be disposed on the inclined surface 120s and the bottom surface 120b of the recess 125. The active layer 130 can be disposed across the inclined surface 120s and the bottom surface 120b of the recess 125.

[0153] The active layer 130 can contact the seed layer 120 on the inclined surface 120s of the recess 125. Additionally, the active layer 130 can contact the seed layer 120 on the bottom surface 120b of the recess 125. The portions of the active layer 130 that contact the inclined surface 120s and the bottom surface 120b of the recess 125 can be crystallized to form a channel portion 130n. According to another embodiment of this disclosure, the channel portion 130n can extend from the inclined surface 120s to the bottom surface 120b. Specifically, the portions of the channel portion 130n on the inclined surface 120s and the portions of the channel portion 130n on the bottom surface 120b can be connected to each other.

[0154] The gate 150 may overlap with the active layer 130. The gate 150 may be configured to face the inclined surface 120s, with the active layer 130 interposed between the gate 150 and the inclined surface 120s. Alternatively, the gate 150 may be configured to face the bottom surface 120b, with the active layer 130 interposed between the gate 150 and the bottom surface 120b.

[0155] When the seed layer 120 can have a recess 125, the channel portion 130n can have a curved shape. Therefore, the length of the channel portion 130n can be increased. Specifically, when the channel portion 130n can have a curve formed along the longitudinal direction, compared to the case where the channel portion 130n does not have a curve based on the same plane, the length of the channel portion 130n can be increased. Here, the longitudinal direction is the direction connecting the first connecting portion 130a and the second connecting portion 130b.

[0156] The thin film transistor 200 according to another embodiment of the present disclosure includes a source electrode 161 and a drain electrode 162. The source electrode 161 and the drain electrode 162 are spaced apart from each other and each contact the active layer 130. The source electrode 161 and the drain electrode 162 may be provided on the seed layer 120.

[0157] Referring to Figure 5 , the source electrode 161 and the drain electrode 162 are provided on the upper surface of the seed layer 120, and the active layer 130 may be provided on the upper surfaces of the source electrode 161 and the drain electrode 162. The portions of the active layer 130 provided on the source electrode 161 and the drain electrode 162 may not be crystallized and may have excellent conductivity. The portion of the active layer 130 provided on the source electrode 161 may become the first connection portion 130a, and the portion of the active layer 130 provided on the drain electrode 162 may become the second connection portion 130b.

[0158] The concave portion 125 of the seed layer 120 may have a predetermined width w3. The width w3 of the concave portion 125 may be greater than the width w2 of the active layer, w3 > w2. When the width w3 of the concave portion 125 is greater than the width w2 of the active layer, the channel portion 130n may have a curve in the entire width direction. As a result, the influence of the lengthening of the length of the channel portion 130n may occur in the entire width direction of the channel portion 130n.

[0159] The width w3 of the concave portion 125 may be less than the width w1 of the seed layer 120, w3 < w1, or the width w3 of the concave portion 125 may be equal to the width w1 of the seed layer 120, w3 = w1. Additionally, the width w3 of the concave portion 125 may be less than the width w2 of the active layer, w3 < w2.

[0160] Figure 6 is a plan view of a thin film transistor 300 according to another embodiment of the present disclosure, Figure 7 is a cross-sectional view taken along the Figure 6 line IV-IV' of.

[0161] Having Figure 6 and Figure 7 The thin film transistor 300 having the structure of further includes a metal layer 163 provided on the bottom surface 120b of the concave portion 125.

[0162] Specifically, the thin film transistor 300 according to another embodiment of the present disclosure includes a metal layer 163 on a substrate 110, and the seed layer 120 may be provided on the metal layer 163. The seed layer 120 may have a concave portion 125, and the metal layer 163 becomes the bottom surface of the concave portion 125.

[0163] According to another embodiment of the present disclosure, the active layer 130 may contact the metal layer 163. Referring to Figure 7The active layer 130 may include a third connecting portion 130c, which contacts a metal layer 163 disposed on the bottom surface 120b of the recess 125.

[0164] The third connection portion 130c, which contacts the bottom surface 120b of the recess 125 of the active layer 130, is non-crystalline. Therefore, the third connection portion 130c can have an amorphous structure and excellent conductivity. The third connection portion 130c can also function as a wiring portion instead of a channel portion.

[0165] The portion of the active layer 130 that contacts the inclined surface 120s of the recess 125 can crystallize and serve as a channel portion. (Refer to...) Figure 7 The inclined surface 120s of the recess 125 can be separated by the bottom surface 120b and divided into two regions. Therefore, the channel portion 130n can be divided into a first channel portion 130n1 and a second channel portion 130n2.

[0166] Figure 7 The thin-film transistor 300 may have a structure in which two channel sections 130n1 and 130n2 are connected in series. Figure 7 The thin-film transistor 300 corresponds to a structure in which two sub-thin-film transistors 1301 and 1302 are connected in series. The gates 150 of the two sub-thin-film transistors 1301 and 1302 are common.

[0167] For example, the first connection portion 130a can become the source 130a1 of the first sub-thin film transistor 1301, the first channel portion 130n1 can become the channel portion of the first sub-thin film transistor 1301, and the third connection portion 130c can become the drain 130b1 of the first sub-thin film transistor 1301.

[0168] In addition, the second connection portion 130b can become the drain 130b2 of the second sub-thin film transistor 1302, the second channel portion 130n2 can become the channel portion of the second sub-thin film transistor 1302, and the third connection portion 130c can become the source 130a2 of the second sub-thin film transistor 1302.

[0169] In addition, refer to Figure 8 The gate insulating layer 140 can be patterned. The gate insulating layer 140 can be patterned into a shape, for example, corresponding to the gate 150.

[0170] Figure 9 This is a plan view of a thin-film transistor 400 according to another embodiment of the present disclosure. Figure 8 It is along Figure 8 A cross-sectional view taken from line V-V'.

[0171] According to another embodiment of this disclosure, the recess 125 may have various shapes.

[0172] Reference Figure 8 The recess 125 may have an elliptical shape in a plan view. However, another embodiment of this disclosure is not limited to this, and the recess 125 may have a circular or polygonal shape in a plan view.

[0173] Additionally, refer to Figure 9 and Figures 10A to 101 The bottom surface 120b of the recess 125 can have a circular shape in the plan view. Since the bottom surface 120b of the recess 125 can have a circular shape, the third connecting part 130c can also have a circular shape in the plan view.

[0174] Alternatively, the metal layer 163 can be an input terminal for inputting signals to the thin-film transistor 400, or an output terminal for receiving signals from the thin-film transistor 400.

[0175] In the following, a method for manufacturing a thin-film transistor according to one embodiment of the present disclosure will be described.

[0176] Figure 10A This is a cross-sectional view showing a method for manufacturing a thin-film transistor 101 according to one embodiment of the present disclosure.

[0177] A method for manufacturing a thin-film transistor 101 according to an embodiment of the present disclosure includes the following steps: forming a seed material layer 120m on a substrate 110; forming a seed layer 120 having a tilted surface 120s by patterning the seed material layer 120m; forming an active layer 130 that contacts the tilted surface 120s of the seed layer 120; performing a heat treatment on the active layer 130 to partially crystallize the contact tilted surface 120s of the active layer 130; and forming a gate on the active layer 130.

[0178] A seed crystal material layer of 120 μm can be formed on the substrate 110.

[0179] For details, refer to Figure 10B The source electrode 161 can be formed on the substrate 110.

[0180] Furthermore, refer to Figure 10C A seed material layer of 120m and a drain material layer of 162m can be formed on the source electrode 161.

[0181] Reference Figure 10D A photoresist pattern 510 can be formed on the drain material layer 162m.

[0182] Reference Figure 10E The drain material layer 162m can be patterned by etching using a photoresist pattern 510 as a mask. As a result, the drain 162 can be formed.

[0183] Reference Figure 10F The seed material layer 120m is patterned using an additional etching process that uses a photoresist pattern 510 as a mask. As a result, the seed layer 120 can be formed. According to one embodiment of the present disclosure, the seed layer 120 having a tilted surface 120s can be formed by patterning the seed material layer 120m.

[0184] Reference Figure 10G Remove the photoresist pattern 510. The photoresist pattern 510 can be removed through an ashing process.

[0185] Reference Figure 10H An active layer 130 can be formed on the seed layer 120. At least a portion of the active layer 130 can contact the seed layer 120. The active layer 130 can contact the inclined surface 120s of the seed layer 120.

[0186] The active layer 130 may have an amorphous structure. For example, the active layer 130 may be made of an amorphous oxide semiconductor material. The active layer 130 may have a high carrier concentration and may have a conductivity similar to that of a metal or conductor.

[0187] Next, the active layer 130 is heat-treated. When the active layer 130 is heat-treated, the portion of the active layer 130 that contacts the inclined surface 120s of the seed layer 120 can crystallize.

[0188] According to one embodiment of the present disclosure, the active layer 130 may have an amorphous structure before heat treatment, and the portion of the active layer 130 in contact with the seed crystal layer 120 crystallizes through heat treatment.

[0189] The heat treatment temperature can range from 300℃ to 500℃. The heat treatment temperature can vary depending on the thickness of the seed layer 120. The heat treatment temperature can be referred to as the heat treatment temperature.

[0190] Reference Figure 101 As a result of heat treatment, an active layer 130 comprising crystalline and amorphous portions can be formed.

[0191] The crystalline portion of the active layer 130 becomes the channel portion 130n. The amorphous portion of the active layer 130 becomes the first connecting portion 130a and the second connecting portion 130b.

[0192] Reference Figure 11 A gate insulating layer 140 may be formed on the active layer 130, and a gate 150 may be formed on the gate insulating layer 140. The gate 150 may at least partially overlap with the active layer 130. Specifically, the gate 150 may be formed to overlap with the channel portion 130n.

[0193] According to one embodiment of the present disclosure, at least a portion of the gate 150 may be configured to face the inclined surface 120s, and the active layer 130 is interposed between the gate 150 and the inclined surface 120s.

[0194] As a result, a thin-film transistor 101 according to one embodiment of the present disclosure can be manufactured as described above.

[0195] The following will describe in detail a display device that includes at least one of the thin-film transistors described above.

[0196] Figure 12 This is a schematic diagram of a display device 500 according to another embodiment of the present disclosure.

[0197] A display device 500 according to another embodiment of the present disclosure may include a display panel 310, a strobe driver 320, a data driver 330, and a control unit 340.

[0198] The gate line GL and the data line DL are set on the display panel 310, and the pixel P is set in the intersection area of ​​the gate line GL and the data line DL. The image is displayed by driving the pixel P.

[0199] The control unit 340 controls the strobe driver 320 and the data driver 330.

[0200] The control unit 340 uses signals provided from an external system to output a gating control signal GCS for controlling the gating driver 320 and a data control signal DCS for controlling the data driver 330. Furthermore, the control unit 340 samples the input image data from the external system, rearranges it, and provides the rearranged image data (RGB) to the data driver 330.

[0201] The gating control signal GCS may include the gating start pulse GSP, the gating shift clock GSC, the gating output enable signal GOE, the start signal Vst, and the gating clock GCLK. Additionally, the gating control signal GCS may include control signals used to control the shift register.

[0202] Data control signals (DCS) may include source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), polarity control signal (POL), etc.

[0203] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 can convert image data RGB input from the control unit 340 into analog data voltage and provide the data voltage to the data line DL.

[0204] The gating driver 320 sequentially provides gating pulses GP to the gating line GL during one frame. Here, one frame refers to the period during which an image is output through the display panel. Additionally, during the remaining period of one frame during which no gating pulses GP are provided, the gating driver 320 provides a gate cutoff signal Goff to the gating line GL, which enables the switching elements to be turned off. In the following text, the gating pulses GP and the gate cutoff signal Goff are collectively referred to as the scan signal SS.

[0205] According to one embodiment of this disclosure, the gate driver 320 may be mounted on the substrate 110. In this way, the structure in which the gate driver 320 is directly mounted on the substrate 110 is referred to as a gate-in-panel (GIP) structure.

[0206] Figure 11 yes Figure 13 A circuit diagram for a pixel P. Figure 12 yes Figure 14 A planar image of pixel P. Figure 13 It is along Figure 12 The cross-sectional view taken from line VI-VI'.

[0207] Figure 13 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 500, which includes an organic light-emitting diode (OLED) as a display element 710.

[0208] Pixel P includes display element 710 and pixel driver PDC that drives display element 710.

[0209] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided through the gate line GL.

[0210] The data line DL provides the data voltage Vdata to the pixel driver PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0211] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0212] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata provided through the data line DL is supplied to the gate of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata charges a first capacitor C1 formed between the gate and source of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0213] The amount of current supplied to the organic light-emitting diode (OLED) 710 via the second thin-film transistor TR2 is controlled according to the data voltage Vdata, thus the grayscale of the light output from the display element 710 can be controlled.

[0214] Reference Figure 14 and Figure 13 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0215] The substrate 110 can be made of glass or plastic. As the substrate 110, a plastic with flexible properties, such as polyimide (PI), can be used.

[0216] Data line DL and drive power line PL are disposed on substrate 110. In addition, the source S1 of the first thin-film transistor TR1 and the drain D2 of the second thin-film transistor TR2 are disposed on substrate 110.

[0217] The source S1 of the first thin-film transistor TR1 can be integrally formed with the data line DL. The drain D2 of the second thin-film transistor TR2 can be integrally formed with the drive power line PL.

[0218] Seed layer 121 can be disposed on the source S1 of the first thin-film transistor TR1. In addition, seed layer 122 can be disposed on the drain D2 of the second thin-film transistor TR2.

[0219] The drain D1 of the first thin-film transistor TR1 can be disposed on the seed layer 121. In addition, the source S2 of the second thin-film transistor TR2 can be disposed on the seed layer 122.

[0220] The source S1, S2 and the drain D1, D2 are distinguished only for ease of explanation, and the source S1, S2 and the drain D1, D2 can be interchanged.

[0221] Reference Figure 14 and Figure 14 The source S2 of the second thin-film transistor TR2 can extend onto the substrate 110, so that a portion of it can become the first capacitor electrode CE1.

[0222] The active layers A1 and A2 can be set on the seed crystal layers 121 and 122.

[0223] Reference Figure 13 The active layer A1 can be disposed on the source S1, drain D1 and seed layer 121 of the first thin film transistor TR1. The active layer A1 can contact the inclined surface of the seed layer 121.

[0224] Additionally, the active layer A2 can be disposed on the source S2, drain D2, and seed layer 122 of the second thin-film transistor TR2. The active layer A2 can contact the inclined surface of the seed layer 122.

[0225] Active layers A1 and A2 may include, for example, an oxide semiconductor material. Active layers A1 and A2 may be formed from an oxide semiconductor layer made of an oxide semiconductor material. Active layers A1 and A2 may include crystalline and amorphous portions. The channel portions of active layers A1 and A2 may have a crystalline structure. The portions of active layers A1 and A2 that are in contact with the seed layer 120 may be crystalline and have a crystalline structure.

[0226] A gate insulating layer 140 may be disposed on the active layers A1 and A2. The gate insulating layer 140 may have insulating properties and separate the active layers A1 and A2 from the gates G1 and G2. The gate insulating layer 140 may cover the entire surface of the active layers A1 and A2.

[0227] The gate G1 of the first thin-film transistor TR1 and the gate G2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0228] The gate G1 of the first thin-film transistor TR1 overlaps at least partially with the active layer A1 of the first thin-film transistor TR1. The gate G2 of the second thin-film transistor TR2 overlaps at least partially with the active layer A2 of the second thin-film transistor TR2.

[0229] Reference Figure 14 and Figure 14 The second capacitor electrode CE2 can be disposed on the same layer as the gates G1 and G2. The second capacitor electrode CE2 can be connected to the drain D1 of the first thin-film transistor TR1 through the contact hole H1. In addition, a portion of the second capacitor electrode CE2 can extend to the upper part of the active layer A1 of the second thin-film transistor TR2 to become the gate G2 of the second thin-film transistor TR2.

[0230] Optionally, the gate G2 of the second thin-film transistor TR2 may extend over the gate insulating layer 140 and serve as the second capacitor electrode CE2.

[0231] The second capacitor electrode CE2 overlaps with the first capacitor electrode CE1. The first capacitor electrode CE1 and the second capacitor electrode CE2 overlap to form the first capacitor C1.

[0232] The planarization layer 180 can be disposed on the gate electrodes G1 and G2 and the second capacitor electrode CE2. An interlayer insulating film can be further disposed below the planarization layer 180.

[0233] The planarization layer 180 planarizes the upper part of the first thin film transistor TR1 and the second thin film transistor TR2, and protects the first thin film transistor TR1 and the second thin film transistor TR2.

[0234] The first electrode 711 of the display element 710 can be disposed on the planarization layer 180. The first electrode 711 of the display element 710 can be connected to the source S2 of the second thin film transistor TR2 through the contact hole H2 formed in the planarization layer 180.

[0235] The embankment 750 may be disposed at the edge of the first electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0236] An organic light-emitting layer 712 can be disposed on the first electrode 711, and a second electrode 713 can be disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. ​ The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 500 according to the embodiments of this disclosure is an organic light-emitting display device.

[0237] According to another embodiment of this disclosure, the pixel driver PDC can be formed in various structures other than those described above. The pixel driver PDC may include, for example, three or more thin-film transistors and two or more capacitors.

[0238] The present disclosure is not limited to the above embodiments and drawings, and it will be apparent to those skilled in the art that various substitutions, modifications and alterations are possible without departing from the technical details of the present disclosure.

[0239] A thin-film transistor according to one embodiment of the present disclosure can have a vertical structure, which includes a channel portion disposed on an inclined surface of a seed layer. Because the channel portion can have a vertical structure, the length of the channel portion can be ensured even in narrow regions. Therefore, the thin-film transistor according to one embodiment of the present disclosure occupies a small area. Furthermore, when using the thin-film transistor according to one embodiment of the present disclosure, component integration is possible.

[0240] A thin-film transistor according to one embodiment of the present disclosure includes a seed layer and an active layer in contact with the seed layer, and the portion of the active layer in contact with the seed layer may have a crystal structure. The portion of the active layer with a crystal structure may be a channel portion. According to one embodiment of the present disclosure, the channel portion of the thin-film transistor may have a crystal structure, thus exhibiting excellent hydrogen resistance and excellent electrical stability. Therefore, the thin-film transistor according to one embodiment of the present disclosure can exhibit excellent electrical stability.

[0241] According to one embodiment of this disclosure, thin-film transistors can be manufactured without a conductor-forming process.

[0242] In addition to the effects described above, other features and advantages of this disclosure are described below, or may be clearly understood by those skilled in the art from such description and explanation.

[0243] Cross-references to related applications

[0244] This application claims priority to Korean Patent Application No. 10-2024-0115768, filed on August 28, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A thin film transistor comprising: a seed layer having an inclined surface; an active layer in contact with the seed layer and including a channel portion; and a gate overlapping at least a portion of the active layer, wherein the channel portion has a crystal structure, wherein the channel portion is provided on and in contact with the inclined surface, and wherein at least a portion of the gate is provided to face the inclined surface, with the active layer interposed between the at least a portion of the gate and the inclined surface.

2. The thin film transistor according to claim 1, the active layer further including: wherein, a first connecting portion connected to one side of the channel portion; and a second connecting portion connected to another side of the channel portion opposite to the one side, wherein each of the first connecting portion and the second connecting portion has an amorphous structure, and wherein the seed layer has an amorphous structure.

3. The thin film transistor according to claim 2, the first connecting portion and the second connecting portion do not contact the seed layer. wherein, 4. The thin film transistor according to claim 2, in a plan view, a width of the seed layer is greater than a width of the active layer in a portion where the gate is provided, and wherein wherein the width of the seed layer and the width of the active layer are measured in a direction perpendicular to a line connecting the first connecting portion and the second connecting portion.

5. The thin film transistor according to claim 1, the seed layer is an amorphous layer in which, in a cross section of the seed layer, a ratio of a sum of areas of crystals having a grain size of 1 nm or more to an entire cross-sectional area of the seed layer is 10% or less. wherein, 6. The thin film transistor according to claim 1, 7. The thin film transistor according to claim 1, wherein The seed layer has a lower carrier concentration than the channel portion, and has a carrier concentration of 1.0 x 1014 / cm2or less. 16 ea / cm 3 or less. the seed layer includes at least one oxide semiconductor material selected from the group consisting of an InZnO-based oxide semiconductor material, an InGaZnO-based oxide semiconductor material, an InGaZnSnO-based oxide semiconductor material, a GaZnSnO-based oxide semiconductor material, a GaZnO-based oxide semiconductor material, and a GaO-based oxide semiconductor material. wherein, 8. The thin film transistor according to claim 1, the active layer includes at least one oxide semiconductor material selected from the group consisting of an InGaZnO-based oxide semiconductor material, an InGaO-based oxide semiconductor material, an InGaZnSnO-based oxide semiconductor material, a GaZnSnO-based oxide semiconductor material, a GaZnO-based oxide semiconductor material, a GaO-based oxide semiconductor material, a SnO-based oxide semiconductor material, an InSnO-based oxide semiconductor material, an InSnZnO-based oxide semiconductor material, an InZnO-based oxide semiconductor material, a ZnO-based oxide semiconductor material, an InO-based oxide semiconductor material, and a FeInZnO-based oxide semiconductor material. wherein 9. The thin film transistor according to claim 8, ​ wherein The active layer further includes at least one element selected from beryllium, boron, carbon, aluminum, silicon, iron, calcium, tin, titanium, tantalum, vanadium, yttrium, and zirconium.

10. The thin film transistor according to claim 1, wherein, The seed layer and the active layer include at least one common metal element.

11. The thin film transistor according to claim 1, wherein In a cross section of the channel portion, a ratio of a sum of areas of crystals having a grain size of 1 nm or more to a whole cross-sectional area of the channel portion is 50% or more.

12. The thin film transistor according to claim 1, wherein The channel portion includes at least one crystal plane selected from a 400 crystal plane, a 222 crystal plane, a 220 crystal plane, a 311 crystal plane, and a 001 crystal plane.

13. The thin film transistor according to claim 2, further comprising: a source and a drain spaced apart from each other, wherein the source contacts the seed layer and the first connection portion, and wherein the drain contacts the seed layer and the second connection portion.

14. The thin film transistor according to claim 1, wherein The seed layer has a recess, wherein the recess is defined by the inclined surface and a bottom surface, and wherein the active layer is provided on the inclined surface and on the bottom surface of the recess.

15. The thin film transistor according to claim 14, wherein The bottom surface is a portion of the seed layer, and wherein the channel portion extends from the inclined surface onto the bottom surface.

16. The thin film transistor according to claim 14, further comprising: a metal layer on the bottom surface of the recess, wherein the active layer further includes a third connection portion in contact with the metal layer, wherein the third connection portion has an amorphous structure.

17. A display device including the thin film transistor according to any one of claims 1 to 16.

18. A manufacturing method of a thin film transistor, the manufacturing method comprising the steps of: forming a seed material layer on a substrate; forming a seed layer having an inclined surface by patterning the seed material layer; forming an active layer in contact with the inclined surface of the seed layer; heat-treating the active layer to crystallize a portion of the active layer in contact with the inclined surface; and forming a gate on the active layer, wherein at least a portion of the gate is provided to face the inclined surface, the active layer being interposed between the at least a portion of the gate and the inclined surface.

19. The manufacturing method according to claim 18, wherein, Before the heat-treating, the active layer has an amorphous structure.

20. The manufacturing method according to claim 18, wherein A temperature of the heat-treating is in a range of 300°C to 500°C.

Images