Display device

Abstract

A display device includes: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; first and second thin film transistors disposed on the substrate and spaced apart from each other; a plurality of organic insulating layers disposed on the first and second thin film transistors, the plurality of organic insulating layers having at least one recess; a first electrode disposed on the peripheral portion around the recess and on the recess; a first bank disposed on the first electrode; a second bank disposed on the first bank, the second bank including a first portion disposed on the first electrode in a region corresponding to the recess and a second portion disposed on the first electrode and the organic insulating layer in a region corresponding to the peripheral portion; an organic layer overlapping the recess and disposed on the first electrode; a second electrode disposed on the organic layer and the second bank; a plurality of encapsulation layers disposed on the second electrode; a touch layer disposed on the plurality of encapsulation layers; and a color filter layer disposed on the touch layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0122006, filed on September 9, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This specification relates to a display device. Background Technology

[0004] With the advancement of the information society, the demand for display devices capable of displaying images is constantly increasing, and various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs), are being utilized. In particular, OLED displays, which do not require a separate light source, are experiencing growing demand due to their advantages of being lightweight and thin.

[0005] However, organic light-emitting display panels include an organic layer that emits light, and a portion of the light emitted from the organic layer is trapped inside the device instead of escaping to the outside, resulting in reduced light extraction efficiency and reduced light emission efficiency. Summary of the Invention

[0006] One object of the embodiments of this specification is to provide a display device with improved light extraction efficiency.

[0007] Another object of embodiments of this specification is to provide a display device capable of improving the spreadability of a third encapsulation layer (or organic encapsulation layer) by applying protruding or angular structures to a second dike.

[0008] Another object of the embodiments of this specification is to provide a display device having a structure capable of preventing color mixing between adjacent sub-pixels.

[0009] Another object of embodiments of this specification is to provide a display device capable of increasing the resistance of a thinned light-emitting layer by reducing leakage current between adjacent sub-pixels through forming trenches in an organic insulating layer and a second dike.

[0010] The purpose of this specification is not limited to the foregoing, and other purposes not described herein will be clearly understood by those skilled in the art from the following description.

[0011] To achieve the above object, a display device according to an embodiment can include a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a first thin film transistor and a second thin film transistor disposed on the substrate and spaced apart from each other; a plurality of organic insulating layers disposed on the first thin film transistor and the second thin film transistor, the plurality of organic insulating layers having at least one recess; a first electrode disposed on a peripheral portion located around the recess and on the recess; a first bank disposed on the first electrode; a second bank disposed on the first bank, the second bank including a first portion disposed on the first electrode in a region corresponding to the recess and a second portion disposed on the first electrode and the organic insulating layer in a region corresponding to the peripheral portion; an organic layer overlapping the recess and disposed on the first electrode; a second electrode disposed on the organic layer and the second bank; a plurality of encapsulating layers disposed on the second electrode; a touch layer disposed on the plurality of encapsulating layers; and a color filter layer disposed on the touch layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a plan view of a display device according to an embodiment;

[0013] Figure 2 is a cross-sectional view of a display panel of Figure 1 in a bent state;

[0014] Figure 3 is a plan view illustrating an arrangement of sub-pixels in a display area of Figure 1 ;

[0015] Figure 4 is a cross-sectional view taken along line A-A' of Figure 3 ;

[0016] Figure 5 is an enlarged cross-sectional view of a region X in Figure 4 ;

[0017] Figure 6 is a cross-sectional view of a touch layer according to Figure 4 ;

[0018] Figure 7 is a cross-sectional view taken along line B-B' of Figure 1 ;

[0019] Figure 8 is a cross-sectional view taken along line C-C' of Figure 1 ; and

[0020] Figure 9 is a plan view illustrating an arrangement of sub-pixels in a display area of Figure 1 according to an alternative embodiment. DETAILED DESCRIPTION

[0021] The advantages and features disclosed in the specification and the means for achieving the results can be more readily understood by reference to the following examples described in detail below with reference to the accompanying drawings. The present specification is not limited to the embodiments described herein but can be embodied in various forms, and the embodiments are provided to ensure complete disclosure of the present specification and to fully convey the scope of the present specification to those skilled in the related art.

[0022] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the embodiments of the present application are exemplary, and thus the present application is not limited to the drawings. Throughout the specification, like reference numerals denote like parts. Also, detailed descriptions of known technology can be omitted in the present specification to avoid obscuring the subject matter of the present specification. When terms such as "include", "have", "comprise", or "consist of" are used in the present specification, it is understood that, unless particularly stated otherwise, additional elements or steps can be included. Unless explicitly stated otherwise, when a part is expressed in singular form, it is intended to encompass plural forms as well.

[0023] In explaining a part, it is explained to include an error range even if not explicitly described.

[0024] In describing a positional relationship, for example, when a positional relationship between two parts is described using terms such as "upper", "above", "below", or "next to", one or more other parts can be positioned between the two parts unless "directly" or "immediately" is specified.

[0025] When one device or layer is referred to as "on" another device or layer, it includes the case where the one device or layer is positioned directly on the other device or layer or the case where another device or layer is interposed therebetween.

[0026] Although the terms "first", "second", and the like are used to describe various components, the components are not limited by these terms. The terms are used only to distinguish one component from another component. Although the terms "first", "second", and the like are used to describe various components, the components are not limited by these terms.

[0027] Throughout the specification, the same reference numerals denote the same parts.

[0028] The areas and thicknesses of the respective components shown in the drawings are shown for convenience of description, and the present specification is not necessarily limited to the areas and thicknesses of the illustrated components.

[0029] The respective features of the embodiments of the present disclosure can be technically partially or wholly combined or assembled together in various ways, and each embodiment can be independently implemented or implemented in conjunction with related embodiments.

[0030] Hereinafter, embodiments of the present specification will be described with reference to the accompanying drawings.

[0031] Figure 1 is a plan view of a display device according to an embodiment.

[0032] Referring to Figure 1 , the display device 1 according to an embodiment can include a display panel 100. The display panel 100 can include a display area DA including a plurality of pixels PX and a non-display area NDA surrounding the display area DA. The display area DA can have a rectangular planar shape. However, the display area DA is not limited thereto, and can have a square, circular, elliptical, or other polygonal planar shape. For example, the display area DA can have a rectangular shape including rounded corners, but is not limited thereto, and can also have a rectangular shape including angular corners.

[0033] In an embodiment, the first direction DR1 and the second direction DR2 are different directions intersecting each other, for example, directions perpendicularly intersecting in a plan view. In Figure 1 , the first direction DR1 generally corresponds to an extension direction of a short side of the display panel 100, and the second direction DR2 can correspond to an extension direction of a long side of the display panel 100. However, the directions mentioned in the embodiments are understood as relative directions, and the embodiments are not limited to the mentioned directions.

[0034] The display area DA can include a short side extending along the first direction DR1 and a long side extending along the second direction DR2. The non-display area NDA can surround the display area DA. The non-display area NDA can be disposed on one side and the other side of the display area DA in the first direction DR1, and on one side and the other side of the display area DA in the second direction DR2.

[0035] The display panel 100 can further include a sensor non-display area NDA_S and a sensor hole surrounded by the sensor non-display area NDA_S. In a plan view, the display area DA can surround the sensor holes SH1 and SH2. For example, as Figure 1 shown, the number of the sensor holes SH1 and SH2 can be two, but the embodiments of the present specification are not limited thereto. For example, a single sensor hole can be provided. The two sensor holes SH1 and SH2 can be respectively disposed as an arrangement for an infrared sensor and a camera sensor; however, the embodiments of the present specification are not limited to this configuration. The sensor non-display area NDA_S can be disposed between the sensor holes SH1 and SH2 and the display area DA. The sensor non-display area NDA_S can completely surround the sensor holes SH1 and SH2. No pixels PX can be arranged in the sensor non-display area NDA S.

[0036] The gate driving unit (GIP) can be arranged in the non-display area NDA on each of the two sides of the first direction DR1 of the display area DA. A low-potential voltage line VSSL can be located outside the gate driving unit GIP in the non-display area NDA. For example, as... Figure 1 As shown, the low-potential voltage line VSSL can extend from the flexible printed circuit board FPCB, pass through the sub-region SR and the curved region BR, and is located outside the gate drive unit GIP in the non-display region NDA, while surrounding the display region DA.

[0037] The non-display area NDA located on the opposite side of the display area DA in the second direction DR2 can extend further along the second direction DR2 from the center portion of that side of the display area DA. The width of the non-display area NDA extending further along the second direction DR2 from the center portion of the opposite side of the display area DA in the second direction DR2 in the first direction DR1 can be smaller than the width of the non-display area NDA adjacent to the opposite side of the display area DA in the second direction DR2 in the first direction DR1.

[0038] Display device 1 may include a main region MR, a sub-region SR, and a curved region BR between the main region MR and the sub-region SR. A display region DA and a non-display region NDA surrounding the display region DA on all four sides may form the main region MR, while a portion extending further along a second direction DR2 from the center of the other side of the display region DA may constitute the curved region BR and the sub-region SR. The curved region BR may be located between the sub-region SR and the main region MR. The sub-region SR may include a first pad region PA1 and a second pad region PA2 located at opposite ends of the sub-region SR along the second direction DR2. Display device 1 may also include a data driver DIC and a printed circuit board FPCB. The data driver DIC may be located in the first pad region PA1, and the flexible printed circuit board FPCB may be attached to the second pad region PA2. The first pad region PA1 and the second pad region PA2 may each include multiple pads connecting the data driver DIC and the flexible printed circuit board FPCB. The data driver DIC may be provided, for example, in the form of a driver chip IC, but is not limited thereto. In one embodiment, the data driving unit DIC is arranged as a chip-on-plastic and directly mounted on the display panel 100, but it is not limited to this and can also be arranged as a chip-on-glass or chip-on-film.

[0039] The display panel 100 according to an embodiment may further include a crack detection pattern CSP surrounding a low-potential voltage line VSSL. The crack detection pattern CSP may be arranged to completely surround the display area DA, such as... Figure 1As shown. For example, the crack detection pattern CSP can be located outside the low-potential voltage line VSSL. However, embodiments of this specification are not limited to this, and the crack detection pattern CSP may not be partially located in the non-display area NDA on the opposite side of the display area DA in the second direction DR2.

[0040] Figure 2 It is shown Figure 1 A cross-sectional view of the curved state of the display panel.

[0041] Reference Figure 2 According to the embodiment, the curved region BR of the display panel 100 of the display device 1 can be bent in the thickness direction (or the third direction DR3). Thus, the main region MR and the sub-region SR can overlap in the thickness direction. The display panel 100 can be bent such that the bottom surface of the main region MR and the top surface of the sub-region SR face each other. A flexible printed circuit board (FPCB) can be attached to the end of the sub-region SR.

[0042] Figure 3 It is shown Figure 1 A planar diagram showing the arrangement of subpixels in the display area. Figure 4 It is along Figure 3 A sectional view taken by line A-A'. Figure 4 It can be a diagram showing only a portion of the components and a portion of the area set in a sub-pixel SP, or it can be a diagram showing only a portion of the components and a portion of the area set in the pad area.

[0043] Reference Figure 3 It is a plan view showing the multiple light-emitting areas EA and multiple non-light-emitting areas NEA included in the display area DA of the display panel 100.

[0044] like Figure 3 As shown, the areas of the light-emitting regions EA of at least two sub-pixels SP can be different, but this disclosure is not limited to such differences.

[0045] Each sub-pixel SP within the display area DA may include multiple light-emitting areas EA1 and EA2. Specifically, a sub-pixel SP may include a first light-emitting area EA1 and a second light-emitting area EA2 surrounding the first light-emitting area EA1. A first non-light-emitting area NEA1 may be disposed between the first light-emitting area EA1 and the second light-emitting area EA2. That is, the first light-emitting area EA1 and the second light-emitting area EA2 may be separated by the first non-light-emitting area NEA1.

[0046] like Figure 3As shown, the first luminous region EA1, the second luminous region EA2, and the first non-luminous region NEA1 may have a protruding shape including multiple protrusions in the plan view. However, this specification is not limited to this, and the first luminous region EA1, the second luminous region EA2, and the first non-luminous region NEA1 may have a polygonal shape in the plan view, such as a triangle, a quadrilateral, or a hexagon, or a combination of these shapes.

[0047] A pair of first light-emitting regions EA1 and second light-emitting regions EA2 can be spaced apart from another pair of first light-emitting regions EA1 and second light-emitting regions EA2, and a second non-light-emitting region NEA2 can be disposed between the pair of first light-emitting regions EA1 and second light-emitting regions EA2.

[0048] The second non-light-emitting area NEA2 may correspond to a portion or all of the circuit area (where circuitry is provided for driving the first light-emitting area EA1 and the second light-emitting area EA2).

[0049] Reference Figure 4 The display panel has 100 pixels per square meter (PX). Figure 1 A pixel may include multiple sub-pixels. Each sub-pixel may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, or a white sub-pixel, but the embodiments described herein are not limited thereto.

[0050] The display panel 100 may include a substrate 101, a first thin-film transistor 200, a second thin-film transistor 300, an organic light-emitting diode (OLED), an encapsulation layer 400, a touch layer 500, a black matrix 147, a color filter CF, and a planarization layer 149.

[0051] The display panel 100 may include at least one panel insulating layer located between the substrate 101 and the organic light-emitting diode (OLED). The at least one panel insulating layer may include at least one of the following: multiple buffer layer 103, first insulating layer 107, second insulating layer 109, third insulating layer 111, fourth insulating layer 113, fifth insulating layer 115, sixth insulating layer 117, seventh insulating layer 119, first organic insulating layer 121, second organic insulating layer 123, and third organic insulating layer 125. At least one touch layer may be disposed on the OLED. The at least one touch insulating layer may include at least one of the following: touch buffer layer 501, first touch insulating layer 503, and second touch insulating layer 505.

[0052] The substrate 101 may comprise one or more plastic materials. For example, the substrate 101 may be a multi-substrate comprising multiple plastic materials (e.g., polyimide). For example, the substrate 101 may include a first substrate portion 101a and a second substrate portion 101b, each comprising a plastic material, and a third substrate portion 101c comprising an inorganic insulating material between the first substrate portion 101a and the second substrate portion 101b, but the embodiments described herein are not limited thereto.

[0053] Multiple buffer layers 103 can be disposed on the substrate 101. The multiple buffer layers 103 can minimize or delay the diffusion of moisture or oxygen that permeates the substrate 101. This can be achieved by alternately stacking silicon nitride (SiN) layers. x ) and silicon dioxide (SiO) x The buffer layer 101 may be formed at least once, but the embodiments described herein are not limited thereto.

[0054] The first light-shielding layer 105 may be disposed on the multi-buffer layer 103. The first light-shielding layer 105 can prevent light from passing through the first semiconductor layer 203 of the first thin-film transistor 200. For example, the first semiconductor layer 203 may be configured to overlap with the first light-shielding layer 105. The first light-shielding layer 105 may be a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), copper (Cu), or alloys of any of the aforementioned substances, but the embodiments in this specification are not limited thereto.

[0055] A first insulating layer 107 may be disposed on the multi-buffer layer 103 and the first light-shielding layer 105. The first insulating layer 107 prevents short circuits between the configuration of the first thin-film transistor 200 and the first light-shielding layer 105. The first insulating layer 107 may be made of the same material as the multi-buffer layer 103, but the embodiments described herein are not limited thereto. For example, the first insulating layer 107 may be made of materials such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x It is made of inorganic insulating material, but the embodiments in this specification are not limited thereto.

[0056] The first thin-film transistor 200 may be disposed on the first insulating layer 107. The first thin-film transistor 200 may include a first source 201, a first semiconductor layer 203, a first drain 205, and a first gate 207.

[0057] The first semiconductor layer 203 may be disposed on the first insulating layer 107. The first semiconductor layer 203 may comprise a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon, but the embodiments described herein are not limited thereto. The first semiconductor layer 203 may be formed of a metal oxide semiconductor such as indium gallium zinc oxide. The first semiconductor layer 203 may include a channel region, a source region, and a drain region.

[0058] Polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, thus enabling them to have lower power consumption and improved reliability. Therefore, polycrystalline semiconductor layers can be used to form a first thin-film transistor 200 used as a switching transistor.

[0059] The second insulating layer 109 may be disposed on the first semiconductor layer 203. The second insulating layer 109 may be made of the same material as the first insulating layer 107 and may prevent short circuits between the first semiconductor layer 203 and other components of the first thin-film transistor 200.

[0060] The first gate 207 may be disposed on the second insulating layer 109. The first gate 207 may be arranged to overlap with the channel region of the first semiconductor layer 203 on the second insulating layer 109. The first gate 207 may be constituted by a single-layer or multi-layer structure of a material comprising molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but the embodiments of this specification are not limited to these materials. The first gate 207 may be arranged together with the gate line.

[0061] The third insulating layer 111 may be disposed on the first gate 207. The third insulating layer 111 may be formed by alternately stacking silicon nitride and silicon oxide at least once, but the embodiments in this specification are not limited thereto.

[0062] The first source 201 and the first drain 205 can be disposed on the third insulating layer 111.

[0063] The first source 201 and the first drain 205 can be electrically connected to the first semiconductor layer 203 through contact holes. The first source 201 and the first drain 205 can be made of a metallic material. For example, the first source 201 and the first drain 205 can be composed of a single layer or multiple layers made of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, but the embodiments in this specification are not limited thereto.

[0064] The first source 201 and the first drain 205 can be arranged together with the data line. For example, the data line can be formed on the same layer as the first source 201 and the first drain 205 and made of the same material, but the embodiments in this specification are not limited thereto.

[0065] The storage electrode 220 may be disposed separately from the first thin-film transistor 200. The storage electrode 220 may include a first storage electrode 221 and a second storage electrode 223.

[0066] The first storage electrode 221 may be disposed on the same layer as the first gate 207 and made of the same material, but the embodiments in this specification are not limited thereto.

[0067] The second storage electrode 223 may be disposed on the first storage electrode 221. The second storage electrode 223 may be disposed on the third insulating layer 111, and a capacitor may be formed by using the third insulating layer 111 as the dielectric between the first storage electrode 221 and the second storage electrode 223. The second storage electrode 223 may be made of the same material as the first storage electrode 221, but the embodiments in this specification are not limited thereto.

[0068] The second thin-film transistor 300 may be disposed spaced apart from the first thin-film transistor 200 and the storage electrode 220. The second thin-film transistor 300 may include a second source 301, a second semiconductor layer 303, a second drain 305, and a second gate 307.

[0069] The second source 301 can be formed of the same material as the first source 201. The second drain 305 can be formed of the same material as the first drain 205.

[0070] The fourth insulating layer 113 can be disposed on the storage electrode 220. The second light-shielding layer 114 can be disposed on the fourth insulating layer 113.

[0071] Similar to the first light-shielding layer 105, the second light-shielding layer 114 can prevent light from reaching the second semiconductor layer 303, thereby extending the lifespan of the second thin-film transistor 300. For example, the second semiconductor layer 303 can be configured to overlap with the second light-shielding layer 114.

[0072] The fifth insulating layer 115 may be disposed on the second light-shielding layer 114. The fifth insulating layer 115 may be formed of the same material as the first insulating layer 107, the second insulating layer 109, the third insulating layer 111 and the fourth insulating layer 113, but the embodiments in this specification are not limited thereto.

[0073] The second semiconductor layer 303 may be disposed on the fifth insulating layer 115. The second semiconductor layer 303 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0074] The second semiconductor layer 303 may contain semiconductor materials, such as metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)) or silicon-based semiconductor materials (e.g., amorphous silicon or polycrystalline silicon), but the embodiments described herein are not limited thereto.

[0075] The fifth insulating layer 117 may be disposed on the second semiconductor layer 303. The sixth insulating layer 117 may be made of the same material as the first insulating layer 107, the second insulating layer 109, the third insulating layer 111, the fourth insulating layer 113 or the fifth insulating layer 115, but the embodiments in this specification are not limited thereto.

[0076] The second gate 307 may be disposed on the sixth insulating layer 117. The second gate 307 may be made of the same material as the first gate 207. For example, the second gate 307 may be formed as a single layer or multiple layers of materials such as molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) or alloys thereof, but the embodiments in this specification are not limited thereto.

[0077] The seventh insulating layer 119 may be disposed on the second gate 307. The seventh insulating layer 119 may be formed of the same material as the first insulating layer 107, the second insulating layer 109, the third insulating layer 111, the fourth insulating layer 113, the fifth insulating layer 115 or the sixth insulating layer 117; however, the embodiments in this specification are not limited thereto.

[0078] The first source 201, the first drain 205, the second source 301, and the second drain 305 can be disposed on the seventh insulating layer 119.

[0079] The second source 301 and the second drain 305 may be made of the same material as the first source 201 and the first drain 205, and may be disposed in the same layer, but the embodiments described herein are not limited thereto. For example, the second source 301 and the second drain 305 may be formed as a single layer or multiple layers of materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys of these materials, but the embodiments described herein are not limited thereto. For example, the second source 301 may be electrically connected to the second storage electrode 223. The second source 301 may be electrically connected to the second storage electrode 223 through the seventh insulating layer 119, the sixth insulating layer 117, the fifth insulating layer 115, and the fourth insulating layer 113.

[0080] The first thin-film transistor 200 may be a switching transistor, and the second thin-film transistor 300 may be a driving transistor; however, the embodiments described herein are not limited thereto.

[0081] A first organic insulating layer 121 may be disposed on the second transistor 300. The first organic insulating layer 121 may planarize and protect the upper portions of the first transistor 200 and the second transistor 300. The first organic insulating layer 121 may be formed of an organic material. For example, the first organic insulating layer 121 may be formed of an organic material comprising acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but the embodiments described herein are not limited thereto.

[0082] The second organic insulating layer 123 may be disposed on the first organic insulating layer 121. The second organic insulating layer 123 may be formed of the same material as the first organic insulating layer 121, but the embodiments in this specification are not limited thereto.

[0083] The third organic insulating layer 125 may be disposed on the second organic insulating layer 123. The third organic insulating layer 125 may be formed of the same material as the second organic insulating layer 123 or the first organic insulating layer 121, but the embodiments in this specification are not limited thereto.

[0084] A fourth organic insulating layer (not shown) may be further disposed on the third organic insulating layer 125, but the embodiments described herein are not limited thereto.

[0085] The connecting electrode 122 can be disposed between the first organic insulating layer 121 and the second organic insulating layer 123.

[0086] The connecting electrode 122 can electrically connect the first thin-film transistor 200 to the organic light-emitting diode (OLED). The connecting electrode 122 can be a single layer or multiple layers made of materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys of these materials, but the embodiments in this specification are not limited thereto.

[0087] An organic light-emitting diode (OLED) can be disposed on a third organic insulating layer 125 and a second organic insulating layer 123. The OLED includes a first electrode E1, a light-shielding layer E1, and a second electrode E2. The first electrode E1 can be an anode, and the second electrode E2 can be a cathode, but this specification is not limited thereto.

[0088] The third organic insulating layer 125 may have at least one recess in a sub-pixel region. (Refer to...) Figure 5 Describe the specific shape of the concave part. Figure 5 yes Figure 4 A magnified view of region X in the image.

[0089] The first electrode E1 can be connected to the connecting electrode 122 through contact holes formed in the second organic insulating layer 123 and the third organic insulating layer 125. The first electrode E1 can also be electrically connected to the second thin-film transistor 300 through the connecting electrode 122. The first electrode E1 can be a reflective electrode that reflects light, but the embodiments in this specification are not limited thereto. The first electrode E1 can contain a metallic material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) in the form of Ti / Al / Ti, a stacked structure of aluminum (Al) and titanium (ITO) in the form of ITO / Al / ITO, or an APC alloy, and can be formed as a single layer or multiple layers, but the embodiments in this specification are not limited thereto.

[0090] A light-emitting layer EL may be disposed on the first electrode E1. The light-emitting layer EL may include one or more light-emitting structures (or light-emitting elements) stacked on the first electrode E1 in the order of hole transport layer and electron transport layer or in reverse order. For example, the hole transport layer may include a hole transport layer, a hole injection layer, an electron blocking layer, or a P-type charge generation layer, but the embodiments in this specification are not limited thereto. For example, the electron transport layer may include an electron transport layer, an electron injection layer, a hole blocking layer, or an N-type charge generation layer, but the embodiments in this specification are not limited thereto.

[0091] The light-emitting layer (EL) can be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode (LED), or a micro-mini LED, but the embodiments described herein are not limited to these. For example, the light-emitting layer (EL) of the display panel 100 according to an embodiment of this specification may include an organic light-emitting layer. The light-emitting layer (EL) may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer. The light-emitting layer (EL) may also include a white light-emitting layer, but the embodiments described herein are not limited to these. Figure 6 According to Figure 4 A cross-sectional view of the touch layer. (Refer to...) Figure 6 The detailed structure of the light-emitting layer EL according to the embodiment is described.

[0092] The second electrode E2 can be disposed on the light-emitting layer EL. The second electrode E2 can be a transparent electrode that transmits light, but the embodiments in this specification are not limited thereto. For example, the second electrode E2 can contain a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal through which visible light can be transmitted, but the embodiments in this specification are not limited thereto.

[0093] The first barrier 127 can be configured to expose the first electrode E1. The first barrier 127 can define the light-emitting area of ​​the sub-pixel and can be configured to cover the edge portion (or peripheral portion) of the first electrode E1.

[0094] The first barrier 127 may contain a black material. For example, the first barrier 127 may be formed of a material containing black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but the embodiments in this specification are not limited thereto. When the first barrier 127 is formed of a material containing black pigment or black dye, the first barrier 127 may be a black barrier. When the first barrier 127 is formed of a material containing black pigment or black dye, the first barrier 127 may block light from the outside or block light reflected from the outside, thereby improving the brightness of the display device. The first barrier 127 may be used to absorb light reflected again from below the first barrier 127 in light incident from the outside.

[0095] The second dike 129 may be disposed on the first dike 127. The second dike 129 may contain a transparent material. The second dike 129 may be a transparent dike, but the embodiments described herein are not limited thereto.

[0096] Specifically, the second dike 129 can be disposed on the upper surface or side surface of the first dike 127. The second dike 129 can also be disposed on at least a portion of the first electrode E1 where the first dike 127 is not disposed. For example, the second dike 129 can be disposed on the side surface or upper surface of the first electrode E1 located in a recess of the third organic insulating layer 125. Therefore, compared to the first dike 127, the second dike 129 can have a higher taper angle. (Refer to...) Figure 3 The second dike 129 with a high cone angle can have a protruding shape or an angular shape in the plan view.

[0097] Spacer 131 may be further disposed on the second dike 129. Spacer 131 may be formed of the same material as the second dike 129, but embodiments of this specification are not limited thereto. For example, spacer 131 may be a transparent dike. Spacer 131 may be formed of the same material as the second dike 129, and may be formed simultaneously by a halftone mask, but embodiments of this specification are not limited thereto.

[0098] The first dam 127 and the second dam 129 may include a trench TR. The first dam 127 can form the trench TR by passing through the second organic insulating layer 123 and the third organic insulating layer 125, and the first dam 127 can fill the trench TR. The second dam 129 can be separated by the trench TR. The light-emitting layer EL disposed on the second dam 129 can have a reduced thickness in the trench TR region. The light-emitting layer EL with a reduced thickness can have increased resistance, thereby reducing leakage current between adjacent sub-pixels.

[0099] The light-emitting layer EL can be disposed on the first electrode E1, the first dam 127, the second dam 129, and the spacer 131. The second electrode E2 can be disposed on the light-emitting layer EL.

[0100] Encapsulation layer 400 may be disposed on the second electrode E2. Encapsulation layer 400 may include one or more insulating layers. For example, encapsulation layer 400 may include a first encapsulation layer 401, a second encapsulation layer 403 located on top of the first encapsulation layer 401, and a third encapsulation layer 405 located on top of the second encapsulation layer 403. Encapsulation layer 400 may include one or more inorganic insulating material layers and one or more organic material layers. For example, the first encapsulation layer 401 and the third encapsulation layer 405 may contain inorganic insulating materials, while the second encapsulation layer 403 may contain organic materials, but the embodiments described in this specification are not limited thereto.

[0101] Reference Figure 3 The second dike 129 can improve the scalability of the second encapsulation layer 403 by applying a protruding or angular structure. In this specification, applying a protruding or angular structure to the first dike 127 and the second dike 129 means that the shape formed by the outline of the second dike 129 in a plan view has a protruding or angular shape (or a polygonal shape).

[0102] Touch layer 500 may be disposed on encapsulation layer 400. Touch layer 500 may include touch buffer layer 501, first touch conductive layer, first touch insulating layer 503, second touch insulating layer 505, and second touch conductive layer. Third touch insulating layer may be disposed on second touch conductive layer, but the embodiments in this specification are not limited thereto.

[0103] A first touch conductive layer may be disposed on the touch buffer layer 501. The first touch conductive layer may include a bridging electrode 507. A second touch conductive layer may include a bridging electrode and a sensor electrode 509, which will be described later, and may be disposed at the boundary between adjacent sub-pixels. For example, the bridging electrode 507 and the sensor electrode 509 may be disposed in a non-light-emitting area. The bridging electrode 507 and the sensor electrode 509 may overlap with the black matrix 147 (described later) and the substrate 101 in the vertical direction. The black matrix 147 may cover the bridging electrode 507 and the sensor electrode 509. Therefore, the bridging electrode 507 and the sensor electrode 509 can be prevented from being externally visible.

[0104] A first touch insulating layer 503 and a second touch insulating layer 505 on the first touch insulating layer 503 can be disposed on the first touch conductive layer. The first touch insulating layer 503 and the second touch insulating layer 505 can prevent short circuits between the first touch conductive layer and the second touch conductive layer. The first touch insulating layer 503 can be made of silicon oxide (SiO2). x ), silicon nitride (SiN) xThe second touch insulating layer 505 may be formed in multiple layers, but the embodiments described herein are not limited thereto. The second touch insulating layer 505 may contain organic or inorganic insulating materials, but the embodiments described herein are not limited thereto, and may contain the same material as the first touch insulating layer 503.

[0105] The second touch conductive layer may be disposed on the second touch insulating layer 505. The second touch conductive layer may include sensor electrodes 509.

[0106] The sensor electrode 509 can be electrically connected to the bridging electrode 507 through contact holes formed in the first touch insulating layer 503 and the second touch insulating layer 505.

[0107] The sensor electrode 509 and the bridging electrode 507 may comprise metallic materials. For example, they may be formed of titanium (Ti), nickel (Ni), aluminum (Al), or alloys thereof, and may consist of a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments described herein are not limited thereto.

[0108] Please refer to later Figure 7 Describe the detailed structure of touch layer 500.

[0109] A cover buffer layer 139 can be disposed on the second touch conductive layer. The cover buffer layer 139 can be made of materials such as silicon nitride (SiN). x or silicon dioxide (SiO) x The inorganic insulating material is formed, but the embodiments in this specification are not limited thereto.

[0110] The black matrix 147 can be disposed on the cover buffer layer 139. The black matrix 147 can contain a black material. For example, the black matrix 147 can contain a light-blocking material or a light-absorbing material. For example, the black matrix 147 can be formed of a material containing black pigment or black dye. The black matrix 147 can cover the bridging electrode 507 and the sensor electrode 509. Therefore, the bridging electrode 507 and the sensor electrode 509 can be prevented from being seen from the outside.

[0111] The color filter CF can be set on the black matrix 147.

[0112] Color filters (CFs) can be placed in individual sub-pixels and can block specific colors of light emitted from the light-emitting regions of each sub-pixel. For example, a color filter placed in a sub-pixel emitting red light can be configured to block light of colors other than red. However, the embodiments described in this specification are not limited thereto.

[0113] The color filter CF can directly contact each of the side and top surfaces of the black matrix 147. For example, multiple color filters CF can be spaced apart at the boundaries between adjacent sub-pixels, but the embodiments in this specification are not limited to this, and can overlap in the vertical direction relative to the substrate.

[0114] A planarization layer 149 may be disposed on the color filter CF. The planarization layer 149 can be used to planarize the steps formed by the color filter CF. The planarization layer 149 may contain an organic insulating material.

[0115] Figure 5 yes Figure 4 An enlarged sectional view of region X in [the image]. References from previous sections will be omitted. Figure 4 The description is a repetitive explanation.

[0116] Reference Figure 5 The third organic insulating layer 125 may have at least one recess CON in the sub-pixel region. The third organic insulating layer 125 may surround the recess CON and may have a peripheral portion S located around the recess CON. The recess CON may include a flat portion CONP and a sloping portion CONS surrounding the flat portion CONP.

[0117] The flat portion CONP of the recess CON can be a portion whose surface is parallel to the surface of the substrate 101, and the inclined portion CONS can be a portion surrounding the flat portion CONP. The surface of the inclined portion CONS has a predetermined angle relative to the surface of the substrate 101. That is, the surface of the inclined portion CONS may not be parallel to the surface of the substrate 101.

[0118] The flat portion CONP of the recess can be disposed on the second organic insulating layer 123, and the inclined portion CONS can be formed on the side surface of the third organic insulating layer 125.

[0119] The first electrode E1 can be disposed on the peripheral portion S of the third organic insulating layer 125 and on the recess CON. In the region overlapping with the recess CON, the first electrode E1 can include a first region A1 and a second region A2 extending from the first region A1. In the first region A1, the surface of the first electrode E1 is parallel to the surface of the substrate 101. In the second region A2, the surface of the first electrode E1 has a predetermined angle relative to the surface of the substrate 101. That is, the surface of the second region A2 may not be parallel to the surface of the substrate 101. The first electrode E1 can extend from the second region A2 and include a third region A3, in which the surface of the first electrode E1 is parallel to the surface of the substrate 101. The third region A3 can be the region overlapping with the peripheral portion S of the recess CON.

[0120] The first dam 127 may be disposed on the third organic insulating layer 125 and a portion of the first electrode E1. The first dam 127 may be configured to overlap with the outer periphery S of the recess CON disposed in the third organic insulating layer 125. The first dam 127 may also be configured to overlap with the third region A3 of the first electrode E1.

[0121] The second dike 129 may be disposed on the first dike 127 and a portion of the first electrode E1. The second dike 129 may include a first portion P1 and a second portion P2. The first portion P1 and the second portion P2 may be physically connected. The first portion P1 may overlap with the side surface of the first dike 127, the upper surface of the first electrode E1 exposed by the first dike 127, and the first electrode E1 within the recess CON. The first portion P1 may respectively contact the side surface of the first dike 127, the upper surface of the first electrode E1 exposed by the first dike 127, and the first electrode E1 within the recess CON. The first portion P1 may not overlap with the upper surface of the first dike 127, but the embodiments of this specification are not limited thereto. The first portion P1 may overlap with or correspond to the recess CON.

[0122] The second part P2 may overlap with the upper surface of the first embankment 127. The second part P2 may not overlap with the side surface of the first embankment 127, but the embodiments described herein are not limited thereto. The second part P2 may correspond to or overlap with the peripheral part S.

[0123] The first dam 127 and the second dam 129 can be configured to expose a portion of the upper surface of the first electrode E1 in the region overlapping with the recess CON. That is, at least one sub-pixel can have a region of the first electrode E1 that does not overlap with the first dam 127 and the second dam 129.

[0124] The light-emitting layer EL can be disposed on the first electrode E1. The light-emitting layer EL can be formed by a directional deposition or coating method. For example, the light-emitting layer EL can be formed by physical vapor deposition (e.g., evaporation).

[0125] The luminescent layer EL formed in this way can be thinner in the region with a predetermined angle relative to the horizontal plane than in the region parallel to the horizontal plane.

[0126] For example, the thickness of the light-emitting layer EL disposed in the region corresponding to the inclined portion CONS of the recess CON can be thinner than the thickness of the light-emitting layer EL disposed on the upper surface of the first electrode E1 exposed by the second embankment 129. Furthermore, the thickness of the light-emitting layer EL disposed in the region corresponding to the inclined portion CONS of the recess CON can be thinner than the thickness of the light-emitting layer EL disposed on the peripheral portion S of the recess CON.

[0127] However, the thickness conditions of the light-emitting layer EL in this specification are not limited to this, and the thickness of the light-emitting layer EL can correspond to the thickness at various locations.

[0128] The first electrode E1 may include a reflective electrode. The first electrode E1 may be configured as a flat portion CONP and an inclined portion CONS covering the recess CON of the third organic insulating layer 125.

[0129] The second electrode E2 can be formed of a translucent or transparent conductive material. Therefore, a portion of the light emitted from the light-emitting layer EL can be reflected by the first electrode E1 in the region corresponding to the inclined portion CONS and extracted to the outside of the panel 100. When a portion of the light emitted from the light-emitting layer EL is reflected by the second region A2 of the first electrode E1 and extracted to the outside, light can be emitted without being absorbed by the second electrode E2.

[0130] At least one sub-pixel may include at least two luminescent regions EA1 and EA2. A non-luminescent region NEA1 may be disposed between the two luminescent regions EA1 and EA2.

[0131] Specifically, the first luminescent region EA1 may be a region corresponding to a portion of the recess CON of the third organic insulating layer 125. The first luminescent region EA1 may be a region in the flat portion CONP of the recess CON that does not overlap with the first portion P1 of the second embankment 129.

[0132] In the first light-emitting region EA1, a portion of the light L1 emitted from the light-emitting layer EL can be emitted through the light-emitting layer EL and the second electrode E2. Additionally, in the first light-emitting region EA1, a portion of the light L1 emitted from the light-emitting layer EL (referred to as the first light in the following description) can reach the first electrode E1, be reflected by the first electrode E1, and then sequentially pass through the light-emitting layer EL and the second electrode E2 to be extracted to the outside of the panel. The first light-emitting region EA1 can be surrounded by a first non-light-emitting region NEA1.

[0133] The first non-luminescent region NEA1 can correspond to the area where the second embankment 129 overlaps with the flat portion CONP of the recess CON. Specifically, the first non-luminescent region NEA1 can correspond to the area where the first portion P1 of the second embankment 129 overlaps with the flat portion CONP of the recess CON.

[0134] The first non-light-emitting region NEA1 can be a region where a portion of the light L3 emitted from the light-emitting layer EL is guided toward the region corresponding to the first portion P1 of the second embankment 129, but the light L3 is not extracted to the outside. In other words, the first non-light-emitting region NEA1 can be a region where light emitted from the light-emitting layer EL is emitted in a direction parallel to the planar portion CONP and reaches the first electrode E1, but the light is not reflected to the outside and remains trapped within the sub-pixel.

[0135] The second light-emitting region EA2 can be configured to surround the first non-light-emitting region NEA1. The second light-emitting region EA2 can be the region corresponding to the area where the first electrode E1 overlaps with the inclined portion CONS of the recess CON. Alternatively, the second light-emitting region EA2 can be the region corresponding to the second region A2 of the first electrode E1.

[0136] A portion of the light L2 emitted from the light-emitting layer EL (hereinafter referred to as the second light) can be guided toward the region corresponding to the second region A2 of the first electrode E1.

[0137] Specifically, the second light L2 passes through the first portion P1 of the second dam 129 and reaches a region corresponding to a portion of the second region A2 of the first electrode E1. The second light L2 reaching the first electrode E1 is reflected by the first electrode E1 and is extracted to the outside by sequentially passing through the first portion P1 of the second dam 129, the light-emitting layer EL, and the second electrode E2. When the second light L2 is extracted in this manner, the second light-emitting region EA2 is formed.

[0138] The color coordinates of the first emitting region EA1 and the second emitting region EA2 can correspond to each other. For example, the color of the light emitted by the first emitting region EA1 and the second emitting region EA2 can be the same. However, the luminous intensity of the first emitting region EA1 and the second emitting region EA2 can be different, but this specification is not limited to this.

[0139] The first non-emitting region NEA1, located between the first emitting region EA1 and the second emitting region EA2, can be a region where visible light from the first emitting region EA1 and visible light from the second emitting region EA2 are mixed, but this specification is not limited thereto.

[0140] The second non-luminescent region NEA2 can be configured to surround the second luminescent region EA2. The second non-luminescent region NEA2 can correspond to the region in which the second portion P2 of the second embankment 129 is disposed.

[0141] Figure 6 According to Figure 4 A cross-sectional view of the touch layer 500. (The reference to the previous section will be omitted.) Figure 4 The description is a repetitive explanation.

[0142] Reference Figure 6 The second touch conductive layer can be disposed on the second touch insulating layer 505. The second touch conductive layer may include a first sensor electrode 509a and a second sensor electrode 509b. The sensor electrode 509b may be disposed on, for example, a... Figure 1 The first sensor electrode 509a extending on the first direction DR1 as shown and in the example Figure 1The second sensor electrode 509b extends on the second direction DR2 shown, and the second direction DR2 is perpendicular to the first direction DR1.

[0143] The bridging electrode 507 can be electrically connected to the first sensor electrode 509a through contact holes formed in the first touch insulating layer 503 and the second touch insulating layer 505. For example, the first sensor electrode 509a and the bridging electrode 507 can be connected in the first direction DR1. Figure 1 Extending upwards.

[0144] Figure 7 It is along Figure 1 The sectional view taken by line B-B'.

[0145] Reference Figure 7 At least one panel inorganic layer 103, 107, 109, 111, 113, 115, 117, 119 may not extend to the end of the substrate 101. That is, at least one panel inorganic layer 103, 107, 109, 111, 113, 115, 117, 119 may expose the end of the substrate 101, but the embodiments in this specification are not limited thereto.

[0146] In an embodiment, the display panel 100 may further include a crack detection pattern (CSP), a low-potential voltage line (VSSL), and a gate drive unit (GIP). Figure 1 As shown, the low-potential voltage line VSSL can be located between the crack detection pattern CSP and the display area DA, and the gate drive unit GIP can be located between the low-potential voltage line VSSL and the display area DA.

[0147] For example, the gate driver GIP can be composed of a first gate 207 ( Figure 4 The conductive layer located on the same layer as the second light-shielding layer 114 Figure 4 The conductive layer located on the same layer or the first source 201 ( Figure 7 The components are conductive layers located on the same layer, but the embodiments in this specification are not limited to this.

[0148] For example, a crack detection pattern CSP can be set between the first dam D1 and the second dam D2. The crack detection pattern CSP can be formed by the first gate 207 (e.g., Figure 4 As shown) the conductive layer located on the same layer or the second light-shielding layer 114 (as shown) Figure 4 The conductive layer (shown) is located on the same layer as the first source electrode 201, but the embodiments in this specification are not limited thereto. For example, the crack detection pattern CSP may include a conductive layer located on the same layer as the first source electrode 201, but the embodiments in this specification are not limited thereto.

[0149] The low-potential voltage line VSSL can be arranged between the crack detection pattern CSP and the gate drive unit GIP. The low-potential voltage line VSSL can be composed of a conductive layer located on the same layer as the first source 201, but the embodiments in this specification are not limited thereto.

[0150] The first organic insulating layer 121 may cover the gate driver GIP, partially cover one end of the low-potential voltage line VSSL, and expose the other part of the low-potential voltage line VSSL. In this specification, one end refers to the region located in the direction from the non-display area NDA toward the display area DA, and the other end refers to the region located in the direction from the display area DA toward the non-display area NDA.

[0151] The organic insulating layer 121 may have a first connecting electrode CNE1 disposed in the same layer as the connecting electrode 122. The organic insulating electrode CNE1 may be directly connected to the area of ​​the low-potential voltage line VSSL exposed by the first protective layer 121. The first connecting electrode CNE1 may cover the other end of the low-potential voltage line VSSL, but the embodiments in this specification are not limited thereto.

[0152] The second organic insulating layer 123 can be disposed on the first connecting electrode CNE1. The second organic insulating layer 123 can directly contact and cover one end of the first connecting electrode CNE1, and can expose the other part of the first connecting electrode CNE1.

[0153] The third organic insulating layer 125 can be disposed on the second organic insulating layer 123.

[0154] The third organic insulating layer 125 can form the first layer of the first dam D1 and the first layer of the second dam D2. For example, the second dam D2 can overlap with the low-potential voltage line VSSL and cover the other end of the low-potential voltage line VSSL. The second dam D2 can directly contact the first connection electrode CNE1 and cover the other end of the first connection electrode CNE1. The third organic insulating layer 125 forming the first layer of the first dam D1 can directly contact the exposed side surface of at least one of the inorganic layers 103, 107, 109, 111, 113, 115, 117 and 119 of the panel, and can directly contact the upper surface of the substrate 101, but the embodiments in this specification are not limited thereto. The third organic insulating layer 125 can overlap with the gate driver GIP. Although the dam is shown in this specification as consisting of two parts, the dam can consist of three or more parts, or even only one part.

[0155] With the first electrode E1 (e.g.) Figure 4(As shown) A low-potential connection electrode E1a located on the same layer can be disposed on the first connection electrode CNE1 and the third organic insulating layer 125 exposed by the third organic insulating layer 125. The low-potential connection electrode E1a can be electrically connected to the first connection electrode CNE1 exposed by the third organic insulating layer 125. The low-potential connection electrode E1a can be electrically connected to the second electrode E2 (as shown). Figure 4 (As shown).

[0156] First dam 127 and second dam 129 may be disposed on the low-potential connection electrode E1a and the third organic insulating layer 125. First dam 127 and second dam 129 may overlap with the gate driver GIP, overlap with the low-potential connection electrode E1a, and cover the other end of the low-potential connection electrode E1a. First dam 127 and second dam 129 may completely cover the low-potential connection electrode E1a, but embodiments of this specification are not limited thereto. First dam 127 and second dam 129 may expose the central portion and the other end of the first connection electrode CNE1, but embodiments of this specification are not limited thereto. First dam 127 may constitute the second layer of the first dam D1 and the second layer of the second dam D2. In each of dams D1 and D2, first dam 127 may overlap with and completely cover the third organic insulating layer 125 constituting the first layer, but embodiments of this specification are not limited thereto. In the second dam D2, first dam 127 may contact the side surface of the third organic insulating layer 125 and contact the upper surface of the substrate 101, but embodiments of this specification are not limited thereto. The second dike 129 can form the third layer of dams D1 and D2. The second dike 129 forming the third layer of each of dams D1 and D2 can overlap with the first dike 127 forming the second layer and can completely cover the first dike 127, but the embodiments described herein are not limited thereto. In the second dam D2, the second dike 129 can contact the side surface of the first dike 127 and the upper surface of the substrate 101, but the embodiments described herein are not limited thereto.

[0157] Spacer 131 can form the fourth layer of the first dam D1 and the fourth layer of the second dam D2. In each dam D1 and D2, spacer 131 can overlap with the second dike 129 forming the third layer. In the second dam D2, spacer 131 can overlap with the second dike 129 forming the third layer.

[0158] Encapsulation layer 400 may be disposed on spacer 131. First encapsulation layer 401 extends to gate drive unit GIP, low-potential voltage line VSSL, first dam D1, and second dam D2, and may cover the outer surface of second dam D2. Second encapsulation layer 403 may terminate at first dam D1. Second encapsulation layer 403 may overlap with gate drive unit GIP and low-potential voltage line VSSL. Third encapsulation layer 405 extends to gate drive unit GIP, low-potential voltage line VSSL, first dam D1, and second dam D2, and may directly contact first encapsulation layer 401 on first dam D1, crack detection pattern CSP, and second dam D2.

[0159] The touch buffer layer 501 and the first touch insulating layer 503 extend to the gate driver unit GIP, the low-potential voltage line VSSL, the first dam D1 and the second dam D2, and may cover the outer surface of the second dam D2. The second touch insulating layer 505 may extend to the gate driver GIP, the low-potential voltage line VSSL, the first dam D1 and the crack detection pattern CSP, and may terminate at the second dam D2, but the embodiments in this specification are not limited thereto.

[0160] The cover buffer layer 139 may extend to the gate driver GIP, the low potential voltage line VSSL, the first dam D1 and the second dam D2, and may directly contact the outer surface of the second touch insulating layer 505, but the embodiments in this specification are not limited thereto.

[0161] Figure 8 It is along Figure 1 A sectional view taken by line C-C'.

[0162] Reference Figure 4 , Figure 7 and Figure 8 The bending region BR can be set between the sub-region SR and the crack detection pattern CSP. In the bending region BR, the inorganic layers 103, 107, 109, 111, 113, 115, 117 and 119 of the panel can be removed to expose the upper surface of the substrate 101.

[0163] In the first pad region PA1, the first source 201 is arranged (see...) Figure 4 The pad electrode PAD is located in the same layer and can be arranged on the crack detection pattern CSP with the first source 201 (see [reference]). Figure 4 The third connecting electrode CNE3 is set in the same layer.

[0164] The first organic insulating layer 121 can be disposed on the pad electrode PAD and the third connection electrode CNE3. The first organic insulating layer 121 can be disposed in the bending region BR, and the first organic insulating layer 121 can directly contact the upper surface of the substrate 101, and can directly contact the side surfaces of the inorganic layers 103, 107, 109, 111, 113, 115, 117 and 119 of the panel in the bending region BR.

[0165] The second connecting electrode CNE2 can be disposed on the first organic insulating layer 121, and the second connecting electrode CNE2 can be disposed adjacent to the connecting electrode 122 (e.g., Figure 4 (As shown) in the same layer. The second connecting electrode CNE2 can electrically connect the pad electrode PAD and the third connecting electrode CNE3. The second connecting electrode CNE2 can be arranged across the bending region BR and the first pad region PA1 and is arranged above the crack detection pattern CSP.

[0166] The data drive unit (DIC) can be disposed on the pad electrode (PAD). The DIC includes a bump (BUMP), and an anisotropic conductive film (ACF) is disposed between the pad electrode (PAD) and the bump (BUMP), electrically connecting them. The anisotropic conductive film (ACF) can contain multiple conductive balls (CB) dispersed in resin (RS). The pad electrode (PAD) and the bump (BUMP) are electrically connected through the conductive balls (CB).

[0167] A second organic insulating layer 123 may be disposed on the second connection electrode CNE2. The second organic insulating layer 123 may expose the pad electrode PAD.

[0168] A third organic insulating layer 125 may be disposed on the second organic insulating layer 123. The third organic insulating layer 125 may expose the pad electrode (PAD).

[0169] The first encapsulation layer 401 and the third encapsulation layer 405 of the encapsulation layer 400 may extend to a position before the bending region BR. For example, the first encapsulation layer 401 and the third encapsulation layer 405 may extend to a position before the crack detection pattern CSP, but the embodiments of this specification are not limited thereto, and may also overlap with the crack detection pattern CSP. The first encapsulation layer 401 and the third encapsulation layer 405 may not be provided in the bending region BR.

[0170] The touch buffer layer 501 and the first touch insulating layer 503 may extend to the bending region BR. For example, the touch buffer layer 501 and the first touch insulating layer 503 may extend to the crack detection pattern CSP and may also overlap with the crack detection pattern CSP, but the embodiments in this specification are not limited thereto. The touch buffer layer 501 and the first touch insulating layer 503 may not be provided in the bending region BR.

[0171] The second touch insulating layer 505 may overlap with the first dam D1 and the second dam D2. The second touch insulating layer 505 may not be disposed on the outside of the second dam D2, but the embodiments in this specification are not limited thereto.

[0172] The touch connection cable can be electrically connected to the second connection electrode CNE2. The touch connection cable can be used to provide signals applied from the pad electrode PAD and the second connection electrode CNE2 to, for example... Figure 6 The first sensor electrode 509a or the second sensor electrode 509b shown is illustrated. The touch connection cable can be located near components including... Figure 4 The first sensor electrode 509a shown is located in the same layer as the second touch conductive layer, but embodiments of this specification are not limited thereto, and may be located in a layer including, for example, the second touch conductive layer. Figure 4 The bridging electrode 507 shown may be composed of the same layer as the first touch conductive layer, or may be composed of both the first touch conductive layer and the second touch conductive layer, but the embodiments in this specification are not limited thereto.

[0173] The planarization layer 149 can be placed on the touch connection line, and the planarization layer 149 may not be placed in the curved area BR.

[0174] Figure 9 This illustrates an alternative embodiment. Figure 1 A planar diagram showing the arrangement of subpixels in the display area.

[0175] Reference Figure 9 The first light-emitting region EA1 and the second light-emitting region EA2 can have different shapes in a planar view. For example, the first light-emitting region EA1 can be circular in a planar view. The second light-emitting region EA2 can be a protruding shape including multiple protrusions in a planar view. The embodiments in this specification are not limited thereto. See also... Figure 4 The first dike 127 and the second dike 129 can improve the scalability of the second encapsulation layer 403 by applying a protruding shape or an angular shape structure.

[0176] The display device according to various embodiments of this specification can be described as follows.

[0177] The display device according to various embodiments of this specification may include: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; a first thin-film transistor and a second thin-film transistor disposed on the substrate and spaced apart from each other; a plurality of organic insulating layers disposed on the first thin-film transistor and the second thin-film transistor, the plurality of organic insulating layers having at least one recess; a first electrode disposed on a peripheral portion located around the recess and on the recess; a first dam and a second dam including a first portion disposed on the first electrode in a corresponding region of the recess and a second portion disposed on the first electrode and the organic insulating layer in a corresponding region of the peripheral portion; an organic layer overlapping the recess and disposed on the first electrode; a second electrode disposed on the organic layer and the second dam; a plurality of encapsulation layers disposed on the second electrode; a touch layer disposed on the plurality of encapsulation layers; and a color filter layer disposed on the touch layer.

[0178] In the display device according to various embodiments of this specification, the first dam may comprise a black material, and the second dam may comprise a transparent material.

[0179] In the display device according to various embodiments of this specification, the plurality of organic insulating layers may include at least a first organic insulating layer, a second organic insulating layer, and a third organic insulating layer stacked sequentially.

[0180] In the display device according to various embodiments of this specification, the first embankment may further include a trench passing through the second organic insulating layer and the third organic insulating layer.

[0181] In the display device according to various embodiments of this specification, a recess may be formed in the third organic insulating layer, and the recess may include a flat portion and an inclined portion surrounding the flat portion.

[0182] In the display device according to various embodiments of this specification, the first electrode may include a reflective electrode.

[0183] In the display device according to various embodiments of this specification, the flat portion of the recess may include a region in which a first portion of the second embankment does not overlap with the first electrode and corresponds to a first light-emitting region of each of a plurality of sub-pixels.

[0184] The display device according to various embodiments of this specification may further include a second light-emitting region surrounding the first light-emitting region, wherein the second light-emitting region may correspond to the region in which the first electrode overlaps with the inclined portion of the recess.

[0185] In the display device according to various embodiments of this specification, the color coordinates of the first light-emitting region may correspond to the color coordinates of the second light-emitting region.

[0186] The display device according to various embodiments of this specification may further include a first non-light-emitting area disposed between the first light-emitting area and the second light-emitting area.

[0187] In the display device according to various embodiments of this specification, the first non-light-emitting area may correspond to the area where the first portion of the second embankment overlaps with the flat portion of the recess.

[0188] The display device according to various embodiments of this specification may further include a second non-light-emitting region surrounding the second light-emitting region.

[0189] In the display device according to various embodiments of this specification, the second non-light-emitting area may correspond to the area in which the second portion of the second embankment is disposed.

[0190] In the display device according to various embodiments of this specification, the display device may further include a black matrix disposed on a touch layer, the touch layer including a bridging electrode and a sensor electrode disposed on the bridging electrode, and the black matrix overlapping the bridging electrode and the sensor electrode.

[0191] The display device according to various embodiments of this specification may further include a connection electrode disposed on a first organic insulating layer, and the first electrode is connected to a second thin-film transistor through a contact hole passing through a second organic insulating layer and a third organic insulating layer.

[0192] In the display devices according to various embodiments of this specification, connecting electrodes are provided in the curved region.

[0193] In the display device according to various embodiments of this specification, the first thin-film transistor may include a polycrystalline semiconductor layer, a first gate, a first source, and a first drain, and the second thin-film transistor may include an oxide semiconductor layer, a second gate, a second source, and a second drain.

[0194] In the display device according to various embodiments of this specification, in a plan view, at least one of the first light-emitting area, the second light-emitting area, and the first non-light-emitting area may have a protruding shape including a plurality of protrusions.

[0195] In the display device according to various embodiments of this specification, in a plan view, the second embankment may have a protruding shape or an angular shape.

[0196] The embodiments described in this specification are beneficial for providing display devices with improved light extraction efficiency.

[0197] The embodiments described herein are advantageous in providing a display device capable of improving the extension of the third encapsulation layer (or organic encapsulation layer) by applying protruding or angular structures to the second dike.

[0198] The embodiments described herein are advantageous for providing a display device having a structure capable of preventing color mixing between adjacent sub-pixels.

[0199] The embodiments described herein are advantageous in providing a display device that can reduce leakage current between adjacent sub-pixels and increase the resistance of the thinned light-emitting layer by forming trenches in the organic insulating layer and the second dike.

[0200] The effects of this specification are not limited to those described above, and those skilled in the art will clearly understand from the description of the claims other effects not described herein.

[0201] Explanation of reference numerals in the attached figures

[0202] 1: Display device

[0203] 100: Display panel

[0204] DA: Display Area

[0205] NDA: Non-display area

[0206] PX: pixel

Claims

1. A display device comprising: a substrate including a display region having a plurality of subpixels and a non-display region surrounding the display region; a first thin film transistor and a second thin film transistor provided on the substrate and spaced apart from each other; a plurality of organic insulating layers provided on the first thin film transistor and the second thin film transistor, the plurality of organic insulating layers having at least one recess; a first electrode provided on a peripheral portion located around the recess and on the recess; a first bank provided on the first electrode; a second bank provided on the first bank, the second bank including a first portion provided on the first electrode in a region corresponding to the recess and a second portion provided on the first electrode and the organic insulating layer in a region corresponding to the peripheral portion; an organic layer overlapping the recess and provided on the first electrode; a second electrode provided on the organic layer and the second bank; a plurality of encapsulating layers provided on the second electrode; a touch layer provided on the plurality of encapsulating layers; and a color filter layer provided on the touch layer. The first bank includes a black material, and the second bank includes a transparent material.

2. The display device according to claim 1, wherein The plurality of organic insulating layers includes at least a first organic insulating layer, a second organic insulating layer, and a third organic insulating layer stacked in order.

3. The display device according to claim 1, wherein The first bank further includes a trench passing through the second organic insulating layer and the third organic insulating layer.

4. The display device according to claim 3, wherein The recess is formed in the third organic insulating layer, and the recess includes a flat portion and a sloped portion surrounding the flat portion.

5. The display device according to claim 3, wherein The first electrode includes a reflective electrode.

6. The display device according to claim 1, wherein The flat portion of the recess includes a region in which the first portion of the second bank does not overlap the first electrode and corresponds to a first light emitting region of each of the plurality of subpixels.

7. The display device according to claim 5, wherein 8. The display device according to claim 7, further comprising a second light emitting region surrounding the first light emitting region, the second light emitting region corresponding to a region in which the first electrode overlaps the sloped portion of the recess. wherein Color coordinates of the first light emitting region correspond to color coordinates of the second light emitting region.

9. The display device of claim 8, wherein, 10. The display device according to claim 8, further comprising a first non-light emitting region provided between the first light emitting region and the second light emitting region. The first non-light emitting region corresponds to a region in which the first portion of the second bank overlaps the flat portion of the recess.

11. The display device of claim 10, wherein, 12. The display device according to claim 8, further comprising a second non-light emitting region surrounding the second light emitting region. The second non-light emitting region corresponds to a region in which the second portion of the second bank is provided.

13. The display device of claim 12, wherein, 14. The display device according to claim 1, further comprising a black matrix provided on the touch layer, the touch layer including a bridge electrode and a sensor electrode provided on the bridge electrode, and the black matrix overlapping the bridge electrode and the sensor electrode. ​ 15. The display device according to claim 3, further comprising a connection electrode provided over the first organic insulating layer, and the first electrode is connected to the second thin film transistor through a contact hole that passes through the second organic insulating layer and the third organic insulating layer.

16. The display device of claim 15, wherein, The connection electrode is provided in the bending region.

17. The display device of claim 1, wherein, The first thin film transistor includes a polycrystalline semiconductor layer, a first gate, a first source, and a first drain, and the second thin film transistor includes an oxide semiconductor layer, a second gate, a second source, and a second drain.

18. The display device of claim 10, wherein, At least one of the first light-emitting region, the second light-emitting region, and the first non-light-emitting region has a protruding shape including a plurality of protrusions in a plan view.

19. The display device of claim 1, wherein, The second bank has a protruding shape or a corner shape in a plan view.

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