Display device, method of manufacturing same, and electronic device

Abstract

The invention discloses a display device, a method of manufacturing the same, and an electronic device. The display device includes a pixel circuit layer; the via hole layer is arranged on the pixel circuit layer, and the via hole layer comprises a groove; the first through hole and the second through hole penetrate through the via hole layer; a first metal layer electrically connected to the pixel circuit layer through the first through hole; the anode electrode is arranged on the via hole layer; a first emission assembly disposed on the anode electrode; a charge generation layer disposed on the first emission element; and a second emission element disposed on the charge generation layer, in which the pixel circuit layer includes a transistor electrically connected to an initialization voltage node, in which the initialization voltage node is configured to transfer an initialization voltage, and in which the transistor is electrically connected to the charge generation layer through the first metal layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0118731, filed on September 2, 2024, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Various embodiments of the present disclosure relate to a display device, a method of manufacturing a display device, and an electronic device. BACKGROUND

[0003] With the advancement of information technology, display devices have become increasingly important as a medium for connecting users with information. Accordingly, the use of various types of display devices, such as liquid crystal display devices and organic light emitting diode display devices, has significantly increased. SUMMARY

[0004] One aspect of the present disclosure relates to a display device, an electronic device, and a method for manufacturing the display device designed to minimize a leakage current between adjacent sub-pixels.

[0005] However, the object of the present disclosure is not limited to the above-mentioned object, and various modifications can be made without departing from the spirit and scope of the present disclosure.

[0006] Embodiments of the present disclosure provide a display device including a pixel circuit layer; a via layer disposed on the pixel circuit layer, wherein the via layer includes a trench; a first via hole and a second via hole passing through the via layer; a first metal layer electrically connected to the pixel circuit layer through the first via hole; an anode electrode disposed on the via layer; a first emission component disposed on the anode electrode; a charge generation layer disposed on the first emission component; and a second emission component disposed on the charge generation layer, wherein the pixel circuit layer includes a transistor electrically connected to an initialization voltage node, wherein the initialization voltage node is configured to transmit an initialization voltage, and wherein the transistor is electrically connected to the charge generation layer through the first metal layer.

[0007] The display device further includes a separation wall disposed on the first metal layer, wherein the separation wall includes a first separation wall layer; and a second separation wall layer disposed on the first separation wall layer, wherein the second separation wall layer is wider than the first separation wall layer in a direction parallel to a surface of the pixel circuit layer.

[0008] The trench includes a first trench and a second trench, and wherein a height of the first trench is less than a height of the second trench.

[0009] The display device further includes a second metal layer electrically connected to the pixel circuit layer through the second via hole; and a cathode electrode disposed on the second emission component, wherein the second metal layer is in contact with the cathode electrode in a region adjacent to or superposed with the second trench.

[0010] The first metal layer and the second metal layer are disposed in the same plane, wherein the first partition wall is in contact with the first metal layer, and wherein an upper surface of each of the first emission component, the charge generation layer, and the second emission component has a stepped portion.

[0011] The first metal layer is in contact with the charge generation layer in a region adjacent to or superposed with the first trench.

[0012] The charge generation layer is not in contact with the second metal layer.

[0013] The first metal layer is in contact with the charge generation layer in a first contact region, and wherein, in a plan view, the first contact region is spaced apart from the anode electrode and encloses at least a portion of a periphery of the anode electrode.

[0014] The display device further includes a second metal layer electrically connected to the pixel circuit layer through a second via, and a cathode electrode disposed on the second emission component, wherein the cathode electrode is in contact with the second metal layer in a second contact region, and wherein, in a plan view, the second contact region encloses at least a portion of a periphery of the anode electrode.

[0015] The first metal layer is a single layer including titanium (Ti), or a multi-layer including at least one of titanium (Ti), aluminum (Al), copper (Cu), and molybdenum titanium (MoTi).

[0016] A side surface of the anode electrode is positively tapered.

[0017] The display device further includes a display area in which pixels are disposed, wherein the display device is a hole inactive area (HIAA) display device, and a hole is formed in the display area.

[0018] The display device further includes a first sub-pixel and a second sub-pixel, wherein the charge generation layer is not electrically connected between the first sub-pixel and the second sub-pixel.

[0019] The first metal layer is electrically connected to the pixel circuit layer through a second via, wherein the first metal layer is in contact with the charge generation layer in a contact region, and wherein, in a plan view, the contact region encloses a first portion of a periphery of the anode electrode and does not enclose a second portion of the periphery of the anode electrode.

[0020] Embodiments of the present disclosure provide a method of manufacturing a display device, the method comprising: forming a pixel circuit layer comprising a transistor; forming a via layer on the pixel circuit layer; forming a first via hole and a second via hole in the via layer; forming a first metal layer; forming a trench by etching the via layer; forming an anode electrode on the via layer; and forming an emission structure on the anode electrode, wherein the step of forming the emission structure comprises: forming a first emission component on the anode electrode; forming a charge generation layer on the first emission component; and forming a second emission component on the charge generation layer, wherein the transistor comprises an initialization transistor electrically connected to an initialization voltage node, wherein the initialization voltage node is configured to transmit an initialization voltage, wherein the step of forming the charge generation layer comprises contacting the charge generation layer with the first metal layer, and wherein the charge generation layer is electrically connected to the initialization transistor.

[0021] The method further comprises forming a partition wall on the first metal layer, wherein the step of forming the partition wall comprises: forming a first partition wall layer; and forming a second partition wall layer on the first partition wall layer, and wherein the second partition wall layer is wider than the first partition wall layer.

[0022] The step of forming the trench comprises: forming a first trench and a second trench, and wherein the step of forming the first trench and the second trench comprises etching the via layer such that a height of the first trench is smaller than a height of the second trench.

[0023] The method further comprises: forming a second metal layer; and forming a cathode electrode on the second emission component, wherein the second metal layer is electrically connected to the pixel circuit layer through the second via hole, wherein the first metal layer and the second metal layer are formed in the same process, wherein the step of forming the cathode electrode comprises contacting the cathode electrode with the second metal layer, and wherein the second metal layer is electrically connected to a line configured to supply a cathode voltage.

[0024] Each of the first metal layer and the second metal layer is a single layer comprising titanium (Ti) or a multi-layer comprising at least one of titanium (Ti), aluminum (Al), copper (Cu), and molybdenum titanium (MoTi), and wherein the anode electrode has a side surface with a positive taper.

[0025] The first metal layer is electrically connected to the pixel circuit layer through the second via hole, and wherein, in a plan view, an area where the charge generation layer contacts the first metal layer encloses at least a portion of a periphery of the anode electrode.

[0026] Embodiments of the disclosure provide an electronic device including a processor configured to provide input image data and a display device configured to display an image based on the input image data, wherein the display device includes a pixel circuit layer, a via layer disposed on the pixel circuit layer, wherein the via layer includes a trench, a first via hole and a second via hole passing through the via layer, a first metal layer electrically connected to the pixel circuit layer through the first via hole, an anode electrode disposed on the via layer, a first emission component disposed on the anode electrode, a charge generation layer disposed on the first emission component, and a second emission component disposed on the charge generation layer, wherein the pixel circuit layer includes a transistor electrically connected to an initialization voltage node, wherein the initialization voltage node is configured to transmit an initialization voltage, and wherein the transistor is electrically connected to the charge generation layer through the first metal layer.

[0027] Embodiments of the disclosure provide a display device including a pixel circuit layer, a via layer disposed on the pixel circuit layer and including a trench, a via extending through the via layer, a conductive layer electrically connected to the pixel circuit layer through the via, an anode disposed on the via layer, an emission component disposed on the anode, and a charge generation layer disposed on the emission component, wherein the pixel circuit layer includes a transistor configured to provide an initialization voltage, and wherein the transistor is electrically connected to the charge generation layer through the conductive layer. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment of the disclosure.

[0029] Figure 2 is an example of a sub-pixel of Figure 1 .

[0030] Figure 3 is an example of a sub-pixel of Figure 2 .

[0031] Figure 4 is a plan view illustrating an example of a display panel of Figure 1 .

[0032] Figure 5 is an exploded perspective view illustrating a portion of a display panel of Figure 4 .

[0033] Figure 6 is a plan view illustrating an example of any one of the pixels of Figure 5 .

[0034] Figure 7 is a cross-sectional view taken along line I-I' of Figure 6 .

[0035] Figure 8 is a cross-sectional view illustrating an emission structure of Figure 7 .

[0036] Figure 9 is a magnified cross-sectional view illustrating a region A of Figure 7 .

[0037] Figure 10 is a plan view for explaining a contact region according to an embodiment of the disclosure.

[0038] Figure 11 is a cross-sectional view of a display panel according to another embodiment of the disclosure.

[0039] Figure 12 is a plan view for explaining a contact region according to another embodiment of the disclosure.

[0040] Figure 13 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the disclosure.

[0041] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 are schematic cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the disclosure.

[0042] Figure 19 are schematic cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the disclosure.

[0043] Figure 20 is a schematic block diagram illustrating an electronic device including a display device according to an embodiment of the disclosure.

[0044] Figure 21 is a schematic diagram illustrating an example in which the electronic device of Figure 20 is a smart phone.

[0045] Figure 22 is a schematic diagram illustrating an example in which the electronic device of Figure 20 is a tablet computer. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings. For the purpose of clarity, components that are necessary for understanding the operation according to the disclosure will be described, while other components will be omitted to avoid obscuring the point of the disclosure. Accordingly, the disclosure is not limited to the embodiments set forth herein, and can be implemented in various other forms. These embodiments are provided to ensure a thorough and complete comprehension of the disclosure and to fully convey the technical spirit of the disclosure to those skilled in the art.

[0047] It will be understood that when an element is referred to as “joined” or “connected” to another element, the element may be directly joined or connected to said other element, or there may be an intermediary element between them. The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. In the specification, when an element is referred to as “comprising” or “including” a component, it does not exclude another component but may also include other components unless the context clearly indicates otherwise. The phrases “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” should be understood to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term “and / or” can include any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first," "second," etc., can be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element.

[0049] As illustrated in the accompanying drawings, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) are used herein for descriptive purposes to indicate the relationship of one element or feature to another. In addition to the orientations depicted in the drawings, these terms are also intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device shown in the drawings is flipped, an element described as “below” or “under” another element or feature would then be oriented “above” said other element or feature. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented differently (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms should be interpreted accordingly.

[0050] The various embodiments described herein are presented with reference to the accompanying drawings, which are schematic illustrations of idealized embodiments. Variations in the shapes depicted in the drawings are expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but rather include deviations in shape caused, for example, by manufacturing processes. The shapes shown in the drawings are not intended to represent the actual shapes of areas of the device and should not be considered limiting.

[0051] This disclosure relates to a display device designed to reduce leakage current between adjacent sub-pixels, a method of manufacturing the display device, and an electronic device including the display device. The display device includes a pixel circuit layer, a via layer with trenches and vias, and emitting components such as an anode electrode, a charge generation layer, and a cathode electrode. A key feature involves an innovative arrangement of the charge generation layer to connect to an initialization voltage node via transistors, ensuring precise voltage control to prevent operational defects such as "black spot phenomena." The trench and via design plays a crucial role in optimizing electrical connections while minimizing lateral leakage.

[0052] This disclosure details a layered structure including a metal layer for improved conductivity and partition walls for structural and optical separation between sub-pixels. The tandemly arranged emitting components improve light generation and output efficiency while ensuring electrical isolation. This design is particularly suitable for integration into high-density displays, such as OLEDs for smartphones and other compact electronic devices, where leakage control is critical for performance and reliability. Design variations allow for flexibility in implementation while maintaining core functionality.

[0053] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0054] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0055] The display panel 110 may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to the m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to the n-th data line DLn. Here, m and n are natural numbers greater than 1.

[0056] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, each of the subpixels SP can produce light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more subpixels SP can form a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a pixel PXL.

[0057] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal to initiate each frame, a horizontal synchronization signal for coordinating the timing of gate signal output and data signal application, etc.

[0058] In one embodiment, first emission control lines EL1 to m-th emission control lines ELm connected in the row direction to the sub-pixel SP may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control driver may operate under the control of the controller 150.

[0059] The gate driver 120 may be disposed on one side of the display panel 110. However, the embodiments are not limited to the foregoing examples. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically separated from each other. The drivers may be disposed on a first side of the display panel 110 and a second side of the display panel 110 opposite to the first side. Thus, according to the embodiments, the gate driver 120 may be disposed around the display panel 110 in various configurations.

[0060] The data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. The data driver 130 can receive image data DATA and data control signals DCS from the controller 150. The data driver 130 can operate in response to the data control signals DCS. In an embodiment, the data control signals DCS may include a source start pulse, a source shift clock, a source output enable signal, etc.

[0061] The data driver 130 can use the voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn. Therefore, the associated sub-pixel SP can generate light corresponding to the data signal. As a result, an image can be displayed on the display panel 110.

[0062] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0063] Voltage generator 140 can operate in response to a voltage control signal VCS provided from controller 150. Voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to components of display device 100. For example, voltage generator 140 can be configured to receive an input voltage from an external device located outside display device 100, regulate the received voltage, and adjust the regulated voltage to generate multiple voltages.

[0064] Voltage generator 140 can generate a first electrical voltage VDD and a second electrical voltage VSS. The generated first electrical voltage VDD and second electrical voltage VSS can be provided to sub-pixels SP. The first electrical voltage VDD can have a relatively high voltage level. The second electrical voltage VSS can have a lower voltage level than the first electrical voltage VDD. In other embodiments, the first electrical voltage VDD or the second electrical voltage VSS can be provided by an external device disposed outside the display device 100.

[0065] Additionally, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage to be applied to the sub-pixel SP. For example, during sensing operations for measuring the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, a specific reference voltage can be applied to each of the first data lines DL1 to the nth data line DLn. Voltage generator 140 can generate a reference voltage.

[0066] The controller 150 can control the overall operation of the display device 100. The controller 150 can receive input image data IMG and control signals CTRL from external devices to manage the operation of displaying the input image data IMG. The controller 150 can generate a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0067] The controller 150 can convert the input image data IMG to be compatible with the display device 100 or display panel 110, and then output image data DATA. In an embodiment, the controller 150 can align the input image data IMG line by line to match the arrangement of subpixels SP before outputting the image data DATA.

[0068] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component separate from the driver integrated circuit (DIC).

[0069] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the ambient temperature and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0070] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In an embodiment, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can control components such as the data driver 130 and / or the voltage generator 140 to adjust the data signal and the first power voltage VDD and the second power voltage VSS.

[0071] The display device 100 according to the embodiments may be a device configured to display video (e.g., moving images) or still images. The display device 100 can be used not only as a portable electronic device such as a mobile phone, smartphone, tablet PC, smartwatch, and watch phone, but also as a display screen for various products such as televisions, laptops, monitors, advertising panels, and Internet of Things (IoT) devices. In this disclosure, the application areas of the display device 100 are not limited to the specific examples.

[0072] Figure 2 It is shown Figure 1 A block diagram illustrating an example of any subpixel SP in the subpixel SP. Figure 2 The image shows a sub-pixel SPij, which is set in... Figure 1 The subpixels SP are located in the i-th row (where i is an integer equal to or greater than 1 and less than or equal to m) and the j-th column (where j is an integer equal to or greater than 1 and less than or equal to n).

[0073] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0074] The light-emitting element (LD) is connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN can be used for transmission. Figure 1 The first power voltage node is VDD. The second power voltage node, VSSN, can be used for transmission. Figure 1 The node of the second power voltage VSS.

[0075] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via a sub-pixel circuit SPC. The cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0076] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm Figure 1 The first transmit control line EL1 to the m-th transmit control line ELm, and the i-th transmit control line ELi and Figure 1 The j-th data line DLj is one of the first data lines DL1 to the nth data line DLn. The sub-pixel circuit SPC is configured to control the light-emitting element LD in response to signals received through these signal lines.

[0077] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, if the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0078] The sub-pixel circuit SPC can operate in response to a transmission control signal received via the i-th transmission control line ELi. In an embodiment, the i-th transmission control line ELi may include one or more sub-transmission control lines. When the i-th transmission control line ELi includes two or more sub-transmission control lines, the sub-pixel circuit SPC can operate in response to a transmission control signal received via the corresponding sub-transmission control line.

[0079] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage, in response to an emission control signal received via the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0080] Figure 3 It is shown Figure 2 A circuit diagram of an example of a sub-pixel SPij.

[0081] Reference Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0082] The sub-pixel circuit (SPC) can be connected to the i-th gate line GLi', the i-th emitter control line ELi', and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' may also include a third sub-gate line SGL3 and a fourth sub-gate line SGL4. Compared with... Figure 2 Compared to the i-th transmit control line ELi, the i-th transmit control line ELi' may include a first sub-transmit control line SEL1 and a second sub-transmit control line SEL2.

[0083] The sub-pixel circuit SPC may include a first transistor T1 to a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0084] The first transistor T1 is connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 can be connected to the second node N2. Therefore, the first transistor T1 can be turned on based on the voltage level of the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0085] The second transistor T2 can be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 can be connected to the first sub-gate line SGL1. Therefore, the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0086] The third transistor T3 can be connected between the first node N1 and the second node N2. The gate of the third transistor T3 can be connected to the second sub-gate line SGL2. Therefore, the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 can be connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 can be connected to the second sub-emission control line SEL2. Therefore, the fourth transistor T4 can be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0088] A fifth transistor T5 (e.g., also referred to as a first initialization transistor) can be connected between the anode electrode AE ​​of the light-emitting element LD and the first initialization voltage node VINTN1. For example, the fifth transistor T5 can be electrically connected to the first emitting component EU1 forming the light-emitting element LD (see reference). Figure 8 The first initialization voltage can be transmitted to the first transmitting component EU1. The first initialization voltage node VINTN1 is configured to transmit the first initialization voltage. In an embodiment, the first initialization voltage can be transmitted by… Figure 1 The voltage is provided by voltage generator 140. In other embodiments, the first initialization voltage may be provided by an external device outside the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3. Therefore, the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0089] The sixth transistor T6 is connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 can be connected to the first sub-emitter control line SEL1. Therefore, the sixth transistor T6 can be turned on in response to the emitter control signal of the first sub-emitter control line SEL1.

[0090] A seventh transistor T7 (e.g., also referred to as a second initialization transistor) can be connected between the charge generation layer CGL of the light-emitting element LD and the second initialization voltage node VINTN2. For example, the seventh transistor T7 can be electrically connected to the charge generation layer CGL forming the light-emitting element LD (see reference). Figure 8 And the second initialization voltage can be transmitted to the second transmitting component EU2 (see reference). Figure 8 The second initialization voltage node VINTN2 is configured to transmit the second initialization voltage. In an embodiment, the second initialization voltage can be generated by... Figure 1 The voltage is provided by voltage generator 140. In other embodiments, the second initialization voltage may be provided by an external device outside the display device 100. The gate of the seventh transistor T7 may be connected to the fourth sub-gate line SGL4. Therefore, the seventh transistor T7 may be turned on in response to the gate signal of the fourth sub-gate line SGL4.

[0091] In an embodiment, the second initialization voltage may be the same as the first initialization voltage. However, this disclosure is not limited to the foregoing example, and the second initialization voltage may differ from the first initialization voltage depending on the characteristics of the first transmitting component EU1 and the second transmitting component EU2. In an embodiment, a signal for supplying the first initialization voltage and a signal for supplying the second initialization voltage may be applied simultaneously. However, this disclosure is not limited to this example, and the signals for supplying the first initialization voltage and the signals for supplying the second initialization voltage may be applied at different times.

[0092] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power voltage node VDDN and the second node N2.

[0093] As described, the sub-pixel circuit SPC may include first transistors T1 to seventh transistors T7, a first capacitor C1, and a second capacitor C2. However, the embodiments are not limited to the above. The sub-pixel circuit SPC can be implemented in various forms, all including multiple transistors and one or more capacitors. Depending on the specific implementation of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GL1' and the number of sub-emission control lines included in the i-th emission control line ELi' can vary.

[0094] The first transistor T1 through the seventh transistor T7 can be formed of P-type transistors. Each of the first transistor T1 through the seventh transistor T7 can be formed of a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the embodiments are not limited to the above. For example, at least one of the first transistor T1 through the seventh transistor T7 can be replaced by an N-type transistor.

[0095] In the embodiments, the first transistor T1 to the seventh transistor T7 may include amorphous silicon semiconductor, single crystal silicon semiconductor, polycrystalline silicon semiconductor or oxide semiconductor, etc.

[0096] A light-emitting element (LD) may include an anode electrode (AE), a cathode electrode (CE), and an emitting layer (or emitting structure (see reference)). Figure 8 The emitting layer can be disposed between the anode electrode AE ​​and the cathode electrode CE. When the transmission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are set to low level after the data signal transmitted through the j-th data line DLj affects the voltage at the second node N2, the fourth transistor T4 and the sixth transistor T6 can be turned on. The first transistor T1 can also be turned on according to the voltage at the second node N2, allowing current to flow from the first power voltage node VDDN to the second power voltage node VSSN. Therefore, the light-emitting element LD can emit light proportional to the amount of current.

[0097] Figure 4 It is shown Figure 1 A floor plan of an example of display panel 110.

[0098] Reference Figure 4 As Figure 1 The example display panel DP of the display panel 110 depicted may include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA may be positioned around the display area DA.

[0099] In embodiments, the display panel DP may be a Hole-In-Active-Area (HIAA) display panel, wherein a hole (e.g., a hole accommodating a camera or stacked with a camera) is formed in the display area DA. For example, the display device 100 according to an embodiment may be a HIAA display device. However, this disclosure is not limited to the foregoing examples.

[0100] Display panel DP can include substrate SUB, subpixel SP, and pad (also known as "solder pad") PD.

[0101] When the display panel DP is used as a display for head-mounted displays (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, augmented reality (AR) devices, etc., the display panel DP can be positioned very close to the user's eyes. In such cases, a relatively high density of subpixels SP may be required. To achieve this increased pixel density, a silicon substrate can be used to implement the substrate SUB. The subpixels SP and / or the display panel DP can be formed on the substrate SUB, which is a silicon substrate. A display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see reference). Figure 1 This can be referred to as an OLED on silicon (OLEDoS) display device.

[0102] Subpixels SP can be disposed on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to the foregoing examples. For example, subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, subpixels SP can be arranged in a pentile pattern. ® Arrangement. The first direction DR1 can refer to the row direction, and the second direction DR2 can refer to the column direction.

[0103] Two or more sub-pixels SP can form a pixel PXL.

[0104] Components for controlling subpixels SP can be positioned on the substrate SUB within the non-display area NDA. For example, components such as those connected to the subpixels SP... Figure 1 The lines shown, from the first gate line GL1 to the m-th gate line GLm and from the first data line DL1 to the n-th data line DLn, can be arranged in the non-display area NDA.

[0105] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 can be integrated into the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 can be mounted on the display panel DP and positioned in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In one embodiment, the temperature sensor 160 can be positioned in the non-display area NDA to sense the temperature of the display panel DP.

[0106] The pad PD can be positioned on the substrate SUB within the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wirelines. For example, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn.

[0107] The pad PD can connect the display panel DP to the display device 100 (see reference). Figure 1 Other component interface connections. In an embodiment, the voltage and signals required for the operation of components included in the display panel DP can be obtained from the PD via the pad PD. Figure 5 The driver integrated circuit (DIC) is provided. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be supplied from the driver integrated circuit (DIC) via the pad PD. In addition, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0108] In this embodiment, the circuit board can be electrically connected to the pad PD via a conductive adhesive assembly such as an anisotropic conductive film. Here, the circuit board can be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board and electrically connected to the pad PD.

[0109] In this embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including linear and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0110] In one embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In another embodiment, the display panel DP is flexible, foldable, or rollable. In the foregoing cases, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0111] Figure 4 It is shown Figure 5 An exploded perspective view of a portion of the display panel (DP). For clarity and simplicity, Figure 4 The diagram schematically depicts the display panel DP and... Figure 4 The portion corresponding to pixels PXL1 and PXL2 within the pixel PXL. The remaining portions of the display panel DP corresponding to other pixels can be configured in a similar manner.

[0112] Reference Figure 5 and Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel to a third sub-pixel SP1, SP2, and SP3. However, the embodiments are not limited to the foregoing examples. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0113] exist Figure 2 The illustration shows a case where the first to third sub-pixels SP1, SP2, and SP3 have a rectangular shape and the same size when viewed on a third direction DR3, which intersects the first direction DR1 and the second direction DR2. However, the embodiment is not limited to the foregoing example. The first to third sub-pixels SP1, SP2, and SP3 can have various shapes.

[0114] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), an outer coating layer (OC), and a cover window (CW).

[0115] In embodiments, the substrate SUB may include a silicon wafer substrate formed by semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0116] A pixel circuit layer (PCL) may be disposed on a substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may be used as at least some of circuit components, lines, etc. The conductive patterns may include copper, but the embodiments are not limited thereto.

[0117] The circuit elements may include the individual sub-pixel circuits SPCs (see reference) for the first to third sub-pixels SP1, SP2, and SP3. Figure 2 The sub-pixel circuit SPC may include transistors and one or more capacitors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode superimposed on the semiconductor portion. Hereinafter, the term "superimposed on" may mean "superimposed on when viewed in a plane," where a plane refers to a surface on which the substrate SUB is disposed. In an embodiment, when the substrate SUB is formed from a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is formed from a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane formed in a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other on a third direction DR3, with an insulating layer disposed therebetween.

[0118] The lines of the pixel circuit layer (PCL) may include signal lines (e.g., gate lines, emit control lines, and data lines) connected to each of the first to third sub-pixels SP1, SP2, and SP3. The lines may also include connections to... Figure 2 The first power voltage node VDDN line. Additionally, the line may include connections to... Figure 2 The second power voltage node VSSN line.

[0119] The light-emitting element layer (LDL) may include an anode electrode (AE), a separator wall (PW), an emission structure (EMS), and a cathode electrode (CE).

[0120] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​can include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0121] A separator wall (PW) can be disposed on the pixel circuit layer (PCL). The separator wall (PW) can surround the anode electrode (AE). The separator wall (PW) can correspond to a pixel defining layer that defines the emission regions corresponding to the first sub-pixels (SP1) to the third sub-pixels (SP3), respectively. The separator wall (PW) can include an opening (OP) superimposed on the region where the anode electrode (AE) can be disposed. For example, the anode electrode (AE) can be disposed in the opening (OP) defined by the separator wall (PW). Each emission region corresponding to the first sub-pixels (SP1) to the third sub-pixels (SP3) can be defined according to the opening (OP) in the separator wall (PW). In regions adjacent to the boundaries of neighboring sub-pixels, the separator wall (PW) can cause discontinuities in the emission structure (EMS).

[0122] In this embodiment, the separator wall PW may comprise an inorganic material. In this case, the separator wall PW may comprise multiple inorganic layers stacked on top of each other. For example, the separator wall PW may comprise silicon oxide (SiO₂). x ) and silicon nitride (SiN) x ).

[0123] The emitting structure EMS can be disposed on the anode electrode AE. The emitting structure EMS may include an emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0124] In an embodiment, the transmitting structure EMS can fill the opening OP in the partition wall PW and can also be disposed on the upper part of the partition wall PW. In other words, at least a portion of the transmitting structure EMS can fill each of the openings OP in the partition wall PW and can be interrupted at the boundary of the region defining the partition wall PW (e.g., at the boundary between the partition wall PW and its opening OP). For example, the portions of the transmitting structure EMS corresponding to the first sub-pixels SP1 to the third sub-pixels SP3 can be separated from each other, and each portion is aligned and positioned with the corresponding opening OP in the partition wall PW. However, the embodiments are not limited to the foregoing examples.

[0125] The cathode electrode CE can be disposed on the emitter structure EMS. In an embodiment, the cathode electrode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, the cathode electrode CE can be a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3. Alternatively, in an embodiment, the cathode electrode CE can fill the opening OP of the separator wall PW and terminate at the boundary between the separator wall PW and its opening OP. In this case, the cathode electrode CE can be disposed individually for each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0126] The cathode electrode CE can be a thin-film metal layer with a thickness sufficient to allow light emitted from the emitting structure EMS to pass through. The cathode electrode CE can be made of a metallic material with a relatively small thickness or of a transparent conductive material. In embodiments, the cathode electrode CE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, zinc aluminum oxide, zinc gallium oxide, zinc tin oxide, and tin gallium oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and compounds thereof. However, the material of the cathode electrode CE is not limited to the foregoing examples.

[0127] Any one of the anode electrodes AE, the portion of the emission structure EMS superimposed on any one of the anode electrodes AE, and the portion of the cathode electrode CE superimposed on the portion of the emission structure EMS can be understood as constituting a light-emitting element LD (refer to...). Figure 6 In other words, each of the light-emitting elements (LDs) in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a portion of the emission structure EMS superimposed on the anode electrode AE, and a portion of the cathode electrode CE superimposed on the portion of the emission structure EMS. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported to the emission layer of the emission structure EMS, where holes and electrons form excitons. Light is generated when the excitons transition from the excited state to the ground state. The brightness of the emitted light is determined by the amount of current flowing through the emission layer, while the wavelength range of the light depends on the configuration of the emission layer.

[0128] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In embodiments, the encapsulation layer TFE can include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layers can include silicon nitride, silicon oxide, or silicon oxynitride (SiO2). x N y For example, the organic layer may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic and inorganic layers of the encapsulation layer TFE are not limited to the foregoing examples.

[0129] The encapsulation layer TFE may also include aluminum oxide (AlO) xA thin film, including aluminum oxide, can be positioned on the upper surface of the TFE encapsulation layer facing the optical functional layer OFL and / or below the lower surface of the TFE encapsulation layer facing the light-emitting element layer LDL.

[0130] Thin films including alumina can be formed using atomic layer deposition (ALD). However, the embodiments are not limited to the foregoing examples. The encapsulation layer TFE may also comprise a thin film formed from at least one of a variety of materials suitable for improving encapsulation efficiency.

[0131] The optical functional layer (OFL) can be disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0132] A color filter layer (CFL) can be disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL can be configured to filter light emitted from the emission structure (EMS) and selectively output light of a wavelength range or color corresponding to each sub-pixel. The CFL may include color filters (CFs) corresponding to first sub-pixels SP1 through third sub-pixels SP3, respectively. Each of the color filters (CFs) allows light within the wavelength range corresponding to the associated sub-pixel to pass through it. For example, the color filter (CF) corresponding to the first sub-pixel SP1 allows red light to pass through it, the color filter (CF) corresponding to the second sub-pixel SP2 allows green light to pass through it, and the color filter (CF) corresponding to the third sub-pixel SP3 allows blue light to pass through it. Depending on the light emitted from the emission structure (EMS) of each sub-pixel, at least some of the color filters (CFs) may be omitted.

[0133] A lens array LA can be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixels SP1 through SP3, respectively. Each of the lenses LS can output and guide light emitted from the emission structure EMS along a designated path, thereby improving light output efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the outer coating OC. In embodiments, the lenses LS may include organic materials. In embodiments, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not limited to the foregoing examples.

[0134] In an embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA are offset relative to the openings OP in the partition wall PW in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. Specifically, in the central region of the display area DA, the center of each color filter CF and the center of each lens LS may be aligned with or superimposed with the center of their corresponding openings OP in the partition wall PW. For example, in the central region of the display area DA, each opening OP of the partition wall PW may be completely superimposed with its corresponding color filter CF of the color filter layer CFL and its corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed along the third direction DR3, the centers of the color filters CF and the lenses LS may be offset in a planar direction relative to the center of their corresponding openings OP in the partition wall PW. For example, in the region of the display area DA adjacent to the non-display area NDA, each opening OP of the partition wall PW may be partially superimposed with its corresponding color filter CF of the color filter layer CFL and its corresponding lens LS of the lens array LA. Therefore, light emitted from the emission structure EMS in the central part of the display area DA can be effectively guided to the display surface in the normal direction. At the same time, light emitted from the emission structure EMS near the periphery of the display area DA can be effectively guided at an angle inclined relative to the normal direction of the display surface.

[0135] An outer coating OC can be disposed on the lens array LA. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the emission structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layers from foreign matter such as dust and moisture. For example, the outer coating OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC can include epoxy resin, but the embodiments are not limited thereto. The outer coating OC can have a lower refractive index than the lens array LA.

[0136] A cover window (CW) may be disposed on the outer coating (OC). The cover window (CW) may be configured to protect the underlying layer. The cover window (CW) may have a higher refractive index than the outer coating (OC). The cover window (CW) may include glass, but embodiments are not limited thereto. For example, the cover window (CW) may include an encapsulating glass layer configured to protect components disposed beneath it. In other embodiments, the cover window (CW) may be omitted.

[0137] Figure 5 It shows Figure 6 A plan view of any one of the pixels in an embodiment. Figure 5 For clarity and simplicity, only schematic depictions are provided. Figure 5The first pixel PXL1 is one of the first pixels PXL1 and the second pixel PXL2. The other pixels can be configured in the same way as the first pixel PXL1.

[0138] Reference Figure 6 and Figure 5 The first pixel PXL1 may include the first sub-pixel SP1 to the third sub-pixel SP3 arranged on the first direction DR1.

[0139] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA formed around the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA formed around the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA formed around the third emission region EMA3.

[0140] The first emission region EMA1 can be a light-emitting structure EMS (see reference). Figure 7 The first emission region EMA2 can be the region where light is emitted from the emission structure EMS corresponding to the second sub-pixel SP1. The second emission region EMA3 can be the region where light is emitted from the emission structure EMS corresponding to the third sub-pixel SP3.

[0141] Figure 6 It is according to the embodiments of this disclosure along Figure 7 A sectional view taken by line I-I'. Figure 8 In this version, the optical functional layer OFL, outer coating OC, and cover window CW are omitted. Figure 7 It is shown Figure 7 A cross-sectional view of the EMS (Emission System) transmitter structure.

[0142] Reference Figure 2 It provides a base SUB and a pixel circuit layer PCL disposed on the base SUB.

[0143] The substrate SUB may include a silicon wafer substrate formed by semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0144] The pixel circuit layer (PCL) can be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include various circuit elements for the first sub-pixel SP1 to the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL can include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 can be a sub-pixel circuit (SPC) included in the first sub-pixel SP1 (see reference). Figure 7 The transistor T_SP2 of the second sub-pixel SP2 can be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 can be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. For example, Figure 3 Each of the transistors T_SP1, T_SP2, and T_SP3 shown can be used as... Figure 7 The seventh transistor T7 corresponds to the second initialization transistor shown in the diagram. Figure 6 In the image, for clarity and simplicity, only one transistor is shown for each sub-pixel, and the remaining circuit elements are omitted.

[0145] The transistor T_SP1 of the first sub-pixel SP1 may include the source region SRA, the drain region DRA, and the gate electrode GE.

[0146] The source region (SRA) and drain region (DRA) can be disposed within the substrate (SUB). A well (WL) formed by ion implantation can also be disposed within the substrate (SUB). The source region (SRA) and drain region (DRA) can be spaced apart from each other within the well (WL). The region between the source region (SRA) and drain region (DRA) within the well (WL) can be referred to as the channel region. The gate electrode (GE) can be stacked with the channel region between the source region (SRA) and drain region (DRA) and can be disposed within the pixel circuit layer (PCL). The gate electrode (GE) can be spaced apart from the well (WL) or channel region by an insulating material such as a gate insulating layer (GI). The gate electrode (GE) can include a conductive material.

[0147] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA via a drain connector DRC passing through one or more insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA via a source connector SRC passing through one or more insulating layers.

[0148] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be implemented as one of the transistors of the first sub-pixel SP1.

[0149] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured in the same way as the transistor T_SP1 of the first sub-pixel SP1.

[0150] Therefore, the substrate SUB and the pixel circuit layer PCL can include the individual circuit elements of the first sub-pixel SP1 to the third sub-pixel SP3.

[0151] A via layer VIAL can be disposed on the pixel circuit layer PCL. The via layer VIAL may include a first via layer VIAL1 and a second via layer VIAL2. The first via layer VIAL1 can be disposed on the pixel circuit layer PCL to cover the pixel circuit layer PCL and can be characterized by an overall flat surface. The first via layer VIAL1 is configured to planarize the stepped portions of the pixel circuit layer PCL. The first via layer VIAL1 may include silicon oxide (SiO2). x Silicon nitride (SiN) x The embodiments are not limited to at least one of silicon carbonitride (SiCN) and silicon carbonitride (SiCN).

[0152] The light-emitting element layer (LDL) can be disposed on the first via layer (VIAL1). The LDL may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a second via layer (VIAL2), a first anode electrode (AE1) to a third anode electrode (AE3), a separator wall (PW), an emission structure (EMS), and a cathode electrode (CE). In an embodiment, the first reflective electrode (RE1) to the third reflective electrode (RE3) may be omitted.

[0153] The first reflective electrode RE1 to the third reflective electrode RE3 can be respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3 on the first via layer VIAL1. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element disposed in the pixel circuit layer PCL through a corresponding via passing through the first via layer VIAL1.

[0154] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can serve as total reflection mirrors, reflecting light emitted from the emitting structure EMS toward the display surface (or the cover window CW). The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may comprise a metallic material suitable for reflecting light. The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may comprise at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from the foregoing, but the embodiments are not limited thereto. In embodiments, the first reflecting electrodes RE1 to the third reflecting electrodes RE3 may be formed from multiple layers including aluminum (Al) or silver (Ag), but this disclosure is not limited thereto.

[0155] In an embodiment, the connecting electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode can improve the electrical connection between the corresponding reflective electrode and the corresponding circuit element of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited to this. In an embodiment, the corresponding reflective electrode may be positioned between multiple layers of the connecting electrode.

[0156] In an embodiment, a buffer pattern may be further disposed below at least one of the first reflective electrodes RE1 to the third reflective electrode RE3. The buffer pattern may include inorganic materials such as silicon carbonitride, but the embodiment is not limited thereto. With the buffer pattern in the appropriate position, the height of the corresponding reflective electrode on the third-direction DR3 can be adjusted.

[0157] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a half-reflection mirror. For example, the combination of each of the first reflecting electrodes RE1 to the third reflecting electrodes RE3 with the cathode electrode CE can form a resonant structure in the corresponding sub-pixel. Light emitted from the emission layer of the emission structure EMS can be amplified by reflecting back and forth between the corresponding reflecting electrode and the cathode electrode CE. The amplified light can then be emitted through the cathode electrode CE. In the context of this application, the distance between each reflecting electrode and the cathode electrode CE can be interpreted as the resonant distance of the light emitted from the emission layer of the corresponding emission structure EMS.

[0158] To flatten the stepped portion between the first reflective electrode RE1 and the third reflective electrode RE3, a second via layer VIAL2 can be disposed on the first via layer VIAL1 and the first reflective electrodes RE1 to RE3. The second via layer VIAL2 can cover the entire surface of the first reflective electrodes RE1 to RE3 and the first via layer VIAL1.

[0159] The first anode electrode AE1 to the third anode electrode AE3 can be disposed on the second via layer VIAL2, and stacked with the first reflective electrode RE1 to the third reflective electrode RE3 respectively. When viewed on a third-party DR3, the first anode electrode AE1 to the third anode electrode AE3 can have the same... Figure 8 The first emission regions EMA1 to the third emission regions EMA3 have similar shapes. Each of the first anode electrodes AE1 to the third anode electrodes AE3 is connected to its corresponding reflective electrode among the first reflective electrodes RE1 to the third reflective electrodes RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 through a first anode via A_VIA1 passing through the second via layer VIAL2. The second anode electrode AE2 can be connected to the second reflective electrode RE2 through a second anode via A_VIA2 passing through the second via layer VIAL2. The third anode electrode AE3 can be connected to the third reflective electrode RE3 through a third anode via A_VIA3 ​​passing through the second via layer VIAL2.

[0160] In the embodiments, the first anode electrode AE1 to the third anode electrode AE3 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x The materials are at least one of the transparent conductive materials selected from indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1 to the third anode electrode AE3 are not limited to the foregoing examples. For example, the first anode electrode AE1 to the third anode electrode AE3 may include titanium nitride.

[0161] In one embodiment, each of the first anode electrode AE1 to the third anode electrode AE3 may be formed of a multilayer structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are sequentially stacked. However, this disclosure is not limited to the foregoing example. In another embodiment, each of the first anode electrode AE1 to the third anode electrode AE3 may be formed of a single-layer structure comprising indium tin oxide (ITO).

[0162] A metal layer ML can be disposed on a via layer VIAL (or a second via layer VIAL2). The metal layer ML may include a first metal layer ML1 and a second metal layer ML2. The metal layer ML may contact the via layer VIAL (or the second via layer VIAL2). The first metal layer ML1 and the second metal layer ML2 may not be physically in contact with each other. For example, in an embodiment, a first emitter region EMA1 may separate the first metal layer ML1 and the second metal layer ML2 adjacent to the first emitter region EMA1 from each other. The first metal layer ML1 can be electrically connected to transistor T_SP1 through a first via VIA1 passing through the via layer VIAL (or the first via layer VIAL1 and the second via layer VIAL2). In other words, the first metal layer ML1 can be electrically connected to transistor T_SP1 through a first via VIA1 passing through the first via layer VIAL1 and the second via layer VIAL2. The first metal layer ML1 can be electrically connected to a seventh transistor T7 through the first via VIA1. The first via VIA1 may pass through at least a portion of the pixel circuit layer PCL. The second metal layer ML2 can be electrically connected to a line for supplying a second electrical voltage (e.g., cathode voltage) via a second via VIA2 passing through the via layer VIAL (or the first via layer VIAL1 and the second via layer VIAL2). In other words, the second via VIA2 can pass through both the first via layer VIAL1 and the second via layer VIAL2. The second via VIA2 can also pass through at least a portion of the pixel circuit layer PCL.

[0163] The metal layer ML (or each of the first metal layer ML1 and the second metal layer ML2) may include at least one conductive material. For example, the metal layer ML may include at least one of titanium (Ti), aluminum (Al), copper (Cu), and molybdenum titanium (MoTi). For example, the metal layer ML may be formed from a single layer including titanium (Ti), or from multiple layers including at least one of titanium (Ti), aluminum (Al), copper (Cu), and molybdenum titanium (MoTi). For example, the metal layer ML may have any of the following: a multilayer structure including titanium (Ti) and aluminum (Al), a multilayer structure including titanium (Ti) and copper (Cu), and a multilayer structure including copper (Cu) and molybdenum titanium (MoTi).

[0164] A separator wall PW can be disposed on the via layer VIAL. At least a portion of the separator wall PW can be disposed on the metal layer ML. For example, a portion of the separator wall PW can be disposed on the first metal layer ML1, and a portion of the separator wall PW can be disposed on the second metal layer ML2. As an example, for the first metal layer ML1 and the second metal layer ML2 adjacent to the first emitter region EMA1, the first emitter region EMA1 can separate the portion of the separator wall PW disposed on the first metal layer ML1 from the portion of the separator wall PW disposed on the second metal layer ML2. A portion of the separator wall PW can contact the first metal layer ML1, and a portion of the separator wall PW can contact the second metal layer ML2.

[0165] In an embodiment, the separator PW may include multiple inorganic layers. For example, the separator PW may include a first separator layer PW1 and a second separator layer PW2, each of which is an inorganic insulating layer. For example, the first separator layer PW1 may include silicon nitride (SiN). x The second separator layer PW2 may include silicon oxide (SiO2). x ).

[0166] The first partition wall layer PW1 and the second partition wall layer PW2 can be stacked on the thickness direction (e.g., third-direction DR3) of the pixel circuit layer PCL. For example, the first partition wall layer PW1 can be disposed on the via layer VIAL. At least a portion of the first partition wall layer PW1 can contact the upper surfaces of the first metal layer ML1 and the second metal layer ML2. The second partition wall layer PW2 can be disposed on the first partition wall layer PW1. The second partition wall layer PW2 can contact the upper surface of the first partition wall layer PW1.

[0167] The first partition wall layer PW1 may have a smaller width than the second partition wall layer PW2. For example, compared to the first partition wall layer PW1, the second partition wall layer PW2 may protrude further outward in the first direction DR1 or the second direction DR2. In embodiments, the partition wall PW may have a "T"-shaped structure. For example, the partition wall PW may form a pointed structure (or undercut structure) in which the first partition wall layer PW1 is more inwardly recessed than the second partition wall layer PW2.

[0168] The separator wall PW can have a pointed structure. When depositing material to form the emission structure EMS, the emission structure EMS can be segmented into portions corresponding to the individual sub-pixels SPX1, SPX2, and SPX3 that are separated from each other. For example, at least some layers of the emission structure EMS can be segmented at the boundary regions between sub-pixels SPX1, SPX2, and SPX3. For example, at least some layers of the emission structure EMS can be separated at the boundary regions of the emission regions EMA1, EMA2, and EMA3 of sub-pixels SPX1, SPX2, and SPX3. This segmentation reduces the risk of leakage current flowing between adjacent sub-pixels SPX1, SPX2, and SPX3.

[0169] The emitting structure EMS can be disposed on the anode electrode AE ​​of the opening OP in the spacer wall PW. Additionally, at least a portion of the emitting structure EMS can be disposed on the spacer wall PW. As described above, the emitting structure EMS can be divided during deposition by the spacer wall PW between adjacent sub-pixels SPX1, SPX2, and SPX3. This division reduces the risk of current leakage from each of the first sub-pixels SP1 to the third sub-pixels SP3 through the layer of the emitting structure EMS to adjacent sub-pixels during the operation of the display panel DP. As a result, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability.

[0170] Reference Figure 7 The EMS (Emitting System) can have a series structure in which a first transmitting component EU1 and a second transmitting component EU2 are stacked. Figure 9 Each of the first light-emitting elements LD1 to the third light-emitting element LD3 has essentially the same configuration.

[0171] Each of the first emitting component EU1 and the second emitting component EU2 may include at least one emitting layer configured to generate light in response to an applied current. The first emitting component EU1 may include a first emitting layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emitting layer EML1 may be disposed between the first electron transport component ETU1 and the first hole transport component HTU1. The second emitting component EU2 may include a second emitting layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emitting layer EML2 may be disposed between the second electron transport component ETU2 and the second hole transport component HTU2.

[0172] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0173] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0174] A connection layer, which can be implemented as a charge generation layer CGL, can be disposed between the first emitter component EU1 and the second emitter component EU2 to connect the first emitter component EU1 and the second emitter component EU2 to each other. Specifically, the charge generation layer CGL can electrically connect the first emitter component EU1 and the second emitter component EU2 to each other. In embodiments, the charge generation layer CGL can have a stacked structure including a p-doped layer and an n-doped layer. For example, the p-doped layer can include p-type dopants (such as 1,4,5,8,9,11-hexaazabenzophenanthrene hexacarboxynitrile (HAT-CN), tetracyanoquinone dimethyl ether (TCNQ), or 2-(7-dicyanomethylene-1,3,4,5,6,8,9,10-octafluoro-7H-pyrene-2-ylidene)-malonadionitrile (NDP-9)), and the n-doped layer can include alkali metals, alkaline earth metals, lanthanides, or combinations thereof. However, the embodiments are not limited to the foregoing examples.

[0175] In an embodiment, the first emitting layer EML1 and the second emitting layer EML2 can emit light of different colors. The light emitted from the first emitting layer EML1 and the second emitting layer EML2 can be combined to produce white light. For example, the first emitting layer EML1 can produce blue light, and the second emitting layer EML2 can produce yellow light. In an embodiment, the second emitting layer EML2 can have a stacked structure including a first sub-emitting layer configured to produce red light and a second sub-emitting layer configured to produce green light. Red and green light can be mixed to produce yellow light. In this case, an intermediate layer configured to transport holes and / or block electron transport can be included between the first and second sub-emitting layers to improve performance.

[0176] In other embodiments, the first emitting layer EML1 and the second emitting layer EML2 can produce light of the same color.

[0177] The cathode electrode CE can be disposed on the emitting structure EMS. The cathode electrode CE can be used as a semi-reflective mirror, thereby allowing it to partially transmit and partially reflect light emitted from the emitting structure EMS.

[0178] A first light-emitting element can be formed by the first anode electrode AE1, the portion of the emitting structure EMS superimposed on the first anode electrode AE1, and the portion of the cathode electrode CE superimposed on the first anode electrode AE1. A second light-emitting element can be formed by the second anode electrode AE2, the portion of the emitting structure EMS superimposed on the second anode electrode AE2, and the portion of the cathode electrode CE superimposed on the second anode electrode AE2. A third light-emitting element can be formed by the third anode electrode AE3, the portion of the emitting structure EMS superimposed on the third anode electrode AE3, and the portion of the cathode electrode CE superimposed on the third anode electrode AE3.

[0179] Figure 7 It is shown Figure 10 An enlarged cross-sectional view of region A. Figure 10 This is a plan view used to illustrate the contact areas according to embodiments of the present disclosure. To show the arrangement relationship between the contact areas (CNT1 and CNT2) and the anode electrode AE, Figure 7 A schematic plan view of the anode electrode AE ​​is provided.

[0180] Reference Figure 9 and Figure 9 The via layer VIAL (or the second via layer VIAL2) may include trenches TCH. The trenches TCH may surround the area where the anode electrode AE ​​is disposed. The trenches TCH may include a first trench TCH1 and a second trench TCH2. Both the first trench TCH1 and the second trench TCH2 may refer to grooves formed in the via layer VIAL (or the second via layer VIAL2). Both the first trench TCH1 and the second trench TCH2 may form stepped portions on the surface (e.g., the upper surface) of the via layer VIAL (or the second via layer VIAL2).

[0181] The first trench TCH1 may be adjacent to the first metal layer ML1. For example, the first trench TCH1 may be positioned closer to the first metal layer ML1 than to the second metal layer ML2. The second trench TCH2 may be adjacent to the second metal layer ML2. For example, the second trench TCH2 may be positioned closer to the second metal layer ML2 than to the first metal layer ML1.

[0182] In this embodiment, the first trench TCH1 and the second trench TCH2 may have different heights. For example, the first trench TCH1 may have a first trench height H1. The second trench TCH2 may have a second trench height H2. The second trench height H2 may be greater than the first trench height H1. The trench height may be defined as the linear distance from the bottom of the trench to the upper surface of the second via layer VIAL2.

[0183] The anode electrode AE ​​may not be positioned within the first trench TCH1 or the second trench TCH2. For example, the anode electrode AE ​​may not be stacked with the first trench TCH1 or the second trench TCH2.

[0184] The anode electrode AE ​​may be characterized by a positively tapered side surface. "Positively tapered" indicates that the width (e.g., the width defined in the first direction DR1 or the second direction DR2) decreases as the anode electrode AE ​​extends in the third direction DR3. This positively tapered design helps prevent the charge generation layer CGL from short-circuiting at the edge of the anode electrode AE.

[0185] A first emission component EU1 may be disposed on the anode electrode AE, and at least a portion of the first emission component EU1 may be disposed in the first trench TCH1 and the second trench TCH2. In other words, the first emission component EU1 may be in direct contact with the anode electrode AE, the bottom of the first trench TCH1, and the bottom of the second trench TCH2. At least a portion of each of the first trench TCH1 and the second trench TCH2 may be filled with the first emission component EU1. Since the second via layer VIAL2 includes the first trench TCH1 and the second trench TCH2, the surface (e.g., the upper surface) of the first emission component EU1 may have a stepped profile. For example, relative to the third direction DR3, the upper surface of the first emission component EU1 in the region overlapping with the first trench TCH1 may be higher than the upper surface of the first emission component EU1 in the region overlapping with the second trench TCH2.

[0186] A charge generation layer CGL can be disposed on the first emitter assembly EU1, and at least a portion of the charge generation layer CGL can be disposed in the first trench TCH1 and the second trench TCH2. The charge generation layer CGL can be in direct contact with the first emitter assembly EU1. Because the second via layer VIAL2 includes the first trench TCH1 and the second trench TCH2, the surface (e.g., the upper surface) of the charge generation layer CGL can have a stepped profile. For example, relative to the third direction DR3, the upper surface of the charge generation layer CGL in the region overlapping with the first trench TCH1 can be higher than the upper surface of the charge generation layer CGL in the region overlapping with the second trench TCH2.

[0187] The charge-generating layer CGL can be in physical contact with the first metal layer ML1 in a region superimposed on (or adjacent to) the first trench TCH1. For example, refer to Figure 10 and Figure 9 The charge-generating layer CGL can be in physical contact with the first metal layer ML1 in the first contact region CNT1. The first contact region CNT1 can be spaced apart from the anode electrode AE ​​and positioned around the anode electrode AE. The first contact region CNT1, where the first metal layer ML1 and the charge-generating layer CGL contact, can be located near (or on) the upper surface of the second via layer VIAL2. For example, in a plan view, the first contact region CNT1 may not overlap with the anode electrode AE. For example, in a plan view, the first contact region CNT1 can be spaced apart from the anode electrode AE ​​and partially surround the periphery of the anode electrode AE. In an embodiment, the first contact region CNT1 may only surround a portion of the anode electrode AE, rather than completely surrounding the periphery of the anode electrode AE.

[0188] The charge generation layer CGL can contact the first metal layer ML1, thereby establishing an electrical connection between the charge generation layer CGL and the first metal layer ML1. The first metal layer ML1 can also be electrically connected to the seventh transistor T7, and therefore can receive the second initialization voltage.

[0189] The charge generation layer CGL can transmit the supplied second initialization voltage to the second emitting component EU2. If the second emitting component EU2 is not fully initialized, black float may occur, where a solid black is not displayed on the display panel DP, and a faint color appears instead when no power is supplied to the sub-pixels SP1, SP2, and SP3 (e.g., when the intention is to display black). Instead, this disclosure provides a configuration in which the second emitting component EU2 can be initialized by supplying the second initialization voltage separately to the charge generation layer CGL, thereby preventing black float.

[0190] The charge generation layer CGL may not be in physical contact with the second metal layer ML2. For example, in the region superimposed with the second trench TCH2, the charge generation layer CGL may not be in physical contact with the second metal layer ML2.

[0191] The charge generation layer CGL can be divided by the partition wall PW between the first sub-pixel and the third sub-pixels SP1, SP2, and SP3. For example, the charge generation layer CGL can be cut off at the boundary of the partition wall PW to ensure that it is not electrically connected between the first sub-pixel and the third sub-pixels SP1, SP2, and SP3. As a result, current cannot flow through the charge generation layer CGL between the first sub-pixel and the third sub-pixels SP1, SP2, and SP3, effectively preventing leakage current between the first sub-pixel and the third sub-pixels SP1, SP2, and SP3.

[0192] The display device 100 according to this disclosure may include structures (e.g., trench TCH, separator wall PW, and metal layer ML) to prevent leakage current between the first sub-pixel and the third sub-pixels SP1, SP2, and SP3, thereby improving the reliability of the display device 100. Furthermore, in embodiments where the display device 100 is implemented as a HIAA display device, this structure can also prevent moisture penetration in areas where holes are formed in the display area DA.

[0193] The second emitter component EU2 can be disposed on the charge generation layer CGL, and at least a portion of the second emitter component EU2 can be disposed in the second trench TCH2. Since the second via layer VIAL2 includes the first trench TCH1 and the second trench TCH2, the surface (e.g., the upper surface) of the second emitter component EU2 can have a stepped profile.

[0194] In one embodiment, the second transmitting component EU2 may contact the side surface of the partition wall PW in the region where it overlaps (or is adjacent to) the first trench TCH1. The second transmitting component EU2 may not contact the side surface of the partition wall PW in the region where it overlaps (or is adjacent to) the second trench TCH2.

[0195] The cathode electrode CE can be disposed on the second emitting assembly EU2. Since the second via layer VIAL2 includes a first trench TCH1 and a second trench TCH2, the surface of the cathode electrode CE (e.g., the upper surface) can have a stepped portion.

[0196] The cathode electrode CE can be in physical contact with the second metal layer ML2 in a region that is stacked with (or adjacent to) the second trench TCH2. For example, refer to Figure 10 and Figure 11 The cathode electrode CE can be in physical contact with the second metal layer ML2 in the second contact region CNT2. The second contact region CNT2 can be spaced apart from the anode electrode AE ​​and positioned around the anode electrode AE. For example, in a plan view, the second contact region CNT2 may not overlap with the anode electrode AE. For example, in a plan view, the second contact region CNT2 can be spaced apart from the anode electrode AE ​​and surround at least a portion of the periphery of the anode electrode AE. In an embodiment, the second contact region CNT2 may only surround a portion of the anode electrode AE, rather than completely surrounding the periphery of the anode electrode AE. The second contact region CNT2 can be physically separated from the first contact region CNT1.

[0197] The cathode electrode CE can contact the second metal layer ML2, establishing an electrical connection between the cathode electrode CE and the second metal layer ML2. The second metal layer ML2 can then be electrically connected to a line supplying a second electrical voltage, and thus can receive the second electrical voltage (e.g., the cathode voltage).

[0198] The cathode electrode CE may not be in physical contact with the first metal layer ML1. For example, in the region where it overlaps (or is adjacent to) the first trench TCH1, the cathode electrode CE may not be in physical contact with the first metal layer ML1. More precisely, the cathode electrode CE may be in contact with the separator wall PW.

[0199] The cathode electrode CE and the charge generation layer CGL can share the same configuration in the first sub-pixel to the third sub-pixel SP1, SP2 and SP3, so that each of the first sub-pixel to the third sub-pixel SP1, SP2 and SP3 can be individually controlled by the second power voltage and the second initialization voltage supplied to them.

[0200] Figure 12 This is a cross-sectional view of a display panel according to another embodiment of the present disclosure. Figure 12 This is a plan view used to illustrate the contact area CNT' according to another embodiment. To show the arrangement relationship between the contact area CNT' and the anode electrode AE, Figure 11 A schematic plan view of the anode electrode AE ​​is presented.

[0201] Figure 9 The embodiments shown are similar to Figure 11 The difference in the embodiments shown is that the trenches do not have different heights. In the following text, descriptions of the elements or features already discussed will be omitted.

[0202] Reference Figure 11 The trenches TCH' can be formed to have the same (or uniform) height.

[0203] The first metal layer ML1' can be connected to the first via VIA1 and the second via VIA2. The first metal layer ML1' can be electrically connected to transistor T_SP1 through the first via VIA1 and the second via VIA2 passing through the via layer VIAL (or the first via layer VIAL1 and the second via layer VIAL2). The first metal layer ML1' can be electrically connected to the seventh transistor T7 through the first via VIA1 and the second via VIA2.

[0204] The charge-generating layer CGL can be in physical contact with the first metal layer ML1' in the region superimposed with the trench TCH'. For example, refer to Figure 12 and Figure 13 to Figure 18The charge-generating layer CGL can be in physical contact with the first metal layer ML1' in the contact region CNT'. The contact region CNT' can be spaced apart from and positioned around the anode electrode AE. For example, the contact region CNT' may not overlap with the anode electrode AE ​​in a plan view. For example, in a plan view, the contact region CNT' can be spaced apart from the anode electrode AE ​​and surround at least a portion of the periphery of the anode electrode AE. In an embodiment, the contact region CNT' may surround only a portion of the anode electrode AE, rather than completely surrounding the periphery of the anode electrode AE.

[0205] The cathode electrode CE can span from the first sub-pixel to the third sub-pixel SP1, SP2, and SP3 (e.g., the cathode electrode CE can extend from the first sub-pixel SP1 to the third sub-pixel SP3), and supplies cathode voltage to the first sub-pixel to the third sub-pixel SP1, SP2, and SP3 through the cathode voltage application region CE_A above the emission structure EMS. For example, the cathode electrode CE can receive the cathode voltage at a position higher than the plane on which the first metal layer ML1' is disposed.

[0206] In the following text, reference will be made to Figure 13 A method for manufacturing a display device 100 according to an embodiment of the present disclosure is described. Descriptions of elements that are repeated in detail in the previous description are omitted.

[0207] Figure 14 to Figure 18 This is a flowchart illustrating a method for manufacturing a display device 100. Figure 13 This is a schematic cross-sectional view illustrating a method of manufacturing a display device 100 according to an embodiment of the present disclosure.

[0208] Reference Figure 14 The method of manufacturing the display device 100 may include the steps of forming a through hole in the via layer, forming a metal layer, forming a partition wall, forming a trench by etching the via layer, forming an anode electrode, forming an emission structure, and forming a cathode electrode.

[0209] Reference Figure 15 Before step S100 of forming vias in the via layer, a pixel circuit layer PCL can be formed on the substrate SUB. The pixel circuit layer PCL includes a conductive layer constituting a sub-pixel circuit SPC for driving a light-emitting element LD and an insulating layer disposed between the conductive layers.

[0210] After forming the pixel circuit layer PCL, a step of forming a via layer VIAL can be performed. The step of forming the via layer VIAL may include forming a first via layer VIAL1 and forming a second via layer VIAL2. The first via layer VIAL1 can be formed on the pixel circuit layer PCL. The second via layer VIAL2 can be formed on the first via layer VIAL1.

[0211] In an embodiment, the step of forming the reflective electrode RE can be performed between the step of forming the first via layer VIAL1 and the step of forming the second via layer VIAL2. The step of forming the reflective electrode RE may include the steps of forming the first reflective electrode RE1 to the third reflective electrode RE3. The first reflective electrode RE1 can be formed in the region defining the first sub-pixel SP1. The second reflective electrode RE2 can be formed in the region defining the second sub-pixel SP2. The third reflective electrode RE3 can be formed in the region defining the third sub-pixel SP3.

[0212] Reference Figure 16 Step S100, which involves forming vias in the via layer, may include forming an anode via A_VIA, a first via VIA1, and a second via VIA2 in the via layer VIAL. The anode via A_VIA, the first via VIA1, and the second via VIA2 can be formed using a photolithography process. The anode via A_VIA, the first via VIA1, and the second via VIA2 can be formed in substantially the same configuration within the region defined by the first sub-pixel SP1 to the third sub-pixel SP3.

[0213] The anode via A_VIA can be formed to pass through the second via layer VIAL2 and stacked with the reflective electrode RE. The reflective electrode RE can contact the anode via A_VIA.

[0214] Both the first via VIA1 and the second via VIA2 can be formed to pass through the second via layer VIAL2 and the first via layer VIAL1. Furthermore, each of the first via VIA1 and the second via VIA2 can be formed to pass through at least a portion of the pixel circuit layer PCL. The first via VIA1 and the second via VIA2 can be formed in a region that is not superimposed on the anode electrode AE.

[0215] Reference Figure 17 Step S200, forming the metal layers, may include forming a first metal layer ML1 and a second metal layer ML2. The steps of forming the first metal layer ML1 and the second metal layer ML2 may include forming a base metal layer by depositing materials used to form the first metal layer ML1 and the second metal layer ML2, and etching the base metal layer. The base metal layer may be etched to form the first metal layer ML1 and the second metal layer ML2.

[0216] In embodiments, one or more of chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes may be used to deposit layers in the configuration of the display device 100. In embodiments, one or more of wet etching and dry etching may be used as etching processes. However, this disclosure is not limited to the specific examples.

[0217] The first metal layer ML1 and the second metal layer ML2 can be formed using the same process. For example, the first metal layer ML1 and the second metal layer ML2 can be formed using the same etching process. The first metal layer ML1 and the second metal layer ML2 can be disposed on the same plane. For example, the first metal layer ML1 and the second metal layer ML2 can be disposed on and in contact with the second via layer VIAL2.

[0218] In step S200 of forming a metal layer, a first metal layer ML1 may be formed. A first via VIA1 may be filled with the first metal layer ML1. The first metal layer ML1 may contact the first via VIA1. In step S200 of forming a metal layer, a second metal layer ML2 may be formed. A second via VIA2 may be filled with the second metal layer ML2. The second metal layer ML2 may contact the second via VIA2. In step S200 of forming a metal layer, the first metal layer ML1 may be electrically connected to the seventh transistor T7, and the second metal layer ML2 may be electrically connected to a line for supplying a second electrical voltage (e.g., cathode voltage).

[0219] Reference Figure 18 In the step of forming the partition wall PW, a partition wall PW with a multi-layer stacked structure can be formed. For example, the step of forming the partition wall PW may include the step of forming a first partition wall layer PW1 and the step of forming a second partition wall layer PW2. At least a portion of the partition wall PW can be formed on the first metal layer ML1. At least a portion of the partition wall PW can be formed on the second metal layer ML2.

[0220] The steps of forming the partition wall PW may include forming a first substrate partition wall layer by depositing material for forming a first partition wall layer PW1, forming a second substrate partition wall layer by depositing material for forming a second partition wall layer PW2, and etching the first and second substrate partition wall layers. The first and second substrate partition wall layers may be etched to form the first partition wall layer PW1 and the second partition wall layer PW2, respectively. The first substrate partition wall may be etched deeper than the second substrate partition wall layer, such that the second partition wall layer PW2 may protrude further toward the peripheral region (or outward) than the first partition wall layer PW1. In other words, the second partition wall layer PW2 may be wider than the first partition wall layer PW1 in the first direction DR1.

[0221] Reference Figure 9 The step S400 of forming trenches by etching the via layer may include the step of forming trench TCH by etching the via layer VIAL (e.g., the second via layer VIAL2). The step of forming trench TCH may include the step of forming a first trench TCH1 and the step of forming a second trench TCH2.

[0222] Each of the regions defining the first to third sub-pixels SP1, SP2, and SP3 may include a first trench region A1, a second trench region A2, and an intermediate region MA. The first trench region A1 may correspond to the region where the first trench TCH1 will be formed by etching the second via layer VIAL2. The first trench region A1 may be adjacent to the first metal layer ML1. The second trench region A2 may correspond to the region where the second trench TCH2 will be formed by etching the second via layer VIAL2. The second trench region A2 may be adjacent to the second metal layer ML2. The intermediate region MA may be the region surrounded by the trench TCH and may correspond to the region where the anode electrode AE ​​will be disposed.

[0223] The steps of forming the first trench TCH1 may include applying a photoresist to overlap with the second trench region A2 and the intermediate region MA, followed by etching the second via layer VIAL2 overlapped with the first trench region A1. During the steps of forming the first trench TCH1, the photoresist can be removed from the region overlapped with the first trench region A1, allowing the first trench TCH1 to be formed by etching the second via layer VIAL2 in the region overlapped with the first trench region A1.

[0224] The step of forming the second trench TCH2 may include applying a photoresist to overlap with the first trench region A1 and the intermediate region MA, followed by etching the second via layer VIAL2 overlapped with the second trench region A2. During the step of forming the second trench TCH2, the photoresist can be removed from the region overlapped with the second trench region A2, allowing the second trench TCH2 to be formed by etching the second via layer VIAL2 in the region overlapped with the second trench region A2.

[0225] Optionally, in an embodiment, the steps of forming the first trench TCH1 and the second trench TCH2 may include setting a photoresist to overlap with the first trench region A1, the second trench region A2, and the intermediate region MA, followed by etching the second via layer VIAL2 overlapped with the first trench region A1, the second trench region A2, and the intermediate region MA. In this case, the photoresist may have different thicknesses in the respective regions overlapped with the first trench region A1, the second trench region A2, and the intermediate region MA. For example, the photoresist may have its maximum thickness in the region overlapped with the intermediate region MA and its minimum thickness in the region overlapped with the second trench region A2. For example, the photoresist set in the first trench region A1 and the second trench region A2 may be a halftone photoresist.

[0226] During the formation of the trench TCH, the second trench TCH2 can be etched deeper than the first trench TCH1, and the height of the second trench TCH2 can be greater than the height of the first trench TCH1. Therefore, the surface of the second via layer VIAL2 can have a stepped portion.

[0227] After step S400, which involves etching the via layer to form a trench, step S500, which involves forming an anode electrode, can be performed. In step S500, an anode electrode AE ​​can be formed on the second via layer VIAL2. The anode electrode AE ​​can be formed in a region overlapping with the intermediate region MA. The anode electrode AE ​​can be formed with a positively tapered side surface.

[0228] Reference Figure 13 and Figure 11 Step S600, which forms the emission structure, may include forming a first emission component EU1, forming a charge generation layer CGL on the first emission component EU1, and forming a second emission component EU2 on the charge generation layer CGL. The first emission component EU1, the charge generation layer CGL, and the second emission component EU2 may be deposited by a deposition process.

[0229] During the step of forming the charge generation layer CGL, the charge generation layer CGL may be formed. The charge generation layer CGL may be in physical contact with the first metal layer ML1 in the region superimposed with the first trench TCH1. The charge generation layer CGL may not be in physical contact with the second metal layer ML2 in the region superimposed with the second trench TCH2.

[0230] After step S600 of forming the emission structure, step S700 of forming the cathode electrode can be performed. In step S700 of forming the cathode electrode, the cathode electrode CE can be formed. The cathode electrode CE can be in physical contact with the second metal layer ML2 in the region where it is superimposed with the second trench TCH2. The cathode electrode CE can also be in non-physical contact with the first metal layer ML1 in the region where it is superimposed with the first trench TCH1.

[0231] In the following text, reference will be made to Figure 13 , Figure 19 and Figure 19 A method for manufacturing a display device 100 according to an embodiment of the present disclosure is described. Figure 11 This is a schematic cross-sectional view illustrating a method of manufacturing a display device 100 according to an embodiment of the present disclosure.

[0232] Reference Figure 13 , Figure 19 and Figure 20 Step S200, forming a metal layer, may include forming a first metal layer ML1'. Forming the first metal layer ML1' may include forming a base metal layer by depositing a material for forming the first metal layer ML1' and etching the base metal layer. The base metal layer may be etched to form the first metal layer ML1'.

[0233] In step S200, a first metal layer ML1' may be formed. The first through-hole VIA1 and the second through-hole VIA2 may be filled with the first metal layer ML1'. The first metal layer ML1' may contact the first through-hole VIA1 and the second through-hole VIA2.

[0234] Step S400, which involves etching the via layer to form the trench, may include forming a trench TCH' with a uniform height. The trench TCH' may be formed along the periphery of the intermediate region MA and may have a uniform height. For example, in the region where the trench TCH' is formed, the second via layer VIAL2 may be etched to a uniform thickness.

[0235] During the step of forming the charge generation layer CGL, the charge generation layer CGL can be formed. The charge generation layer CGL can be in physical contact with the first metal layer ML1' in the region superimposed with the trench TCH'.

[0236] The charge generation layer CGL can be cut off at the boundary surface of the separator wall PW. As a result, current cannot flow through the charge generation layer CGL between the first sub-pixel and the third sub-pixels SP1, SP2, and SP3.

[0237] Figure 21This is a schematic block diagram illustrating an electronic device 1000 including a display device according to an embodiment of the present disclosure. Figure 20 It is shown Figure 22 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 20 It is shown Figure 20 to Figure 22 The electronic device 1000 is a schematic diagram of an example of a tablet computer.

[0238] Reference Figure 1 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 21 The display device 100. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as... Figure 22 As shown, the electronic device 1000 can be a smartphone. In an embodiment, as... ​ As shown, electronic device 1000 may be a tablet computer. However, the foregoing example is illustrative, and electronic device 1000 is not necessarily limited to the foregoing example. For example, electronic device 1000 may be a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, head-mounted display device, etc.

[0239] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, etc. Processor 1010 can be connected to other components via an address bus, a control bus, a data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can provide input image data to display device 1060. Therefore, display device 1060 can display an image based on the input image data provided from processor 1010.

[0240] The memory device 1020 can store data required for performing operations of the electronic device 1000. The memory device 1020 can be used as working memory and / or buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0241] Storage device 1030 can store data in response to control signals or data from processor 1010. Storage device 1030 may include one or more non-volatile memories to retain data even when electronic device 1000 is powered off. In some embodiments, storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0242] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 1060 may be integrated with I / O device 1040.

[0243] Power supply 1050 can supply the power required to operate electronic device 1000. For example, power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, power supply 1050 can supply power to display device 1060.

[0244] The display device 1060 can display an image in response to image data signals and / or control signals from the processor 1010. The display device 1060 can be connected to other components via a bus or other communication link.

[0245] Embodiments of this disclosure can provide a display device, an electronic device, and a method of manufacturing a display device that can reduce leakage current between adjacent sub-pixels.

[0246] While various exemplary embodiments have been described above, those skilled in the art will appreciate that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure.

[0247] Therefore, the embodiments disclosed in this specification are provided for illustrative purposes and should not be considered as limiting the technical spirit of this disclosure.

Claims

1. A display device comprising: a pixel circuit layer; a via layer disposed on the pixel circuit layer, wherein the via layer comprises a trench; a first via hole and a second via hole passing through the via layer; a first metal layer electrically connected to the pixel circuit layer through the first via hole; an anode electrode disposed on the via layer; a first emission component disposed on the anode electrode; a charge generation layer disposed on the first emission component; and a second emission component disposed on the charge generation layer, wherein the pixel circuit layer comprises a transistor electrically connected to an initialization voltage node, wherein the initialization voltage node is configured to transmit an initialization voltage, and wherein the transistor is electrically connected to the charge generation layer through the first metal layer.

2. The display device of claim 1, further comprising a separation wall disposed on the first metal layer, wherein the separation wall comprising: a first separation wall layer; and a second separation wall layer disposed on the first separation wall layer, wherein the second separation wall layer is wider than the first separation wall layer in a direction parallel to a surface of the pixel circuit layer.

3. The display device of claim 2, wherein the trench comprises a first trench and a second trench, and wherein a height of the first trench is less than a height of the second trench.

4. The display device of claim 3, further comprising: a second metal layer electrically connected to the pixel circuit layer through the second via hole; and a cathode electrode disposed on the second emission component, wherein the second metal layer is in contact with the cathode electrode in a region adjacent to or superposed with the second trench.

5. The display device of claim 4, the first metal layer and the second metal layer are disposed in a same plane, wherein, wherein the first separation wall is in contact with the first metal layer, and wherein an upper surface of each of the first emission component, the charge generation layer, and the second emission component has a stepped portion. the first metal layer is in contact with the charge generation layer in a region adjacent to or superposed with the first trench.

6. The display device according to claim 4, wherein the charge generation layer is not in contact with the second metal layer.

7. The display device according to claim 4, wherein 8. The display device of claim 1, the first metal layer is in contact with the charge generation layer in a first contact region, and wherein, wherein, in a plan view, the first contact region is spaced apart from the anode electrode and encloses at least a portion of a periphery of the anode electrode.

9. The display device of claim 8, further comprising: a second metal layer electrically connected to the pixel circuit layer through the second via hole; and a cathode electrode disposed on the second emission component, wherein the cathode electrode is in contact with the second metal layer in a second contact region, and wherein, in a plan view, the second contact region encloses at least a portion of the periphery of the anode electrode. the first metal layer is a single layer comprising titanium or a multi-layer comprising at least one of titanium, aluminum, copper, and molybdenum titanium. a side surface of the anode electrode is positively tapered.

10. The display device according to claim 1, wherein ​ 11. The display device according to claim 1, wherein ​ 12. The display device according to claim 1, further comprising a display area provided with a pixel including a first sub-pixel and a second sub-pixel, wherein the display device is an active area aperture display device, and an aperture is formed in the display area, and wherein the charge generation layer is not electrically connected between the first sub-pixel and the second sub-pixel.

13. The display device according to claim 1, wherein the first metal layer is electrically connected to the pixel circuit layer through the second via hole, wherein the first metal layer is in contact with the charge generation layer in a contact area, wherein the contact area, in a plan view, encloses a first portion of a periphery of the anode electrode and does not enclose a second portion of the periphery of the anode electrode.

14. A method of manufacturing a display device, the method comprising: forming a pixel circuit layer including a transistor; forming a via hole layer on the pixel circuit layer; forming a first via hole and a second via hole in the via hole layer; forming a first metal layer; forming a trench by etching the via hole layer; forming an anode electrode on the via hole layer; and forming an emission structure on the anode electrode, wherein the step of forming the emission structure includes forming a first emission component on the anode electrode, forming a charge generation layer on the first emission component, and forming a second emission component on the charge generation layer, wherein the transistor includes an initialization transistor electrically connected to an initialization voltage node, wherein the initialization voltage node is configured to transmit an initialization voltage, wherein the step of forming the charge generation layer includes bringing the charge generation layer into contact with the first metal layer, and wherein the charge generation layer is electrically connected to the initialization transistor. forming a separation wall on the first metal layer, 15. The method of claim 14, further comprising: wherein the step of forming the separation wall includes: forming a first separation wall layer; and forming a second separation wall layer on the first separation wall layer, and wherein the second separation wall layer is wider than the first separation wall layer.

16. The method according to claim 15, the step of forming the trench includes forming a first trench and a second trench, and wherein wherein the step of forming the first trench and the second trench includes etching the via hole layer such that a height of the first trench is less than a height of the second trench.

17. The method according to claim 16, further comprising: forming a second metal layer; and forming a cathode electrode on the second emission component, wherein the second metal layer is electrically connected to the pixel circuit layer through the second via hole, wherein the first metal layer and the second metal layer are formed in the same process, wherein the step of forming the cathode includes bringing the cathode into contact with the second metal layer, and wherein the second metal layer is electrically connected to a line configured to supply a cathode voltage.

18. The method according to claim 17, each of the first metal layer and the second metal layer is a single layer including titanium or a multi-layer including at least one of titanium, aluminum, copper, and molybdenum titanium, and ​ wherein, ​ The anode electrode has a positive tapering side surface.

19. The method of claim 14, wherein The first metal layer is electrically connected to the pixel circuit layer through the second via hole, and In a plan view, an area where the charge generation layer contacts the first metal layer surrounds at least part of a periphery of the anode electrode.

20. An electronic device comprising: a processor configured to provide input image data; and a display device configured to display an image based on the input image data, wherein the display device comprises: a pixel circuit layer; a via hole layer disposed on the pixel circuit layer, wherein the via hole layer comprises a trench; a first via hole and a second via hole passing through the via hole layer; a first metal layer electrically connected to the pixel circuit layer through the first via hole; an anode electrode disposed on the via hole layer; a first emission component disposed on the anode electrode; a charge generation layer disposed on the first emission component; and a second emission component disposed on the charge generation layer, wherein the pixel circuit layer comprises: a transistor electrically connected to an initialization voltage node, wherein the initialization voltage node is configured to transmit an initialization voltage, and wherein the transistor is electrically connected to the charge generation layer through the first metal layer.

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