Method of manufacturing display panel, display panel manufactured by using the method, and electronic device including the display panel

Abstract

A method of manufacturing a display panel, a display panel manufactured by using the method, and an electronic device including the display panel are provided. The method comprises the following steps: forming a display layer on a first surface of a substrate, wherein the substrate is provided with the first surface and a second surface which are opposite to each other; etching a second surface of the substrate to reduce a thickness of the substrate and removing a portion of the substrate corresponding to the hole forming region to form a first hole in the substrate; forming the polarizing layer in such a manner that the display layer is interposed between the polarizing layer and the substrate to position the polarizing layer to correspond to the entire surface of the display layer; and forming a second hole bonded to the first hole by removing a portion of the polarizing layer corresponding to an edge of the hole forming region and a portion of the display layer corresponding to an edge of the hole forming region.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0121801, filed on September 6, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0171449, filed on November 26, 2024, with the entire disclosure of each of the Korean Patent Applications incorporated herein by reference. Technical Field

[0002] One or more aspects of embodiments of this disclosure relate to a method of manufacturing a display panel, a display panel manufactured using the method, and an electronic device including the display panel. For example, it relates to a method of manufacturing a display panel with a low defect rate, a display panel manufactured using the method, and an electronic device including the display panel. Background Technology

[0003] Display panels of electronic devices such as televisions, monitors, smartphones, and / or tablet PCs include a display area and a peripheral area outside the display area. In electronic devices that include such display panels, a relatively larger display area is desired or required, and one or more suitable functions are added to the electronic device. Therefore, research is underway on display panels capable of including or incorporating one or more suitable components within the display area, and on electronic devices that include such display panels. Summary of the Invention

[0004] The problem with comparable display panels and electronic devices including such comparable display panels is that defects frequently occur during the manufacturing process or during the use of the display panels or electronic devices.

[0005] One or more aspects of embodiments of this disclosure relate to a method of manufacturing a display panel having a low defect rate, a display panel manufactured using the method, and an electronic device including the display panel.

[0006] However, it should be noted that these objectives are merely examples, and the scope of the invention is not limited to the aspects mentioned herein. Rather, other objectives of one or more embodiments of this disclosure will be apparent to those skilled in the art from the following description.

[0007] Additional aspects of one or more embodiments will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosed embodiments.

[0008] According to one or more embodiments, a method of manufacturing a display panel includes the following steps: disposing a display layer on a first surface of a substrate having a first surface and a second surface opposite to each other (back to back); etching the second surface of the substrate to reduce the thickness of the substrate and removing a portion of the substrate corresponding to a hole forming region to form a first hole in the substrate; disposing a polarizing layer such that the display layer is placed between a polarizing layer and the substrate to position the polarizing layer corresponding to the entire surface of the display layer; and disposing a second hole bonded to the first hole by removing portions of the polarizing layer and portions of the display layer, each of the portions of the polarizing layer and the display layer corresponding to the edge of the hole forming region.

[0009] The method may further include the following steps: setting scratches in the substrate to correspond to the edge of the hole forming region, wherein the step of etching a second surface of the substrate includes etching the second surface of the substrate such that an etchant penetrates the scratches to remove the portion of the substrate corresponding to the hole forming region.

[0010] The step of setting the second hole may include irradiating the portion of the polarization layer corresponding to the edge of the hole formation region with a laser beam.

[0011] The step of setting the second hole may include irradiating a portion of the polarization layer with a laser beam until a portion (location) of the first surface of the substrate corresponding to the edge of the hole-forming region is exposed.

[0012] The method may further include the following steps: providing a bottom protective layer that covers the lower surface of the display layer exposed by the first hole, the second surface of the substrate, and the inner surface of the first hole.

[0013] The step of setting the second hole may include irradiating a laser beam such that a portion of the bottom protective layer is removed from the inner surface of the first hole.

[0014] The step of creating the second hole may include irradiating a laser beam such that a portion of the bottom protective layer on the second surface of the substrate is removed to expose the portion of the second surface of the substrate surrounding the first hole.

[0015] According to one or more embodiments, a display panel includes: a substrate having a first surface and a second surface opposite to the first surface (e.g., the first and second surfaces may be back-to-back with each other) and having a first hole through the first and second surfaces; and a display layer and a polarizing layer on the display layer, the display layer and the polarizing layer being above the first surface of the substrate and having a second hole, wherein the second hole overlaps with the first hole when viewed from a direction perpendicular to the substrate, wherein the inner surface of the second hole is a continuous surface up to the first surface of the substrate without steps, and the portion of the first surface between the display layer and the first hole does not include an organic film (e.g., there is no organic film on the first surface of the substrate between the display layer and the first hole).

[0016] The area of ​​the second aperture on the lower surface of the polarization layer in the direction towards the display layer can be equal to the area of ​​the second aperture on the upper surface of the display layer in the direction towards the polarization layer.

[0017] The second hole can be constructed as part of the first surface of the substrate.

[0018] The portion of the first surface of the substrate exposed by the second hole may be around the first hole (around the first hole).

[0019] The display panel may also include a bottom protective layer on a second surface of the substrate and having a third hole corresponding to the first hole.

[0020] The area of ​​the third hole can be larger than the area of ​​the first hole.

[0021] The area of ​​the third hole on the upper surface of the bottom protective layer in the direction facing the substrate can be equal to the area of ​​the second hole on the lower surface of the display layer in the direction facing the substrate.

[0022] When viewed from a direction perpendicular to the substrate, the edge of the third hole can overlap with the edge of the second hole on the lower surface of the display layer in the direction facing the substrate.

[0023] The edge of the third hole in the bottom protective layer may include a thermally deformable portion.

[0024] The edge of the second hole in the polarization layer may include a thermally deformable portion.

[0025] According to one or more embodiments, an electronic device includes a display panel, a camera, and a bottom cover, wherein the display panel includes: a substrate having a first surface and a second surface opposite to the first surface (e.g., the first and second surfaces are back-to-back with each other), and having a first hole through the first and second surfaces; a display layer and a polarizing layer on the display layer, the display layer and the polarizing layer being above the first surface of the substrate and having a second hole, the second hole overlapping the first hole when viewed from a direction perpendicular to the substrate, wherein the inner surface of the second hole is a continuous surface up to the first surface of the substrate without steps, the portion of the first surface between the display layer and the first hole does not include an organic film (e.g., there is no organic film on the first surface of the substrate between the display layer and the first hole), and the camera is located between the display panel and the bottom cover.

[0026] The area of ​​the second aperture on the lower surface of the polarization layer in the direction towards the substrate can be equal to the area of ​​the second aperture on the upper surface of the display layer in the direction towards the polarization layer.

[0027] The second hole can be constructed as part of the first surface of the substrate.

[0028] The portion of the first surface of the substrate exposed by the second hole may be around the first hole (around the first hole).

[0029] The electronic device may also include a bottom protective layer on a second surface of the substrate and having a third hole corresponding to the first hole.

[0030] The area of ​​the third hole can be larger than the area of ​​the first hole.

[0031] The area of ​​the third hole is equal to the area of ​​the second hole on the lower surface of the display layer in the direction facing the substrate.

[0032] When viewed from a direction perpendicular to the substrate, the edge of the third hole can overlap with the edge of the second hole on the lower surface of the display layer in the direction facing the substrate.

[0033] The edge of the third hole in the bottom protective layer may include a thermally deformable portion.

[0034] The edge of the second hole in the polarization layer includes a thermally deformed portion.

[0035] Other aspects and features beyond those described herein will become apparent from the published drawings, claims, and detailed description. Attached Figure Description

[0036] The accompanying drawings are included to provide a further understanding of the foregoing and other aspects and features of certain embodiments disclosed, and the drawings are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments that will become clearer from the following description taken in conjunction with the drawings. In the drawings: Figure 1 It is a perspective view schematically showing an electronic device according to one or more embodiments; Figure 2 It is shown schematically. Figure 1 An exploded perspective view of an electronic device; Figure 3 It is shown schematically. Figure 1 A block diagram of an electronic device; Figure 4 This is a schematic plan view of a display panel according to one or more embodiments; Figure 5 It is shown schematically. Figure 4 A side view of the display panel; Figure 6 It is schematically shown along Figure 4 A sectional view of the display panel cut by line A-A'; Figures 7 to 14 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the manufacturing process of the display panel; Figure 15 It is an illustrative representation of including Figure 1 A plan view of the display panel in an electronic device; Figure 16 Is included Figure 15 The equivalent circuit diagram of the pixel circuit in the display panel where electricity is connected to the light-emitting diode; Figure 17 It is shown schematically. Figure 15 A floor plan of a portion of the display panel; Figure 18 It is schematically shown along Figure 17 A sectional view of the display panel taken by line B-B'; and Figure 19 It is a schematic cross-sectional view showing a portion of a display panel according to one or more embodiments. Detailed Implementation

[0037] Referring now to embodiments in more detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Therefore, embodiments are described herein only by reference to the accompanying drawings to explain aspects of embodiments of this specification.

[0038] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b and c” means only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all of a, b and c, or variations thereof.

[0039] Because the disclosure allows for one or more suitable modifications and numerous embodiments, exemplary embodiments will be shown in the accompanying drawings and described in more detail in the written description. The effects and features of the disclosure, as well as the methods of implementing it, will be apparent from the embodiments and drawings described in detail herein. However, the subject matter of the disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0040] In the following description, the disclosed embodiments will be described in more detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding components are indicated by the same reference numerals, and their redundant descriptions may be omitted.

[0041] In the embodiments below, when an element such as a layer, film, region, or plate is referred to as being "on" another element, the element may be directly on the other element, or there may be an intervening element between them. Furthermore, for ease of description, the dimensions of the elements in the figures may be exaggerated or reduced. For example, because the dimensions and thicknesses of the elements in the figures may be arbitrarily shown for ease of description, the embodiments below are not limited thereto.

[0042] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0043] In the embodiments described below, although terms such as “first” and “second” are used to describe one or more suitable elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another.

[0044] In the embodiments described below, terms such as “comprising,” “including,” “having,” and variations thereof indicate the presence of the stated features or elements, but do not preclude the presence or addition of one or more other features or elements. Unless clearly indicated otherwise in the context, singular expressions such as “a,” “an,” and “the” include plural expressions.

[0045] In this specification, the expression "A and / or B" means A, B, or A and B. Furthermore, the expression "at least one of A and B (species / beings)" means A, B, or A and B.

[0046] In the following embodiments, when a layer, region, or element is referred to as "bonded to" or "connected to" another layer, region, or element, that layer, region, or element may be directly or indirectly bonded to or connected to said other layer, region, or element. For example, an intermediary layer, region, or element may be present. For example, when a layer, region, or element is referred to as "electrically connected to" or "electrically bonded to" another layer, region, or element, that layer, region, or element may be directly or indirectly electrically connected to or electrically bonded to said other layer, region, or element. For example, an intermediary layer, region, or element may be present.

[0047] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “bottom,” and / or “top” are used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another (other) element or feature. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “under” another element or feature would subsequently be positioned “above” or “above” said other element or feature. Thus, the term “below” can encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0048] Unless otherwise defined, all terms used in this specification (including chemical, technical, and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0049] The term “may” will be understood to refer to “one or more embodiments of this disclosure,” some of which include the described elements, and some of which exclude the element and / or include optional elements. Similarly, optional language such as “or” refers to “one or more embodiments of this disclosure,” each including the corresponding listed item.

[0050] As used herein, the phrase “consisting essentially of” means that any additional components will not substantially affect the chemical, physical, optical, or electrical properties of the semiconductor film.

[0051] In the following description, a display panel and an electronic device according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0052] electronic devices Figure 1 This is a schematic perspective view of an electronic device 1 according to one or more embodiments. Figure 2 It is shown schematically. Figure 1 An exploded perspective view of electronic device 1, and Figure 3 It is shown schematically. Figure 1 Block diagram of electronic device 1.

[0053] Reference Figure 1 and Figure 2The electronic device 1, as a means for displaying moving and / or still images, can be a portable electronic device (such as a mobile phone, smartphone, tablet PC, mobile communication terminal, e-notebook, e-reader, portable multimedia player (PMP), navigation and / or ultra-mobile PC (UMPC)) and / or can be a variety of suitable products (such as a television, laptop computer, monitor, billboard and / or Internet of Things (IoT) device). The electronic device 1 according to one or more embodiments can also be a wearable device (such as a smartwatch, watch phone, glasses-type display and / or head-mounted display (HMD)). The electronic device 1 according to one or more embodiments can also be a vehicle's instrument cluster, a central information display (CID) on the vehicle's central instrument panel and / or dashboard, an interior mirror display replacing the vehicle's side mirrors, and / or a display behind the front seats serving as an entertainment device for rear-seat passengers.

[0054] exist Figure 1 and Figure 2 In this context, for ease of description, electronic device 1 according to one or more embodiments is shown as a smartphone. Electronic device 1 may include a cover window 70, a display panel 10, a data driver 20, a display circuit board 30, a component 40, a bracket 60, a main circuit board 50, a battery 80, and / or a bottom cover 90.

[0055] In the plan view of this specification, "left", "right", "up" and "down" indicate the directions when viewing the display panel 10 from a direction perpendicular to the display panel 10. For example, "left" represents the -x direction, "right" represents the +x direction, "up" represents the +y direction, and "down" represents the -y direction.

[0056] Electronic device 1 can appear to have a roughly rectangular shape in a plan view. For example, as shown... Figure 1 As shown, electronic device 1 can have a generally rectangular shape in the xy-plane, having a short side in the x-axis direction and a long side in the y-axis direction. The corners where the short side in the x-axis direction and the long side in the y-axis direction meet can be rounded to have a set or specific curvature, or set at right angles (e.g., formed as right angles). The planar shape of electronic device 1 is not limited to a rectangle, and can include other polygonal, elliptical, or irregular shapes.

[0057] The cover window 70 can be placed above the display panel 10 to cover the upper surface of the display panel 10. The cover window 70 can protect the upper surface of the display panel 10.

[0058] The cover window 70 may include a transparent cover unit DA 70 corresponding to the display panel 10 and a light-shielding cover unit NDA 70 surrounding the transparent cover unit DA 70. Light from the display area DA of the display panel 10 can pass through the transparent cover unit DA 70 and travel to the outside. The light-shielding cover unit NDA 70 may include an opaque material (e.g., a colored opaque material) that blocks light (or reduces light transmission). The light-shielding cover unit NDA 70 may include a pattern visible to the user when no image is displayed.

[0059] Covering window 70 may include glass and / or plastic. If covering window 70 includes glass, it may include ultra-thin glass. If covering window 70 includes plastic, it may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate.

[0060] Display panel 10 may be located below cover window 70. Display panel 10 may be stacked with transparent cover unit DA 70 of cover window 70. Display panel 10 may include display area DA. Display area DA is an area where an image can be displayed. Display area DA may include an area (hereinafter, component area) that transmits light emitted from component 40 or camera 531 below display panel 10 or transmits light traveling toward component 40 or camera 531. In embodiments, display area DA may be considered to be outside component area to surround component area. Component 40 may include sensors using visible light, infrared light, and / or sound, etc.

[0061] The opening area OA can be located within the display area DA. The opening area OA can be a substrate 100 included in the display panel 10 (see...). Figure 6 and Figure 18 The opening (e.g., by the base 100 included in the display panel 10) is located in the display panel 10. Figure 6 and Figure 18 (The opening is limited). For example, Figure 2 As shown, the opening region OA may be (e.g., located) at the upper center of the display region DA, and the display region DA outside the opening region OA may have a shape surrounding the opening region OA. In one or more embodiments, the opening region OA may be located within the display region DA in one or more suitable ways (such as at (e.g., located) the upper left portion or the upper right portion of the display region DA). Although Figure 2 An opening region OA is shown within the display region DA, but the display panel 10 may have multiple opening regions OA.

[0062] The component area described here may be or includes such an opening area OA. Figure 2 The location of the opening area OA is shown to correspond to the location of the camera 531 below the display panel 10. For example, in a plan view, the opening area OA may be superimposed on the camera 531. In one or more embodiments, if desired, the location of the opening area OA may correspond to the location of at least a portion of component 40. For example, in a plan view, the opening area OA may be superimposed on at least one of the first component 41, second component 42, third component 43, and fourth component 44 included in component 40. Hereinafter, for ease of description, the location of the opening area OA is described as corresponding to the location of the camera 531 below the display panel 10.

[0063] The intermediate region MA, which can be referred to as the first region, can be located between the display region DA and the opening region OA. For example, the intermediate region MA, which can be referred to as the first region, can be located outside the opening region OA. In a plan view, the intermediate region MA can have a closed loop shape that completely surrounds the opening region OA. The display region DA can be referred to as the second region outside the first region.

[0064] Display panel 10 can be a light-emitting display panel including light-emitting diodes (LEDs). The LEDs can be organic light-emitting diodes (OLEDs) including an organic light-emitting layer (organic emission layer) and / or inorganic light-emitting diodes including inorganic materials. Inorganic light-emitting diodes can include PN diodes containing inorganic semiconductor materials. When a voltage is applied to a PN junction diode in the forward direction, holes and electrons can be injected, and the energy generated by the recombination of holes and electrons can be converted into light energy, thereby emitting light of a set or specific color. The inorganic light-emitting diodes described herein can have widths ranging from a few micrometers to hundreds of micrometers. Inorganic light-emitting diodes can be referred to as micro-light-emitting diodes (LEDs).

[0065] The display panel 10 can be a rigid display panel that is not easily bent or a flexible display panel that is easily bent, folded and / or rolled. For example, the display panel 10 can be a foldable display panel, a curved display panel with a curved display surface, a bent display panel in which the area other than the display surface is bent, a rollable display panel that can be rolled and / or unfolded, and / or a stretchable display panel.

[0066] Display panel 10 may be a transparent display panel that allows objects or backgrounds behind display panel 10 to be visible from the front of display panel 10. In embodiments, display panel 10 may be a reflective display panel capable of reflecting light from objects in front of display panel 10 or light from the background behind display panel 10.

[0067] The data driver 20 may be mounted on the display panel 10 as an integrated circuit (IC). In another embodiment, the data driver 20 may be mounted on the display circuit board 30.

[0068] The display circuit board 30 may be located on one side of the display panel 10 (e.g., fixed to one side of the display panel 10). The display circuit board 30 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) that is not easily bent, or a composite printed circuit board comprising both an FPCB and a rigid PCB (e.g., comprising both an FPCB and a rigid PCB). A touch sensor driving unit may be mounted on the display circuit board 30. The touch sensor driving unit may be configured (e.g., formed) as an IC. The touch sensor driving unit may be electrically coupled to the touch electrodes of the touchscreen layer of the display circuit board 30 via the display circuit board 30.

[0069] The touchscreen layer of the display panel 10 can detect user touch input by using at least one or more suitable touch methods, such as resistive film method and electrostatic capacitance method. When the touchscreen layer of the display panel 10 detects user touch input in electrostatic capacitance manner, the touch sensor driving unit can apply a driving signal to the driving electrode of the touch electrode and detect the voltage charged in the mutual electrostatic capacitance (hereinafter referred to as "mutual capacitance") between the driving electrode and the sensing electrode of the touch electrode to determine whether the user touch has been received.

[0070] User touches can include contact touches and proximity touches. A contact touch indicates that the user's finger or an object such as a pen is in direct contact with the overlay window 70 on the touchscreen layer. A proximity touch indicates that the user's finger or an object such as a pen is positioned near the overlay window 70, such as hovering. The touch sensor driving unit can send sensor data to the main processor 510 based on the detected voltage, and the main processor 510 can analyze the sensor data and calculate the touch coordinates of the touch input.

[0071] The control unit, gate driver, and data driver 20 that supply the driving voltage for driving the pixels of the display panel 10 can be on the display circuit board 30.

[0072] A bracket 60 for supporting the display panel 10 may be located below the display panel 10. The bracket 60 may comprise plastic, metal, or both. The bracket 60 may have a first camera hole CMH1, a battery hole BH, a cable hole CAH, and a component hole CPH corresponding to component 40. A camera 531 is inserted into the first camera hole CMH1, a battery 80 is disposed in the battery hole BH, and a cable connected to the display circuit board 30 passes through the cable hole CAH. When viewed from a third-party direction (z-axis direction), the component hole CPH may overlap with component 40 of the main circuit board 50. For reference, when viewed from a third-party direction (z-axis direction), the display area DA of the display panel 10 may overlap with component 40 of the main circuit board 50. In another embodiment, the bracket 60 may not have the component hole CPH.

[0073] Component 40 of electronic device 1 may include a first component 41, a second component 42, a third component 43, and a fourth component 44 stacked with display panel 10. Each of the first component 41, the second component 42, the third component 43, and the fourth component 44 may include at least one selected from a proximity sensor, an illuminance sensor, an iris sensor, a facial recognition sensor, and a camera (or image sensor). A proximity sensor using infrared light can detect objects approaching the upper surface of electronic device 1, and an illuminance sensor can detect the brightness of light incident on the upper surface of electronic device 1. In some embodiments, an iris sensor can capture an image of the iris of a person above the upper surface of electronic device 1, and a camera can capture an image of an object above the upper surface of electronic device 1. Component 40 is not limited to proximity sensors, illuminance sensors, iris sensors, facial recognition sensors, and cameras, and may include one or more suitable sensors.

[0074] The main circuit board 50 and the battery 80 can be located below the bracket 60. The main circuit board 50 can be a rigid printed circuit board or an FPCB.

[0075] The main circuit board 50 may include a main processor 510, a camera 531, a main connector 55, and component 40. The main processor 510 may be configured (e.g., formed) as an IC. When necessary or desired, the electronic device 1 may include not only the camera 531 above the upper surface of the main circuit board 50, but also a camera below the lower surface of the main circuit board 50. Each of the main processor 510 and the main connector 55 may be on either the upper or lower surface of the main circuit board 50. The main circuit board 50 may be electrically coupled to the display circuit board 30 via the main connector 55.

[0076] The main processor 510 can control all functions of the electronic device 1. For example, the main processor 510 can output digital video data to the data driver 20, so that the image is displayed on the display panel 10. The main processor 510 can receive input sensing data from the touch sensor driver unit. The main processor 510 can determine whether a user touch has been received based on the sensing data, and perform operations corresponding to the user's direct touch and / or proximity touch. The main processor 510 can be an application processor, a central processing unit, and / or a system-on-a-chip, each of which includes an IC.

[0077] Camera 531 can process image frames such as still images and / or moving images obtained by an image sensor in camera mode, and output the processed image frames to main processor 510. Camera 531 may include at least one selected from camera sensors (e.g., charge-coupled devices (CCDs) and / or complementary metal-oxide-semiconductor (CMOSs), light sensors (or image sensors), and laser sensors.

[0078] A cable passing through the cable hole CAH defined in the bracket 60 can be coupled to the main connector 55, so that the main connector 55 can be electrically coupled to the display circuit board 30.

[0079] Electronic device 1 can be made of, for example Figure 3 The block diagram shown illustrates that electronic device 1 can be represented as including, in addition to the main processor 510, [other components]. Figure 3 The wireless communication unit 520, input unit 530, sensor unit 540, output unit 550, interface unit 560, memory 570 and / or power supply unit 580 shown are included.

[0080] The wireless communication unit 520 may include at least one of the following: a broadcast receiving module 521, a mobile communication module 522, a wireless internet module 523, a short-range communication module 524, and a location information module 525.

[0081] The broadcast receiving module 521 can receive broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include satellite channels and terrestrial channels.

[0082] Mobile communication module 522 can transmit and receive radio signals to at least one of the following: an external terminal, a server on a mobile communication network, and a base station established according to technical standards or communication methods used for mobile communication (e.g., Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA2000), Enhanced Voice Data Optimized or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and LTE-A Advanced (LTE-A)). The radio signals may include one or more suitable forms of data, such as voice call signals, video call signals, and / or data transmitted and received according to text / multimedia messages.

[0083] Wireless Internet module 523 is a module for wireless Internet connectivity. Wireless Internet module 523 can be configured to transmit and receive wireless signals in a communication network according to wireless Internet technologies. Wireless Internet technologies may include, for example, Wireless LAN (WLAN), Wi-Fi, Wi-Fi Direct, and / or Digital Living Network Alliance (DLNA).

[0084] The short-range communication module 524, which ensures short-range communication, can support short-range communication by using at least one of the following technologies: Bluetooth, Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra-Wideband (UWB), Internet of Things (ZigBee), Near Field Communication (NFC), Wi-Fi, Wi-Fi Direct, and Wireless Universal Serial Bus (USB). The short-range communication module 524 can support wireless communication between electronic device 1 and a wireless communication system, between electronic device 1 and another electronic device, or between electronic device 1 and the network where another electronic device (or an external server) resides, via a wireless local area network (WLAN). The WLAN can be a wireless personal area network (WPAN). The other electronic device can be a wearable device capable of exchanging data with (or linking to) electronic device 1.

[0085] The location information module 525, which is a module for obtaining the location (or current location) of electronic device 1, may include a global positioning system (GPS) module and / or a Wi-Fi module.

[0086] Input unit 530 may include an image input unit such as camera 531 for inputting image signals, an audio input unit such as microphone 532 for inputting audio signals, and an input device 533 for receiving information from a user. Camera 531 can process image frames (such as still images and / or moving images) acquired by an image sensor in video call mode and / or shooting mode. The processed image frames can be displayed on display panel 10 or stored in memory 570. Microphone 532 can process external audio signals into electroacoustic data. The processed audio data can be used differently depending on the function being performed (or the application being run) in electronic device 1.

[0087] The main processor 510 can control the operation of the electronic device 1 to correspond to information received via the input device 533. The input device 533 may include mechanical input components (such as buttons, dome switches, scroll wheels, or scroll wheel switches located on the rear or side surface of the electronic device 1) and / or touch input components. The touch input components may include the touch screen layer of the display panel 10.

[0088] Sensor unit 540 may include one or more sensors configured to sense at least one of information within electronic device 1, information about the surrounding environment of electronic device 1, and user information, and generate corresponding sensing signals. Based on the sensing signals, main processor 510 may control the driving and / or operation of electronic device 1 and / or perform data processing, functions, and / or operations associated with applications installed in electronic device 1. Sensor unit 540 may be a proximity sensor, illuminance sensor, and / or facial recognition sensor as described herein with respect to component 40. Sensor unit 540 may include an accelerometer, magnetic sensor, G-sensor, gyroscope sensor, motion sensor, RGB sensor, infrared (IR) sensor, finger scanning sensor, ultrasonic sensor, optical sensor, and / or battery level sensor. In some embodiments, sensor unit 540 may include environmental sensors and / or chemical sensors. Environmental sensors may include, for example, barometers, hygrometers, thermometers, radiation detection sensors, thermal detection sensors, and / or gas detection sensors. Chemical sensors may include, for example, electronic noses, healthcare sensors, and / or biometric sensors.

[0089] The output unit 550 can generate outputs associated with vision, hearing and touch, and may include at least one of the display panel 10, audio output unit 551, haptic module 552 and optical output unit 553.

[0090] Display panel 10 can be configured to display (or output) information processed in electronic device 1. For example, display panel 10 can be configured to display execution screen information of an application driven in electronic device 1 and / or display user interface (UI) and / or graphical user interface (GUI) information based on the execution screen information. Display panel 10 may include a display layer for displaying images and a touch screen layer for detecting user touch input. Therefore, display panel 10 can be used as one of the input devices 533 that provide an input interface between electronic device 1 and the user, and can also be used as an output unit 550 that provides an output interface between electronic device 1 and the user.

[0091] The audio output unit 551 can output audio data received from the wireless communication unit 520 or stored in the memory 570 in call signal receiving mode, call mode or recording mode, voice recognition mode and / or broadcast receiving mode, etc. The audio output unit 551 can output audio signals associated with functions performed in the electronic device 1 (such as call signal receiving sound and / or message receiving sound, etc.). The audio output unit 551 may include a receiver and / or a speaker. At least one of the receiver and speaker may be a sound generating device attached below the display panel 10 and causing the display panel 10 to vibrate to output sound. The sound generating device may be a piezoelectric element and / or a piezoelectric actuator that contracts and expands in response to an electrical signal, and / or an exciter that generates magnetic force by using a voice coil and causes the display panel 10 to vibrate.

[0092] The haptic module 552 can generate one or more suitable haptic effects that can be felt by a user. The haptic module 552 can provide vibrations as haptic effects to the user. The haptic module 552 can transmit haptic effects not only through direct contact, but can also be implemented so that the user can feel the haptic effects through muscle sensation in their fingers and / or arms.

[0093] The optical output unit 553 can output a signal to notify the user of an event by using light from a light source. Examples of events occurring in the electronic device 1 may include receiving a message, receiving a call signal, receiving a missed call, an alarm, a schedule alarm, a schedule reminder, receiving an email, receiving information through an application, etc. The signal output from the optical output unit 553 can be implemented by the electronic device 1 emitting monochromatic or multi-colored light from its front or back. When the electronic device 1 detects the user's recognition of the event, it can terminate the signal output.

[0094] Interface unit 560 serves as a channel for connecting to one or more suitable types of external devices of electronic device 1. Interface unit 560 may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio input / output (I / O) port, a video I / O port, and a headphone port. When electronic device 1 is connected to an external device via interface unit 560, electronic device 1 can perform appropriate or suitable control associated with the connected external device.

[0095] Memory 570 may store data supporting one or more suitable functions of electronic device 1. Memory 570 may store multiple applications running on electronic device 1, data for the operation of electronic device 1, and instructions. At least some of the multiple applications may be downloaded from an external server via wireless communication. Memory 570 may store applications for the operation of main processor 510, or may temporarily store input / output data (e.g., such as a phone book, messages, still images, and / or moving images). In some embodiments, memory 570 may store tactile data for vibrations provided to tactile module 552 in one or more suitable modes, and audio data associated with one or more suitable sounds provided to audio output unit 551.

[0096] The memory 570 may include a storage medium selected from at least one type of flash memory, hard disk memory, solid-state drive (SSD) memory, silicon disk drive (SDD) memory, multimedia card micro memory, card memory (e.g., secure digital (SD) or extreme digital (XD) memory), random access memory (RAM), static RAM (SRAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), programmable ROM (PROM), magnetic storage, magnetic disk, and optical disk.

[0097] Under the control of the main processor 510, the power supply unit 580 can receive external power and / or internal power and supply power to each of the components included in the electronic device 1. The power supply unit 580 may include a battery 80. In some embodiments, the power supply unit 580 may have a connection port, and the connection port may be configured as an example of an interface unit 560 to which an external charger supplying power for battery charging is electrically connected. In embodiments, the power supply unit 580 may be configured to wirelessly charge the battery 80. The battery 80 may not be stacked with the main circuit board 50 in the third direction (z-axis direction). The battery 80 may be stacked with the battery hole BH of the bracket 60.

[0098] The lower cover 90 can form the external shape of the electronic device 1 and can have an opening that exposes a portion of the display panel 10. The lower cover 90 can be assembled with the display panel 10 such that the display area of ​​the display panel 10 is exposed through the opening in the lower cover 90. The lower cover 90 can be positioned such that the display panel 10 is positioned between the lower cover 90 and the cover window 70. The lower cover 90 can be located below the main circuit board 50 and the battery 80. The lower cover 90 can be fixed and secured to the bracket 60. The lower cover 90 can form the lower external shape of the electronic device 1. The lower cover 90 can include plastic, metal, or both plastic and metal.

[0099] A second camera aperture CMH2 may be provided (e.g., formed) in the lower cover 90, through which the lower surface of camera 531 is exposed. The position of camera 531 and the positions of the corresponding first camera aperture CMH1 and second camera aperture CMH2 are not limited to... Figure 1 and Figure 2 The embodiments shown are subject to various modifications. For example, camera 531 may be located between display panel 10 and lower cover 90. In some embodiments, when viewed from a direction perpendicular to display panel 10, camera 531 may be superimposed on the opening region OA of display region DA.

[0100] Figure 4 This is a schematic plan view of a display panel 10 according to one or more embodiments. Figure 5 It is shown schematically. Figure 4 A side view of the display panel 10. The electronic device 1 described herein may include... Figure 4 and Figure 5 The display panel 10 shown in the image.

[0101] Display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the portion in which an image is displayed, and multiple pixels may be present in the display area DA. The display area DA may have one or more suitable shapes (such as circles, ellipses, polygons, and / or defined or specific shapes). Figure 4 The display area DA is shown to have a roughly rectangular shape with rounded edges.

[0102] The peripheral region PA can be located outside the display region DA. The portion of the peripheral region PA located at the bottom of the display region DA and extending in the first direction (x-axis direction) may have a width in the first direction (x-axis direction) that is smaller than the width of the display region DA in the first direction (x-axis direction). This structure allows at least a portion of the peripheral region PA to be easily bent.

[0103] Figure 4The planar shape of the display panel 10 shown may be substantially the same as the shape of the substrate 100 included in the display panel 10. When describing the display panel 10 as including a display area DA and a peripheral area PA outside the display area DA, it may refer to the substrate 100 including the display area DA and the peripheral area PA outside the display area DA. Hereinafter, for ease of description, it is described that the substrate 100 includes the display area DA and the peripheral area PA.

[0104] Display panel 10 may include a main region MR, a curved region BR outside the main region MR, and a sub-region SR separated from or spaced apart from the main region MR (e.g., spaced apart or separated), with the curved region BR located between the main region MR and the sub-region SR. The main region MR may be located on one side of the curved region BR, and the sub-region SR may be located on the other side of the curved region BR. Figure 5 As shown, the display panel 10 can be bent in the curved region BR, and when viewed from a third direction (e.g., the z-axis direction), at least a portion of the sub-region SR can be superimposed on the main region MR. Figure 5 The illustration shows the display panel 10 bent; however, one or more embodiments are not limited to this. In another embodiment, the display panel 10 may not be bent. In this embodiment, the sub-region SR may be directly integrated into the main region MR. The sub-region SR may be a non-display area.

[0105] The data driver 20 can be located in a sub-region SR of the display panel 10. The data driver 20 can be located on the display panel 10 in the form of an IC. For example, the data driver 20 can be a data driver IC configured to generate data signals.

[0106] The display circuit board 30 can be fixed to the end of the sub-region SR of the display panel 10. The display circuit board 30 can be electrically bonded to the data driver 20, etc., via the pad (or "soldering pad") of the sub-region SR of the display panel 10.

[0107] See here for reference. Figure 2 As described, the display panel 10 may have an opening region OA located within the display area DA. Furthermore, the display panel 10 may have an intermediate region MA located between the display area DA and the opening region OA.

[0108] Figure 6 It is schematically shown along Figure 4 The cross-sectional view of the display panel 10, taken along line A-A'. For ease of explanation, Figure 6 Not only is the display panel 10 shown, but also the cover window 70 and the camera 531 are shown together. As described herein, the electronic device 1 may include the display panel 10 and the camera 531 located in the opening area 0A of the display panel 10.

[0109] The display panel 10 may include: a substrate 100 having a first surface and a second surface that are opposite to each other (e.g., back to back); a display layer DIL on the first surface, which is the upper surface of the substrate 100 (in the +z direction); a polarizing layer POL on the display layer DIL; and a bottom protective layer BPL on the second surface, which is the lower surface of the substrate 100.

[0110] The display layer (DIL) may include a display element (or light-emitting element) that emits light to display an image. The display element may include a light-emitting diode (such as an organic light-emitting diode including an organic emitting layer). In embodiments, the display element may be an inorganic light-emitting diode comprising inorganic materials. The inorganic light-emitting diode may include a PN diode comprising inorganic semiconductor materials. When a voltage is applied to the PN junction diode in the forward direction, holes and electrons can be injected, and the energy generated by the recombination of holes and electrons can be converted into light energy, thereby emitting light of a set or specific color. The aforementioned light-emitting diode may have a width of several micrometers to hundreds of micrometers or several nanometers to hundreds of nanometers.

[0111] One or more embodiments are not limited thereto. For example, the display layer DIL may include a quantum dot layer. For example, light generated from an emission layer included in the display layer DIL and having a wavelength belonging to a set or specific band can be converted into light of a preset wavelength by the quantum dot layer.

[0112] In addition to the display elements, the display layer (DIL) may also include driving circuitry for driving the display elements. The driving circuitry may include, for example, thin-film transistors and capacitors. The driving circuitry may be located below the display elements.

[0113] The Display Layer (DIL) may also include a touchscreen layer. The touchscreen layer included in the DIL can obtain coordinate information based on external inputs such as touch events. The touchscreen layer may include sensing electrodes (or touch electrodes) and signal lines (traces) electrically coupled to the sensing electrodes. The touchscreen layer can detect external input using mutual capacitance and / or self-capacitance.

[0114] The touchscreen layer included in the display layer (DIL) can be on top of the display element. The touchscreen layer can be directly disposed (e.g., formed) on the display element, or it can be disposed separately (e.g., formed) and then attached to the display element by an adhesive layer such as an optically transparent adhesive. In embodiments, the touchscreen layer can be disposed (e.g., formed) sequentially after the processes of setting the display element and the encapsulation layer protecting the display element, and in embodiments, the adhesive layer may not be placed between the touchscreen layer and the display element.

[0115] The polarization layer (POL) can have anti-reflective properties. If desired, a phase retardation layer can be placed between the polarization layer (POL) and the display layer (DIL). The phase retardation layer can be, for example, a λ / 4 waveplate. The phase retardation layer and the polarization layer (POL) can reduce the reflectivity of light (external light) incident from the outside through the cover window 70 toward the display panel 10. In the following description, when the display panel 10 includes a phase retardation layer, the polarization layer (POL) is considered to include the phase retardation layer.

[0116] A bottom protective layer (BPL) may be located on the lower surface of the substrate 100 (in the -z direction). The bottom protective layer BPL may comprise materials such as polyethylene terephthalate, polyethylene naphthalate, and / or polyimide. The bottom protective layer BPL may be used to protect the lower surface of the substrate 100. In an embodiment, the bottom protective layer BPL may be opaque. In an embodiment, a user can clearly view the image generated from the display layer DIL on the substrate 100. For this purpose, the bottom protective layer BPL may comprise an opaque material such as carbon black.

[0117] To improve the transmittance of the opening region OA, the display panel 10 may include a through-hole 10H. The through-hole 10H can penetrate the substrate 100, the display layer DIL, the polarizing layer POL, and the bottom protective layer BPL. For example, the substrate 100 may have a first hole H1, the display layer DIL and the polarizing layer POL may have a second hole H2 that overlaps with the first hole H1 when viewed from a direction perpendicular to the substrate 100, and the bottom protective layer BPL may have a third hole H3 that overlaps with the first hole H1 when viewed from a direction perpendicular to the substrate 100, thereby providing (e.g., forming) a through-hole 10H that penetrates the substrate 100, the display layer DIL, the polarizing layer POL, and the bottom protective layer BPL. In this case, the inner surface of the second hole H2 of the display layer DIL and the polarizing layer POL can be a continuous surface extending to the upper surface of the substrate 100 (in the +z direction). If the inner surface of the second hole H2 is a continuous surface extending to the upper surface of the substrate 100, it can be indicated that the inner surface of the second hole H2 does not have a step up to the upper surface of the substrate 100. For reference, a step may exist between the second aperture H2 of the display layer DIL and the polarizing layer POL and the first aperture H1 of the substrate 100. This will be described in more detail elsewhere here. In such a display panel 10, the organic film can be removed from the first surface, which is the upper surface of the substrate 100, between the display layer DIL and the first aperture H1 (e.g., there is no organic film on the first surface, which is the upper surface of the substrate 100, between the display layer DIL and the first aperture H1). This will also be described in more detail.

[0118] Cover window 70 may be on top of display panel 10. Cover window 70 may be attached to polarizing layer POL by means of an adhesive layer including an adhesive (such as optically clear adhesive). Cover window 70 may cover through hole 10H included in display panel 10.

[0119] The opening area OA can be the area where the through hole 10H of the display panel 10 is located. In response to the opening area OA, electronic components such as camera 531 or component 40 can be placed (in the -z direction of the display panel 10). For example, the electronic components can be superimposed on the opening area OA in a plan view. Figure 6 The camera 531 is shown to be positioned corresponding to the opening area OA as described herein. If necessary or desired, at least a portion of the camera 531 may be positioned within the through-hole 10H of the display panel 10.

[0120] Methods for manufacturing display panels Figures 7 to 14 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the steps of the display panel 10.

[0121] The substrate 100 has a suitable or sufficient thickness and has a first surface and a second surface that are opposite to each other (e.g., back-to-back). A display layer DIL is disposed (e.g., formed) on the first surface, which is the upper surface of the substrate 100 (in the +z direction). The substrate 100 may include a glass substrate. A temporary protective layer TPL may be disposed (e.g., formed) on the upper surface of the display layer DIL in a direction away from the substrate 100 (in the +z direction) to protect the upper surface of the display layer DIL. The temporary protective layer TPL may be disposed (e.g., formed) using inkjet printing and / or spin coating methods. The temporary protective layer TPL may include polyethylene terephthalate, polyethylene naphthalate, and / or polyimide. In embodiments, the temporary protective layer TPL may be pre-disposed (e.g., formed) in the form of a flat sheet using the materials mentioned herein, and then bonded (e.g., attached) to the display layer DIL using an adhesive.

[0122] Then, as Figure 8 As shown, scratches are provided (e.g., formed) inside the substrate 100. Figure 8 Dashed lines represent scratches that are set (e.g., formed) within the substrate 100. The area where the first hole H1 described here is set (e.g., formed) can be referred to as the hole-forming region. The portion of the substrate 100 where the scratches are set (e.g., formed) can correspond to the edge of the hole-forming region. Because Figure 8This is a cross-sectional view, so the portion of the substrate 100 where a scratch is formed is indicated by two dashed lines. However, the scratches can be approximately uniformly formed in the substrate 100 to correspond to the edges of the hole-forming region. Scratches can be formed by irradiating the substrate 100 with a laser beam. For example, by focusing a laser beam on the portion of the substrate 100 where a scratch is to be formed and then irradiating that portion, a scratch can be formed at that location on the substrate 100.

[0123] After creating scratches within the substrate 100 in this manner, a second surface of the substrate 100, serving as the lower surface of the substrate 100 (in the -z direction), can be etched to reduce the thickness of the substrate 100 (e.g., to make the substrate 100 thinner). When etching the lower surface of the substrate 100 to make the substrate 100 thinner, a wet etching method utilizing an etchant can be used. Any suitable solution capable of etching glass can be used as an etchant. For example, etchants comprising HF, HCl, phosphoric acid, and / or nitric acid can be used. For example, an etchant comprising 10 wt% HF, 40 wt% HNO3, 40 wt% H3PO4, and 10 wt% deionized water (DI water) can be used, or an etchant comprising 20 wt% HF, 45 wt% HNO3, 20 wt% H3PO4, and 15 wt% deionized water can be used.

[0124] When an etchant is used to etch the second surface, which is the lower surface of the substrate 100, the etchant penetrates into scratches that are provided (e.g., formed) within the substrate 100. Therefore, the substrate is etched along the scratches provided (e.g., formed) within the substrate 100. Figure 9 This illustrates reducing the thickness of the substrate 100 in this manner, and etching the substrate 100 along the edge of the hole-forming region. (See diagram.) Figure 9 As shown, when the substrate 100 is etched along the edge of the hole-forming region, the portion of the substrate 100 corresponding to the portion where the first hole H1 will be formed separates from the remaining portion of the substrate 100. Therefore, when the portion separated from the remaining portion is removed, as... Figure 10 As shown, a first hole H1 is provided (e.g., formed) in the substrate 100. Therefore, the portion of the lower surface of the display layer DIL corresponding to the first hole H1 in the substrate 100 is exposed.

[0125] After that, as Figure 11As shown, a bottom protective layer (BPL) is disposed (e.g., formed) on a second surface of the substrate 100, which serves as the lower surface of the substrate 100. For example, the bottom protective layer BPL is disposed (e.g., formed) to cover the lower surface of the display layer DIL exposed by the first hole H1 of the substrate 100, the lower surface of the substrate 100, and the inner surface of the first hole H1. The bottom protective layer BPL can be disposed (e.g., formed) using inkjet printing and / or spin coating methods. To form the bottom protective layer BPL, if necessary, the display panel 10 being manufactured can be flipped so that the lower surface of the substrate 100 is positioned in the +z direction from the upper surface of the substrate 100. The materials used to dispose of the bottom protective layer BPL are as described herein.

[0126] After setting the bottom protective layer (BPL), remove the temporary protective layer (TPL) on the display layer (DIL). The temporary protective layer (TPL) can be removed in one or more suitable ways. For example, it can be removed by a wet etching method using an etchant, by a dry etching method, and / or by simply physically peeling the temporary protective layer (TPL) off from the display layer (DIL). If the temporary protective layer (TPL) is pre-set (e.g., formed) in the form of a plate and attached to the display layer (DIL) using an adhesive, it can be removed from the display layer (DIL) by reducing the adhesive's tackiness. For example, the temporary protective layer (TPL) can be removed by irradiating the adhesive layer with ultraviolet light to reduce the adhesive's tackiness.

[0127] like Figure 12 As shown, after removing the temporary protective layer TPL, a polarizing layer POL can be disposed (e.g., formed) on the display layer DIL to correspond to the entire surface of the display layer DIL, such that the display layer DIL lies between the polarizing layer POL and the substrate 100. For example, the polarizing layer POL can be pre-disposed (e.g., formed) in the form of a flat plate and then attached to the display layer DIL using an adhesive. If desired, a phase retardation layer such as a λ / 4 waveplate can be disposed (e.g., formed) on the display layer DIL, and the polarizing layer POL can be disposed (e.g., formed) on the phase retardation layer. When the display panel 10 includes a phase retardation layer, for ease of description, the polarizing layer POL can be considered to include the phase retardation layer as described herein.

[0128] Then, as Figure 13 As shown, the portions of the polarization layer POL and the display layer DIL corresponding to the edge of the aperture formation region are removed. For example, a laser beam LB is irradiated onto the portion of the polarization layer POL corresponding to the edge of the aperture formation region, thereby removing the corresponding portions of the polarization layer POL and the display layer DIL. Figure 13This is a cross-sectional view, and therefore shows two laser beams LB. However, the laser beams LB can be irradiated along the edge of the hole-forming region. The laser beams LB can be irradiated until the portion of the first surface, which is the upper surface of the substrate 100, corresponding to the edge of the hole-forming region is exposed.

[0129] like Figure 13 As shown, when the laser beam LB irradiates along the edge of the aperture forming region, the portion of the display layer DIL and polarizing layer POL that will form (e.g., create) the second aperture H2 separates from the remaining portion of the display layer DIL and polarizing layer POL. Therefore, as... Figure 14 As shown, when the separated portion is removed, a second hole H2 is formed in the display layer DIL and the polarization layer POL, which is bonded to the first hole H1.

[0130] In an embodiment, when the second aperture H2 is formed, the laser beam LB irradiates the polarization layer POL and the substrate 100. In this process, a portion of the bottom protective layer BPL on the inner surface of the first aperture H1 can be removed. In some embodiments, such as Figure 13 and Figure 14 As shown, because the substrate 100 is transparent due to its inclusion of glass, the laser beam LB can penetrate the substrate 100 and remove a portion of the bottom protective layer BPL on the lower surface of the substrate 100 (in the -z direction). Therefore, the portion of the second surface of the lower surface of the substrate 100 that is not covered by the bottom protective layer BPL and surrounds the first hole H1 can be presented as an annular shape in the plan view. Furthermore, the bottom protective layer BPL can have a third hole H3 corresponding to the first hole H1 of the substrate 100.

[0131] In some embodiments, when the second hole H2 is configured in this manner, the laser beam LB irradiates the polarization layer POL and the substrate 100 until a first surface, which is the upper surface of the substrate 100, is exposed corresponding to the edge of the hole-forming region, such that an organic film can be removed at least in the region of the first surface, which is the upper surface of the substrate 100, where the laser beam LB is irradiated. For example, in a display panel 10 manufactured as described herein, an organic film, such as an organic insulating film, can be removed from the first surface, which is the upper surface of the substrate 100, between the display layer DIL and the first hole H1 (e.g., where no organic film, such as an organic insulating film, exists on the first surface, which is the upper surface of the substrate 100, between the display layer DIL and the first hole H1). For example, in Figure 14 In the process, between the portion denoted as A1 and the portion denoted as A2, an organic film can be removed from the first surface, which is the upper surface of the substrate 100 (for example, there is no organic film on the first surface, which is the upper surface of the substrate 100).

[0132] As described herein, a second aperture H2 is set (e.g., formed) using a laser beam LB; therefore, the edge of the second aperture H2 of the polarization layer POL may include a thermally deformable portion. Similarly, the edge of the third aperture H3 of the bottom protective layer BPL may include a thermally deformable portion.

[0133] A second aperture H2 is formed in the display layer DIL and polarization layer POL by a laser beam LB, so that the inner surface H2S of the second aperture H2 in the display layer DIL and polarization layer POL can be a continuous surface up to the upper surface of the substrate 100. The continuous inner surface H2S of the second aperture H2 can mean that there are no steps from the inner surface H2S of the second aperture H2 up to the upper surface of the substrate 100. Therefore, the area of ​​the second aperture H2 at the lower surface of the polarization layer POL facing the display layer DIL can be equal to the area of ​​the second aperture H2 at the upper surface of the display layer DIL facing the polarization layer POL.

[0134] A step may exist between the second hole H2 of the display layer DIL and polarizing layer POL and the first hole H1 of the substrate 100. This is because the second hole H2 of the display layer DIL and polarizing layer POL exposes a portion of the first surface that forms the upper surface of the substrate 100. The portion of the upper surface of the substrate 100 that is not covered by the display layer DIL and is exposed may have a shape surrounding the first hole H1 of the substrate 100; therefore, this portion may appear as an annular shape in a plan view. Furthermore, the area A2 of the second hole H2 at the lower surface of the display layer DIL may be wider than the area A1 of the first hole H1 at the upper surface of the substrate 100.

[0135] As described here, a third hole H3 is formed in the bottom protective layer BPL by irradiating the laser beam LB, which forms the second hole H2, and the area of ​​the third hole H3 in the bottom protective layer BPL can be wider than the area A1 of the first hole H1 in the substrate 100 at the upper surface of the substrate 100. Since the substrate 100 is transparent because it includes glass, the laser beam LB passes through the substrate 100, and as... Figure 13 and Figure 14 As shown, a portion of the bottom protective layer BPL on the lower surface of the substrate 100 is also removed. Since the third hole H3 is also simultaneously (e.g., synchronously) formed by the laser beam LB that irradiates to form the second hole H2, the area A3 of the third hole H3 on the upper surface of the bottom protective layer BPL facing the substrate 100 can be equal to the area A2 of the second hole H2 on the lower surface of the display layer DIL facing the substrate 100. For example, when viewed in a direction perpendicular to the substrate 100 (z-axis direction), the edge of the third hole H3 on the upper surface of the bottom protective layer BPL can overlap with the edge of the second hole H2 on the lower surface of the display layer DIL.

[0136] Figure 15 It is an illustrative representation of including Figure 1 A plan view of the display panel 10 in the electronic device 1. (See diagram below.) Figure 15 As shown and described herein, the display panel 10 may include an opening region OA, an intermediate region MA, which may be referred to as a first region, a display region DA, which may be referred to as a second region, and a peripheral region PA. For example, the substrate 100 of the display panel 10 may be considered to include a first hole H1 corresponding to the opening region OA, a display region DA outside and surrounding the first hole H1, an intermediate region MA between the first hole H1 and the display region DA, and a peripheral region PA outside the display region DA.

[0137] The display panel 10 may include multiple pixels P in the display area DA, and the display panel 10 may use light emitted from the pixels P to display images. Each of the pixels P may use a light-emitting diode to emit red, green, or blue light. The pixels P may be electrically connected to scan lines SL and data lines DL.

[0138] In the peripheral region PA, scan drivers 11 and 12 that can provide scan signals to each of the pixels P, data driver 20 that can provide data signals to each of the pixels P, a first power line (e.g., a drive voltage line) for providing a drive voltage to each of the pixels P, and a second power line for providing a common voltage (e.g., a second power voltage) to each of the pixels P can be provided.

[0139] The intermediate region MA may surround the opening region OA. The intermediate region MA may not include (e.g., may not have) display elements such as light-emitting diodes. Of course, if desired, the display elements may also be located in the intermediate region MA, and in embodiments, pixel circuitry electrically coupled to the display elements may be located within the intermediate region MA or within the display region DA. Some of the signal lines of pixels P located adjacent to the opening region OA in which signals are provided to pixels P within the display region DA may pass through the intermediate region MA.

[0140] For example, the data line DL can span the display area DA, but a portion of the data line DL can bypass the through hole 10H of the display panel 10, which is set (e.g., formed) in the opening area OA, through the middle area MA along the edge of the through hole 10H. Figure 15 The data lines DL are shown to cross the display area DA along the y-axis direction, but some data lines DL bypass the opening area OA to partially surround the opening area OA in the middle area MA.

[0141] Some of the scan lines SL may include a first portion and a second portion, which extend across the display area DA along the x-axis and are separated from each other through the opening area OA. In an embodiment, the first portion of the scan line SL located on one side of the opening area OA (in the -x direction) may be electrically coupled to a scan driver 11 located on the other side of the opening area OA (in the -x direction), and the second portion of the scan line SL located on the other side of the opening area OA (in the +x direction) may be electrically coupled to a scan driver 12 located on the other side of the opening area OA (in the +x direction). Therefore, the scan lines SL do not need to bypass the opening area OA to partially surround the opening area OA through the intermediate area MA. If the display panel 10 has only one scan driver, some scan lines SL may bypass the opening area OA to partially surround the opening area OA in the intermediate area MA.

[0142] Figure 15 The diagram shows a data driver 20 positioned on a substrate 100 adjacent to one edge of the substrate 100 (in the -y direction); however, one or more embodiments are not limited to this. For example, the data driver 20 may be electrically bonded to a printed circuit board of the display panel 10 via a pad located at one edge of the display panel 10. And, as... Figure 15 As shown, when the data driver 20 is located on the substrate 100 adjacent to one edge of the substrate 100 (in the -y direction), a portion of the substrate 100 may be as referenced here. Figure 5 The curve is as described, such that the portion of the base 100 with the data driver 20, etc., is superimposed on the display area DA and positioned behind the display area DA.

[0143] Figure 16 Is included Figure 15 The equivalent circuit diagram of the pixel circuit PC in the display panel 10, which is electrically connected to the light-emitting diode (LED).

[0144] like Figure 16 As shown, the pixel circuit PC, which includes multiple thin-film transistors and capacitors, can be electrically connected to the light-emitting diode (LED). Figure 16 The pixel circuit PC shown includes seven thin-film transistors T1 to T7 and a storage capacitor Cst. However, one or more embodiments may not be limited to this, and the number of thin-film transistors and capacitors, as well as their interconnections, may be appropriately varied.

[0145] Multiple thin-film transistors T1 to T7 and storage capacitor Cst can be coupled to signal lines SL, SL-1, SL+1, EL and DL, initialization voltage line VL and / or drive voltage line PL. At least one of these lines (e.g., drive voltage line PL) can be shared by adjacent pixel P.

[0146] The multiple thin-film transistors T1 to T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7.

[0147] Light-emitting diodes (LEDs), such as OLEDs, can include pixel electrodes and counter electrodes. The pixel electrodes of the LED can receive a drive current supply via an emitter control transistor T6 connected to a drive transistor T1, and the counter electrode can receive a second power voltage ELVSS. The LED can produce light with a brightness corresponding to the drive current.

[0148] although Figure 16 The illustration shows multiple thin-film transistors T1 to T7, all of which are P-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (PMOS), but one or more embodiments are not limited thereto. For example, each (e.g., all) of the multiple thin-film transistors T1 to T7 may be an N-channel MOSFET (NMOS). In embodiments, some of the multiple thin-film transistors T1 to T7 may be PMOS, while others may be NMOS. The multiple thin-film transistors T1 to T7 may comprise amorphous silicon or polycrystalline silicon. In embodiments, at least some of the thin-film transistors T1 to T7 may comprise oxide semiconductors.

[0149] The signal lines may include a scan line SL that transmits the scan signal Sn to the switching transistor T2 and the compensation transistor T3, a previous scan line SL-1 that transmits the previous scan signal Sn-1 to the first initialization transistor T4, a next scan line SL+1 that transmits the next scan signal Sn+1 to the second initialization transistor T7, an emit control line EL that transmits the emit control signal En to the operation control transistor T5 and the emit control transistor T6, and a data line DL that crosses the scan line SL and transmits the data signal Dm.

[0150] The driving voltage line PL can transmit the driving voltage ELVDD to the driving transistor T1, and the initialization voltage line VL can transmit the initialization voltage Vint that initializes the driving transistor T1 and the pixel electrode of the light-emitting diode (LED).

[0151] The driving gate electrode of the driving transistor T1 can be coupled to the first capacitor electrode of the storage capacitor Cst. One of the source and drain regions of the driving transistor T1 can be coupled to the driving voltage line PL via the operation control transistor T5, and the other of the source and drain regions of the driving transistor T1 can be coupled to the pixel electrode of the light-emitting diode (LED) via the emitter control transistor T6. The driving transistor T1 can supply driving current to the LED by receiving a data signal Dm in response to the switching operation of the switching transistor T2. For example, the driving transistor T1 can control the amount of current flowing through the LED in response to a voltage change caused by the data signal Dm.

[0152] The gate electrode of switching transistor T2 can be connected to the scan line SL that transmits the scan signal Sn. One of the source and drain regions of switching transistor T2 can be connected to the data line DL, and the other of the source and drain regions of switching transistor T2 can be connected to the drive transistor T1, and then connected to the drive voltage line PL via the operation control transistor T5. Switching transistor T2 can transmit the data signal Dm from the data line DL to the drive transistor T1 in response to the voltage applied to the scan line SL. For example, switching transistor T2 can be turned on in response to the scan signal Sn received through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted through the data line DL to the drive transistor T1.

[0153] The compensation gate electrode of compensation transistor T3 is coupled to scan line SL. One of the source and drain regions of compensation transistor T3 can be coupled to the pixel electrode of light-emitting diode (LED) via emitter control transistor T6. The other of the source and drain regions of compensation transistor T3 can be coupled to the first capacitor electrode of storage capacitor Cst and the drive gate electrode of drive transistor T1. Compensation transistor T3 can be turned on in response to scan signal Sn received via scan line SL, and the diode of drive transistor T1 can be coupled to compensation transistor T3.

[0154] The first initialization gate electrode of the first initialization transistor T4 can be coupled to the previous scan line SL-1. One of the source and drain regions of the first initialization transistor T4 can be coupled to the initialization voltage line VL. The other of the source and drain regions of the first initialization transistor T4 can be coupled to the first capacitor electrode of the storage capacitor Cst and the driving gate electrode of the driving transistor T1. For example, the first initialization transistor T4 can be turned on in response to the previous scan signal Sn-1 received through the previous scan line SL-1, and the initialization operation of the voltage of the driving gate electrode of the driving transistor T1 can be performed by transmitting the initialization voltage Vint to the driving gate electrode of the driving transistor T1.

[0155] The operation control gate electrode of the operation control transistor T5 can be connected to the emitter control line EL. One of the source and drain regions of the operation control transistor T5 can be connected to the drive voltage line PL, and the other can be connected to the drive transistor T1 and the switching transistor T2.

[0156] The emitter control gate electrode of emitter control transistor T6 can be coupled to emitter control line EL, one of the source and drain regions of emitter control transistor T6 can be coupled to drive transistor T1 and compensation transistor T3, and the other of the source and drain regions of emitter control transistor T6 can be electrically coupled to the pixel electrode of light-emitting diode LED.

[0157] The operation control transistor T5 and the emitter control transistor T6 are simultaneously (e.g., synchronously) turned on in response to the emitter control signal En received through the emitter control line EL, and the drive voltage ELVDD is transmitted to the light-emitting diode LED through the drive transistor T1, so that the drive current flows through the light-emitting diode LED.

[0158] The second initialization gate electrode of the second initialization transistor T7 can be coupled to the next scan line SL+1. One of the source and drain regions of the second initialization transistor T7 can be coupled to the pixel electrode of the light-emitting diode (LED), and the other of the source and drain regions of the second initialization transistor T7 can be coupled to the initialization voltage line VL to receive the initialization voltage Vint. The second initialization transistor T7 is turned on in response to the next scan signal Sn+1 received through the next scan line SL+1, and initializes the pixel electrode of the LED. For reference, the next scan line SL+1 can be coupled to the next scan line SL+1. Figure 16 The pixel P shown is adjacent to and electrically coupled to the scan line SL of the pixel on the data line DL. For example, the scan line SL can transmit the same electrical signal with a time difference and can be used as the scan line SL of a pixel or as the next scan line SL+1 of the adjacent pixel.

[0159] The storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the storage capacitor Cst is coupled to the drive gate electrode of the drive transistor T1, and the second capacitor electrode of the storage capacitor Cst is coupled to the drive voltage line PL. The storage capacitor Cst can store the charge corresponding to the difference between the voltage at the drive gate electrode of the drive transistor T1 and the drive voltage ELVDD.

[0160] The detailed operation of each pixel P according to one or more embodiments is as follows.

[0161] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SL-1, the first initialization transistor T4 is turned on, and the driving transistor T1 is initialized by the initialization voltage Vint supplied from the initialization voltage line VL.

[0162] During the data programming period, when a scan signal Sn is supplied via scan line SL, switching transistor T2 and compensation transistor T3 are turned on. In this embodiment, driving transistor T1 is diode-coupled with the turned-on compensation transistor T3 and is biased in the forward direction. Then, a compensation voltage (Dm+Vth, where Vth has a negative value) obtained by subtracting the threshold voltage (Vth) of driving transistor T1 from the data signal Dm supplied from data line DL is applied to the driving gate electrode of driving transistor T1. The driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to opposite terminals of storage capacitor Cst, and storage capacitor Cst stores the charge corresponding to the difference between the voltage at its opposite terminals.

[0163] During the emission period, the operation control transistor T5 and the emission control transistor T6 are turned on in response to the emission control signal En supplied from the emission control line EL. A drive current is generated based on the difference between the voltage at the drive gate electrode of the drive transistor T1 and the drive voltage ELVDD, and the drive current is supplied to the light-emitting diode (LED) through the emission control transistor T6.

[0164] Figure 17 It is shown schematically. Figure 15 A plan view of the opening area OA, the middle area MA, and a portion of the display area DA of the display panel 10. (See attached image.) Figure 17 As shown in the figure, pixel P is set in the display area DA.

[0165] The intermediate region MA, which may be referred to as the first region, may be located between the opening region OA and the display region DA, which may be referred to as the second region. In a plan view, pixels P adjacent to the opening region OA may be separated from each other (e.g., spaced apart or separated) relative to the opening region OA. For example, pixels P may be separated from each other (e.g., spaced apart or separated) in the vertical direction (y-axis direction) relative to the opening region OA, or they may be separated from each other (e.g., spaced apart or separated) in the left-right direction (x-axis direction) relative to the opening region OA.

[0166] In the signal lines supplying signals to the pixel circuitry of the light-emitting diodes associated with each pixel P, the signal lines adjacent to the opening region OA can bypass the opening region OA and / or the via 10H. Some of the data lines DL passing through the display region DA are located in the same column and extend (in the y-axis direction) to provide data signals to the pixel P located on one side of the opening region OA (in the +y direction) and the pixel P located on the other side of the opening region OA (in the -y direction), and can bypass the opening region OA and / or the via 10H along the edge of the opening region OA and / or the via 10H in the intermediate region MA.

[0167] Figure 17 The diagram illustrates a first data line DL1 comprising a first extension DL-L1 electrically bonded to a pixel P located on one side of the opening region OA (in the +y direction), a first extension DL-L1 electrically bonded to the other side of the opening region OA (in the -y direction), and a first bypassing portion DL-C1 that wraps around the opening region OA and / or the via 10H along the edge of the opening region OA and / or the via 10H in the intermediate region MA. The first bypassing portion DL-C1 can electrically bond two first extensions DL-L1 that are separated and / or spaced apart (e.g., spaced apart or separated). Figure 17 As shown, the first bypass portion DL-C1 can be substantially located on one side of the opening region OA (in the +x direction). The first bypass portion DL-C1 can be located on a different layer than the layer on which the first extension portion DL-L1 is positioned, in which case, as Figure 17 As shown, the first bypass portion DL-C1 can be coupled to the first extension portion DL-L1 through the contact hole CNT. In contrast, in another embodiment, the first bypass portion DL-C1 and the first extension portion DL-L1 can also be integrally formed (e.g., integrally disposed).

[0168] Figure 17 The second data line DL2 is shown to include a second extension DL-L2 electrically bonded to a pixel P located on one side of the opening region OA (in the +y direction), a second extension DL-L2 electrically bonded to the other side of the opening region OA (in the -y direction), and a second bypassing portion DL-C2 that bypasses the opening region OA and / or the via 10H along the edge of the opening region OA and / or the via 10H in the intermediate region MA. The second bypassing portion DL-C2 can electrically bond two second extensions DL-L2 that are separated and / or spaced apart (e.g., spaced apart or separated). Figure 17 As shown, the second bypass portion DL-C2 can be substantially located on one side of the opening region OA (in the -x direction). Figure 17As shown, the second bypass portion DL-C2 and the second extension portion DL-L2 can also be integrally formed (e.g., integrally disposed). In one or more embodiments, the second bypass portion DL-C2 may be located on a different layer than the layer on which the second extension portion DL-L2 is positioned, in which case the second bypass portion DL-C2 may be coupled to the second extension portion DL-L2 through a contact hole.

[0169] The scan line SL can be separated or isolated relative to the opening region OA. Figure 17 The diagram illustrates a scan line SL comprising two sub-scan lines SL-L separated relative to the opening region OA. The sub-scan line SL-L on the left side of the opening region OA (in the -x direction) can receive signals from a scan driver 11 on the left side of the display region DA (in the -x direction), and the sub-scan line SL-L on the right side of the opening region OA (in the +x direction) can receive signals from a scan driver 12 on the right side of the display region DA (in the +x direction). In one or more embodiments, these sub-scan lines SL-L can be electrically coupled to each other via a bypass portion in the intermediate region MA, and the display panel 10 may include a scan driver.

[0170] The groove G can be located in the intermediate region MA. The groove G can be between the opening region OA and the region around which the data line DL passes. For example, the groove G can be between the first winding portion DL-C1 and the opening region OA, and between the second winding portion DL-C2 and the opening region OA. In a plan view viewed from a direction substantially perpendicular to the base (z-axis direction), each of the grooves G can have a closed loop shape around the opening region OA. The grooves G can be separated from each other and / or spaced apart (e.g., spaced apart or separated).

[0171] Figure 18 It is schematically shown along Figure 17 A cross-sectional view of the display panel 10 taken by line B-B'.

[0172] The buffer layer 201 may be on the substrate 100. The buffer layer 201 may prevent or reduce the penetration of impurities into the semiconductor layer Act of the thin-film transistor (TFT). The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and / or silicon oxide, and may have a single-layer structure or a multi-layer structure.

[0173] The pixel circuit PC can be located on top of the buffer layer 201. The pixel circuit PC may include a thin-film transistor (TFT) and a storage capacitor Cst. The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and / or a drain electrode DE. Figure 18 The thin-film transistor (TFT) shown can be a driving transistor. See here for reference. Figure 16In the described pixel circuit PC, the emission control transistor T6 is positioned between the driving transistor T1 and the organic light-emitting diode (OLED). In the embodiment, with Figure 18 The structure shown is different; the thin-film transistor (TFT), which serves as the driving transistor, is not bonded to the pixel electrode 221 of the organic light-emitting diode via the contact metal layer CM, but is instead electrically bonded to... Figure 18 The emission control transistor is not shown, and it can be electrically coupled to the pixel electrode 221 of the organic light-emitting diode (OLED). For ease of description, the following is described: Figure 18 The thin-film transistor (TFT) is bonded to the pixel electrode 221 of the organic light-emitting diode (OLED) through a contact metal layer (CM).

[0174] The data line DL of the pixel circuit PC can be electrically coupled to the switching transistor included in the pixel circuit PC.

[0175] The semiconductor layer Act may include polycrystalline silicon. In embodiments, the semiconductor layer Act may include amorphous silicon, oxide semiconductor materials, and / or organic semiconductor materials, etc. The gate electrode GE may include a low-resistance metallic material. For example, the gate electrode GE may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a multilayer or single-layer structure. For example, the gate electrode GE may have a three-layer structure of a molybdenum layer, an aluminum layer, and a molybdenum layer (Mo / Al / Mo).

[0176] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The gate insulating layer 203 may have a single-layer structure or a multi-layer structure.

[0177] The source electrode SE and drain electrode DE can be on the same layer as the data line DL and can include the same materials as the data line DL. The source electrode SE, drain electrode DE, and data line DL can include materials with high conductivity. The source electrode SE and drain electrode DE can include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a multilayer or single-layer structure. For example, the source electrode SE, drain electrode DE, and data line DL can have a multilayer structure of titanium layers, aluminum layers, and titanium layers (Ti / Al / Ti).

[0178] Figure 18The diagram illustrates a thin-film transistor (TFT) comprising both a source electrode SE and a drain electrode DE (e.g., simultaneously including both source electrode SE and drain electrode DE), but one or more embodiments are not limited thereto. For example, the drain region of the semiconductor layer Act of the TFT may be integrally disposed (e.g., formed) with the source region of the semiconductor layer of another TFT, and in embodiments, the TFT may not include (e.g., not have) a drain electrode DE, and the other TFT may not include (e.g., not have) a source electrode. In embodiments, the circuit diagram may show the drain of the TFT as coupled to the source of another TFT. Figure 16 In the pixel circuit PC shown, the drain of the driving transistor T1 and the source of the emitter control transistor T6 are shown as combined. In embodiments, the driving transistor T1 may not include (e.g., not have) a drain electrode, the emitter control transistor T6 may not include (e.g., not have) a source electrode, and the drain region of the semiconductor layer of the driving transistor T1 and the source region of the emitter control transistor T6 may be integrally disposed (e.g., formed) as a single body. Similarly, in Figure 16 In the pixel circuit PC shown, because the source of the driving transistor T1 is coupled to the drain of the operation control transistor T5, the driving transistor T1 may not include (e.g., not have) a source electrode, and the operation control transistor T5 may not include (e.g., not have) a drain electrode. Furthermore, the source region of the semiconductor layer of the driving transistor T1 and the drain region of the operation control transistor T5 can be integrally formed (e.g., constructed) as a single entity. Therefore, the driving transistor T1 may not include (e.g., not have) both a source electrode and a drain electrode (e.g., simultaneously not include (e.g., not have) both a source electrode and a drain electrode).

[0179] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 stacked on top of each other, and a first interlayer insulating layer 205 is located between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may be stacked with a thin-film transistor (TFT). Figure 18 The diagram shows that the gate electrode GE of the thin-film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. Of course, one or more embodiments are not limited to this, and the storage capacitor Cst may not be stacked with the thin-film transistor TFT. A second interlayer insulating layer 207 may cover the storage capacitor Cst. The upper electrode CE2 of the storage capacitor Cst may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a multilayer or single-layer structure.

[0180] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may have a single-layer structure or a multi-layer structure.

[0181] The first organic insulating layer 209 can cover the pixel circuit PC, which includes a thin-film transistor (TFT) and a storage capacitor (Cst).

[0182] The pixel circuit PC can be electrically coupled to the pixel electrode 221. For example, as Figure 18 As shown, the contact metal layer CM can be disposed between the thin-film transistor TFT and the pixel electrode 221. The contact metal layer CM can be bonded to the thin-film transistor TFT through contact holes defined in the first organic insulating layer 209, and the pixel electrode 221 can be bonded to the contact metal layer CM through contact holes defined in the second organic insulating layer 211 covering the contact metal layer CM. The contact metal layer CM can include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a multilayer structure or a single-layer structure. For example, the contact metal layer CM can have a multilayer structure of titanium layer, aluminum layer, and titanium layer (Ti / Al / Ti).

[0183] The first organic insulating layer 209 and the second organic insulating layer 211 may comprise organic insulating materials such as acrylic acid, polystyrene (PS), polymethyl methacrylate (PMMA), BCB (benzocyclobutene), polyimide, and / or HMDSO (hexamethyldisiloxane). For example, the first organic insulating layer 209 and the second organic insulating layer 211 may comprise polyimide. The first organic insulating layer 209 and / or the second organic insulating layer 211 may have a substantially flat upper surface. For example, the first organic insulating layer 209 and / or the second organic insulating layer 211 may be referred to as a planarization layer.

[0184] The pixel electrode 221 on the second organic insulating layer 211 can be a (semi-)transparent electrode or a reflective electrode. For example, the pixel electrode 221 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof, and a transparent or semi-transparent electrode layer on the reflective layer. The transparent or semi-transparent electrode layer may include electrodes made from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. x It is selected from at least one of the following groups: ZnO or ZnO2, indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, pixel electrode 221 may have a three-layer structure of ITO / Ag / ITO.

[0185] Pixel defining layer 215 may be located above second organic insulating layer 211. Pixel defining layer 215 can prevent or reduce arcing at the edges of pixel electrode 221 by covering the edges of pixel electrode 221 and increasing the distance between pixel electrode 221 and common electrode 223 above pixel electrode 221. For example, pixel defining layer 215 has an opening to expose the central portion of pixel electrode 221. Pixel defining layer 215 may be formed by a method such as spin coating and may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene resin, and phenolic resin. In embodiments, pixel defining layer 215 may include silicon nitride (SiN). x ), silicon oxynitride (SiON) and / or silicon oxide (SiO) x Inorganic insulating materials.

[0186] The intermediate layer 222 disposed between the pixel electrode 221 and the common electrode 223 may include an emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a between the emitting layer 222b and the pixel electrode 221, or may include a second functional layer 222c between the emitting layer 222b and the common electrode 223. The emitting layer 222b may emit light of a predetermined color and may include a polymer or a low-molecular-weight organic material.

[0187] The first functional layer 222a may have a single-layer structure or a multi-layer structure. For example, when the first functional layer 222a comprises a polymer material, it may have a single-layer structure including a hole transport layer (HTL) and may include polyethylene dioxythiophene (PEDOT: poly-(3,4-ethylenedioxythiophene)) and / or polyaniline (PANI: polyaniline). When the first functional layer 222a comprises a low molecular weight material, it may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0188] The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0189] In some embodiments, with Figure 18 The structure shown differs from the one described above. The intermediate layer 222 may include a first stack comprising an emission layer 222b and a functional layer, a second stack comprising an emission layer 222b and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The negative and positive charge generation layers can further improve the emission efficiency of a series-connected light-emitting diode (LED) with multiple emission layers.

[0190] The negative charge generation layer can be an n-type (type) charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material. The positive charge generation layer can be a p-type (type) charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material.

[0191] The emitter layer 222b may have a patterned shape corresponding to the pixel electrode 221. Layers other than the emitter layer 222b included in the intermediate layer 222 may be disposed (e.g., formed) in one or more suitable ways. For example, layers other than the emitter layer 222b included in the intermediate layer 222 may be integrally disposed (e.g., formed) as a single body across multiple pixel electrodes 221. Layers other than the emitter layer 222b included in the intermediate layer 222 may also be located in the intermediate region MA.

[0192] The common electrode 223 can be a transparent electrode or a reflective electrode. For example, the common electrode 223 can be a transparent or semi-transparent electrode and can include a metal film containing Li, Ca, Al, Ag, Mg and / or compounds thereof (e.g., LiF) with a small work function. In one or more embodiments, the common electrode 223 may also include a TCO (transparent conductive oxide) film (such as ITO, IZO, ZnO, ZnO2 and / or In2O3) on the metal film.

[0193] The common electrode 223 can be disposed (e.g., formed) as a single body covering the entire display area DA, and can be above the intermediate layer 222 and the pixel defining layer 215. For example, each of the pixel electrodes 221 can correspond to each light-emitting diode (LED), and the common electrode 223 can be integrally disposed (e.g., formed) as a single body to correspond to multiple organic light-emitting diodes (OLEDs). Multiple OLEDs can share the common electrode 223, and the stacked structure of the pixel electrode 221, the intermediate layer 222, and the common electrode 223 can correspond to one OLED.

[0194] The capping layer 230 may be located above the common electrode 223. For example, the capping layer 230 may include LiF. In some embodiments, the capping layer 230 may not be provided.

[0195] Spacer 217 may be on pixel defining layer 215. Spacer 217 may include an organic insulator such as polyimide. In embodiments, spacer 217 may include an inorganic insulator, or may include both organic and inorganic insulators.

[0196] The spacer 217 may comprise a material different from that of the pixel defining layer 215, or it may comprise the same material as the pixel defining layer 215. For example, the pixel defining layer 215 and the spacer 217 may comprise polyimide. When the pixel defining layer 215 and the spacer 217 comprise the same material, a halftone mask may be used to simultaneously (e.g., synchronously) set (e.g., form) the pixel defining layer 215 and the spacer 217 in a single masking process. Within the aforementioned intermediate layer 222, the functional layer or common electrode 223 may cover the spacer 217.

[0197] The thin-film encapsulation layer 300 can cover an organic light-emitting diode (OLED). The thin-film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer, and Figure 18 The thin-film encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. In embodiments, the number and stacking order of the organic and inorganic encapsulation layers can be varied.

[0198] Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Each of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have a single-layer structure or a multi-layer structure. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resins (such as polymethyl methacrylate and / or polyacrylic acid), epoxy resins, polyimides, and / or polyethylene. For example, the organic encapsulation layer 320 may include acrylates.

[0199] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include different materials. For example, the first inorganic encapsulation layer 310 may include silicon oxynitride, and the second inorganic encapsulation layer 330 may include silicon nitride.

[0200] An additional planarization layer (SPL) may be placed on top of the thin-film encapsulation layer 300, and a polarizing layer (POL) may be placed on top of the additional planarization layer (SPL). The additional planarization layer (SPL) is part of the aforementioned display layer (DIL) and may include organic insulating materials such as acrylic acid, polystyrene (PS), polymethyl methacrylate (PMMA), benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO). The additional planarization layer (SPL) may be applied (e.g., formed) by inkjet printing and / or spin coating methods. The additional planarization layer (SPL) may have a substantially flat upper surface. If the display layer (DIL) is included in a touchscreen layer above the thin-film encapsulation layer 300, the additional planarization layer (SPL) may be placed on top of the touchscreen layer.

[0201] As described here and as Figure 18 As shown, the inner surface H2S of the second aperture H2 included in the display layer DIL and polarization layer POL can be a continuous surface extending to the upper surface of the substrate 100. For example, in the polarization layer POL, the additional planarization layer SPL, the second interlayer insulating layer 207, the first interlayer insulating layer 205, the gate insulating layer 203, and / or the buffer layer 201, the inner surface H2S of the second aperture H2 can be formed as a continuous surface without steps.

[0202] Figure 18 The intermediate region MA shown may include a first sub-intermediate region SMA1 and a second sub-intermediate region SMA2. The first sub-intermediate region SMA1 may be relatively farther from the opening region OA of the through hole 10H of the display panel 10 (e.g., the first hole H1 of the substrate 100) than the second sub-intermediate region SMA2. In an embodiment, the second sub-intermediate region SMA2 is closer to the opening region OA than the first sub-intermediate region SMA1. Lines and grooves G1, G2, and G that bypass the opening region OA may be provided in the intermediate region MA.

[0203] Lines such as data lines DL can be set in the first sub-intermediate area SMA1. Figure 18 The data line DL in the first sub-intermediate region SMA1 shown here is referenced here. Figure 17 The described data line DL has a corresponding winding portion (such as the first winding portion DL-C1 and / or the second winding portion DL-C2). The first sub-intermediate region SMA1 can be a line area or winding area that the data line DL bypasses.

[0204] In the first sub-intermediate region SMA1, data lines DL can be arranged alternately, with an insulating layer between them. For example, one of adjacent data lines DL may be below the insulating layer (e.g., the first organic insulating layer 209), while the other may be above the insulating layer (e.g., the first organic insulating layer 209). When the data lines DL are arranged alternately with an insulating layer between them, the distance (Δd, spacing) between adjacent data lines in the plan view can be reduced. Figure 18 The data line DL is shown positioned within the first sub-intermediate region SMA1. However, if necessary or desired, the bypass portion of the scan line SL can also be located within the first sub-intermediate region SMA1.

[0205] Grooves G1, G2, and G can be disposed in the second sub-intermediate region SMA2. Organic layers included in the intermediate layer 222 (such as the first functional layer 222a and / or the second functional layer 222c) can be separated (or separated) by grooves G1, G2, and G. The second sub-intermediate region SMA2 can be referred to as a disconnected (or separated) region of organic layers or a groove region.

[0206] The grooves G1, G2 and G can be provided (e.g., formed) by a layer placed between the substrate 100 and the organic light-emitting diode (OLED) as a display element. Figure 18 A first organic insulating layer 209, which may be referred to as the upper layer, is shown above a second interlayer insulating layer 207, which may be referred to as the lower layer, and the first organic insulating layer 209 includes grooves G1, G2, and G. Each of the grooves G1, G2, and G may be provided (e.g., formed) by multiple layers (e.g., by the upper and lower layers) if necessary or desired.

[0207] In the recesses G1, G2, and G in the intermediate region MA, which may be referred to as the first region, a first recess G1, which is the recess of the opening region OA located closest to the first hole H1 of the substrate 100, may be provided (e.g., formed) in a first upper layer 209a on a second interlayer insulating layer 207, which may be referred to as the lower layer. The first upper layer 209a may be part of the first organic insulating layer 209. In embodiments, during the manufacturing process, the first upper layer 209a may be provided (e.g., formed) simultaneously (e.g., synchronously) with the first organic insulating layer 209 and have the same material, and the first upper layer 209a may be separate from and / or spaced apart (e.g., spaced apart or separated) from the first organic insulating layer 209. The first recess G1 may extend along at least a portion of the opening region OA, or may be referred to herein as Figure 17 The described extension extends along the opening region OA to completely surround the opening region OA. The material used to set the intermediate layer 222, common electrode 223, and cover layer 230 can be placed within the first groove G1. This can also be applied to other grooves described herein.

[0208] The first-1 metal layer M1-1 can be positioned to extend over the second interlayer insulating layer 207, which may be referred to as the lower layer, and the first upper layer 209a. The first-1 metal layer M1-1 can be formed (e.g., constructed) simultaneously with the contact metal layer CM using the same material during the manufacturing process. The first-1 metal layer M1-1 can be positioned relative to the center of the first groove G1 of the first upper layer 209a in the direction (-x direction) toward the opening region OA where the through-hole 10H is located. One end of the first-1 metal layer M1-1 in the direction (-x direction) toward the opening region OA rests on the second interlayer insulating layer 207, which may be referred to as the lower layer, and the other end of the first-1 metal layer M1-1 in the direction toward the center of the first groove G1 can protrude from the first upper layer 209a and lie within the first groove G1.

[0209] In some embodiments, a first-second metal layer M1-2, separate from the first-first metal layer M1-1, may be positioned above the second interlayer insulating layer 207 (which may be referred to as the lower layer) and the first upper layer 209a, in a direction (+x direction) toward the second region DA, relative to the center of the first recess G1. One end of the first-second metal layer M1-2 in the direction toward the center of the first recess G1 may protrude from the first upper layer 209a and lie within the first recess G1.

[0210] In this embodiment, because the end of the first-1 metal layer M1-1 protrudes from the first upper layer 209a and is located within the first groove G1 in the direction toward the center of the first groove G1, and because the end of the first-2 metal layer M1-2 protrudes from the first upper layer 209a and is located within the first groove G1 in the direction toward the center of the first groove G1, the first groove G1 can be considered to have an undercut structure in the set of structures of the first upper layer 209a, the first-1 metal layer M1-1, and the first-2 metal layer M1-2. The portion of the first-1 metal layer M1-1 protruding from the first upper layer 209a can be referred to as a protruding tip, and the length of the protruding tip protruding from the first upper layer 209a can be from about 0.3 micrometers (μm) to about 0.5 μm. For example, the length of the protruding tip can be about 0.4 μm. The length of the protruding tip, which is part of the first-2 metal layer M1-2 and protrudes from the first upper layer 209a, can also be from about 0.3 μm to about 0.5 μm. For example, the length of the protruding tip can be about 0.4 μm.

[0211] As described herein, the functional layer included in the intermediate layer 222 can be configured (e.g., formed) to correspond substantially to the entire surface of the substrate 100, and then a portion of the substrate 100, etc., can be removed to form a through-hole 10H in the display panel 10. Therefore, moisture that permeates from the outside into the functional layer through the through-hole 10H may move along the functional layer to the display area DA and may cause defects. However, in the display panel 10 according to one or more embodiments and the electronic device 1 including the display panel 10, as described herein, a first recess G1 having an undercut structure can be provided (e.g., formed) during the manufacturing process before the intermediate layer 222 is provided (e.g., formed). Therefore, as Figure 18 As shown, the functional layer included in the intermediate layer 222 can be separated by the first groove G1 with an undercut structure, so that even if moisture penetrates into the functional layer through the through hole 10H, the movement of moisture toward the display area DA can be prevented, minimized or reduced.

[0212] As described herein, in the display panel 10 according to one or more embodiments, an organic film (such as an organic insulating film) may not be present on the first surface serving as the upper surface of the substrate 100 between the display layer DIL and the opening region OA (e.g., between the display layer DIL and the first hole H1). For example, Figure 18 This illustrates that no organic film (such as an organic insulating film) exists on the first surface, which serves as the upper surface of the substrate 100, between the inner surface H2S of the second hole H2 and the opening region OA. This structure effectively prevents, minimizes, or reduces the penetration of external moisture (such as moisture permeating through the through-hole 10H) into the functional layer.

[0213] As described herein, in an embodiment where the center of the first groove G1, which is the groove closest to the opening region OA, is positioned in the direction (-x direction) toward the opening region OA, the end of the first metal layer M1-1 in the direction (-x direction) toward the opening region OA can be on a second interlayer insulation layer 207, which may be referred to as the lower layer. The bonding force between the first metal layer M1-1, which includes metal, and the inorganic insulator is stronger than the bonding force between the first metal layer M1-1, which includes metal, and the organic insulator. As described herein, because the second interlayer insulation layer 207 comprises an inorganic insulating material, the end of the first metal layer M1-1 in the direction (-x direction) toward the opening region OA can be firmly bonded to the second interlayer insulation layer 207. This can prevent, minimize, or reduce defects such as delamination between layers near the opening region OA.

[0214] In the recesses G1, G2, and G in the intermediate region MA, which may be referred to as the first region, a second recess G2, the second opening region OA located closest to the through-hole of the substrate 100, may be disposed (e.g., formed) in a second upper layer 209b on a second interlayer insulating layer 207, which may be referred to as the lower layer. The second upper layer 209b may be part of the first organic insulating layer 209. In embodiments, the second upper layer 209b may be disposed (e.g., formed) simultaneously (e.g., synchronously) with the first organic insulating layer 209 during the manufacturing process using the same material, but may be separate from the first organic insulating layer 209 to be positioned between the display region DA and the first upper layer 209a. The second upper layer 209b may be separate from the first upper layer 209a. The second recess G2 may extend along at least a portion of the opening region OA, or may be referred to herein as Figure 17 The description extends around the opening region OA to completely surround the opening region OA.

[0215] The second-first metal layer M2-1 may be on top of the second upper layer 209b and on top of the second interlayer insulating layer 207, which may be referred to as the lower layer. During the manufacturing process, the second-first metal layer M2-1 may be set (e.g., formed) simultaneously (e.g., synchronously) with the contact metal layer CM using the same material. The second-first metal layer M2-1 may be positioned relative to the center of the second groove G2 of the second upper layer 209b in the direction (-x direction) toward the opening region OA where the through hole 10H is located. One end of the second-first metal layer M2-1 in the direction toward the center of the second groove G2 may protrude from the second upper layer 209b and lie within the second groove G2.

[0216] A second-second metal layer M2-2, separate from the second-first metal layer M2-1, may be positioned above the second interlayer insulating layer 207 (which may be referred to as the lower layer) and the second upper layer 209b, in a direction toward the display area DA, which is the second region, relative to the center of the second recess G2. One end of the second-second metal layer M2-2 in the direction toward the center of the second recess G2 may protrude from the second upper layer 209b and lie within the second recess G2.

[0217] In this embodiment, because the end of the second-1 metal layer M2-1 protrudes from the second upper layer 209b and is located within the second groove G2 in the direction toward the center of the second groove G2, and because the end of the second-2 metal layer M2-2 protrudes from the second upper layer 209b and is located within the second groove G2 in the direction toward the center of the second groove G2, the second groove G2 can be considered to have an undercut structure in the set of structures of the second upper layer 209b, the second-1 metal layer M2-1, and the second-2 metal layer M2-2. The portion of the second-1 metal layer M2-1 protruding from the second upper layer 209b can be referred to as a protruding tip, and the length of the protruding tip protruding from the second upper layer 209b can be approximately 1.7 μm. The length of the protruding tip, which is part of the second-2 metal layer M2-2 and protrudes from the second upper layer 209b, can also be approximately 1.7 μm.

[0218] As described herein, the functional layers included in the intermediate layer 222 can be separated by a first groove G1 having an undercut structure, and similarly, by a second groove G2 having an undercut structure. Therefore, even if moisture penetrates into the functional layers exposed to the outside at the inner surface of the through-hole 10H, the movement of moisture toward the display area DA can be effectively prevented, minimized, or reduced.

[0219] like Figure 18As shown, the first-2 metal layer M1-2 and the second-1 metal layer M2-1 can be integrally disposed (e.g., formed) as a single body. Therefore, the first-2 metal layer M1-2 and the second-1 metal layer M2-1 (each of which is part of a single body) can contact each other between the first upper layer 209a and the second upper layer 209b as a lower layer, forming a second interlayer insulating layer 207. The metal layer and the second interlayer insulating layer 207 in contact with each other between the first upper layer 209a and the second upper layer 209b can form an inorganic contact region ICR with strong bonding strength. In an embodiment, as described herein, the end of the first-1 metal layer M1-1 in the direction (-x direction) toward the opening region OA can also contact the second interlayer insulating layer 207 to form an inorganic contact region ICR with strong bonding strength.

[0220] Similar to the functional layer, the common electrode 223 can also be separated in the first groove G1 and the second groove G2. The capping layer 230, including LiF, can also be separated in the first groove G1 and the second groove G2. If the capping layer 230 comprises an inorganic material such as silicon nitride, silicon oxide, and / or silicon oxynitride, the capping layer 230 can be continuously disposed (e.g., formed) without being separated by the first groove G1 and / or the second groove G2. For ease of description, the following description will describe an embodiment where the capping layer 230 is separated by the first groove G1 and the second groove G2.

[0221] The first partition wall PW1 and the second partition wall PW2 can be located in the intermediate region MA. Although Figure 18 The illustration shows a first partition wall PW1 and a second partition wall PW2 positioned within an intermediate region MA, but one or more embodiments are not limited thereto. For example, three partition walls may be positioned within the intermediate region MA. The first partition wall PW1 may be positioned closer to the display region DA than the second partition wall PW2. Each of the first partition wall PW1 and the second partition wall PW2 may extend along the opening region OA to completely surround the opening region OA.

[0222] Each of the first partition wall PW1 and the second partition wall PW2 may include a plurality of sequentially stacked organic insulating layers. For example, the first partition wall PW1 may have a structure in which a portion 209P of the first organic insulating layer 209, a portion 211P of the second organic insulating layer 211, a portion 215P of the pixel defining layer 215, and a portion 217P of the spacer 217 are sequentially stacked. The portion 209P of the first organic insulating layer 209 may be bonded to the first organic insulating layer 209 or may be separated from the first organic insulating layer 209. The second partition wall PW2 may have a structure in which a portion of the first organic insulating layer 209, a portion of the second organic insulating layer 211, and a portion of the pixel defining layer 215 are sequentially stacked.

[0223] like Figure 18 As shown, each or a portion of the common electrode 223 in the functional layer may also be on the first partition wall PW1 and the second partition wall PW2.

[0224] The thin-film encapsulation layer 300, which can prevent or reduce damage or degradation of organic light-emitting diodes (OLEDs) by external impurities, may include at least one organic encapsulation layer and at least one inorganic encapsulation layer as described herein.

[0225] The first inorganic encapsulation layer 310, formed by means of chemical vapor deposition or similar methods, has a relatively superior step coverage compared to the functional layer and / or the common electrode 223. Therefore, as... Figure 18 As shown, the first inorganic encapsulation layer 310 is not separated by the first groove G1 and the second groove G2, and can cover the inner surfaces of the first groove G1 and the second groove G2.

[0226] An organic encapsulation layer 320 can be formed (e.g., created) by applying a monomer onto the substrate 100 and allowing it to cure. In an embodiment, the organic encapsulation layer 320 can be formed (e.g., created) by applying a polymer. When the monomer or polymer is applied onto the substrate 100, the first partition wall PW1 and the second partition wall PW2 can be used to block or reduce the flow of the monomer or polymer in the direction toward the opening region OA. Figure 18 The formation area of ​​the organic encapsulation layer 320 is shown to be limited by the first partition wall PW1. If the first partition wall PW1 and the second partition wall PW2 are absent and the material used to form the organic encapsulation layer 320 is applied to the entire surface of the substrate 100, and then a via 10H is formed (e.g., a hole is created) in the display panel 10, the organic encapsulation layer 320 is exposed on the inner surface of the via 10H. In embodiments, the organic encapsulation layer 320 may become a path for external moisture, etc., to penetrate the inner surface of the via 10H, which could lead to defects (e.g., the organic light-emitting diode OLED of the display area DA may be damaged). However, in the display panel 10 according to one or more embodiments and the electronic device 1 including the display panel 10, the presence of the first partition wall PW1 and the second partition wall PW2 effectively prevents, minimizes, or reduces the occurrence of such defects. For reference, even if an excessive amount of material is applied to the organic encapsulation layer 320 during the process of setting the organic encapsulation layer 320 and the material flows to the outside of the first partition wall PW1, the second partition wall PW2 can prevent or reduce further material flow toward the opening region OA.

[0227] The second inorganic encapsulation layer 330 may be on top of the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 may be in direct contact with the first inorganic encapsulation layer 310 in some regions of the intermediate region MA. For example, as Figure 18 As shown, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can contact each other in some regions of the intermediate region MA that are adjacent to the opening region OA.

[0228] The first groove G1 and the second groove G2 can be located between the second partition wall PW2 and the opening area OA. For example... Figure 18 As shown, a groove G having the same or similar shape as the second groove G2 can be located between the first partition wall PW1 and the second partition wall PW2, and a groove G having the same or similar shape as the second groove G2 can be located between the first partition wall PW1 and the second region (e.g., display region DA). Even in the groove G, there may be a metal layer 210 having a shape similar to the first-2 metal layers M1-2 and the second-1 metal layer M2-1, which are integrally disposed (e.g., formed) as a single body and on the first organic insulating layer 209, such that a tip protruding into the groove G can be disposed (e.g., formed).

[0229] Figure 18 Two recesses G are shown located between the display area DA and the first partition wall PW1, two recesses G are located between the first partition wall PW1 and the second partition wall PW2, and two recesses G1 and G2 are located between the second partition wall PW2 and the opening area OA, resulting in a total of twelve tips. In embodiments, the number of tips can be varied if desired or desired.

[0230] Figure 18 The cross-sectional view of the display panel 10 shown can be considered as a structure surrounding the opening region OA. For example, as described here, when viewed in a direction perpendicular to the upper surface of the substrate 100, Figure 18 Each of the grooves G1, G2, and G can have the following characteristics: Figure 17 The annular shape surrounding the opening region OA is shown in the diagram. Similarly, when viewed in a direction perpendicular to the upper surface of the substrate 100, each of the first partition wall PW1 and the second partition wall PW2 may also have an annular shape surrounding the opening region OA. Similarly, when viewed in a direction perpendicular to the upper surface of the substrate 100, either the first-1 metal layer M1-1 or the first-2 metal layer M1-2 may also have an annular shape surrounding the opening region OA.

[0231] Figure 19This is a schematic cross-sectional view of a portion of a display panel 10 according to one or more embodiments. In the display panel 10 according to one or more embodiments, the buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207 included in the display layer DIL above the substrate 100 have additional grooves AG. The buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207 can be collectively referred to as the inorganic layer. Because the inorganic layer above the substrate 100 and included in the display layer DIL has additional grooves AG, the movement of moisture toward the display area DA can be effectively prevented, minimized, or reduced even if moisture permeates through the inner surface of the via 10H.

[0232] For reference Figure 18 It is shown that the first groove G1 and the second groove G2 are located between the second partition wall PW2 and the opening region OA, and the number of protruding tips protruding towards the center of the first groove G1 is two, and the number of protruding tips protruding towards the center of the second groove G2 is two. For example, Figure 18 Four protruding tips are shown located between the second partition wall PW2 and the opening region OA. Figure 19 It is shown that there are two protruding tips protruding toward the center of a groove G located between the second partition wall PW2 and the opening region OA, and there is one protruding tip protruding in the direction from the groove G toward the opening region OA. For example, Figure 19 Three protruding tips are shown located between the second partition wall PW2 and the opening region OA.

[0233] exist Figure 19 In the display panel 10 shown, the inorganic layer above the substrate 100 and included in the display layer DIL has additional grooves AG as described herein, so that even if moisture permeates through the inner surface of the through-hole 10H, the movement of moisture toward the display area DA can be effectively prevented, minimized, or reduced. Therefore, in Figure 19 The number of protruding tips can be reduced in the display panel 10 shown.

[0234] For reference Figure 18 and Figure 19 Both show two grooves G between the first partition wall PW1 and the second partition wall PW2, and two protruding tips protruding toward the center of each of the grooves G. For example, Figure 18 and Figure 19 All embodiments show four protruding tips between the first partition wall PW1 and the second partition wall PW2. However, one or more embodiments are not limited to this. Figure 19As shown, when the inorganic layer above the substrate 100 and included in the display layer DIL has an additional groove AG, the number of protruding tips between the first separator wall PW1 and the second separator wall PW2 may be less than four. For example, when the inorganic layer above the substrate 100 and included in the display layer DIL has an additional groove AG, there may be three protruding tips between the first separator wall PW1 and the second separator wall PW2.

[0235] Although one or more embodiments have been described with reference to the examples shown in the accompanying drawings, these are merely examples, and those skilled in the art will understand that various suitable modifications and other equivalent embodiments are thus possible. Therefore, the true scope of protection should be determined by the technical concept of the appended claims and their equivalents.

[0236] According to one or more embodiments described herein, a method for manufacturing a display panel with a low defect rate, a display panel manufactured by the method, and an electronic device including the display panel can be implemented. However, the scope of disclosure is not limited to the foregoing.

[0237] Terms such as “basically,” “about,” and “approximately” are used as relative terms rather than terms of degree and are intended to account for inherent biases in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. They may include the stated value and an acceptable range of deviation as determined by one of ordinary skill in the art, taking into account limitations and errors associated with the measurement of the quantity. For example, “about” may refer to one or more standard deviations, or ±30%, ±20%, ±10%, or ±5% of the stated value.

[0238] The numerical ranges disclosed herein include, and are intended to include, all subranges having the same numerical precision. For example, the range “1.0 to 10.0” includes all subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (e.g., 2.4 to 7.6). Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges included within the ranges expressly described herein.

[0239] The display panel, electronic device, apparatus for manufacturing the electronic device, and / or any other related apparatus or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, one or more suitable components of the display panel and / or electronic device may be disposed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, one or more suitable components of the display panel and / or electronic device may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or disposed on a substrate. Additionally, one or more suitable components of the display panel and / or electronic device may be a process or thread running on one or more processors in one or more computing devices, executing computer program instructions, and interacting with other system components to perform one or more suitable functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored on other non-transitory computer-readable media, such as CD-ROMs and / or flash drives. Furthermore, those skilled in the art should recognize that, without departing from the scope of the embodiments of this disclosure, the functions of one or more suitable computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0240] In the context of this application, unless otherwise defined, the term “use” and its variations may be considered synonymous with the term “utilize” and its variations, respectively.

[0241] It will be understood by those skilled in the art that, in view of the entirety of this disclosure, various suitable features of one or more suitable embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in one or more suitable ways, and unless otherwise stated or implied, the various embodiments may be implemented independently of each other or in any suitable combination with each other.

[0242] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that one or more suitable changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A method of manufacturing a display panel, the method comprising the steps of: providing a display layer on a first surface of a substrate, the substrate including the first surface and a second surface, the first surface being opposite to the second surface; etching the second surface to reduce a thickness of the substrate and to remove a portion of the substrate corresponding to a hole forming area to form a first hole in the substrate; providing a polarizing layer corresponding to an entire surface of the display layer, the display layer being between the polarizing layer and the substrate; and providing a second hole coupled to the first hole by removing a portion of the polarizing layer and a portion of the display layer, each of the portion of the polarizing layer and the portion of the display layer corresponding to an edge of the hole forming area. providing a scribe in the substrate, the scribe corresponding to the edge of the hole forming area, 2. The method of claim 1, further comprising the step of: wherein the step of etching the second surface includes applying an etchant to penetrate the scribe and removing the portion of the substrate corresponding to the hole forming area. The step of providing the second hole includes irradiating a laser beam to the portion of the polarizing layer corresponding to the edge of the hole forming area.

3. The method of claim 1, wherein, The step of providing the second hole includes irradiating the laser beam to the portion of the polarizing layer until a portion of the first surface corresponding to the edge of the hole forming area is exposed.

4. The method of claim 3, wherein, providing a bottom protection layer covering a lower surface of the display layer, the second surface, and an inner side surface of the first hole, wherein the lower surface of the display layer is exposed by the first hole.

5. The method of claim 3, further comprising the step of: The step of providing the second hole includes irradiating the laser beam to remove a portion of the bottom protection layer on the inner side surface of the first hole.

6. The method of claim 5, wherein, The step of providing the second hole includes irradiating the laser beam to remove a portion of the bottom protection layer on the second surface and to expose a portion of the second surface around the first hole.

7. The method of claim 6, wherein, 8. A display panel, the display panel comprising: a substrate including a first surface, a second surface opposite to the first surface, and a first hole passing through the first surface and the second surface; a display layer; and a polarizing layer on the display layer, wherein the display layer and the polarizing layer are on the first surface and include a second hole superimposed with the first hole when viewed in a direction perpendicular to the substrate, and wherein an inner side surface of the second hole is a continuous surface of the first surface without a step and a portion of the first surface between the display layer and the first hole does not include an organic film. An area of the second hole at a lower surface of the polarizing layer in a direction toward the display layer is equal to an area of the second hole at an upper surface of the display layer in a direction toward the polarizing layer.

9. The display panel of claim 8, wherein, The second hole is configured to expose a portion of the first surface.

10. The display panel of claim 8, wherein, The portion of the first surface is around the first hole.

11. The display panel of claim 10, wherein, ​ 12.The display panel according to claim 8, further comprising a bottom protection layer on the second surface and including a third hole corresponding to the first hole.

13. The display panel of claim 12, wherein, An area of the third hole is larger than an area of the first hole.

14. The display panel of claim 13, wherein, An area of the third hole at an upper surface of the bottom protection layer in a direction toward the substrate is equal to an area of the second hole at a lower surface of the display layer in the direction toward the substrate.

15. The display panel of claim 13, wherein, An edge of the third hole overlaps with an edge of the second hole at a lower surface of the display layer in a direction toward the substrate when viewed in a direction perpendicular to the substrate.

16. The display panel of claim 12, wherein, An edge of the third hole of the bottom protection layer includes a heat-deformed portion.

17. The display panel of claim 8, wherein, An edge of the second hole of the polarizing layer includes a heat-deformed portion. 18.An electronic device comprising: a display panel; a camera; and a lower cover, wherein the display panel includes a substrate including a first surface, a second surface opposite to the first surface, and a first hole passing through the first surface and the second surface, a display layer, and a polarizing layer on the display layer, wherein the display layer and the polarizing layer are over the first surface and include a second hole overlapping with the first hole when viewed in a direction perpendicular to the substrate, wherein an inner side surface of the second hole is a continuous surface without a step up to the first surface, a portion of the first surface between the display layer and the first hole does not include an organic film, and wherein the camera is between the display panel and the lower cover. An area of the second hole at a lower surface of the polarizing layer in a direction toward the substrate is equal to an area of the second hole at an upper surface of the display layer in a direction toward the polarizing layer.

19. The electronic device of claim 18, wherein, The second hole is configured to expose a portion of the first surface.

20. The electronic device of claim 18, wherein, ​

Images