Wafer adsorption system, and process equipment and process method of semiconductor device

Abstract

The invention discloses a wafer adsorption system, process equipment of a semiconductor device and a process method of the semiconductor device. The wafer adsorption system comprises an electrostatic chuck which is used for placing a wafer, and the surface of the electrostatic chuck is provided with a suction flow channel which is located in the edge area of the wafer; and the gas extraction device is connected with the gas extraction flow channel through a first pipeline group comprising a valve so as to extract the process gas retained in the edge area of the wafer through the gas extraction channel in the deposition process. According to the invention, the abnormal film growth phenomenon at the edge of the wafer can be effectively improved, so that the process yield is improved, the process precision is guaranteed, and the product reliability is improved.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor manufacturing, and specifically to a semiconductor device process equipment, a semiconductor device process method, and a computer-readable storage medium. Background Technology

[0002] In semiconductor manufacturing, wafers must be kept absolutely flat in a vacuum or plasma environment to prevent micron-level displacement from causing circuit failure. Traditional mechanical chucks can easily cause edge damage to wafers when holding them in place. Currently, vacuum chucks and electrostatic chucks are commonly used for wafer adsorption and fixation.

[0003] However, vacuum chucks fail in low-pressure environments. Furthermore, as wafer warpage increases, vacuum chucks gradually become insufficient to meet production demands. Electrostatic chucks, on the other hand, can attract wafers using electrostatic forces. For example, bipolar electrostatic chucks can optimize the electric field distribution by incorporating positive and negative electrodes, thereby ensuring the attraction force and uniformity of wafers and reducing the probability of wafer warpage.

[0004] However, when wafer warpage becomes excessive, a localized electric field forms in the gap between the wafer edge and the electrostatic chuck. Furthermore, because the wafer is situated in a process environment permeated with process gases, this localized electric field attracts charged byproducts from deposition processes (such as the TEOS reaction), leading to abnormal film deposition at the wafer edge. This abnormally long film not only easily causes edge film detachment leading to particulate contamination, but also causes stress concentration at the wafer edge resulting in breakage, deterioration of uniformity in subsequent processes, and decreased packaging reliability, severely impacting process yield and product performance.

[0005] To address the aforementioned problems in prior art, there is an urgent need in the field for a wafer adsorption technology that can effectively improve the abnormally long film phenomenon at the wafer edge, thereby increasing process yield, ensuring process accuracy, and enhancing product reliability. Summary of the Invention

[0006] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0007] To overcome the aforementioned deficiencies in prior art, this invention provides a wafer adsorption system, a semiconductor device process equipment, a semiconductor device process method, and a computer-readable storage medium, which can effectively improve the abnormal long film phenomenon at the wafer edge, thereby improving process yield, ensuring process accuracy, and enhancing product reliability.

[0008] Specifically, the wafer adsorption system provided according to the first aspect of the present invention includes: an electrostatic chuck for placing a wafer, wherein the surface of the electrostatic chuck is provided with an air extraction channel located in the edge region of the wafer; and an air extraction device connected to the air extraction channel via a first pipeline assembly including valves to extract process gases trapped in the edge region of the wafer via the air extraction channel during the deposition process.

[0009] Furthermore, in some embodiments of the present invention, the gas extraction channel includes an annular channel disposed on the outer edge of the wafer.

[0010] Furthermore, in some embodiments of the present invention, the air extraction channel includes a plurality of through holes arranged around the outer edge of the wafer.

[0011] Furthermore, in some embodiments of the present invention, the vias include lateral vias and / or longitudinal vias to extract process gases laterally and / or longitudinally from the edge regions of the wafer.

[0012] Furthermore, in some embodiments of the present invention, the exhaust channel is arranged annularly below the edge of the wafer, and its outer ring radius is smaller than the wafer radius. An exhaust cavity is formed between the lower surface of the wafer and the exhaust channel, so as to increase the pressure difference between the upper and lower surfaces of the wafer edge region through the exhaust cavity during the extraction of the process gas.

[0013] Furthermore, in some embodiments of the present invention, the surface of the electrostatic chuck is provided with a sealing ring located outside the exhaust channel, serving as the outer wall of the exhaust cavity to seal the exhaust cavity during the extraction of the process gas.

[0014] Furthermore, in some embodiments of the present invention, a plurality of micro-protrusions are distributed in the central area of ​​the surface of the electrostatic chuck, and a plurality of micro-channels are formed between adjacent micro-protrusions. The air extraction device is connected to the micro-channels via the first pipeline group to continuously extract the gas between the wafer and the electrostatic chuck during the electrostatic adsorption of the wafer.

[0015] Furthermore, the semiconductor device process equipment provided according to the second aspect of the present invention includes: a reaction chamber in which a wafer is placed for a deposition process; the wafer adsorption system provided in the first aspect of the present invention, disposed in the reaction chamber, for completely adsorbing the wafer onto the surface of an electrostatic chuck during the deposition process; and a second pipeline assembly connecting the reaction chamber and an air extraction device for extracting reaction byproducts from the reaction chamber after the deposition process is completed.

[0016] Furthermore, the process method for the semiconductor device provided in the third aspect of the present invention is implemented via the process equipment for the semiconductor device provided in the second aspect of the present invention. The process method includes the following steps: after the wafer is fed into the reaction chamber, a preset process formulation is executed; during the deposition process, an electrostatic chuck is activated and a valve in the pipeline assembly is opened to completely adsorb the wafer onto the surface of the electrostatic chuck; and in response to the completion of the deposition process, a valve in the first pipeline assembly is closed and a second pipeline assembly is opened to extract the reaction byproducts from the reaction chamber.

[0017] Furthermore, according to a fourth aspect of the present invention, a computer-readable storage medium is provided having computer instructions stored thereon. When the computer instructions are executed by a processor, a process method for implementing the semiconductor device described above according to the third aspect of the present invention is implemented. Attached Figure Description

[0018] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0019] Figure 1 A schematic diagram of a process apparatus for a semiconductor device according to some embodiments of the present invention is shown.

[0020] Figure 2 A cross-sectional schematic diagram of the air extraction channel of the annular flow channel structure provided according to some embodiments of the present invention is shown.

[0021] Figure 3A A cross-sectional schematic diagram of the air extraction channel of the through-hole structure provided according to some embodiments of the present invention is shown.

[0022] Figure 3B A cross-sectional schematic diagram of the air extraction channel of the transverse through-hole structure provided according to some embodiments of the present invention is shown.

[0023] Figure 3CA top view of the air extraction channel of the through-hole structure provided according to some embodiments of the present invention is shown.

[0024] Figure 4A A cross-sectional schematic diagram of an air extraction channel provided according to other embodiments of the present invention is shown.

[0025] Figure 4B for Figure 4A The diagram shows a top view of the air extraction duct.

[0026] Figure 5 A flowchart of a process method for a semiconductor device according to some embodiments of the present invention is shown.

[0027] Figure label:

[0028] 100 process equipment;

[0029] 110 reaction chamber;

[0030] 120 Second Pipeline Assembly;

[0031] 200 wafer adsorption system;

[0032] 210 electrostatic chuck;

[0033] 211 Annular Flow Channel;

[0034] 212 through hole;

[0035] 220 air extraction device;

[0036] 230 First Pipeline Group;

[0037] 231 valve;

[0038] 410 air extraction channel;

[0039] 411 slot;

[0040] 412 air extraction port;

[0041] 420 vacuum cavity;

[0042] 430 sealing ring;

[0043] 440 micro-bosses;

[0044] 441 microchannels;

[0045] Steps S510~S530. Detailed Implementation

[0046] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0047] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0048] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0049] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0050] As mentioned above, vacuum chucks fail in low-pressure environments. While electrostatic chucks can reduce the probability of wafer warpage, excessive wafer warpage can create a localized electric field in the gap between the wafer edge and the electrostatic chuck. Furthermore, because the wafer is in a process environment permeated with process gases, this localized electric field can attract charged byproducts from deposition processes (such as the TEOS reaction), leading to abnormal film deposition at the wafer edge. This abnormally long film not only easily causes edge film detachment leading to particulate contamination, but also causes stress concentration at the wafer edge leading to breakage, deterioration of uniformity in subsequent processes, and decreased packaging reliability, severely impacting process yield and product performance.

[0051] To address the aforementioned problems in the prior art, this invention provides a wafer adsorption system, a semiconductor device process equipment, a semiconductor device process method, and a computer-readable storage medium, which can effectively improve the abnormal long film phenomenon at the wafer edge, thereby improving process yield, ensuring process accuracy, and enhancing product reliability.

[0052] In some non-limiting embodiments, the wafer adsorption system provided in the first aspect of the present invention can be configured in the process equipment of the semiconductor device provided in the second aspect of the present invention, and used to implement the process method of the semiconductor device provided in the third aspect of the present invention.

[0053] Specifically, in some non-limiting embodiments, the computer-readable storage medium described above in the fourth aspect of the present invention stores a computer program product thereon. The computer program product includes computer instructions. A processor is connected to the memory and configured to execute the computer instructions included in the computer program product to implement a process method for a semiconductor device as provided in the third aspect of the present invention.

[0054] The working principle of the wafer adsorption system described below will be described with reference to embodiments of semiconductor device process equipment and methods. Those skilled in the art will understand that these embodiments of semiconductor device process equipment and methods are merely non-limiting implementations provided by the present invention, intended to clearly demonstrate the main concepts of the invention and provide specific solutions convenient for public implementation, rather than limiting all operating modes or functions of the wafer adsorption system. Similarly, the wafer adsorption system is also only one non-limiting implementation provided by the present invention, and does not limit all operating modes or functions of these semiconductor device process equipment, or the implementing entities of each step in the semiconductor device process methods.

[0055] First, please refer to Figure 1 . Figure 1A schematic diagram of a process apparatus for a semiconductor device according to some embodiments of the present invention is shown.

[0056] like Figure 1 As shown, in some embodiments of the present invention, the semiconductor device process equipment 100 may mainly include a reaction chamber 110, a wafer adsorption system 200, and a second pipeline group.

[0057] Specifically, in Figure 1 In the illustrated embodiment, a wafer is placed inside the reaction chamber 110 for the deposition process. This reaction chamber 110 can adapt to the timing requirements of various thin film preparation processes such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and metal-organic chemical vapor deposition (MOCVD), and can be configured with corresponding structures and accessories, which are not limited here. Optionally, the process equipment 100 may include multiple reaction chambers 110 to improve equipment efficiency and increase output. A wafer adsorption system 200 can be located within several reaction chambers 110 to completely adsorb the wafers onto the surface of electrostatic chucks during the deposition process. A second piping group 120 can connect each reaction chamber 110 to a vacuum device 220 to extract reaction byproducts from each reaction chamber 110 after the deposition process for chamber cleaning. Optionally, the second piping group 120 can directly use a foreline to reduce modifications to existing equipment.

[0058] Furthermore, such as Figure 1 As shown, the wafer adsorption system 200 mainly includes an electrostatic chuck 210 and a vacuum device 220. The electrostatic chuck 210 is used to place the wafer. Furthermore, based on an existing electrostatic chuck (such as a bipolar electrostatic chuck), a vacuum channel is added to its surface. This vacuum channel is located in the edge region of the wafer.

[0059] The extraction device 220 can be connected to the extraction air passage via a first conduit assembly 230 including a valve 231. Specifically, in Figure 1 In the illustrated embodiment, two gas lines of equal length can be connected from the bottom of the two electrostatic chucks 210 to the support base and converge at valve 231. A line then extends from valve 231 to a second pipeline group 120, forming an airflow path between the surface of the electrostatic chucks 210 and the second pipeline group 120 (such as a pre-line pipeline). Using the extraction device 220, process gases trapped in the edge region of the wafer can be extracted via the extraction channel during the deposition process within the reaction chamber 110, thereby improving the long film formation at the wafer edge.

[0060] Next, please refer to Figure 2 . Figure 2A cross-sectional schematic diagram of the air extraction channel of the annular flow channel structure provided according to some embodiments of the present invention is shown.

[0061] like Figure 2 As shown, in some optional embodiments, the extraction channel may include an annular channel 211 disposed on the outer edge of wafer 01. The annular channel 211 corresponds to the area outside the coverage of wafer 01. In this embodiment, by forming an annular channel 211 on the disk surface on the outer edge of wafer 01, the process gas at the edge of wafer 01 can be extracted by the extraction device 220 through the annular channel 211, so that it does not remain in the pocket position at the edge of wafer 01, thereby improving the situation of long films at the wafer edge.

[0062] In addition, the present invention provides other embodiments. Please see below. Figure 3A and Figure 3C . Figure 3A A cross-sectional schematic diagram of the air extraction channel of the through-hole structure provided according to some embodiments of the present invention is shown. Figure 3C A top view of the air extraction channel of the through-hole structure provided according to some embodiments of the present invention is shown.

[0063] In such Figure 3A and Figure 3C In the illustrated embodiment, the extraction channel may include a plurality of through-holes 212 arranged around the outer edge of wafer 01. The through-holes 212 correspond to the area outside the coverage of wafer 01. In this embodiment, by opening through-holes 212 on the disk surface outside the edge of wafer 01, process gases at the edge of wafer 01 can be extracted through the through-holes 212 and then by the extraction device 220, so that they do not remain in the pocket position at the edge of wafer 01, thereby improving the situation of long films at the wafer edge.

[0064] In some embodiments of the present invention, the flow direction of the through hole 212 is not limited. Those skilled in the art can make adaptive designs based on the available space at the edge position of the electrostatic chuck 210 of different specifications and types.

[0065] Specifically, such as Figure 3A As shown in these optional embodiments, if the lateral space at the edge of the electrostatic chuck 210 is limited, the through-hole 212 can be configured as a vertical through-hole. Through the vertical through-hole, process gases in the edge region of wafer 01 can be extracted vertically (e.g., ...). Figure 3A (As indicated by the arrow in the image).

[0066] For example, please see Figure 3B . Figure 3B A cross-sectional schematic diagram of the air extraction channel of the transverse through-hole structure provided according to some embodiments of the present invention is shown.

[0067] like Figure 3B and Figure 3C As shown, in some alternative embodiments, if the longitudinal space at the edge of the electrostatic chuck 210 is limited, the via 212 can be configured as a lateral via. Through the lateral via, process gases in the edge region of wafer 01 can be laterally extracted (e.g., ...). Figure 3B (As indicated by the arrow in the image).

[0068] In addition, combined Figure 3A and Figure 3B As shown, in some optional embodiments, if there is sufficient space at the edge of the electrostatic chuck 210 in both the horizontal and vertical directions, horizontal and vertical through holes can be opened simultaneously on the outer side of the wafer edge to accelerate the extraction rate of process gas at the wafer edge and ensure that the process gas at that location is completely extracted.

[0069] Next, please refer to Figure 4A . Figure 4A A cross-sectional schematic diagram of an air extraction channel provided according to other embodiments of the present invention is shown.

[0070] like Figure 4A In the illustrated embodiment, the gas extraction channel 410 can be annularly disposed below the edge of the wafer. The outer radius of the gas extraction channel 410 is smaller than the radius of the wafer 01. A gas extraction cavity 420 is formed between the lower surface of the wafer 01 and the gas extraction channel 410. During the process of extracting process gases through the gas extraction channel 410, the pressure difference between the upper and lower surfaces of the edge region of the wafer 01 can be increased through the sealed gas extraction cavity 420, thereby providing targeted adsorption force for the edge of the wafer 01 and helping to improve the long film condition at the wafer edge.

[0071] Preferably, continue as follows Figure 4AAs shown, the surface of the electrostatic chuck 210 can be provided with a sealing ring 430. The sealing ring 430 can be located outside the suction channel 410, serving as the outer wall of the suction cavity 420. That is, the sealing ring 430, the lower surface of the wafer 01, and the bottom surface and inner wall of the suction channel 410 can together form a sealed suction cavity 420. By replacing the outer wall of the suction cavity 420 with the sealing ring 430, the suction cavity 420 can be sealed during the extraction of process gas, preventing gas leakage at the edge of the wafer 01. Once the suction cavity 420 leaks during the extraction of process gas, the pressure difference between the upper and lower surfaces of the edge region of the wafer 01 will decrease, thereby reducing the vacuum adsorption force of the electrostatic chuck 210 on the edge of the wafer 01, and thus failing to meet the adsorption requirements for wafers with high warpage. In other words, in this embodiment, by adding a suction cavity 420 below the edge of the wafer 01, it is equivalent to adding a vacuum adsorption function to the traditional electrostatic chuck. The electrostatic chuck 210 with wafer edge vacuum adsorption function can not only remove the process gas at the edge of wafer 01 through the pumping device 220 so that it does not remain in the pocket position at the edge of wafer 01, but also reduce the gap between the edge of wafer 01 and the surface of the electrostatic chuck, thereby avoiding the formation of local electric field from the source, and thus further improving the long film condition at the wafer edge.

[0072] Continue as Figure 4A As shown, in some preferred embodiments, the central area of ​​the surface of the electrostatic chuck 210 may also be distributed with multiple dimples 440, forming an array of dimples. Multiple microchannels 441 can be formed between adjacent dimples 440. The vacuum device 220 can be connected to the microchannels 441 via the first conduit group 230 to continuously extract gas between the wafer 01 and the electrostatic chuck 210 during the electrostatic wafer adsorption process. In this embodiment, the array of dimples 440 allows the electrostatic chuck 210 to perform both electrostatic adsorption and vacuum adsorption modes. Before the deposition process, the vacuum device 220 can use these microchannels 441 as vacuum channels to quickly expel air between the wafer 01 and the electrostatic chuck 210, thereby helping to improve the adhesion of the electrostatically adsorbed wafer. Especially when combined with the aforementioned vacuum cavity 420 located below the edge of wafer 01, the electrostatic chuck, which includes vacuum adsorption functions in both the central and edge regions, not only overcomes the shortcomings of traditional electrostatic chucks—such as uneven distribution of electrostatic adsorption force for high-warpage wafers and inability to overcome the wafer's own warpage stress—but also overcomes the problem of traditional vacuum chucks being prone to failure under low-pressure environments. It can meet the adsorption requirements of large-size, high-warpage wafers.

[0073] In addition, please combine Figure 4B A shared understanding. Figure 4B for Figure 4AThe diagram shows a top view of the air extraction duct.

[0074] like Figure 4B As shown, in some embodiments, the suction channel 410 located at the edge region of the electrostatic chuck 210 can be connected to the micro-channel 441 located in the central region, thereby enabling vacuum adsorption of both the edge and center regions of the wafer 01 using only one suction device 220. Specifically, for example, slots 411 can be formed in the four directions of 3, 6, 9, and 12 o'clock of the suction channel 410 to connect the suction channel 410 and the micro-channel 441 in the central region. Furthermore, a suction hole 412 can be present in the central region of the electrostatic chuck 210, with a support base connected below it to guide process gas outwards during suction. Figure 1 and Figure 4B It is understood that only by connecting the exhaust channel 410 and the microchannel 441 can a passage be formed for the gas on the surface of the electrostatic chuck 210. The exhaust path of the process gas at the edge of wafer 01 is to pass through the exhaust channel 410, the microchannel 441, and the exhaust hole 412 in sequence, be drawn into the second pipeline group 120, and finally enter the exhaust device 220.

[0075] Optionally, combined Figure 2 As shown in Figure 4, in Figure 2 In the provided embodiments, the annular flow channel 211 located on the outer edge of the surface of the electrostatic chuck 210 can be connected to the micro flow channel 441 located in the central region. This allows for the removal of process gas trapped in the edge region of the wafer 01 and vacuum adsorption of its central region using only one set of pumping device 220, achieving two different functions.

[0076] This concludes the basic description of the semiconductor device process equipment 100 provided in the first aspect of the present invention, and the wafer adsorption system 200 provided in the second aspect of the present invention disposed therein. Next, please refer to... Figure 5 To gain a clearer understanding of the working principle of the wafer adsorption system 200 described above. Figure 5 A flowchart of a process method for a semiconductor device according to some embodiments of the present invention is shown.

[0077] like Figure 5 As shown, in some embodiments, the semiconductor device manufacturing process can be implemented via the semiconductor device manufacturing equipment 100 described above. The semiconductor device manufacturing process mainly includes steps S510 to S530.

[0078] First, step S510 can be performed: after the wafer is fed into the reaction chamber, the preset process formula is executed.

[0079] Specifically, combined Figure 1 It is understood that after the wafer is fed into the reaction chamber 110, the process pressure and temperature within the chamber can be adjusted to achieve the target range of the process formulation. For example, the process pressure within the chamber can be adjusted to 0~600 torr, and the temperature within the chamber can be adjusted to 400~540℃.

[0080] Then, step S520 can be performed: during the deposition process, the electrostatic chuck is turned on and the valve in the pipeline group is opened to completely adsorb the wafer onto the surface of the electrostatic chuck.

[0081] Specifically, combined Figure 1 and Figure 2 , Figure 3A or Figure 3B As shown, in some embodiments, during the deposition process, valve 231 in the first pipeline group 230 can be opened to extract the process gas at the edge of the wafer via the suction device 220 and the suction channel in the electrostatic chuck 210 located outside the edge of the wafer 01, so that it does not remain in the pocket position at the edge of the wafer 01, thereby improving the situation of abnormally long films at the edge of the wafer.

[0082] Furthermore, combined Figure 1 and Figure 4A As shown, in some other embodiments, during the deposition process, after opening valve 231 in the first pipeline group 230, the process gas at the wafer edge can be extracted via the suction device 220 through the suction channel 410 located below the edge of the electrostatic chuck 210. Simultaneously, the pressure difference between the upper and lower surfaces of the wafer edge region can be increased. In this embodiment, not only can the process gas trapped in the pocket position at the edge of the wafer 01 be removed by suction, but the gap between the wafer 01 edge and the surface of the electrostatic chuck can also be reduced, enhancing the adsorption force on the high warp wafer edge position, thus preventing the formation of local electric fields from the source, thereby further improving the long film condition at the wafer edge.

[0083] Next, step S530 can be performed: in response to the completion of the deposition process, the valve in the first pipeline group is closed and the second pipeline group is opened to extract the reaction byproducts in the reaction chamber.

[0084] Specifically, continue to combine Figure 1 It is understood that in some embodiments, valve 231 can be closed after the chamber deposition process and purging step are completed. Afterwards, the wafer can be subjected to quality inspection to verify whether there are any abnormalities in the thin film deposition at the wafer edges. For example, the wafer can be sliced ​​and then observed using a scanning electron microscope (SEM) to see if there are any abnormally long films at the wafer edges.

[0085] In summary, the present invention provides a wafer adsorption system, a semiconductor device process equipment, a semiconductor device process method, and a computer-readable storage medium, which can effectively improve the abnormal long film phenomenon at the wafer edge, thereby improving process yield, ensuring process accuracy, and enhancing product reliability.

[0086] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0087] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in a generalized manner in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0088] The various illustrative logic modules and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0089] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0090] In one or more exemplary embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functionality may be stored or transmitted as one or more instructions or code on or through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Any connection is also legitimately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used in this article, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0091] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer chucking system, comprising: The system comprises: an electrostatic chuck on which a wafer is placed, wherein a surface of the electrostatic chuck is provided with an evacuation flow channel located at an edge region of the wafer; and an evacuation device connected to the evacuation flow channel via a first pipe set comprising valves to evacuate process gas remaining at the edge region of the wafer via the evacuation channel during a deposition process. The evacuation flow channel comprises an annular flow channel arranged outside the edge of the wafer.

2. The wafer chucking system of claim 1, wherein, The evacuation flow channel comprises a plurality of through holes arranged around the outside of the edge of the wafer.

3. The wafer chucking system of claim 1, wherein, The through holes comprise transverse through holes and / or longitudinal through holes to evacuate process gas at the edge region of the wafer transversely and / or longitudinally.

4. The wafer chucking system of claim 3, wherein, The evacuation flow channel is annularly arranged below the edge of the wafer, and has an outer ring radius smaller than the radius of the wafer, forming an evacuation cavity between the lower surface of the wafer and the evacuation flow channel to increase the pressure difference between the upper and lower surfaces of the edge region of the wafer during evacuation of the process gas.

5. The wafer chucking system of claim 1, wherein, The surface of the electrostatic chuck is provided with a sealing ring located outside the evacuation flow channel as an outer sidewall of the evacuation cavity to seal the evacuation cavity during evacuation of the process gas.

6. The wafer chucking system of claim 5, wherein, The surface of the electrostatic chuck is provided with a plurality of micro-bumps distributed in a central region, and a plurality of micro-flow channels are formed between adjacent micro-bumps, and the evacuation device is connected to the micro-flow channels via the first pipe set to continuously evacuate gas between the wafer and the electrostatic chuck during electrostatic adsorption of the wafer.

7. The wafer chucking system of claim 5, wherein, The system comprises:

8. A process apparatus for a semiconductor device, characterized by comprising: a reaction chamber in which a wafer is placed for a deposition process; a wafer adsorption system as claimed in any one of claims 1 to 7 arranged in the reaction chamber to completely adsorb the wafer on a surface of an electrostatic chuck during the deposition process of the wafer; and a second pipe set connected to the reaction chamber and an evacuation device to evacuate reaction byproducts in the reaction chamber after the deposition process is completed. The process method comprises the following steps when implemented via a process equipment of a semiconductor device as claimed in claim 8: after the wafer is sent into the reaction chamber, a preset process recipe is executed; 9. A process method for a semiconductor device, characterized by, during the deposition process, the electrostatic chuck is turned on and the valves in the pipe set are opened to completely adsorb the wafer on the surface of the electrostatic chuck; and in response to completion of the deposition process, the valves in the first pipe set are closed and the second pipe set is opened to evacuate reaction byproducts in the reaction chamber. The computer instructions are executed by the processor to implement the process method of a semiconductor device as claimed in claim 9. The computer instructions are executed by the processor to implement the process method of a semiconductor device as claimed in claim 9.

10. A computer readable storage medium having stored thereon computer instructions, wherein, ​

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