Formation method of aluminum interconnection structure
By forming grooves in the dielectric layer and filling them with aluminum metal layers during the back-end fabrication of semiconductor devices, the problems of increased resistivity and decreased yield in copper interconnect structures are solved, and an aluminum interconnect structure with low resistivity and high yield is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-03-10
AI Technical Summary
In semiconductor integrated circuit manufacturing, as critical dimensions decrease, the resistivity of copper metal lines increases, leading to increased RC delay and decreased yield. The problem of poor step coverage in PVD process is difficult to solve.
After forming a groove in the dielectric layer, a barrier layer is first formed, and then an aluminum metal layer is filled into the groove through at least two deposition cycles. The aluminum metal layer is then melted by heat treatment or radiation baking to fill the groove, which solves the problem of poor step coverage in the PVD process.
This achieves low resistivity in aluminum interconnect structures with small dimensions, improving the yield and electrical performance of semiconductor devices.
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Figure CN121646342A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a forming method of an aluminum interconnection structure. BACKGROUND
[0002] In the back end of line (BEOL) process of semiconductor integrated circuit manufacturing, in order to reduce the resistor-capacitance delay, it is necessary to reduce the resistivity of the metal line in the metal interconnection structure as much as possible. Since copper (Cu) is the non-precious metal with the lowest resistivity, copper is generally selected as the metal line in the current metal interconnection structure.
[0003] However, with the reduction of the critical dimension (CD) of the metal line in the metal interconnection structure, the use of copper as the metal line is restricted in the following aspects, resulting in the decline of the reliability and yield of semiconductor device products: (1) Since the seed layer of the copper metal line is generally formed by a physical vapor deposition (PVD) process, the poor step coverage of this process is particularly obvious at a small size; (2) The size effect of the resistivity of the metal line is increasingly obvious, and copper no longer has the advantage of low resistance; (3) The material of the barrier layer replaces the material of the metal line, and becomes the main source of the resistivity in the metal interconnection structure.
[0004] Therefore, copper is no longer the best choice for the metal line that is most conducive to reducing RC delay and ensuring yield. In view of this, it is urgent to provide a new metal interconnection structure that can have lower resistivity and higher yield on the basis of reducing RC delay. SUMMARY
[0005] The present application provides a forming method of an aluminum interconnection structure, which can solve the problem of low yield and high resistivity of the copper metal line at a small width in the related art, and the method comprises:
[0006] forming a groove in a dielectric layer, the width of the groove being less than 30 nanometers, the dielectric layer being formed above a substrate, the substrate being used to form a semiconductor device;
[0007] forming a barrier layer on the surface of the dielectric layer and the groove;
[0008] forming an aluminum metal layer to fill the groove through at least two deposition cycles;
[0009] performing a planarization process to remove the aluminum metal layer and the barrier layer outside the groove;
[0010] The deposition cycle includes: forming an aluminum metal layer by a PVD process, and performing heat treatment or radiation baking treatment on the aluminum metal layer to melt the aluminum metal layer to reduce the accumulation of aluminum at the recess opening.
[0011] In some embodiments, the thickness of the aluminum metal layer formed by the PVD process in each deposition cycle is 5 angstroms to 60 angstroms.
[0012] In some embodiments, the temperature of the heat treatment or radiation baking in each deposition cycle is 100 degrees Celsius to 350 degrees Celsius.
[0013] In some embodiments, the thickness of the barrier layer is 5 angstroms to 30 angstroms.
[0014] In some embodiments, the barrier layer includes a titanium nitride layer.
[0015] In some embodiments, the forming of the barrier layer on the surface of the dielectric layer and the recess includes:
[0016] The barrier layer is formed by depositing a titanium nitride layer by a CVD process.
[0017] In some embodiments, the forming of the barrier layer on the surface of the dielectric layer and the recess includes:
[0018] The barrier layer is formed by depositing a titanium nitride layer by an ALD process.
[0019] The technical solution of the present application has at least the following advantages:
[0020] By forming a barrier layer after forming a recess in a dielectric layer in the back-end-of-line process of a semiconductor device, and then filling an aluminum metal layer in the recess by at least two deposition cycles, the problem of filling defects caused by poor step coverage of the PVD process is solved, and since the resistivity of aluminum is higher than that of copper at a width of 30 nanometers, the yield and electrical performance of the device product are improved. BRIEF DESCRIPTION OF DRAWINGS
[0021] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.
[0022] Figure 1 is a simulation diagram of the resistivity of different metals at different widths;
[0023] Figure 2is a simulation diagram of resistivity of copper metal lines and aluminum metal lines under different widths;
[0024] Figure 3 is a simulation diagram of resistivity of copper contact holes and aluminum contact holes under different heights and different metal line widths;
[0025] Figure 4 is a flow chart of a forming method of an aluminum interconnection structure provided by an exemplary embodiment of the present application;
[0026] Figures 5 to 13 is a schematic diagram of a forming process of an aluminum interconnection structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0027] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present application.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0029] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements, or it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0030] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0031] The RC delay of the metal layer can be calculated by the following formula:
[0032]
[0033] where RC is the RC delay of the metal layer, p is the resistivity of the metal layer, k is the relative dielectric constant, e0 is the vacuum permittivity, L is the length of the metal layer, p is the critical dimension (usually the width) of the metal layer, and T is the thickness of the metal layer (or the inter-layer dielectric (ILD) layer). As can be seen from the formula, for a patterned metal interconnect structure, the key to reducing the RC delay is to reduce the resistivity.
[0034] However, as mentioned above, due to the reduction of the critical dimension, the thickness of the barrier layer cannot be reduced indefinitely to ensure its functionality, and thus the volume of the metal line in the trench of the metal interconnect structure decreases, resulting in a decrease in its contribution to the resistivity.
[0035] Under the condition of taking into account the surface scattering effect, the resistivity of the metal layer can be calculated by the following formula:
[0036]
[0037] p0 is the resistivity of the metal at a macroscopic size, l is the average free path of the electrons of the metal, w is the width of the metal layer, h is the thickness of the metal layer, and p is the specular reflection factor. If the specular reflection factor p→0 (0.05 is taken), assuming that the metal layer contains no defects, w = h = d; then the formula can be further simplified as:
[0038]
[0039] When the width of the metal layer is reduced to close to its average free path of electrons, the influence of surface and grain boundary scattering on the conductivity of the electrons is significantly enhanced, and the average free path of electrons of copper is 39.9 nanometers (nm), which is much larger than that of aluminum, which is 18.9 nanometers.
[0040] Based on the above formula, the resistivity of different metals at different widths can be simulated, Figure 1 The simulation results of the resistivity of metal ruthenium, cobalt, rhodium, copper, and aluminum at different widths are shown, and it can be seen that when the width is below 30 nanometers (especially 23 nanometers), the resistivity of aluminum and copper is close, and when the width is further reduced, the resistivity of aluminum is less than that of copper.
[0041] Calculation of resistivity of metal wire
[0042] Taking a copper interconnect structure (which can also be referred to as “copper damascene”) with a cobalt (Co) metal layer and a tantalum nitride (TaN) layer as the barrier layer as an example, the resistivity of the metal line (the barrier layer in the trench and the copper metal layer wrapped in the barrier layer) satisfies the following formula:
[0043]
[0044] wherein R is the resistivity of the metal line of the copper interconnect structure, S is the cross-sectional area of the copper metal layer, R Cu is the resistivity of the copper metal layer, R Co is the resistivity of the cobalt metal layer, R TaN is the resistivity of the tantalum nitride layer, S Cu is the cross-sectional area of the copper metal layer, S Co is the cross-sectional area of the cobalt metal layer, S TaN is the cross-sectional area of the tantalum nitride layer.
[0045] If the thickness T Co of the cobalt metal layer is taken as 28 angstroms, the thickness T TaN of the tantalum nitride layer is taken as 15 angstroms, the resistivity R Cu of the copper metal layer is taken as 1.67 x 10-6 ohm-cm, and the resistivity R Co of the cobalt metal layer is taken as 4.99 x 10-6 ohm-cm, and the effect of grain boundary scattering on resistivity is taken into account, then we have:
[0046]
[0047] While the aluminum interconnect structure (also referred to as "aluminum damascene") generally employs a titanium nitride (TiN) layer as the barrier layer, the resistivity of the metal line (the barrier layer in the recess and the aluminum metal layer coated in the barrier layer) satisfies the following formula:
[0048]
[0049] wherein R' is the resistivity of the metal line of the aluminum interconnect structure, S' is the cross-sectional area of the aluminum metal layer, R Al is the resistivity of the aluminum metal layer, R TiN is the resistivity of the titanium nitride, S Al is the cross-sectional area of the aluminum metal layer, S TiN is the cross-sectional area of the titanium nitride layer.
[0050] If the thickness T Co of the titanium nitride layer is taken as 20 angstroms, the resistivity R Al of the aluminum metal layer is taken as 2.65 x 10-6 ohm-cm, and the effect of grain boundary scattering on resistivity is taken into account, then we have:
[0051]
[0052] Based on the above formula, the resistivity of the copper metal line and the aluminum metal line at different widths can be simulated, Figure 2 the simulation results are shown, and it is not difficult to see that when the width is ≤ 30 nanometers (especially 23 nanometers), the resistivity of the aluminum metal line is lower.
[0053] Calculation of resistivity of via
[0054] Taking a copper interconnect structure with a cobalt metal layer and a tantalum nitride layer as the barrier layer as an example, the resistivity of its contact hole (the barrier layer in the through hole and the copper metal layer covering the barrier layer) satisfies the following formula:
[0055]
[0056] Where r is the resistivity of the contact hole in the copper interconnect structure, and h Cu h is the height of the copper metal layer, and h is the height of the contact hole. Co h is the thickness of the cobalt metal layer. TaN The thickness is the tantalum nitride layer.
[0057] If the thickness h of the cobalt metal layer is taken Co =28 angstroms, thickness h of tantalum nitride layer TaN =15 angstroms, resistivity R of the copper metal layer Cu and the resistivity R of the cobalt metal layer Co Taking into account the effect of grain boundary scattering on resistivity, we have:
[0058]
[0059] Taking an aluminum interconnect structure with a titanium nitride layer as the barrier layer as an example, the resistivity of its contact holes (the barrier layer in the through-hole and the aluminum metal layer covering the barrier layer) satisfies the following formula:
[0060]
[0061] Where r' is the resistivity of the contact hole in the copper interconnect structure, and h Al h is the height of the aluminum metal layer, h' is the height of the contact hole, h TiN The thickness is the titanium nitride layer.
[0062] If the thickness h of the titanium nitride layer is taken TiN =20 angstroms, resistivity R of the aluminum metal layer Al Taking into account the effect of grain boundary scattering on resistivity, we have:
[0063]
[0064] Based on the above formula, the resistivity of copper and aluminum contact holes at different heights (thicknesses) and with different metal line widths can be simulated. Figure 3 The simulation results show that when the height (thickness) is ≥200 nm, the resistivity of the aluminum contact hole is lower.
[0065] It should be noted that the values entered into the above formula are commonly used parameters in the manufacturing of device products, and their values themselves have little impact on the calculation.
[0066] As mentioned above, compared to copper interconnect structures, aluminum interconnect structures have lower resistivity in both metal lines and contact vias. Therefore, embodiments of this application provide a method for forming an aluminum interconnect structure that, while maintaining low resistivity, solves the filling defect problem caused by poor step coverage in the PVD process.
[0067] refer to Figure 4 It illustrates a flowchart of a method for forming an aluminum interconnect structure according to an exemplary embodiment of this application. This method can be applied to semiconductor manufacturing processes with processes below 5 nanometers, such as... Figure 4 As shown, the method includes:
[0068] Step S1: A groove is formed in the dielectric layer, the width of which is less than 30 nanometers. The dielectric layer is formed on top of a substrate used to form a semiconductor device.
[0069] refer to Figure 5 This illustrates a cross-sectional view after grooves have been formed in the dielectric layer. For example, such as... Figure 5 As shown, a dielectric layer 220 is formed on a substrate 211, which is used to form a semiconductor device. Figure 5 (Not shown in the image), a groove 301 is formed in the dielectric layer 220.
[0070] The groove 301 may include a first sub-groove 3011 located above and a second sub-groove 3012 located below. The first sub-groove 3011 and the second sub-groove 3012 are connected, and the width of the first sub-groove 3011 is greater than the width of the second sub-groove 3012. In this embodiment, the width of the groove 301 is defined as the width W of the first sub-groove 301, which is less than 30 nanometers. Optionally, the height of the second sub-groove 3012 is greater than 200 nanometers; the first sub-groove 3011 and the second sub-groove can be formed by two photolithography processes, which will not be elaborated here.
[0071] It should be noted that the embodiments of this application are illustrated by forming metal lines in the first dielectric layer 220 on the substrate 211. In practical applications, this can be implemented in any dielectric layer above the substrate.
[0072] Step S2: A barrier layer is formed on the surface of the dielectric layer and the groove.
[0073] refer to Figure 6 This illustrates a cross-sectional schematic diagram after a barrier layer has been formed on the surfaces of the dielectric layer and the groove. For example, such as... Figure 6 As shown, a titanium nitride layer can be deposited using an atomic layer deposition (ALD) process to form the barrier layer 230. Optionally, the thickness of the barrier layer 230 is from 5 angstroms to 30 angstroms.
[0074] Step S3, forming the aluminum metal layer to fill the recess by at least two deposition cycles, each deposition cycle including: forming the aluminum metal layer by PVD process, and performing heat treatment or radiation baking treatment on the aluminum metal layer to melt the aluminum metal layer to reduce the aluminum accumulation at the opening of the recess.
[0075] In the back-end-of-line process, the formation process of the metal silicide layer (e.g., titanium silicon (TiSi x ) layer / silicon (Si) layer, nickel silicon (NiSi) layer / silicon layer) requires the temperature of the heat treatment to be less than 700 degrees Celsius (℃), and the melting point of aluminum (660.3 degrees Celsius) is much lower than the melting point of copper (1083.4 degrees Celsius), therefore, forming the aluminum metal layer to fill the recess by multiple deposition cycles can achieve melting of the aluminum accumulation at the opening of the recess 301 (including the opening of the first sub-recess 3011 and the opening of the second sub-recess 3012) at a lower temperature and without causing penetration of the metal silicide of the semiconductor device due to melting.
[0076] Optionally, the thickness of the aluminum metal layer formed by the PVD process in each deposition cycle is 5 angstroms to 60 angstroms; optionally, the temperature of the heat treatment or the radiation baking in each deposition cycle is 100 degrees Celsius (℃) to 350 degrees Celsius. In the following, the formation of the aluminum metal layer to fill the recess by three deposition cycles is exemplarily described, and the number of deposition cycles and related parameters can be set according to requirements in actual applications.
[0077] Reference is made to Figure 7 which shows a cross-sectional schematic view after the aluminum metal layer is formed by the PVD process in the first deposition cycle; reference is made to Figure 8 which shows a cross-sectional schematic view after the heat treatment or the radiation baking treatment is performed on the aluminum metal layer to melt the aluminum metal layer in the first deposition cycle. Exemplarily, as shown in Figure 7 and Figure 8 , the aluminum metal layer 241 is formed by the PVD process, the aluminum metal layer 241 is melted by the heat treatment or the radiation baking treatment, and the aluminum accumulation at the opening is reduced to form the aluminum metal layer 2411 with a more uniform thickness.
[0078] Reference is made to Figure 9 which shows a cross-sectional schematic view after the aluminum metal layer is formed by the PVD process in the second deposition cycle; reference is made to Figure 10 which shows a cross-sectional schematic view after the heat treatment or the radiation baking treatment is performed on the aluminum metal layer to melt the aluminum metal layer in the second deposition cycle. Exemplarily, as shown in Figure 9 and Figure 10 , the aluminum metal layer 242 is formed by the PVD process, the aluminum metal layer 242 is melted by the heat treatment or the radiation baking treatment, the aluminum accumulation at the opening is reduced to form the aluminum metal layer 2421 with a more uniform thickness, and the second sub-recess 3012 is filled with the aluminum metal layer.
[0079] refer to Figure 11 It shows a schematic cross-sectional view after an aluminum metal layer is formed by PVD process in the third deposition cycle; Reference Figure 12 It shows a schematic cross-sectional view after the aluminum metal layer has been melted by heat treatment or radiation baking during the third deposition cycle. For example, as... Figure 11 and Figure 12 As shown, after forming an aluminum metal layer 243 using a PVD process, the aluminum metal layer 243 is melted through heat treatment or radiation baking, reducing aluminum buildup at the opening and forming a more uniform aluminum metal layer 2431, at which point the groove 301 is filled. If the thickness of the aluminum metal layer still does not meet the requirements after three deposition cycles, it can be adjusted as follows: Figure 13 As shown, another aluminum metal layer 244 is deposited.
[0080] Step S4: Perform planarization to remove the aluminum metal layer and barrier layer outside the groove.
[0081] For example, planarization can be performed by chemical mechanical polishing (CMP) to remove the aluminum metal layer and barrier layer outside the groove 301. The barrier layer and aluminum metal layer in the first sub-groove 3011 constitute the metal line of the aluminum metal interconnect structure, and the barrier layer and aluminum metal layer in the second sub-groove 3012 constitute the contact hole of the aluminum metal interconnect structure.
[0082] In summary, in the embodiments of this application, after forming a groove in the dielectric layer in the back-end process of semiconductor devices, a barrier layer is first formed, and then an aluminum metal layer is filled in the groove through at least two deposition cycles. Since the aluminum metal layer is heated after each deposition cycle, the filling defect problem caused by poor step coverage in the PVD process is solved. Furthermore, since the resistivity of aluminum is higher than that of copper at a width of 30 nanometers, the yield and electrical performance of the device products are improved.
[0083] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method of forming an aluminum interconnect structure, comprising: Comprising: forming a recess in a dielectric layer, the recess having a narrowest region with a width less than 30 nanometers, the dielectric layer formed over a substrate, the substrate used to form a semiconductor device; forming a barrier layer on a surface of the dielectric layer and the recess; filling the recess with an aluminum metal layer by at least two deposition cycles; performing a planarization process to remove the aluminum metal layer and the barrier layer outside the recess; wherein the deposition cycle comprises: forming an aluminum metal layer by a PVD process, and performing a heat treatment or a radiation baking treatment to the aluminum metal layer to melt the aluminum metal layer to reduce aluminum accumulation at the opening of the recess.
2. The method of claim 1, wherein, The thickness of the aluminum metal layer formed by the PVD process in each deposition cycle is from 5 angstroms to 60 angstroms.
3. The method of claim 2, wherein, The temperature of the heat treatment or the radiation baking in each deposition cycle is from 100 degrees Celsius to 350 degrees Celsius.
4. The method according to any one of claims 1 to 3, characterized in that, The thickness of the barrier layer is from 5 angstroms to 30 angstroms.
5. The method of claim 4, wherein, The barrier layer comprises a titanium nitride layer.
6. The method of claim 5, wherein, The forming of the barrier layer on the surface of the dielectric layer and the recess comprises: depositing a titanium nitride layer by a CVD process to form the barrier layer.
7. The method of claim 5, wherein, The forming of the barrier layer on the surface of the dielectric layer and the recess comprises: depositing a titanium nitride layer by an ALD process to form the barrier layer.