Semiconductor device structure and forming method thereof

Abstract

The invention provides a semiconductor device structure and a forming method thereof. The semiconductor device structure includes an interconnect structure disposed over a substrate, a first dielectric layer disposed over the interconnect structure, and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer includes a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV. The semiconductor device structure also includes a third dielectric layer disposed on the second dielectric layer and a first conductive feature disposed on the third dielectric layer. The first conductive feature includes a first portion extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer, and a second portion disposed on the third dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and particularly to semiconductor device structures and methods of forming thereof. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Advances in IC materials and design have led to the production of several generations of ICs, each generation being smaller and more complex than the previous one. However, these advancements have increased the complexity of IC fabrication and manufacturing, requiring corresponding developments in IC processing and manufacturing to achieve these advancements. Throughout the evolution of ICs, functional density (the number of interconnected components per chip area) has generally increased, while geometric dimensions (the smallest components that can be created using manufacturing processes) have decreased. Summary of the Invention

[0003] The purpose of this disclosure is to provide a semiconductor device structure and a method for forming the same, in order to solve at least one of the aforementioned problems.

[0004] This disclosure provides a semiconductor device structure including an interconnect structure, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a first conductive component. The interconnect structure is disposed above a substrate. The first dielectric layer is disposed above the interconnect structure. The second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer includes a dielectric material having a k-value greater than about 20 and a band gap less than about 5 eV. The third dielectric layer is disposed on the second dielectric layer. The first conductive component is disposed on the third dielectric layer, wherein the first conductive component includes a first portion extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer, and a second portion disposed on the third dielectric layer.

[0005] This disclosure provides a semiconductor device structure, including an interconnect structure, a metal-insulator-metal structure, a passivation layer, and a conductive component. The interconnect structure is disposed on a substrate. The metal-insulator-metal structure is disposed within the interconnect structure, wherein the metal-insulator-metal structure includes a first electrode layer, a second electrode layer, a first dielectric layer, a third electrode layer, and a second dielectric layer. The second electrode layer is disposed above the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The third electrode layer is disposed above the second electrode layer. The second dielectric layer is disposed between the second electrode layer and the third electrode layer, wherein at least one of the first and second dielectric layers includes a dielectric material having a k-value greater than about 20 and a band gap less than about 5 eV. The passivation layer is disposed on the metal-insulator-metal structure. The conductive component is disposed above the passivation layer, wherein the conductive component includes a first portion extending through the metal-insulator-metal structure and the passivation layer, and a second portion disposed above the passivation layer.

[0006] This disclosure provides a method for forming a semiconductor device structure, comprising depositing a first dielectric layer over an interconnect structure; depositing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV; depositing a third dielectric layer on the second dielectric layer; forming openings in the first, second, and third dielectric layers by a plasma process; and releasing static charge accumulated on the surfaces of the first and third dielectric layers through the second dielectric layer. Attached Figure Description

[0007] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0008] Figure 1A , Figure 1B , Figure 1C ,as well as Figure 1D These are cross-sectional views of various manufacturing stages of a semiconductor device structure, according to some embodiments.

[0009] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H ,as well as Figure 2I This is a cross-sectional view of various manufacturing stages of a semiconductor device structure according to an alternative embodiment.

[0010] Figure 3 This is a cross-sectional view of one of the various manufacturing stages of a semiconductor device structure according to an alternative embodiment.

[0011] The annotations in the attached figures are explained as follows: 100: Semiconductor Device Structure 102:Substrate 106: Interconnection Structure 108: Intermetallic dielectric layer 110, 116, 126, 128, 180, 182, 206: Dielectric layers 112, 142, 152, 188: Conductive components 114: Etching Stop Layer 118, 208: Metal-Insulator-Metal Structure 120, 202: First electrode layer 122, 204: Second electrode layer 124: Third electrode layer 130, 146: Passivation layer 132: Buffer layer 134: Masking layer 136, 150, 186: Opening 138: Barrier Layer 138s, 140s, 142s: Side surface 140: Seed layer 142b: Bottom 142t: Top 144: Adhesive layer 148, 190: Dielectric materials 184: Photoresist layer 188a: Line section 188b: Through hole portion. Detailed Implementation

[0012] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0013] Furthermore, spatially relative terms may be used, such as "below," "under," "lower," "above," "above," "top," "higher," etc., to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0014] The following describes some embodiments of the invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Some of the stages may be replaced or omitted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0015] Figures 1A-1D These are cross-sectional views of various manufacturing stages of a semiconductor device structure 100 according to some embodiments. Figure 1A As shown, the semiconductor device structure 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes at least a crystalline semiconductor layer on its surface. The substrate 102 may contain a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is formed of Si. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In another embodiment, the insulating layer is an oxygen-containing material, such as an oxide. In some embodiments, the substrate 102 is a wafer, such as a 200 mm wafer, a 300 mm wafer, a 450 mm wafer, or a wafer of other suitable size.

[0016] The substrate 102 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). For example, phosphorus is used as a dopant for an n-type field-effect transistor (NFET), while boron is used as a dopant for a p-type field-effect transistor (PFET).

[0017] In some embodiments, one or more elements are formed on substrate 102. These elements can be any suitable element, such as a transistor, diode, image sensor, resistor, capacitor, inductor, storage cell, or a combination thereof. In some embodiments, the element is a transistor, such as a metal oxide semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, PFETs / NFETs, or other suitable transistors. The transistor can be a planar field-effect transistor (FET), FinFETs, a nanostructure transistor, or other suitable transistor. A nanostructure transistor can comprise a nanosheet transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MCB) transistor, or any transistor having a gate electrode surrounding the channel. One or more elements can be formed using a front end of line (FEOL) process.

[0018] like Figure 1AAs shown, the semiconductor device structure 100 may further include an interconnect structure 106 disposed above the substrate 102. The interconnect structure 106 includes an intermetallic dielectric (IMD) layer 108 and a plurality of conductive components (not shown) disposed on the IMD layer 108. The conductive components may be wires and conductive vias. The interconnect structure 106 includes multiple layers of conductive components, and the conductive components are disposed on each layer to provide electrical paths to various components of one or more underlying components. The conductive components may be made of one or more electrically conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, the conductive components may be made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium nitride silicon, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, silicon tungsten nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof.

[0019] IMD layer 108 comprises one or more dielectric materials to provide isolation for various conductive components. IMD layer 108 may comprise multiple dielectric layers embedded with multiple layers of conductive components. IMD layer 108 is made of a dielectric material, such as SiOx, SiOxCyHz, or SiOxCy, where x, y, and z are integers or non-integers. In some embodiments, IMD layer 108 comprises a dielectric material having a dielectric constant (k) value of about 1 to about 5. IMD layer 108 can be formed by any suitable process, such as chemical vapor deposition (CVD), spin coating, or plasma-enhanced chemical vapor deposition (PECVD).

[0020] like Figure 1A As shown, the interconnect structure 106 may further include a dielectric layer 110 and one or more conductive components 112 formed therein. The dielectric layer 110 may be the top layer of the interconnect structure 106. The dielectric layer 110 may contain the same material as the IMD layer 108, and the conductive components 112 may contain the same material as the conductive components formed in the IMD layer 108. A barrier layer (not shown) may be disposed between the conductive components 112 and the dielectric layer 110. The interconnect structure 106 may be formed using a back end of line (BEOL) process.

[0021] An etch stop layer 114 can be disposed on the interconnect structure 106, such as... Figure 1AAs shown. The etch stop layer 114 may comprise SiC, SiN, SiCN, SiOC, SiOCN, metal oxides, metal nitrides, or other suitable materials. In some embodiments, the etch stop layer has a k-value less than about 10 and a band gap greater than about 5.4 eV. In some embodiments, the etch stop layer 114 has a thickness of about 100 nm to about 200 nm. A dielectric layer 116 is disposed on the etch stop layer 114. The dielectric layer 116 may comprise the same material as the IMD layer 108. In some embodiments, the dielectric layer 116 has a thickness of about 400 nm to about 1000 nm. The dielectric layer 116 may be formed by any suitable process, such as CVD, spin coating, or PECVD.

[0022] like Figure 1B As shown, dielectric layer 180 is disposed on dielectric layer 116. Dielectric layer 180 comprises a dielectric material having a high k-value and a low band gap. In some embodiments, the dielectric material of dielectric layer 180 has a k-value greater than about 20 and a band gap less than about 5 eV. The k-value of the dielectric material of dielectric layer 180 can be between about 20 and about 60, and the band gap of the dielectric material of dielectric layer 180 can be between about 2.5 eV and about 4.5 eV. In some embodiments, dielectric layer 180 is formed of, or contains, TiO2, TiO, BaO, or Ta2O5. In some embodiments, dielectric layer 180 is formed of, or contains, TiO2, TiO, or BaO. In some embodiments, dielectric layer 180 is formed of, or contains, TiO2 or BaO. In some embodiments, the dielectric layer 180 is formed of TiO2 or contains TiO2. In some embodiments, the dielectric layer 180 is formed of BaO or contains BaO. The dielectric layer 180 provides an electrical current path to release static charge accumulated on the semiconductor device structure 100. Static charge may accumulate on the surface of the semiconductor device structure 100 during plasma processing. For example, during a subsequent plasma etching process to form opening 186 (… Figure 1CDuring the construction of dielectric layers 182, 180, and etch stop layer 114, static charge may accumulate on the surfaces of these layers. Due to this accumulated static charge, current may flow through dielectric layers 182, 180, and etch stop layer 114, potentially causing device degradation. Because dielectric layer 180 comprises a dielectric material with a high k-value and a low bandgap, the accumulated static charge can be released. Dielectric layer 180 serves as a current path for reducing plasma-induced damage (PID). In some embodiments, dielectric layer 180 has a thickness of about 1 angstrom to about 20 angstroms, for example, from about 5 angstroms to about 15 angstroms. If the thickness of dielectric layer 180 is less than about 5 angstroms, the thickness is insufficient to provide a current path for releasing static charge. On the other hand, if the thickness of dielectric layer 180 is greater than about 15 angstroms, it may result in high parasitic capacitance due to the high k value of dielectric layer 180. Dielectric layer 180 can be formed by any suitable process, such as atomic layer deposition (ALD), CVD, or PECVD.

[0023] Another dielectric layer 182 is disposed on dielectric layer 180, such as Figure 1B As shown. In some embodiments, dielectric layer 182 comprises the same material as dielectric layer 116 and is formed by the same process as dielectric layer 116. In some embodiments, dielectric layer 182 has a thickness of about 400 nm to about 1000 nm. In some embodiments, dielectric layer 182 is formed by PECVD, and the plasma of PECVD causes electrostatic charge to accumulate on the surface of semiconductor device structure 100. Similarly, in some embodiments, dielectric layer 116 is formed by PECVD, and the plasma of PECVD also causes electrostatic charge to accumulate on the surface of semiconductor device structure 100.

[0024] like Figure 1C As shown, a photoresist layer 184 is formed on a dielectric layer 182, and an opening 186 is formed on dielectric layers 182, 180, 116, and an etch stop layer 114 to expose the conductive component 112. The opening 186 can be formed by one or more etching processes. The etching process can be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the one or more etching processes are plasma etching processes. Therefore, static charge may accumulate on the surface of the semiconductor device structure 100. Static charge accumulated on the surface of the semiconductor device structure 100 due to the plasma etching process used to form the opening 186 and / or the PECVD process used to form the dielectric layers 116 and 182 is released through the dielectric layer 180. The dielectric layer 180 is electrically connected to the subsequently formed conductive component 188. Figure 1D Furthermore, static charge can be released through the conductive component 188.

[0025] In some embodiments, dielectric layer 180 is not an etch stop layer because an etch stop layer between dielectric layers 116 and 182 is not required during the formation of opening 186. In some embodiments, due to the presence of dielectric layer 180, which contains a material different from that of dielectric layers 116 and 182, three different etch processes can be performed. For example, a first etch process is performed to remove a portion of dielectric layer 182, a second etch process is performed to remove a portion of dielectric layer 180 exposed by the removal of a portion of dielectric layer 182, and a third etch process is performed to remove a portion of dielectric layer 116 exposed by the removal of a portion of dielectric layer 180. Without dielectric layer 180, opening 186 can be formed by a single etch process because dielectric layers 116 and 182 contain the same material. However, without dielectric layer 180, the static charge accumulating on the surfaces of dielectric layers 116 and 182 can lead to device degradation.

[0026] like Figure 1D As shown, conductive components 188 are formed in each of the openings 186. Conductive components 188 may comprise an electrically conductive material, such as a metal. In some embodiments, conductive components 188 comprise the same material as conductive components 112. In some embodiments, conductive components 188 comprise copper. Conductive components 188 include through-hole portions 188b and line portions 188a, such as... Figure 1D As shown. The via portion 188b extends through the etch stop layer 114, dielectric layer 116, dielectric layer 180, and dielectric layer 182. The line portion 188a is formed on the dielectric layer 182. The conductive component 188 can be formed by any suitable process. In some embodiments, the conductive component 188 is a redistribution layer (RDL).

[0027] After the conductive component 188 is formed, a dielectric material 190 is formed on the dielectric layer 182 and the conductive component 188. The dielectric material 190 can be any suitable dielectric material. In some embodiments, the dielectric material 190 is a polymer, such as polyimide. The dielectric material 190 can be formed by any suitable process, such as spin coating, CVD, FCVD, or laminating.

[0028] As described above, the static charge accumulated on the surfaces of dielectric layers 182 and 116 can be released through dielectric layer 180 and conductive component 188.

[0029] Figures 2A to 2I This is a cross-sectional view of various manufacturing stages of the semiconductor device structure 100 according to an alternative embodiment. (See diagram below.) Figure 2A As shown, the semiconductor device structure 100 includes a substrate 102 and an interconnect structure 106 disposed above the substrate 102. One or more components may be disposed on the substrate 102, for example on... Figure 1A The one or more elements mentioned above. The interconnect structure 106 includes an IMD layer 108, a dielectric layer 110, and conductive components 112 formed in the dielectric layer 110, such as... Figure 2A As shown. The etch stop layer 114 and the dielectric layer 116 can be disposed on the interconnect structure 106.

[0030] like Figure 2A As shown, a metal-insulator-metal (MIM) structure 118 is disposed on a dielectric layer 116, and a passivation layer 130 is disposed on the MIM structure 118. The MIM structure 118 includes a first electrode layer 120, a second electrode layer 122 disposed above the first electrode layer 120, and a third electrode layer 124 disposed above the second electrode layer 122. The first electrode layer 120, the second electrode layer 122, and the third electrode layer 124 may contain electrically conductive materials, such as metals or metal nitrides. In some embodiments, the first electrode layer 120, the second electrode layer 122, and the third electrode layer 124 may contain Al, Cu, W, Ti, Ta, TiN, TaN, or other suitable electrically conductive materials.

[0031] The MIM structure 118 further includes a dielectric layer 126 disposed between the first electrode layer 120 and the second electrode layer 122, and a dielectric layer 128 disposed between the second electrode layer 122 and the third electrode layer 124. In some embodiments, dielectric layers 126 and 128 may contain the same material as dielectric layer 180. Compared to conventional dielectric materials in MIM structures, dielectric layers 126 and 128 contain dielectric materials with low band gaps, which can be used as current paths to release static charges accumulated on the surface of the semiconductor device structure 100 due to plasma processing. In some embodiments, the dielectric materials of dielectric layers 126 and 128 have a k-value greater than about 20 and a band gap less than about 5 eV. The k-value of the dielectric materials of dielectric layers 126 and 128 may be between about 20 and about 60, and the band gap of the dielectric materials of dielectric layers 126 and 128 may be between about 2.5 eV and 4.5 eV. In some embodiments, dielectric layers 126, 128 are formed of TiO2, TiO, BaO, or Ta2O5, or contain TiO2, TiO, BaO, or Ta2O5.

[0032] In some embodiments, one of dielectric layers 126 and 128 comprises the same material as dielectric layer 180, while the other of dielectric layers 126 and 128 comprises a high-k dielectric material having a k value greater than about 7. In some embodiments, the high-k dielectric material in one of dielectric layers 126 and 128 can be an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, or other suitable materials. In some embodiments, the k value of the dielectric layer 126 or 128 comprising the same material as dielectric layer 180 is greater than the k value of the dielectric layer 126 or 128 comprising the high-k dielectric material. For example, one of dielectric layers 126 and 128 contains BaO, which has a k-value of approximately 33 and a band gap of approximately 4.3 eV, while the other dielectric layer contains HfO2, which has a k-value of approximately 24 and a band gap of approximately 6 eV. Although the low band gap of the BaO-containing dielectric layer can release accumulated static charge, the high k-value of the BaO-containing dielectric layer may lead to an increase in parasitic capacitance. Therefore, if both dielectric layers 126 and 128 contain BaO, the parasitic capacitance of the MIM structure 118 may be excessively high.

[0033] In some embodiments, the thicknesses of dielectric layers 126 and 128 are different. For example, the dielectric layer containing a low-bandgap dielectric material in dielectric layers 126 and 128 can be thinner than the dielectric layer containing a high-k dielectric material in dielectric layers 126 and 128. Because the k-value of the low-bandgap dielectric material can be greater than the k-value of the high-k dielectric material, if the thickness of the dielectric layer containing the low-bandgap dielectric material in dielectric layers 126 and 128 is equal to the thickness of the dielectric layer containing the high-k dielectric material in dielectric layers 126 and 128, the parasitic capacitance may be excessively high. In some embodiments, the thickness of the dielectric layer containing the low-bandgap dielectric material in dielectric layers 126 and 128 ranges from about 1 angstrom to about 20 angstroms, for example from about 5 angstroms to about 15 angstroms, and the thickness of the dielectric layer containing the high-k dielectric material in dielectric layers 126 and 128 is greater than about 20 angstroms, for example from about 25 angstroms to about 100 angstroms.

[0034] In some embodiments, one of dielectric layers 126 and 128 comprises two or more dielectric layers. For example, dielectric layer 126 (or dielectric layer 128) comprises a first dielectric layer formed of a low bandgap dielectric material and a second dielectric layer formed of a high-k dielectric material. The first dielectric layer may comprise TiO2, TiO, BaO, or Ta2O5, and the second dielectric layer may comprise oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. The k-value of the second dielectric layer is less than that of the first dielectric layer, and the bandgap of the second dielectric layer is greater than that of the first dielectric layer. The other dielectric layer 128 (or dielectric layer 126) may comprise a single dielectric layer, such as a dielectric layer formed of a high-k dielectric material.

[0035] In some embodiments, dielectric layer 126 (or dielectric layer 128) comprises a first dielectric layer formed of a low-bandgap dielectric material, a second dielectric layer formed of a high-k dielectric material, and a third dielectric layer formed of a low-bandgap dielectric material. The second dielectric layer is disposed between the first and third dielectric layers. In some embodiments, the first and third dielectric layers are formed of the same low-bandgap dielectric material. Therefore, the k-values ​​of the first and third dielectric layers are greater than the k-value of the second dielectric layer, and the band gaps of the first and third dielectric layers are smaller than the band gap of the second dielectric layer. The first and third dielectric layers may each comprise TiO2, TiO, BaO, or Ta2O5, and the second dielectric layer may comprise oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Another dielectric layer 128 (or dielectric layer 126) may comprise a single dielectric layer, such as a dielectric layer formed of a high-k dielectric material.

[0036] like Figure 2A As shown, a passivation layer 130 is disposed above the MIM structure 118. The passivation layer 130 may comprise oxide or SiN. In some embodiments, the passivation layer 130 comprises the same material as the dielectric layer 116. In some embodiments, the thickness of the passivation layer 130 may be greater than or equal to the thickness of the dielectric layer 116. For example, the thickness of the passivation layer 130 may be from about 350 nm to about 550 nm.

[0037] A buffer layer 132 is disposed on the passivation layer 130, and a masking layer 134 is disposed on the buffer layer 132, such as Figure 2A As shown. The buffer layer 132 may contain a metal oxide, such as aluminum oxide (AlxOy), where x and y can be integers or non-integers. The material of the buffer layer 132 may differ from that of the subsequently formed barrier layer 138. Figure 2C The buffer layer 132 is made of a material that allows it to have different etch selectivity compared to the barrier layer 138. The buffer layer 132 can be formed by any suitable process, such as ALD, CVD, or PVD. In some embodiments, the buffer layer 132 is a conformal layer formed by a conformal process, such as ALD. The term "conformal" is used herein to describe layers having substantially the same thickness in different regions. The thickness of the buffer layer 132 can be at least 1 nm to serve as a stress-relieving buffer layer. In some embodiments, the thickness of the buffer layer 132 is from about 1 nm to about 50 nm. If the thickness of the buffer layer 132 is less than about 1 nm, the buffer layer 132 may be insufficient to relieve stress. On the other hand, if the thickness of the buffer layer 132 is greater than about 50 nm, the manufacturing cost may increase without significant advantages. Additionally, the buffer layer 132 can be used as an etch stop layer during the removal of a portion of the barrier layer 138. Therefore, in some embodiments, the thickness of the buffer layer 132 depends on the thickness of the barrier layer 138, which in... Figure 2C It contains a detailed description.

[0038] The masking layer 134 may comprise one or more layers. In some embodiments, the masking layer 134 comprises a nitride, such as TiN. The masking layer 134 may be patterned by forming a patterned impedance layer (not shown) on the masking layer 134. The pattern of the patterned impedance layer may be transferred to the masking layer 134 and then to a layer disposed beneath the masking layer 134.

[0039] like Figure 2B As shown, opening 136 is formed in buffer layer 132, passivation layer 130, MIM structure 118, and etch stop layer 114 to expose conductive component 112. Opening 136 can be formed by one or more etching processes. The etching process can be dry etching, wet etching, or a combination thereof. In some embodiments, a portion of mask layer 134 is removed by a dry etching process. Figure 2A A portion of the buffer layer 132 is removed using a wet etching process, and a portion of the passivation layer 130, MIM structure 118, dielectric layer 116, and etch stop layer 114 are removed using one or more dry etching processes. In some embodiments, the dry etching process is a plasma etching process, and static charge may accumulate on the surface of the semiconductor device structure 100, such as on the surface of dielectric layer 116, etch stop layer 114, and passivation layer 130. The accumulated static charge can be released by one or both of the dielectric layers 126 and 128. The mask layer 134 can be removed by a multi-pass etching process.

[0040] like Figure 2CAs shown, a barrier layer 138 is formed on the buffer layer 132 and in the opening 136, and a seed layer 140 is formed on the barrier layer 138. The barrier layer 138 can prevent metal from entering the subsequently formed conductive component 142. Figure 2D It diffuses into the passivation layer 130 and the dielectric layers 116, 126, and 128. For example... Figure 2C As shown, the barrier layer 138 contacts the passivation layer 130, the MIM structure 118, the dielectric layer 116, the etch stop layer 114, and the conductive component 112. The barrier layer 138 may contain a nitride, such as a metal nitride, for example, a refractory metal nitride. In some embodiments, the barrier layer 138 contains an electrically conductive material. In some embodiments, the barrier layer 138 contains tantalum nitride (TaN). The barrier layer 138 can be formed by any suitable process, such as ALD, CVD, or PVD. In some embodiments, the barrier layer 138 is a conformal layer formed by a conformal process. The barrier layer 138 can have a thickness of about 1 nm to about 50 nm. If the thickness of the barrier layer 138 is less than 1 nm, the barrier layer 138 may be insufficient to prevent metal diffusion. On the other hand, if the thickness of the barrier layer 138 is greater than 50 nm, the manufacturing cost may increase without significant advantages.

[0041] The seed layer 140 may contain the same material as the conductive component 112 and may be formed by any suitable process, such as ALD, CVD, or PVD. In some embodiments, the seed layer 140 is a conformal layer formed by ALD.

[0042] like Figure 2D As shown, conductive component 142 is formed in opening 136 ( Figure 2C The conductive component 142 is formed within the opening 136 and over a portion of the passivation layer 130 and the barrier layer 138. The conductive component 142 can be formed by first forming a sacrificial layer (not shown) in the opening 136 and over the passivation layer 130. The sacrificial layer can be formed on the seed layer 140. In some embodiments, the sacrificial layer is an impedance layer. The sacrificial layer can be patterned so that the sacrificial layer disposed in the opening 136 and over a portion of the passivation layer 130 can be removed. In other words, the opening is formed by removing a portion of the sacrificial layer. The opening may include opening 136 (… Figure 2C The larger opening is located in the sacrificial layer above the opening 136 and above a portion of the passivation layer 130. Then, a conductive component 142 is formed in the opening, and the sacrificial layer is removed by a stripping process. The conductive component 142 formed by this process does not undergo a dry etching process, which could affect the roughness of the side surfaces of the conductive component 142. If the side surfaces 142s are exposed to a dry etching process, the subsequent adhesion layer 144 formed on the side surfaces 142s will be affected. Figure 2EThe opposite side surface 142s may have poor adhesion. Therefore, without using a dry etching process to form the conductive component 142, the adhesive layer 144 ( Figure 2E The adhesion to the side surface 142s of the conductive component 142 can be improved. In some embodiments, the conductive component 142 is an RDL. In some embodiments, the conductive component 188 ( Figure 1D It is formed using the same process as conductive component 142.

[0043] The conductive component 142 may comprise an electrically conductive material, such as a metal. The conductive component 142 may comprise the same material as the seed layer 140. In some embodiments, the seed layer 140 and the conductive component 142 comprise Cu. In some embodiments, the seed layer 140 is optional, and the conductive component 142 is formed on the barrier layer 138. The conductive component 142 may extend through the passivation layer 130, the MIM structure 118, and the dielectric layer 116. The conductive component 142 may be electrically connected to the conductive component 112, and the first electrode layer 120 and the third electrode layer 124 of the MIM structure 118. The conductive component 142 may be formed by any suitable process, such as PVD or ECP. The conductive component 142 includes a bottom 142b disposed in the opening 136 (…). Figure 2C The top 142t is located above the bottom. In some embodiments, the bottom 142b can be a conductive hole, and the top 142t can be a conductive line. The top 142t of the conductive member 142 can be disposed on the seed layer 140, and other portions of the seed layer 140 can be exposed.

[0044] like Figure 2E As shown, the exposed portion of the seed layer 140 is removed, and an adhesive layer 144 is formed on the top 142t of the conductive component 142. The removal of the exposed portion of the seed layer can be performed using a wet etching process. A wet etching process can remove a negligible amount from the top 142t of the conductive component 142. However, because it is not a dry etching process, the adhesion of the adhesive layer 144 to the top 142t of the conductive component 142 is substantially unaffected. The adhesive layer 144 can be formed on a portion of the barrier layer 138 and on the top 142t of the conductive component 142. The adhesive layer 144 can be a nitride, such as SiN. In some embodiments, the conductive component 142 has tensile stress, and the adhesive layer 144 also has tensile stress for better adhesion to the top 142t of the conductive component 142. The adhesive layer 144 can be formed by any suitable process, such as ALD, CVD, PEVCD, or PVD. The adhesive layer 144 may have a thickness of about 10 nm to about 50 nm.

[0045] like Figure 2FAs shown, a portion of the adhesive layer 144 and a portion of the barrier layer 138 are removed. The portion of the adhesive layer 144 can be removed by anisotropic etching. Anisotropic etching can be a dry etching process that removes portions of the adhesive layer 144 formed on horizontal surfaces, such as the top surface of the top 142t of the conductive component 142 and portions of the adhesive layer 144 on the barrier layer. Therefore, the portion of the barrier layer 138 located below the removed portion of the adhesive layer 144 is exposed, and the side surface 142s is covered by the adhesive layer 144.

[0046] Next, because the barrier layer 138 may contain an electrically conductive material, the exposed portion of the barrier layer can be removed. To protect the side surface 142s of the top 142t of the conductive component 142, an adhesive layer 144 is formed on the side surface 142s of the top 142t of the conductive component 142 before the exposed portion of the barrier layer 138 is removed. Therefore, after the exposed portion of the seed layer 140 is removed, instead of immediately removing the exposed portion of the barrier layer 138, other additional processes can be performed, such as forming the adhesive layer 144 and removing a portion of the adhesive layer to expose a portion of the barrier layer 138 to protect the side surface 142s of the top 142t of the conductive component 142.

[0047] like Figure 2F As shown, after the exposed portion of the barrier layer 138 is removed, the side surface 138s of the barrier layer 138 is exposed. The seed layer 140 includes the side surface 140s, and the adhesive layer 144 contacts the barrier layer 138, the side surface 140s of the seed layer 140, and the side surface 142s of the top 142t of the conductive member 142. The side surface 138s of the barrier layer 138 can extend outward from the side surface 140s of the seed layer 140, and the gap between the side surface 138s and the side surface 140s can be the thickness of the adhesive layer 144, which can range from about 10 nm to about 50 nm.

[0048] like Figure 2G As shown, a passivation layer 146 is formed on the side surfaces 138s of the buffer layer 132, the side surfaces of the barrier layer 138, the adhesive layer 144, and the top surface of the top 142t of the conductive component 142. Since the passivation layer 146 may contain the same material as the adhesive layer 144, the passivation layer 146 adheres to the adhesive layer 144. In some embodiments, the passivation layer 146 has compressive stress to protect the conductive component 142 from subsequent formation of the conductive component 152. Figure 2IThe passivation layer 146 with compressive stress may not adhere to the side surface 142s of the top 142t of the conductive component 142. Therefore, as described above, by using an adhesive layer 144 with tensile stress, the passivation layer 146 can adhere to the adhesive layer 144, and the adhesive layer 144 can adhere to the side surface 142s of the top 142t of the conductive component 142.

[0049] In some embodiments, the adhesive layer 144 and the passivation layer 146 comprise the same material but have different stresses. The stresses of the adhesive layer 144 and the passivation layer 146 can be controlled by various factors, such as plasma power and / or precursor flow rate. For example, in some embodiments, the adhesive layer 144 comprises SiN, has tensile stress, and is formed by a first PECVD process. The passivation layer 146 comprises SiN, has compressive stress, and is formed by a second PECVD process. The first PECVD process has a first plasma power and a first silicon-containing precursor flow rate. The second PECVD process has a second plasma power substantially greater than the first plasma power and a second silicon-containing precursor flow rate substantially greater than the first silicon-containing precursor flow rate. The silicon-containing precursor in both the first and second PECVD processes can be silane.

[0050] In some embodiments, the passivation layer 146 has a thickness of about 500 nm to about 1500 nm, for example, about 800 nm to about 1200 nm. As described above, the adhesive layer 144 has a thickness of about 10 nm to about 50 nm. In some embodiments, the thickness of the passivation layer 146 can be about 10 times to about 150 times the thickness of the adhesive layer 144. If the thickness of the passivation layer 146 is less than about 10 times the thickness of the adhesive layer 144, the passivation layer 146 may be insufficient to protect the conductive component 142 from the conductive component 152 ( Figure 2I The stress effect of the passivation layer 146. On the other hand, if the thickness of the passivation layer 146 is greater than about 150 times the thickness of the adhesive layer 144, the risk of the passivation layer 146 peeling off from the conductive component 142 will increase.

[0051] like Figure 2H As shown, dielectric material 148 is formed on passivation layer 146, and opening 150 is formed on dielectric material 148 and passivation layer 146 to expose conductive component 142. Dielectric material 148 can be any suitable dielectric material. In some embodiments, dielectric material 148 is a polymer, such as polyimide. Dielectric material 148 can be formed by any suitable process, such as spin coating, CVD, FCVD, or lamination. Opening 150 can be formed by any suitable process, such as dry etching process, wet etching process, or a combination thereof.

[0052] like Figure 2IAs shown, conductive component 152 is formed in opening 150 ( Figure 2H In some embodiments, conductive component 152 may contact conductive component 142. Conductive component 152 may comprise an electrically conductive material, such as a metal. In some embodiments, conductive component 152 comprises Cu, Ni, Au, Ag, Pd, Al, Sn, or other suitable metals. In some embodiments, conductive component 152 is a conductive bump, such as... Figure 2I As shown. Figure 2I As shown, in some embodiments, the passivation layer 146 contacts the buffer layer 132, the barrier layer 138, the adhesive layer 144, the conductive component 142, the dielectric material 148, and the conductive component 152.

[0053] exist Figures 2E to 2I The process described can also be performed in, for example Figure 1D This is implemented on the semiconductor device structure 100 shown. In some embodiments, in Figure 1D The dielectric material 190 shown is in Figure 2I The dielectric material 148 shown, and in Figure 1D The semiconductor device structure 100 shown also includes a buffer layer 132, a barrier layer 138, a seed layer 140, an adhesive layer 144, a passivation layer 146, and a conductive component 152.

[0054] Figure 3 This is a cross-sectional view of one of the various manufacturing stages of the semiconductor device structure 100 according to an alternative embodiment. In some embodiments, the semiconductor device structure 100 includes a dielectric layer 116 disposed on an etch stop layer 114, which is disposed on a conductive member 112. For clarity, in Figure 3Dielectric layer 110 is omitted. A first electrode layer 120 is disposed on dielectric layer 116, dielectric layer 206 is disposed on dielectric layer 116 and first electrode layer 202, and a second electrode layer 204 is disposed on dielectric layer 206. First electrode layer 202 and second electrode layer 204 may contain the same material as first electrode layer 120. First electrode layer 202 and second electrode layer 204 may be patterned to form multiple MIM structures 208 (two shown), with dielectric layer 206 disposed between first electrode layer 202 and second electrode layer 204 in all MIM structures 208. For example, firstly, a continuous conductive layer is deposited on dielectric layer 116, and then the continuous conductive layer is patterned to form multiple first electrode layers 202 on dielectric layer 116. Next, dielectric layer 206 is deposited on dielectric layer 116 and first electrode layer 202. Dielectric layer 206 may be a continuous layer disposed on multiple first electrode layers 202. Another continuous conductive layer is deposited on dielectric layer 206, and the continuous conductive layer is patterned to form a plurality of second electrode layers 204 above corresponding first electrode layers 202. In some embodiments, dielectric layer 206 comprises the same material as dielectric layer 180, and dielectric layer 206 serves as a current path for reducing plasma-induced damage (PID). Therefore, in some embodiments, dielectric layer 206 extends through the entire substrate 102. Figure 1A This releases static charge accumulated in different layers of the semiconductor device structure 100. In some embodiments, the dielectric layer 206 comprises two or more layers, for example, in... Figure 2A The dielectric layer 126 or 128 is a dielectric layer of two or more layers.

[0055] like Figure 3 As shown, a passivation layer 130 is formed on the dielectric layer 206 and the second electrode layer 204. A conductive component 142 extends through the passivation layer 130, the plurality of MIM structures 208, the dielectric layer 116, and the etch stop layer 114, thereby electrically contacting the conductive component 112, such as... Figure 3 As shown. The barrier layer 138 and the seed layer 140 can be disposed between the conductive component 142 and the passivation layer 130, the MIM structure 208, the dielectric layer 116, and the etch stop layer 114. The dielectric material 148 is disposed on the passivation layer 130 and the conductive component 142.

[0056] This disclosure provides a semiconductor device structure in various embodiments, including a dielectric layer 180 disposed between two dielectric layers 116, 182. The dielectric layer 180 has a k-value greater than about 20 and a band gap less than about 5 eV. Some embodiments can achieve several advantages. For example, the dielectric layer 180 can be used as a current path to release static charge accumulated on the surfaces of the dielectric layers 116, 182 during plasma processing. Therefore, device degradation is reduced.

[0057] One embodiment is a semiconductor device structure. The semiconductor device structure includes an interconnect structure, a first dielectric layer, and a second dielectric layer. The interconnect structure is disposed above a substrate. The first dielectric layer is disposed above the interconnect structure. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer includes a dielectric material having a k-value greater than about 20 and a band gap less than about 5 eV. The semiconductor device structure further includes a third dielectric layer and a first conductive component, the third dielectric layer being disposed on the second dielectric layer. The first conductive component is disposed on the third dielectric layer. The first conductive component includes a first portion extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer, and a second portion disposed on the third dielectric layer.

[0058] In some embodiments, the second dielectric layer comprises TiO2, TiO, BaO, or Ta2O5. In some embodiments, the second dielectric layer has a thickness of about 1 angstrom to about 20 angstroms. In some embodiments, the semiconductor device structure further includes an etch stop layer disposed between the interconnect structure and the first dielectric layer, wherein a first portion of the first conductive member extends through the etch stop layer. In some embodiments, the semiconductor device structure further includes a fourth dielectric layer, wherein the etch stop layer is disposed on the fourth dielectric layer. In some embodiments, the semiconductor device structure further includes a second conductive member, wherein the first conductive member is electrically connected to the second conductive member. In some embodiments, the first conductive member is a redistribution layer.

[0059] Another embodiment is a semiconductor device structure. The semiconductor device structure includes an interconnect structure and a metal-insulator-metal structure. The interconnect structure is disposed on a substrate. The metal-insulator-metal structure (MIM) is disposed within the interconnect structure. The metal-insulator-metal structure includes a first electrode layer, a second electrode layer, a first dielectric layer, a third electrode layer, and a second dielectric layer. The second electrode layer is disposed above the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The third electrode layer is disposed above the second electrode layer. The second dielectric layer is disposed between the second electrode layer and the third electrode layer. At least one of the first and second dielectric layers includes a dielectric material having a k-value greater than about 20 and a band gap less than about 5 eV. The semiconductor device structure also includes a passivation layer and a conductive component. The passivation layer is disposed on the metal-insulator-metal structure. The conductive component is disposed above the passivation layer. The conductive component includes a first portion extending through the metal-insulator-metal structure and the passivation layer, and a second portion disposed above the passivation layer.

[0060] In some embodiments, the first dielectric layer and the second dielectric layer comprise different materials. In some embodiments, the first dielectric layer comprises TiO2, TiO, BaO, or Ta2O5, and the second dielectric layer comprises oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. In some embodiments, the first dielectric layer has a first thickness, and the second dielectric layer has a second thickness greater than the first thickness. In some embodiments, the k-value of the first dielectric layer is greater than the k-value of the second dielectric layer. In some embodiments, the first thickness is about 1 angstrom to about 20 angstroms. In some embodiments, the first dielectric layer and the second dielectric layer comprise the same material. In some embodiments, the band gap of the dielectric material is about 2.5 eV to about 4.5 eV. In some embodiments, the k-value of the dielectric material is about 20 to about 60.

[0061] Another embodiment is a method for forming a semiconductor device structure. The method includes depositing a first dielectric layer over an interconnect structure and depositing a second dielectric layer on the first dielectric layer. The second dielectric layer comprises a dielectric material having a k-value greater than about 20 and a band gap less than about 5 eV. The method further includes depositing a third dielectric layer on the second dielectric layer, forming openings in the first, second, and third dielectric layers using a plasma process, and releasing static charges accumulated on the surfaces of the first and third dielectric layers through the second dielectric layer.

[0062] In some embodiments, the first and third dielectric layers are deposited using a plasma process. In some embodiments, the method of forming the semiconductor device structure further includes depositing an etch stop layer on an interconnect structure, wherein the first dielectric layer is deposited on the etch stop layer. In some embodiments, the method of forming the semiconductor device structure further includes forming conductive components in an opening, wherein the conductive components contact the second dielectric layer.

[0063] The foregoing outlines components of several embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, comprising: an interconnect structure disposed over a substrate; a first dielectric layer disposed over the interconnect structure; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer comprises a dielectric material having a k-value greater than about 20 and a bandgap less than about 5 eV; a third dielectric layer disposed on the second dielectric layer; and a first conductive feature disposed on the third dielectric layer, wherein the first conductive feature comprises a first portion extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer, and a second portion disposed on the third dielectric layer.

2. The semiconductor device structure of claim 1, wherein the second dielectric layer comprises TiO2, TiO, BaO, or Ta2O5.

3. The semiconductor device structure of claim 1, further comprising an etch stop layer disposed between the interconnect structure and the first dielectric layer, wherein the first portion of the first conductive feature extends through the etch stop layer.

4. A semiconductor device structure, comprising: an interconnect structure disposed over a substrate; a metal-insulator-metal structure disposed in the interconnect structure, wherein the metal-insulator-metal structure comprises: a first electrode layer; a second electrode layer disposed over the first electrode layer; a first dielectric layer disposed between the first electrode layer and the second electrode layer; a third electrode layer disposed over the second electrode layer; and a second dielectric layer disposed between the second electrode layer and the third electrode layer, wherein at least one of the first dielectric layer and the second dielectric layer comprises a dielectric material having a k-value greater than about 20 and a bandgap less than about 5 eV; a passivation layer disposed on the metal-insulator-metal structure; and a conductive feature disposed over the passivation layer, wherein the conductive feature comprises a first portion extending through the metal-insulator-metal structure and the passivation layer, and a second portion disposed over the passivation layer.

5. The semiconductor device structure of claim 4, wherein the first dielectric layer comprises TiO2, TiO, BaO, or Ta2O5, and the second dielectric layer comprises an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu.

6. The semiconductor device structure of claim 5, wherein the first dielectric layer has a first thickness, and the second dielectric layer has a second thickness greater than the first thickness.

7. The semiconductor device structure of claim 6, wherein the first dielectric layer has a k-value greater than a k-value of the second dielectric layer.

8. The semiconductor device structure of claim 4, wherein the bandgap of the dielectric material is about 2.5 eV to about 4.5 eV.

9. A method of forming a semiconductor device structure, comprising: depositing a first dielectric layer over an interconnect structure; depositing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV; depositing a third dielectric layer on the second dielectric layer; forming an opening in the first dielectric layer, the second dielectric layer, and the third dielectric layer by a plasma process; and releasing electrostatic charges accumulated on surfaces of the first dielectric layer and the third dielectric layer through the second dielectric layer.

10. The method of claim 9, wherein the first dielectric layer and the third dielectric layer are deposited by a plasma process.

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