High-conductivity and heat-dissipation chip and manufacturing method thereof

Abstract

The invention provides a high-conductivity and heat-dissipation chip and a manufacturing method thereof. The manufacturing method of the high-conductivity and heat-dissipation chip comprises the following steps: providing a substrate with a first surface and a second surface opposite to the first surface, forming at least one arc-shaped groove in the substrate, and filling a heat-dissipation material in the at least one groove; therefore, the heat dissipation effect of the substrate can be improved, the substrate structure is protected, and the service life of the substrate is prolonged.

Description

TECHNICAL FIELD

[0001] The present application relates to a chip and a process thereof, in particular, to a process for manufacturing a chip with high conductivity and heat dissipation, and a structure of the chip with high conductivity and heat dissipation. BACKGROUND

[0002] Semiconductor is widely used in consumer goods or electronic devices, such as laser, rectifier, oscillator, light emitter, amplifier, light detector, etc.

[0003] As electronic components, with the progress of technology, simplification is the trend of development. However, for common wafer materials such as silicon, germanium or gallium arsenide, the thermal and electrical conductivity coefficients are small, so the thermal and electrical conductivity effects are poor. For example, when used in high-power electronic components, they are easily damaged by thermal expansion or thermal stress.

[0004] In the prior art, metal materials that can conduct heat and electricity are added to semiconductor materials. However, due to the different expansion coefficients of metal and semiconductor materials, internal stress is easily generated to damage the semiconductor material (such as wafer).

[0005] Therefore, how to improve the thermal and electrical conductivity of the wafer or chip through structural design improvement to overcome the above-mentioned defects has become one of the important issues to be solved in this industry. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a manufacturing method of a chip with high conductivity and heat dissipation, which comprises: providing a substrate having a first surface and an opposite second surface, the substrate being arranged on a carrier plate. Grinding the second surface of the substrate. Coating a first photoresist on the second surface to form a first photoresist layer. Exposing the first photoresist layer through a first mask to form a preset pattern on the first photoresist layer, the preset pattern comprising at least one arc. Developing the first photoresist layer to form a plurality of trenches corresponding to the preset pattern. Etching the substrate corresponding to the plurality of trenches to form at least one groove in the substrate. Removing the first photoresist layer. Sputtering a seed layer on the substrate, the seed layer covering the second surface and the bottom wall of the at least one groove. Coating a second photoresist to form a second photoresist layer on the seed layer. Exposing the second photoresist layer through a second mask to form an electroplating area in the second photoresist layer in the at least one groove. Developing the second photoresist layer to remove the electroplating area. Electroplating a metal material in the at least one groove, the metal material filling the at least one groove. Removing the second photoresist layer. Peeling off the substrate and the carrier plate.

[0007] According to a feasible embodiment, the thickness of the ground substrate is less than or equal to 100 microns.

[0008] According to a feasible embodiment, the depth of the at least one groove is greater than or equal to 90 microns.

[0009] The application also provides a method for manufacturing a high-conductivity and high-heat-dissipation chip, comprising: providing a substrate having a first surface and an opposite second surface, the substrate being disposed on a carrier; grinding the second surface of the substrate; sputtering a seed layer on the second surface of the substrate; electroplating a metal layer on the seed layer corresponding to the second surface; and separating the substrate from the carrier.

[0010] According to an embodiment, the thickness of the ground substrate is less than or equal to 10 microns.

[0011] According to an embodiment, the thickness of the metal layer is greater than or equal to 90 microns.

[0012] According to an embodiment, the method for manufacturing a high-conductivity and high-heat-dissipation chip further comprises a dividing step of cutting the substrate into a plurality of chips after the substrate is separated from the carrier.

[0013] According to an embodiment, the substrate is a gallium arsenide substrate, and the carrier is a sapphire substrate.

[0014] According to an embodiment, the seed layer is at least one of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), palladium (Pd), carbon (C), tin (Sn), tungsten (W), titanium / copper (Ti / Cu), titanium / silver (Ti / Ag), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), chromium / silver (Cr / Ag), and chromium / nickel (Cr / Ni), an alloy, or a combination thereof.

[0015] According to an embodiment, the metal layer is at least one of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), tin (Sn), palladium (Pd), nickel / gold (Ni / Au), nickel / palladium / gold (Ni / Pd / Au), nickel / silver (Ni / Ag), and copper / nickel / silver (Cu / Ni / Au), an alloy, or a combination thereof.

[0016] According to an embodiment, the predetermined pattern is a pattern having a spiral, one end of the spiral being located at an edge of the substrate.

[0017] The application also provides a high-conductivity and high-heat-dissipation chip, comprising a chip body, a seed layer, and a filling body. The chip body has a first surface and a second surface, and at least one groove is formed on the second surface, at least a portion of the at least one groove being arc-shaped. The seed layer is located on the second surface and the bottom wall of the at least one groove. The filling body is a metal material, and the filling body fills the at least one groove.

[0018] According to an embodiment, the thickness of the chip body is less than or equal to 100 microns.

[0019] According to an embodiment, the at least one trench of the chip body has a depth of greater than or equal to 90 microns.

[0020] According to an embodiment, the at least one trench of the chip body has a spiral shape.

[0021] According to an embodiment, one end of the spiral is located at an edge of the chip body.

[0022] The present application also provides a high-conductivity and heat-dissipation chip, comprising a chip body, a seed layer, and a metal layer. The chip body has a first surface and a second surface. The seed layer is located on the second surface. The metal layer is formed of a metal material, and the metal layer is located on the seed layer. The thickness of the chip body is less than or equal to 10 microns. The thickness of the metal layer is greater than or equal to 90 microns.

[0023] According to an embodiment, the seed layer of the high-conductivity and heat-dissipation chip is at least one of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), palladium (Pd), carbon (C), tin (Sn), tungsten (W), titanium / copper (Ti / Cu), titanium / silver (Ti / Ag), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), chromium / silver (Cr / Ag), and chromium / nickel (Cr / Ni), an alloy, or a combination.

[0024] According to an embodiment, the metal material of the high-conductivity and heat-dissipation chip is at least one of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), tin (Sn), palladium (Pd), nickel / gold (Ni / Au), nickel / palladium / gold (Ni / Pd / Au), nickel / silver (Ni / Ag), and copper / nickel / silver (Cu / Ni / Au), an alloy, or a combination.

[0025] For details of other functions and embodiments of the present application, see the following description with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments described in the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0027] Figure 1 Process flow diagram for the manufacturing method of the high-conductivity and heat-dissipation chip of an embodiment of the present application;

[0028] Figure 2 Appearance schematic diagram of the high-conductivity and heat-dissipation chip of an embodiment of the present application;

[0029] Figure 3 For Figure 2 a partial cross-sectional view of the embodiment shown in FIG. 1;

[0030] Figure 4 a process flow diagram of a method for manufacturing a high-conductivity and heat-dissipation chip according to another embodiment of the present application;

[0031] Figure 5 a schematic view of the appearance of a high-conductivity and heat-dissipation chip according to another embodiment of the present application;

[0032] Figure 6 For Figure 5 a cross-sectional view of the embodiment shown in FIG. 1. DETAILED DESCRIPTION

[0033] In the following embodiments, the positional relationships described include: up, down, left, and right, which are based on the directions in which the components are shown in the drawings, unless otherwise specified.

[0034] Referring to Figure 1 a process flow diagram of a method for manufacturing a high-conductivity and heat-dissipation chip according to another embodiment of the present application. The method 100 for manufacturing a high-conductivity and heat-dissipation chip includes at least steps S1 to S14.

[0035] Step S1: A substrate is provided, the substrate has a first surface and an opposite second surface, and the substrate is disposed on a carrier plate. In some embodiments, the substrate is a gallium arsenide substrate (wafer). The carrier plate is, for example but not limited to, sapphire.

[0036] Step S2: The second surface of the substrate is ground. In some embodiments, the thickness of the substrate is ground to be less than or equal to 100 microns, forming a thin film layer.

[0037] Step S3: A first photoresist is coated on the second surface, forming a first photoresist layer.

[0038] Step S4: The first photoresist layer is exposed through a first mask, so that the first photoresist layer forms a predetermined pattern, the predetermined pattern including at least one arc shape. According to some embodiments, the photoresist layer is exposed by a yellow light. The predetermined pattern is, for example, a circular shape, a bracket shape, or a U shape. According to some embodiments, the predetermined pattern is a pattern with a vortex.

[0039] Step S5: The first photoresist layer is developed, forming a plurality of trenches corresponding to the predetermined pattern.

[0040] Step S6: The substrate is etched corresponding to the plurality of trenches, forming at least one groove in the substrate. In some embodiments, in the horizontal direction, one end of the groove is located at the edge of the substrate. According to some embodiments, after etching, the depth of the groove is greater than or equal to 90 microns.

[0041] In some embodiments, the width W of the trench is 5-10 micrometers. In some embodiments, the width W of the trench is 8 micrometers.

[0042] Step S7: Remove the first photoresist layer.

[0043] Step S8: Sputter a seed layer onto the substrate, the seed layer covering the second surface and the bottom wall of at least one trench. (See...) Figure 3 According to some embodiments, the seed layer is at least one, an alloy, or a combination of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), palladium (Pd), carbon (C), tin (Sn), tungsten (W), titanium / copper (Ti / Cu), titanium / silver (Ti / Ag), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), chromium / silver (Cr / Ag), and chromium / nickel (Cr / Ni). According to some embodiments, the seed layer is a tungsten-titanium alloy and gold (TiW / Au).

[0044] Step S9: Apply a second photoresist to form a second photoresist layer on the seed layer.

[0045] Step S10: Expose the second photoresist layer through the second photomask to form an electroplating area in the second photoresist layer within at least one trench.

[0046] Step S11: Develop the second photoresist layer and remove the electroplated area.

[0047] Step S12: Electroplating a metal material into at least one trench, filling at least one trench completely. According to some embodiments, the metal material is at least one, an alloy, or a combination of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), tin (Sn), palladium (Pd), nickel / gold (Ni / Au), nickel / palladium / gold (Ni / Pd / Au), nickel / silver (Ni / Ag), and copper / nickel / silver (Cu / Ni / Au). According to some embodiments, the trench is filled with copper metal, which has good thermal conductivity.

[0048] Step S13: Remove the second photoresist layer.

[0049] Step S14: Separate the substrate from the carrier plate. According to some embodiments, the adhesive layer between the substrate and the carrier plate can be softened by light heating or other heating methods, making the substrate and the carrier plate separable.

[0050] exist Figure 1 In the illustrated embodiment, the manufacturing method of the high conductivity and heat dissipation chip further includes a dicing step S15. After step S14, step S15 is performed to dicing the substrate to form multiple chips. It should be noted that each chip after dicing has a chip body, a seed layer, and metal material filled in the trench (see below for details).

[0051] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the appearance of a high conductivity and heat dissipation chip Z1 according to an embodiment of this application. Figure 3 for Figure 2 A partial cross-sectional view of the illustrated embodiment. In this embodiment, the high conductivity and heat dissipation chip Z1 includes a chip body 1, a seed layer 2, and a filler 3. The chip body 1 has a first surface 11 and a second surface 12, and the chip body 1 has a trench 13 formed on the second surface 12. At least a portion of the trench 13 is arc-shaped. Figure 2 As shown, trench 13 is vortex-shaped. One end of the vortex is located at the edge of the chip body 1. Seed layer 2 is located on the second surface 12 and the bottom wall 131 of trench 13, as shown. Figure 3 As shown. The filler 3 is made of metal and fills the groove 13 completely.

[0052] According to some embodiments, the seed layer 2 is at least one, an alloy, or a combination of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), palladium (Pd), carbon (C), tin (Sn), tungsten (W), titanium / copper (Ti / Cu), titanium / silver (Ti / Ag), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), chromium / silver (Cr / Ag), and chromium / nickel (Cr / Ni). According to some embodiments, the seed layer 2 is a tungsten-titanium alloy and gold (TiW / Au).

[0053] According to some embodiments, the metallic material is at least one, alloy, or combination of titanium (Ti), nickel (Ni), copper (Cu), chromium (Cr), silver (Ag), gold (Au), tin (Sn), palladium (Pd), nickel / gold (Ni / Au), nickel / palladium / gold (Ni / Pd / Au), nickel / silver (Ni / Ag), and copper / nickel / silver (Cu / Ni / Au). According to some embodiments, the trench 13 is filled with copper metal.

[0054] According to some embodiments, the thickness of the chip body is less than or equal to 100 micrometers.

[0055] According to some embodiments, the depth of trench 13 is greater than or equal to 90 micrometers.

[0056] Please see Figure 4 This is a schematic diagram illustrating the process of manufacturing a high conductivity and heat dissipation chip according to another embodiment of this application. In this embodiment, the manufacturing method of the high conductivity and heat dissipation chip includes at least steps P1 to P6.

[0057] Step P1: Provide a substrate having a first surface and an opposite second surface, the substrate being disposed on a carrier plate.

[0058] Step P2: Grinding the second surface of the substrate. According to some embodiments, after fine grinding, the thickness of the substrate is less than or equal to 10 micrometers.

[0059] Step P3: Sputter a seed layer onto the second surface of the substrate.

[0060] Step P4: Corresponding to the second surface, electroplating metal material forms a metal layer on the seed layer. The thickness of the metal layer is greater than or equal to 90 micrometers.

[0061] Step P5: Separate the substrate from the carrier plate.

[0062] For information involving metal layers and seed layers, please refer to the above description. Figure 4 The illustrated embodiments and Figure 1 The difference in the illustrated embodiment is that, Figure 1 The metallic material is filled in the trench. Figure 4 A metallic material forms a metallic layer, which covers the seed layer (see...). Figure 5 or Figure 6 ).

[0063] In this embodiment, the manufacturing method of the high conductivity and heat dissipation chip further includes a dicing step P6. After step P5, step P6 is performed to dice the substrate to form multiple chips. According to some embodiments, each of the diced chips has a chip body, a seed layer, and a metal layer (see below for details).

[0064] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the appearance of a high conductivity and heat dissipation chip Z2 according to an embodiment of this application. Figure 6 for Figure 5 The illustrated embodiment is a cross-sectional view. The high conductivity and heat dissipation chip Z2 includes a chip body 1, a seed layer 2, and a metal layer 4. The chip body 1 has a first surface 11 and a second surface 12. The seed layer 2 is located on the second surface 12. The metal layer 4 is formed of a metallic material and is located on the seed layer 2. The thickness of the chip body 1 is less than or equal to 10 micrometers. The thickness of the metal layer 4 is greater than or equal to 90 micrometers.

[0065] For details regarding the structure and materials of the chip body 1, seed layer 2, and metal layer 4, please refer to the above description. Figure 5 and Figure 2 The difference in the illustrated embodiment is that, Figure 2 The high conductivity and heat dissipation chip Z1 shown has its metal material filled in the trench 131. Figure 6 The high conductivity and heat dissipation chip Z2 shown has a metal layer 4 formed by its metal material, which covers the seed layer 2.

[0066] "Beneficial effects of the embodiments"

[0067] One of the beneficial effects of this application is that the manufacturing method of the high conductivity and heat dissipation chip provided by this application can design a heat dissipation structure and fill heat dissipation material in the thin substrate (chip) by "electroplated metal material in at least one trench of the substrate, and the metal material fills at least one trench", so as to improve the problem of high heat generated by the substrate (chip) under use, increase the heat dissipation effect of the substrate (chip), protect the substrate (chip) structure and extend the service life of the substrate (chip).

[0068] One of the beneficial effects of this application is that the chip provided by this application can improve the heat dissipation function of the thin substrate (chip) through the technical solutions of "the chip (substrate) has at least one trench, which is formed on the second surface, and at least a portion of the trench is arc-shaped" and "the filler is a metal material, which fills the at least one trench", so as to improve the heat dissipation problem in application, thereby strengthening the structure of the substrate (chip) and extending the service life of the substrate (chip).

[0069] Furthermore, the trench has at least one arc shape, so that the metal material filling the trench can effectively resist thermal stress within the substrate (chip) without thermal expansion damaging the chip. According to one embodiment, the trench is vortex-shaped, and one end of the trench is located at the edge of the chip.

[0070] Another beneficial effect of this application is that the manufacturing method of the high conductivity and heat dissipation chip provided by this application can fully cover the surface of the substrate (chip) by using the technical solution of "electroplated metal material to form a metal layer on the second surface", which can further improve the heat dissipation effect of high power chip, protect the substrate (chip) structure and extend the service life of substrate (chip).

[0071] Furthermore, another beneficial effect of this application is that the high conductivity and heat dissipation chip provided by this application can, through the technical solution of "the metal layer is formed of a metal material and is located on the seed layer. The thickness of the chip body is less than or equal to 10 micrometers. The thickness of the metal layer is greater than or equal to 90 micrometers", a metal layer is set on the surface of a thin substrate (chip). In this way, the heat dissipation effect of the high-power chip can be improved, the substrate (chip) structure can be protected and the service life of the substrate (chip) can be extended.

[0072] The embodiments and / or implementation methods described above are merely preferred embodiments and / or implementation methods for implementing the technology of this application, and are not intended to limit the implementation methods of the technology of this application in any way. Any person skilled in the art may make some modifications or alterations to other equivalent embodiments without departing from the scope of the technical means disclosed in this application, but these should still be regarded as the technology or embodiments that are substantially the same as those of this application.

Claims

1. A method for manufacturing a high-conductivity and high-heat-dissipation chip, characterized by comprising the steps of: A method for manufacturing a high-conductivity and high-heat-dissipation chip includes: ​ providing a substrate having a first surface and an opposite second surface, the substrate being disposed on a carrier substrate, the second surface being exposed; grinding the second surface of the substrate; applying a first photoresist on the second surface to form a first photoresist layer; exposing the first photoresist layer through a first mask to form a predetermined pattern on the first photoresist layer, the predetermined pattern including at least one arc shape; developing the first photoresist layer to form a plurality of trenches corresponding to the predetermined pattern; etching the substrate corresponding to the plurality of trenches to form at least one groove in the substrate; removing the first photoresist layer; sputtering a seed layer on the substrate, the seed layer covering the second surface and a bottom wall of the at least one groove; applying a second photoresist to form a second photoresist layer on the seed layer; exposing the second photoresist layer through a second mask to form an electroplating area on the second photoresist layer in the at least one groove; developing the second photoresist layer to remove the electroplating area; electroplating a metal material in the at least one groove, the metal material filling the at least one groove; removing the second photoresist layer; and peeling the substrate from the carrier substrate.

2. A method of manufacturing a high-conductivity and heat-dissipation chip, characterized by comprising: A method for manufacturing a high-conductivity and high-heat-dissipation chip includes: providing a substrate having a first surface and an opposite second surface, the substrate being disposed on a carrier substrate, the second surface being exposed; grinding the second surface of the substrate; sputtering a seed layer on the second surface of the substrate; corresponding to the second surface, electroplating a metal material on the seed layer to form a metal layer; and peeling the substrate from the carrier substrate.

3. The method of manufacturing a highly conductive and heat dissipating chip according to claim 1 or 2, wherein The method for manufacturing a high-conductivity and high-heat-dissipation chip further includes a segmentation step, after the peeling of the substrate from the carrier substrate, cutting the substrate into a plurality of chips.

4. The method of manufacturing a highly conductive and heat dissipating chip according to claim 1 or 2, wherein The substrate is a gallium arsenide substrate, and the carrier substrate is a sapphire substrate.

5. The method of manufacturing a highly conductive and heat dissipating chip according to claim 1 or 2, wherein The seed layer is at least one of titanium, nickel, copper, chromium, silver, gold, palladium, carbon, tin, tungsten, titanium / copper, titanium / silver, titanium / nickel, chromium / copper, chromium / silver, and chromium / nickel, an alloy, or a combination.

6. The method of manufacturing a highly conductive and heat dissipating chip according to claim 1 or 2, wherein The metal material is at least one of titanium, nickel, copper, chromium, silver, gold, tin, palladium, nickel / gold, nickel / palladium / gold, nickel / silver, and copper / nickel / silver, an alloy, or a combination.

7. The method of claim 1, wherein the method further comprises: The predetermined pattern is a pattern having a vortex.

8. The method of claim 1, wherein the method further comprises: One end of the at least one groove is located at an edge of the substrate.

9. The method of claim 1, wherein the method further comprises: The thickness of the substrate after grinding is less than or equal to 100 microns.

10. The method of claim 1, wherein the method further comprises: The depth of the at least one groove is greater than or equal to 90 microns.

11. The method of claim 1, wherein the method further comprises: The thickness of the substrate after grinding is less than or equal to 10 microns.

12. The method of claim 2, wherein the high conductive and heat dissipating chip is manufactured by the steps of: The thickness of the metal layer is greater than or equal to 90 microns. ​ 13. A high conductive and heat dissipating chip, characterized in that, A high-conductivity and high-heat-dissipation chip includes: a chip body having a first surface and a second surface, the chip body having at least one groove formed on the second surface, at least a portion of the at least one groove having an arc shape; a seed layer located on the second surface and a bottom wall of the at least one groove; and a filling body being a metal material, the filling body filling the at least one groove.

14. A high conductive and heat dissipating chip, characterized in that, A high-conductivity and high-heat-dissipation chip includes: a chip body having a first surface and a second surface; a seed layer on the second surface; and a metal layer formed of a metal material, the metal layer on the seed layer; wherein a thickness of the chip body is less than or equal to 10 microns; and wherein a thickness of the metal layer is greater than or equal to 90 microns.

15. The highly conductive and heat dissipating chip of claim 13 or 14, wherein, the seed layer is at least one of titanium, nickel, copper, chromium, silver, gold, palladium, carbon, tin, tungsten, titanium / copper, titanium / silver, titanium / nickel, chromium / copper, chromium / silver, and chromium / nickel, an alloy, or a combination.

16. The highly conductive and heat dissipating chip of claim 13 or 14, wherein, the metal material is at least one of titanium, nickel, copper, chromium, silver, gold, tin, palladium, nickel / gold, nickel / palladium / gold, nickel / silver, and copper / nickel / silver, an alloy, or a combination.

17. The highly conductive and heat dissipating chip of claim 13, wherein, a thickness of the chip body is less than or equal to 100 microns.

18. The highly conductive and heat dissipating chip of claim 13, wherein, a depth of the at least one trench is greater than or equal to 90 microns.

19. The highly conductive and heat dissipating chip of claim 13, wherein, the at least one trench is a spiral shape.

20. The highly conductive and heat dissipating chip of claim 13, wherein, one end of the at least one trench is at an edge of the chip body.

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