Diamond substrate-based semiconductor heterogeneous integrated chip structure and preparation method thereof
By employing diamond substrates and high thermal conductivity materials in semiconductor heterogeneous integrated chips, the performance degradation problem caused by self-heating effect of semiconductor devices under high power was solved, achieving improvements in high frequency, high power and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-12
- Publication Date
- 2026-03-10
AI Technical Summary
As semiconductor power devices become smaller and their power increases, their reliability and stability are challenged, especially due to the self-heating effect of the active region of the chip, which leads to performance degradation at high power.
The semiconductor heterogeneous integrated chip structure using a diamond substrate includes a diamond substrate, contact electrodes, metal interconnects, inter-chip isolation dielectric, inverted Si-based devices, GaAs-based devices, and GaN-based devices. Isolation is achieved through device isolation regions, and heat dissipation performance is improved by utilizing high thermal conductivity materials and high-k dielectric layers.
It improves the heat dissipation performance and stability of semiconductor heterogeneous integrated chips, solves the self-heating effect problem, enables high-frequency and high-power applications, and improves the stability of devices.
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Figure CN121646355A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices, in particular to a semiconductor hetero-integrated chip structure based on a diamond substrate and a preparation method thereof. BACKGROUND
[0002] With the continuous development of semiconductor power devices, higher output power and frequency are required. At the same time, in order to achieve higher integration, the size of the device also needs to be reduced. However, with the miniaturization of the size and the increase of the power, the reliability and stability of the device are greatly challenged. Due to the increase of the power density, the self-heating effect problem of the chip active area becomes serious, resulting in performance deterioration under high power. SUMMARY
[0003] In order to solve the above technical problems, the purpose of the present application is to provide a semiconductor hetero-integrated chip structure based on a diamond substrate and a preparation method thereof, to improve the heat dissipation performance of the integrated chip of different semiconductor materials and to improve the stability of the integrated chip.
[0004] The first technical solution adopted by the present application is: a semiconductor hetero-integrated chip structure based on a diamond substrate, comprising a diamond substrate, a contact electrode, a metal interconnection line, an inter-chip isolation medium, an inverted Si-based device, an inverted GaAs-based device, an inverted GaN-based device, a device isolation region and a source back via connection layer arranged in order from bottom to top, wherein the inverted Si-based device, the inverted GaAs-based device and the inverted GaN-based device are isolated by the device isolation region. The diamond substrate is used for heat dissipation; The contact electrode is used to realize the electrical connection of the diamond substrate and the electronic device; The metal interconnection line is used to connect different electronic devices; The inter-chip isolation medium is used to fill the diamond substrate flat; The inverted Si-based device realizes the preset target function as needed; The inverted GaAs-based device realizes the preset target function as needed; The inverted GaN-based device realizes the preset target function as needed; The device isolation region is used to form electrical isolation between different active device regions; The source back via connection layer is used to lead out the source of each device to the back surface and unify grounding.
[0005] Further, it further comprises: The material of the diamond substrate is diamond, and the thickness is 30-1500 μm; The metal interconnection line is any one of lead Au, Al, Cu; The material of the interlayer isolation medium is AlN. The material of the device isolation region is SiO2.
[0006] Further, the inverted Si-based device comprises, from bottom to top, a Si-based device source electrode, a Si-based device drain electrode, a Si-based device gate metal electrode, a gate dielectric layer, a doped Si material, a Si substrate, and a first source back via, a part of the contact surface of the Si-based device source electrode, the Si-based device drain electrode, and the Si-based device gate metal electrode being connected to a contact electrode arranged on the diamond substrate, respectively, and a part of the contact surface of the Si-based device source electrode being grounded through the first source back via and a source back via connection layer, wherein: The Si-based device source electrode is used as an injection end of carriers, as a starting point of the majority carriers into the conductive channel of the device. The Si-based device drain electrode is used as a collection end of carriers, as a terminal point of the majority carriers leaving the conductive channel of the device. The Si-based device gate metal electrode is used to realize switching and amplification of the circuit by applying a voltage. The gate dielectric layer is used to form a “capacitive dielectric” between the gate metal electrode and the Si substrate, to realize physical and electrical isolation. The doped Si material is used to accurately control its conductivity type (N-type or P-type) and conductivity. The Si substrate is used as a mechanical support carrier and an electrical performance basic platform for building all semiconductor components and integrated circuits. The first source back via is used to lead out the source electrode of the device to the back surface for unified grounding.
[0007] Further, the gate dielectric layer is a high-k dielectric layer, which is formed on the doped Si material and the Si substrate by atomic layer deposition, and after F ions are injected into the gate dielectric layer, nitrogen elements are doped into the gate dielectric layer by decoupling plasma nitridation process and post-nitridation annealing process, the material of the gate dielectric layer is HfO2, ZrO2, TaO2, HfO2, ZrO2, TaO2, or an oxide composed of two or more of them, and the thickness of the Si substrate is 10-150 μm.
[0008] Further, the inverted GaAs-based device comprises, from bottom to top, a GaAs-based device source electrode, a GaAs-based device drain electrode, a GaAs-based device gate metal electrode, a GaAs-based device barrier layer, a GaAs-based device channel layer, a GaAs-based device buffer layer, a GaAs substrate layer, and a second source back via, a portion of the contact surface of the GaAs-based device source electrode, the GaAs-based device drain electrode, and the GaAs-based device gate metal electrode are connected to the contact electrode arranged on the diamond substrate, respectively, and a portion of the contact surface of the GaAs-based device source electrode is connected to the ground through the second source back via and the source back via connection layer, wherein: The GaAs-based device source electrode is used as the injection end of the carriers, and serves as the starting point of the majority carriers entering the conductive channel of the device. The GaAs-based device drain electrode is used as the collection end of the carriers, and serves as the terminal point of the majority carriers leaving the conductive channel of the device. The GaAs-based device gate metal electrode is used for switching and amplifying the circuit by applying a voltage. The GaAs-based device barrier layer is used for controlling and restricting the flow of carriers, and forms an energy barrier for carrier transport. The GaAs-based device channel layer is used to provide a transport path for the carriers. The GaAs-based device buffer layer is used for insulation and isolation, and supports the growth of the active layer. The GaAs substrate layer is used as a mechanical support carrier and an electrical performance basic platform for building all semiconductor components and integrated circuits. The second source back via is used to lead out the source electrode of the device to the back surface for unified grounding.
[0009] Further, the material of the GaAs-based device barrier layer is one of AlGaAs or AlInGaAs or InGaP, the material of the GaAs-based device channel layer is one of GaAs or InGaAs, a two-dimensional electron gas channel is formed at the interface region between the AlGaAs barrier layer and the GaAs-based device channel layer, the GaAs-based device barrier layer further has a Si-doped layer inside, and the portions of the GaAs-based device source electrode, the GaAs-based device drain electrode, and the GaAs-based device barrier layer that are in contact with each other are all AuGe alloy layers.
[0010] Further, the inverted GaN-based device comprises, from bottom to top, a GaN-based device source electrode, a GaN-based device drain electrode, a GaN-based device gate metal electrode, a GaN-based device barrier layer, a GaN-based device channel layer, a GaN-based device buffer layer, a GaN-based device substrate layer, and a third source back via, the contact surfaces of the GaN-based device source electrode, the GaN-based device drain electrode, and the GaN-based device gate metal electrode are connected to the contact electrodes arranged on the diamond substrate, respectively, and the contact surface of the GaN-based device source electrode is connected to the ground through the third source back via and the source back via connection layer, wherein: The GaN-based device source electrode is used as the injection end of the carriers, and serves as the starting point of the majority carriers entering the conductive channel of the device. The GaN-based device drain electrode is used as the collection end of the carriers, and serves as the terminal point of the majority carriers leaving the conductive channel of the device. The GaN-based device gate metal electrode is used for switching and amplifying the circuit by applying a voltage. The GaN-based device barrier layer is used for controlling and restricting the flow of carriers, and forms an energy barrier for the carrier transport. The GaN-based device channel layer is used for providing a transport path for the carriers. The GaN-based device buffer layer is used for isolation and insulation, and supports the growth of the active layer. The GaN-based device substrate layer is used as a mechanical support carrier and an electrical performance basic platform for building all semiconductor components and integrated circuits. The third source back via is used for leading out the source electrode of the device to the back surface and connecting to the ground.
[0011] Further, the material of the GaN-based device barrier layer is one of AlGaN, InAlN, or AlN, the material of the GaN-based device channel layer is GaN, the GaN-based device source electrode and the GaN-based device drain electrode form ohmic contact with the GaN-based device barrier layer, the GaN-based device gate metal electrode forms Schottky contact with the GaN-based device barrier layer, and the heterojunction interface formed by the GaN-based device channel layer and the GaN-based device barrier layer has a two-dimensional electron gas as a conductive channel.
[0012] Further, the first source back via, the second source back via, and the third source back via are all circular holes or square holes, the diameters are all 1-100 μm, and the filling materials are all one of Au or Cu.
[0013] The second technical solution adopted by the present application is a preparation method of a semiconductor heterojunction integrated chip structure based on a diamond substrate, comprising the following steps: Select Si-based wafer, prepare Si-based device, set Si-based device source electrode, Si-based device drain electrode and Si-based device gate metal electrode, thin the back surface of Si substrate, etch to prepare first source electrode back via, polish the front surface of Si substrate; Select GaAs-based wafer, prepare GaAs-based device, set GaAs-based device source electrode, GaAs-based device drain electrode and GaAs-based device gate metal electrode, thin the back surface of GaAs substrate, etch to prepare second source electrode back via, polish the front surface of GaAs substrate; Select GaN-based wafer, prepare GaN-based device, set GaN-based device source electrode, GaN-based device drain electrode and GaN-based device gate metal electrode, thin the back surface of GaN-based device substrate layer, etch to prepare third source electrode back via, polish the front surface of GaN-based device substrate layer; Set interchip isolation medium, contact electrode and metal interconnection line on the diamond substrate, and polish the surface; Invert the Si-based device, GaAs-based device and GaN-based device, and bond with the diamond substrate, the Si-based device source electrode, the Si-based device drain electrode, the Si-based device gate metal electrode, the GaAs-based device source electrode, the GaAs-based device drain electrode, the GaAs-based device gate metal electrode, the GaN-based device source electrode, the GaN-based device drain electrode and the GaN-based device gate metal electrode are connected with the contact electrode on the diamond substrate respectively, to obtain a bonded wafer surface; Deposit medium and polish the bonded wafer surface, etch to prepare source electrode back via, deposit the metal of source electrode back via connection layer, to obtain a semiconductor heterojunction integrated chip based on the diamond substrate.
[0014] The device and the preparation method have the advantages that the device and the preparation method do not change the traditional semiconductor chip manufacturing process, use the diamond substrate, improve the heat dissipation performance of the integrated chip of different semiconductor materials, solve the problem that the self-heating effect of the active area of the traditional integrated chip becomes serious due to the increase of the power density, and improve the performance deterioration problem under high power, which is beneficial to improve the self-heating effect, realize high-frequency and high-power application, and improve the stability of the integrated chip. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 is a frame schematic diagram of the semiconductor heterojunction integrated chip structure based on the diamond substrate of the application; Figure 2 is a step schematic diagram of the preparation method of the semiconductor heterojunction integrated chip structure based on the diamond substrate of the application.
[0016] Figure reference numerals: 1. Diamond substrate; 2. Contact electrode; 3. Metal interconnect; 4. Inter-chip isolation dielectric; 51. Silicon-based device; 52. GaAs-based device; 53. GaN-based device; 5. Source electrode of Si-based device; 6. Drain electrode of Si-based device; 7. Gate metal electrode of Si-based device; 8. Gate dielectric layer; 9. Doped Si material; 10. Si substrate; 11. Source electrode of GaAs-based device; 12. Drain electrode of GaAs-based device; 13. Gate metal electrode of GaAs-based device; 14. Barrier layer of GaAs-based device; 15. 16. GaAs-based device channel layer; 17. GaAs-based device buffer layer; 18. GaAs substrate; 19. GaN-based device source electrode; 20. GaN-based device drain electrode; 21. GaN-based device gate metal electrode; 22. GaN-based device barrier layer; 23. GaN-based device channel layer; 24. GaN-based device buffer layer; 25. GaN-based device substrate layer; 261. Device isolation region; 262. First source back via; 263. Second source back via; 264. Third source back via; 27. Source back via connection layer. Detailed Implementation
[0017] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
[0018] First, it's important to note that low heat dissipation has become a crucial factor limiting the performance improvement of semiconductor power devices, and this heat dissipation capability is primarily determined by the substrate material. Diamond, as an ultra-wide bandgap semiconductor material, currently boasts the highest thermal conductivity among substrates, reaching 22 W / cm·K. This is 44 times, 14.6 times, and 5.5 times that of sapphire (0.5 W / cm·K), silicon (1.5 W / cm·K), and silicon carbide (4 W / cm·K), respectively. Compared to commonly used SiC and Si-based semiconductor microwave power devices, diamond-based semiconductor power devices offer superior heat dissipation capabilities, potentially enabling smaller size and higher power density power devices. This will promote the miniaturization, integration, and high-power applications of future RF power devices and related systems.
[0019] Based on this, the device structure proposed in this embodiment includes, from bottom to top, a diamond substrate, contact electrodes and metal interconnects, an inverted Si-based device, an inverted GaAs-based device, and an inverted GaN-based device. The use of a diamond substrate structure can improve the heat dissipation capacity of the device-related system, and solve the problem that the self-heating effect of the active region of the chip becomes serious due to the increase in power density in heterogeneous integrated semiconductor device-related systems, leading to performance degradation under high power. This is beneficial to improve its self-heating effect, realize high-frequency and high-power applications, and improve the stability of the device-related system.
[0020] Reference Figure 1 This invention provides a semiconductor heterogeneous integrated chip structure based on a diamond substrate, comprising, from bottom to top, a diamond substrate, contact electrodes, metal interconnects, an inter-chip isolation medium, an inverted Si-based device, an inverted GaAs-based device, an inverted GaN-based device, a device isolation region, and a source back via connection layer. The inverted Si-based device, the inverted GaAs-based device, and the inverted GaN-based device are isolated by the device isolation region, wherein: The diamond substrate is used to solve the heat dissipation bottleneck of high-power, high-density integrated devices; The contact electrodes are used to achieve electrical connection between the diamond substrate and electronic devices; The metal interconnects are used for electrical connections between different devices to achieve a specific circuit function. The inter-chip isolation medium is used to fill the diamond substrate, enabling a more stable connection between the diamond substrate and the electronic device. The inverted Si-based device can perform specific functions as needed, such as amplification, and a much stronger output can be precisely and proportionally controlled with a weak control signal. The inverted GaAs-based device can perform specific functions as needed, such as amplification, and can precisely and proportionally control a much stronger output with a weak control signal. The inverted GaN-based device can perform specific functions as needed, such as amplification, and a much stronger output can be precisely and proportionally controlled with a weak control signal. The device isolation region is used to form electrical isolation between different active device regions to prevent them from interfering with each other; The source back via connection layer is used to bring the source of each device out to the back and ground it uniformly.
[0021] In this embodiment, the diamond substrate 1 is made of diamond and has a thickness of 30-1500 μm. The metal interconnects 3 are made of Au, Al, or Cu, which have good conductivity, high chemical stability, and low electromobility. Specific circuit functions are achieved by depositing the metal interconnects 3 on the diamond substrate 1. The inter-chip isolation dielectric 4 is made of a material with high thermal conductivity and low coefficient of thermal expansion, such as AlN. The device isolation region 25 is made of SiO2. The source back via 26 is a circular or square hole with a diameter of 1-100 μm, and the filling material includes Au or Cu.
[0022] The inverted Si-based device 51, the inverted GaAs-based device 52, and the inverted GaN-based device 53 are isolated by the device isolation region 25, and some of their electrodes are connected by metal interconnects 3. Some of the source electrodes 5 of the Si-based device, 11 of the GaAs-based device, and 18 of the GaN-based device are grounded through source back vias and source back via connection layers 27, thereby forming a circuit with certain functions.
[0023] Furthermore, the diamond substrate is made of diamond and has a thickness of 30-1500 μm; the metal interconnects are any one of Au, Al, and Cu; the inter-chip isolation medium is made of AlN; and the isolation region of the device is made of SiO2.
[0024] Furthermore, the inverted Si-based device includes, from bottom to top, a Si-based device source electrode, a Si-based device drain electrode, a Si-based device gate metal electrode, a gate dielectric layer, a doped Si material, a Si substrate, and a first source back via. Partial contact surfaces of the Si-based device source electrode, the Si-based device drain electrode, and the Si-based device gate metal electrode are respectively connected to contact electrodes disposed on a diamond substrate. Partial contact surfaces of the Si-based device source electrode are grounded through the first source back via and a source back via connection layer. The source electrode of the Si-based device is used as the carrier injection end, serving as the starting point for majority carriers to enter the conductive channel of the device. The drain electrode of the Si-based device is used as the collection end for charge carriers, serving as the endpoint for majority charge carriers to leave the conductive channel of the device. The gate metal electrodes of the Si-based device are used to realize core functions such as switching and amplification of the circuit by applying voltage; The gate dielectric layer serves as a highly efficient, electrically modulated "capacitive dielectric" between the gate metal electrode and the silicon substrate, while simultaneously achieving reliable physical and electrical isolation. The doped Si material is a key technology for precisely controlling its conductivity type (N-type or P-type) and conductivity (resistivity). The Si substrate is used as a mechanical support carrier and electrical performance foundation platform for building all semiconductor components and integrated circuits; The first source back via is used to bring the source of the device out to the back for unified grounding.
[0025] In this embodiment, the inverted Si-based device 51 includes, from bottom to top, a Si-based device source electrode 5, a Si-based device drain electrode 6, and a Si-based device gate metal electrode 7, a gate dielectric layer 8, a doped Si material 9, a Si substrate 10, and a first source back via 261; the portion of the Si-based device source electrode 5, the portion of the Si-based device drain electrode 6, and the portion of the Si-based device gate metal electrode 7 are respectively connected to the contact electrode 2 disposed on the diamond substrate 1.
[0026] In the inverted Si-based device 51, the gate dielectric layer 8 is a high-k dielectric layer, and its material is HfO2, ZrO2, or TaO2, or an oxide composed of two or more of HfO2, ZrO2, and TaO2. In the inverted Si-based device 51, the gate dielectric layer 8 is formed on the doped Si material 9 and the Si substrate 10 by atomic layer deposition. In the inverted Si-based device 51, F ions are implanted into the gate dielectric layer 8. After F ion implantation into the gate dielectric layer 8, nitrogen is incorporated into the gate dielectric layer 8 through a decoupled plasma nitriding process and a post-nitriding annealing process.
[0027] More specifically, the gate dielectric layer is a high-k dielectric layer, which is formed on the doped Si material and Si substrate by atomic layer deposition. After F ions are implanted into the gate dielectric layer, nitrogen is incorporated into the gate dielectric layer by a decoupled plasma nitriding process and a post-nitriding annealing process. The material of the gate dielectric layer is an oxide composed of two or more of HfO2, ZrO2, TaO2, HfO2, ZrO2, and TaO2. The thickness of the Si substrate is 10-150 μm.
[0028] Furthermore, the inverted GaAs-based device includes, from bottom to top, a GaAs-based device source electrode, a GaAs-based device drain electrode, a GaAs-based device gate metal electrode, a GaAs-based device barrier layer, a GaAs-based device channel layer, a GaAs-based device buffer layer, a GaAs substrate layer, and a second source back via. Partial contact surfaces of the GaAs-based device source electrode, the GaAs-based device drain electrode, and the GaAs-based device gate metal electrode are respectively connected to contact electrodes disposed on a diamond substrate. Partial contact surfaces of the GaAs-based device source electrode are grounded through the second source back via and a source back via connection layer. The source electrode of the GaAs-based device is used as the carrier injection end, serving as the starting point for majority carriers to enter the conductive channel of the device. The drain electrode of the GaAs-based device is used as the collection end for charge carriers, serving as the endpoint for majority charge carriers to leave the conductive channel of the device. The gate metal electrode of the GaAs-based device is used to realize the core functions of the circuit, such as switching and amplification, by applying voltage; The barrier layer of the GaAs-based device is used to control and confine the flow of charge carriers (electrons or holes), forming an energy barrier for charge carrier transport, thereby realizing specific electrical functions, such as modulating current, providing isolation, or restricting charge carriers from entering a specific region. The channel layer of the GaAs-based device is used to provide a high-speed, lossless transport path for charge carriers (usually electrons) and is the core region for current conduction. The GaAs-based device buffer layer is used for isolation and insulation. Its core mission is to grow a high-quality crystal template with extremely high resistivity and extremely low defect density on a semi-insulating GaAs substrate to support the subsequent growth of the active layer. The GaAs substrate layer is used as a mechanical support carrier and electrical performance foundation platform for building all semiconductor components and integrated circuits; The second source back via is used to bring the source of the device out to the back for unified grounding.
[0029] More specifically, the material of the barrier layer of the GaAs-based device is one of AlGaAs, AlInGaAs, or InGaP, the material of the channel layer of the GaAs-based device is one of GaAs or InGaAs, a two-dimensional electron gas channel is formed in the interface region between the AlGaAs barrier layer and the channel layer of the GaAs-based device, and a Si doped layer is also present inside the barrier layer of the GaAs-based device. The portions of the source electrode and the drain electrode of the GaAs-based device that are in contact with the barrier layer of the GaAs-based device are all AuGe alloy layers.
[0030] In this embodiment, the inverted GaAs-based device 52 includes, from bottom to top, a GaAs-based device source electrode 11, a GaAs-based device drain electrode 12, a GaAs-based device gate metal electrode 13, a GaAs-based device barrier layer 14, a GaAs-based device channel layer 15, a GaAs-based device buffer layer 16, a GaAs substrate layer 17, and a second source back via 262; the portion of the GaAs-based device source electrode 11, the portion of the GaAs-based device drain electrode 12, and the portion of the GaAs-based device gate metal electrode 13 are respectively connected to the contact electrode 2 disposed on the diamond substrate 1.
[0031] In the inverted GaAs-based device 52, the material of the GaAs-based device barrier layer 14 is AlGaAs, AlInGaAs, or InGaP; the material of the GaAs-based device channel layer 15 is GaAs or InGaAs; a two-dimensional electron gas channel is formed in the interface region between the AlGaAs barrier layer 14 and the GaAs-based device channel layer 15; the interior of the GaAs-based device barrier layer 14 also has a Si-doped layer, which is used to provide electrons at least; the portions of the GaAs-based device source electrode 11 and the GaAs-based device drain electrode 12 that are in contact with the GaAs-based device barrier layer 14 are both AuGe alloy layers.
[0032] The Si-doped layer was obtained by delta-doping of Si atomic layers, with the Si atomic layers distributed in a planar region and a doping concentration of 2 × 10⁻⁶. 12 cm -2 ~5×10 12 cm -2 The portions of the GaAs-based device source electrode 11 and GaAs-based device drain electrode 12 that contact the GaAs-based device barrier layer 14 are both AuGe alloy layers, and the AuGe alloy layer also contains AuGa compounds. The material of the GaAs-based device barrier layer 14 is AlGaAs; the GaAs-based device barrier layer 14 also contains Ge atoms, wherein the AuGa compounds in the AuGe alloy layer are formed by the diffusion of some Ga atoms from the GaAs-based device barrier layer 14 to the AuGe alloy layer and their reaction with the Au atoms in the AuGe alloy layer, and the Ge atoms in the GaAs-based device barrier layer 14 are formed by the diffusion of some Ge atoms from the AuGe alloy layer to the GaAs-based device barrier layer 14, and the Ge atoms fill the Ga vacancies formed by the diffusion of Ga atoms in the GaAs-based device barrier layer 14. Both the GaAs-based device source electrode 11 and GaAs-based device drain electrode 12 include sequentially stacked AuGe alloy layers, Ni layers, and Au layers. The thickness of the AuGe alloy layer is 80nm to 100nm.
[0033] Furthermore, the inverted GaN-based device includes, from bottom to top, a GaN-based device source electrode, a GaN-based device drain electrode, a GaN-based device gate electrode, a GaN-based device barrier layer, a GaN-based device channel layer, a GaN-based device buffer layer, a GaN-based device substrate layer, and a third source back via. Partial contact surfaces of the GaN-based device source electrode, the GaN-based device drain electrode, and the GaN-based device gate electrode are respectively connected to contact electrodes disposed on a diamond substrate. Partial contact surfaces of the GaN-based device source electrode are grounded through the third source back via and a source back via connection layer. The source electrode of the GaN-based device is used as the carrier injection end, serving as the starting point for majority carriers to enter the conductive channel of the device. The drain electrode of the GaN-based device is used as the collection end of the charge carriers, serving as the endpoint for the majority of charge carriers to leave the conductive channel of the device. The gate metal electrode of the GaN-based device is used to realize the core functions of the circuit, such as switching and amplification, by applying voltage; The barrier layer of the GaN-based device is used to control and confine the flow of charge carriers (electrons or holes), forming an energy barrier for charge carrier transport, thereby realizing specific electrical functions, such as modulating current, providing isolation, or restricting charge carriers from entering a specific region. The channel layer of the GaN-based device is used to provide a high-speed, lossless transport path for charge carriers (usually electrons) and is the core region for current conduction. The GaN-based device buffer layer is used for isolation and insulation. Its core mission is to grow a high-quality crystal template with extremely high resistivity and extremely low defect density on a semi-insulating GaN substrate to support the subsequent growth of the active layer. The GaN-based device substrate layer serves as a mechanical support carrier and an electrical performance foundation platform for constructing all semiconductor components and integrated circuits. The third source back via is used to bring the source of the device out to the back for unified grounding.
[0034] More specifically, the material of the barrier layer of the GaN-based device is one of AlGaN, InAlN, or AlN, the material of the channel layer of the GaN-based device is GaN, the source electrode and the drain electrode of the GaN-based device both form ohmic contacts with the barrier layer of the GaN-based device, the gate metal electrode of the GaN-based device forms a Schottky contact with the barrier layer of the GaN-based device, and the heterojunction interface formed by the channel layer and the barrier layer of the GaN-based device has a two-dimensional electron gas, which serves as a conductive channel.
[0035] In this embodiment, the inverted GaN-based device 53 includes, from bottom to top, a GaN-based device source electrode 18, a GaN-based device drain electrode 19, a GaN-based device gate metal electrode 20, a GaN-based device barrier layer 21, a GaN-based device channel layer 22, a GaN-based device buffer layer 23, a GaN-based device substrate layer 24, and a third source back via 263; the GaN-based device source electrode 18, GaN-based device drain electrode 19, and GaN-based device gate metal electrode 20 are respectively connected to the contact electrode 2 disposed on the diamond substrate 1.
[0036] The inverted GaN-based device 53 includes a GaN-based device substrate layer 24, a GaN-based device buffer layer 23, a GaN-based device channel layer 22, and a GaN-based device barrier layer 21. A GaN-based device source electrode 18, a GaN-based device drain electrode 19, and a GaN-based device gate metal electrode 20 are disposed on the GaN-based device barrier layer 21. The material of the GaN-based device barrier layer 21 is AlGaN, InAlN, or AlN. The material of the GaN-based device channel layer 22 is GaN. The GaN-based device source electrode 18 and the GaN-based device drain electrode 19 both form ohmic contacts with the GaN-based device barrier layer 21. The GaN-based device gate metal electrode 20 forms a Schottky contact with the GaN-based device barrier layer 21. A two-dimensional electron gas is generated near the heterojunction interface formed by the GaN-based device channel layer 22 and the GaN-based device barrier layer 21, which serves as a conductive channel.
[0037] Reference Figure 2 A method for fabricating a semiconductor heterogeneous integrated chip structure based on a diamond substrate includes the following steps: S100. Select a Si-based wafer, fabricate a Si-based device, set the source electrode, drain electrode and gate metal electrode of the Si-based device, thin the back side of the Si substrate, etch the first source back via, and polish the front side of the Si substrate. S200. Select a GaAs-based wafer, fabricate a GaAs-based device, set the source electrode, drain electrode, and gate metal electrode of the GaAs-based device, thin the back side of the GaAs substrate, etch to prepare the second source back via, and polish the front side of the GaAs substrate. S300. Select a GaN-based wafer, fabricate a GaN-based device, set the source electrode, drain electrode and gate metal electrode of the GaN-based device, thin the back side of the GaN-based device substrate, etch the third source back via, and polish the front side of the GaN-based device substrate. S400: An inter-chip isolation medium, contact electrodes, and metal interconnects are disposed on a diamond substrate, and the surface is polished. S500: Invert the Si-based device, GaAs-based device, and GaN-based device and bond them to a diamond substrate. Connect the source electrode, drain electrode, and gate electrode of the Si-based device, the source electrode, drain electrode, and gate electrode of the GaAs-based device, the source electrode, drain electrode, and gate electrode of the GaN-based device, and the contact electrode on the diamond substrate respectively to obtain the bonded wafer surface. S600: Deposit dielectric and polish the bonded wafer surface, etch to prepare source back vias, deposit metal of source back via connection layer, and obtain semiconductor heterogeneous integrated chip based on diamond substrate.
[0038] In this embodiment, a Si-based wafer is selected to fabricate a Si-based device 51, with a source electrode 5, a drain electrode 6, and a gate electrode 7. The back side of the Si substrate 10 is thinned, and the front side is polished. A GaAs-based wafer is selected to fabricate a GaAs-based device 52, with a source electrode 11, a drain electrode 12, and a gate electrode 13. The back side of the GaAs substrate 17 is thinned, and the front side is polished. A GaN-based wafer is selected to fabricate a GaN-based device 53, with a source electrode 18, a drain electrode 19, and a gate electrode 20. The back side of the GaN substrate layer 24 is thinned, and the front side is polished. An inter-wafer isolation medium 4, contact electrodes 2, and metal interconnects 3 are disposed on a diamond substrate 1 and the surface is polished. Si-based devices 51, GaAs-based devices 52, and GaN-based devices 53 are inverted and bonded to the diamond substrate 1. The source electrode 5, drain electrode 6, and gate metal electrode 7 of the Si-based devices, the source electrode 11, drain electrode 12, gate metal electrode 13, source electrode 18, drain electrode 19, and gate metal electrode 20 of the GaN-based devices are respectively connected to the contact electrodes 2 on the diamond substrate 1. Based on the bonded wafer surface, a dielectric is deposited and polished. Source back vias are etched and the metal of the source back via connection layer 27 is deposited.
[0039] In this process, after thinning the back side of the Si substrate 10, a first source back via 261 is etched and a metal source back via connection layer 27 is deposited. After thinning the back side of the GaAs substrate 17, a second source back via 262 is etched and a metal source back via connection layer 27 is deposited. After thinning the back side of the GaN-based device substrate 24, a third source back via 263 is etched and a metal source back via connection layer 27 is deposited. The etching of the source back via is skipped, and the metal source back via connection layer 27 is deposited.
[0040] Therefore, the embodiments of the present invention have the following advantages compared with the prior art: 1) This invention does not change the traditional semiconductor chip manufacturing process, but uses a diamond substrate to improve the heat dissipation performance of integrated chips made of different semiconductor materials. It can solve the problem that the self-heating effect of the active area of the chip becomes serious due to the increase of power density, which leads to the performance degradation under high power. It is beneficial to improve its self-heating effect, realize high frequency and high power applications, and improve the stability of integrated chips.
[0041] 2) The method for fabricating integrated chips based on diamond substrates provided by this invention is simple and relatively controllable, compatible with existing processes, and can significantly improve the performance of integrated devices.
[0042] 3) The method for fabricating various semiconductor heterogeneous integrated chips based on diamond substrates provided by this invention is suitable for a wide variety of semiconductor materials for integrated chips and has good scalability. In addition to the Si-based, GaAs-based and GaN-based devices of this invention, it is also applicable to InP-based, Ga2O3-based, two-dimensional materials, amorphous oxide and other semiconductor chips.
[0043] In summary, this invention can solve the problem that the self-heating effect of the active region of the chip becomes serious due to the increase of power density in traditional semiconductor heterogeneous chip solutions, leading to performance degradation at high power. It is beneficial to improve the self-heating effect, realize the high density, miniaturization and high power of heterogeneous integrated chips, and improve the stability of integrated devices.
[0044] The content of the above method embodiments is applicable to this structural embodiment. The specific functions implemented in this structural embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.
[0045] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.
Claims
1. A semiconductor hetero-integrated chip structure based on a diamond substrate, characterized in that, It comprises, from bottom to top, a diamond substrate, a contact electrode, a metal interconnection line, a wafer spacing medium, an inverted Si-based device, an inverted GaAs-based device, an inverted GaAs-based device, a device isolation region and a source back via connection layer, wherein: The diamond substrate is used for heat dissipation; The contact electrode is used to realize the electrical connection between the diamond substrate and the electronic device; The metal interconnection line is used to connect different electronic devices; The wafer spacing medium is used to fill the diamond substrate; The inverted Si-based device realizes the preset target function as needed; The inverted GaAs-based device realizes the preset target function as needed; The inverted GaAs-based device realizes the preset target function as needed; The device isolation region is used to form electrical isolation between different active device regions; The source back via connection layer is used to lead out the source of each device to the back surface and ground uniformly.
2. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 1, wherein, It also comprises: The material of the diamond substrate is diamond, and the thickness is 30-1500μm; The metal interconnection line is any one of lead Au, Al and Cu; The material of the wafer spacing medium is AlN; The material of the device isolation region is SiO2.
3. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 2, wherein, The inverted Si-based device comprises, from bottom to top, a Si-based device source electrode, a Si-based device drain electrode, a Si-based device gate metal electrode, a gate dielectric layer, a doped Si material, a Si substrate and a first source back via, wherein: The Si-based device source electrode is used as the injection end of the carrier, which is the starting point of the majority carrier into the device conductive channel; The Si-based device drain electrode is used as the collection end of the carrier, which is the end point of the majority carrier leaving the device conductive channel; The Si-based device gate metal electrode is used for switching and amplifying circuits by applying voltage; The gate dielectric layer is used to form a "capacitive dielectric" between the gate metal electrode and the silicon substrate, realizing physical and electrical isolation; The doped Si material is used to accurately control its conductivity type (N-type or P-type) and conductivity; The Si substrate is used as a mechanical support carrier and an electrical performance basic platform for building all semiconductor components and integrated circuits; The first source back via is used to lead out the source of the device to the back surface and ground uniformly.
4. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 3, wherein, The gate dielectric layer is a high-k dielectric layer, which is formed on the doped Si material and Si substrate by atomic layer deposition, and after F ions are implanted in the gate dielectric layer, nitrogen elements are doped into the gate dielectric layer by decoupling plasma nitridation process and post-nitridation annealing process, the material of the gate dielectric layer is HfO2, ZrO2, TaO2, HfO2, ZrO2, TaO2, or an oxide composed of two or more of them, and the thickness of the Si substrate is 10-150 μm.
5. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 4, wherein, The inverted GaAs-based device comprises, from bottom to top, a GaAs-based device source electrode, a GaAs-based device drain electrode, a GaAs-based device gate metal electrode, a GaAs-based device barrier layer, a GaAs-based device channel layer, a GaAs-based device buffer layer, a GaAs substrate layer, and a second source back via, the partial contact surfaces of the GaAs-based device source electrode, the GaAs-based device drain electrode, and the GaAs-based device gate metal electrode are respectively connected with the contact electrodes arranged on the diamond substrate, and the partial contact surface of the GaAs-based device source electrode is connected with the ground through the second source back via and a source back via connection layer, wherein: The GaAs-based device source electrode is used as the injection end of carriers, and serves as the starting point of the majority carriers entering the conductive channel of the device; The GaAs-based device drain electrode is used as the collection end of carriers, and serves as the terminal point of the majority carriers leaving the conductive channel of the device; The GaAs-based device gate metal electrode is used for realizing the switching and amplification of the circuit by applying voltage; The GaAs-based device barrier layer is used for controlling and restricting the flow of carriers, and forms the energy barrier for the transport of carriers; The GaAs-based device channel layer is used for providing the transport path for carriers; The GaAs-based device buffer layer is used for isolation and insulation, and supports the growth of the active layer; The GaAs substrate layer is used as the mechanical support carrier and the electrical performance basic platform for constructing all semiconductor components and integrated circuits; The second source back via is used for leading out the source electrode of the device to the back surface for unified grounding.
6. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 5, wherein, The material of the GaAs-based device barrier layer is one of AlGaAs, AlInGaAs, and InGaP, the material of the GaAs-based device channel layer is one of GaAs and InGaAs, a two-dimensional electron gas channel is formed in the interface region between the AlGaAs barrier layer and the GaAs-based device channel layer, the GaAs-based device barrier layer further has a Si doped layer inside, and the portions of the GaAs-based device source electrode, the GaAs-based device drain electrode, and the GaAs-based device barrier layer that are in contact with each other are all AuGe alloy layers.
7. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 6, wherein, The inverted GaN-based device comprises, from bottom to top, a GaN-based device source electrode, a GaN-based device drain electrode, a GaN-based device gate metal electrode, a GaN-based device barrier layer, a GaN-based device channel layer, a GaN-based device buffer layer, a GaN-based device substrate layer, and a third source electrode back via, the contact surfaces of the GaN-based device source electrode, the GaN-based device drain electrode, and the GaN-based device gate metal electrode are connected to the contact electrodes arranged on the diamond substrate, respectively, and the contact surface of the GaN-based device source electrode is connected to the ground through the third source electrode back via and the source electrode back via connection layer, wherein: The GaN-based device source electrode is used as the injection end of the carriers, and serves as the starting point of the majority carriers entering the conductive channel of the device; The GaN-based device drain electrode is used as the collection end of the carriers, and serves as the terminal point of the majority carriers leaving the conductive channel of the device; The GaN-based device gate metal electrode is used for switching and amplifying the circuit by applying voltage; The GaN-based device barrier layer is used for controlling and restricting the flow of carriers, and forms an energy barrier for carrier transport; The GaN-based device channel layer is used for providing a transport path for the carriers; The GaN-based device buffer layer is used for isolation and insulation, and supports the growth of the active layer; The GaN-based device substrate layer is used as a mechanical support carrier and an electrical performance basic platform for building all semiconductor components and integrated circuits; The third source electrode back via is used to lead out the source electrode of the device to the back surface for unified grounding.
8. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 7, wherein, The material of the GaN-based device barrier layer is one of AlGaN, InAlN, or AlN, the material of the GaN-based device channel layer is GaN, the GaN-based device source electrode and the GaN-based device drain electrode form ohmic contact with the GaN-based device barrier layer, the GaN-based device gate metal electrode forms Schottky contact with the GaN-based device barrier layer, and the heterojunction interface formed by the GaN-based device channel layer and the GaN-based device barrier layer has two-dimensional electron gas as the conductive channel.
9. The semiconductor hetero-integrated chip structure based on a diamond substrate according to claim 8, wherein, The first source electrode back via, the second source electrode back via, and the third source electrode back via are all circular holes or square holes, the diameters are all 1-100 μm, and the filling materials are all one of Au or Cu.
10. A method of fabricating a semiconductor hetero-integrated chip structure based on a diamond substrate, characterized in that, The method comprises the following steps: Selecting a Si-based wafer, preparing a Si-based device, arranging a Si-based device source electrode, a Si-based device drain electrode, and a Si-based device gate metal electrode, thinning the back surface of the Si substrate, etching to prepare a first source electrode back via, and polishing the front surface of the Si substrate; Selecting a GaAs-based wafer, preparing a GaAs-based device, arranging a GaAs-based device source electrode, a GaAs-based device drain electrode, and a GaAs-based device gate metal electrode, thinning the back surface of the GaAs substrate, etching to prepare a second source electrode back via, and polishing the front surface of the GaAs substrate; Select a GaN-based wafer, prepare a GaN-based device, set a source electrode, a drain electrode and a gate metal electrode of the GaN-based device, thin the back of a substrate layer of the GaN-based device, etch and prepare a third source back via, polish the front of the substrate layer of the GaN-based device; Set an inter-chip isolation medium, a contact electrode and a metal interconnection line on a diamond substrate, and polish the surface; Invert the Si-based device, the GaAs-based device and the GaN-based device, and bond them with the diamond substrate; connect the source electrode, the drain electrode, the gate metal electrode of the Si-based device, the source electrode, the drain electrode and the gate metal electrode of the GaAs-based device, and the source electrode, the drain electrode and the gate metal electrode of the GaN-based device with the contact electrode on the diamond substrate respectively, and obtain a bonded wafer surface; Deposit a medium on the bonded wafer surface and polish it, etch and prepare a source back via, deposit a metal of a source back via connection layer, and obtain a semiconductor hetero-integrated chip based on the diamond substrate.