Chip-embedded TGV glass substrate and manufacturing method thereof

Abstract

The invention discloses a chip-embedded TGV glass substrate and a manufacturing method thereof. The method comprises the following steps: providing a glass core plate; forming a temporary metal mask layer on the first surface of the glass core plate; performing pattern transfer and etching on the temporary metal mask layer; performing dry etching on the glass core plate in the second pattern area to form a first TGV hole; etching the glass core plate in the first pattern area and the second pattern area through a dry method to form a second TGV hole and deepen the depth of the first TGV hole; removing the temporary metal mask layer, performing metallization to form a first conductive through hole and a second conductive through hole, and manufacturing a first rewiring layer; grinding the second surface of the glass core plate until the first conductive through hole is exposed; etching the glass core plate through a dry method to form a cavity until the second conductive through hole is exposed; providing a chip, and embedding the chip into the cavity; therefore, no-damage cavity processing is realized, and the problems of surface damage, dimensional deviation, lateral erosion, microcracks or surface roughening and the like of the substrate are effectively avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor advanced packaging technology, in particular to a TGV glass substrate embedded with a chip and a manufacturing method thereof. BACKGROUND

[0002] With the chip process entering the 3nm and below nodes, Moore's Law is gradually slowing down, and packaging technology has become a key breakthrough to improve system performance. Compared with the thermal stability defects (warp rate > 0.3% @ 200℃), high signal loss (0.5dB / cm @ 10GHz) and line width limitation of organic substrates, glass substrates have become the preferred carrier for advanced packaging such as HBM4 stacking and CPO optical interconnection due to their adjustable CTE, ultra-low dielectric loss, support for semiconductor lithography process, and ability to achieve fine line processing.

[0003] In the context of the current demand for heterogeneous integration of chips, embedded packaging has rapidly risen due to its ability to simultaneously solve the two major problems of "Moore's Law slowing down" and "system-level power wall". Embedded packaging requires pre-etching cavities in the substrate manufacturing process for chip mounting. Traditional cavity manufacturing processes include mechanical milling slotting, chemical etching, and laser processing. Mechanical milling slotting can easily cause glass breakage and micro-cracks, affecting the mechanical strength of the substrate; chemical etching has the problems of serious side etching and uneven etching, making it difficult to control the size accuracy of the cavity; laser processing increases the surface roughness, affecting the reliability of subsequent metallization processes. These process defects severely limit the application of glass substrates in embedded packaging.

[0004] Therefore, there is a need to develop a new glass substrate embedded structure and its manufacturing process to improve the reliability and service life of glass substrates and meet market demand. SUMMARY

[0005] The present application aims to at least partially solve one of the above technical problems. To this end, the present application aims to provide a TGV glass substrate embedded with a chip and a manufacturing method thereof, which realizes non-damage cavity processing through ICP dry etching, effectively avoiding problems such as substrate surface damage, size deviation, side etching, micro-cracks or surface roughening, and improving packaging density and long-term stability.

[0006] To achieve the above-mentioned purpose, the present application proposes in a first aspect a manufacturing method of a TGV glass substrate embedded with a chip, comprising the following steps:

[0007] providing a glass core plate, the glass core plate having opposite first and second surfaces;

[0008] A temporary metal mask layer is formed on the first surface of the glass core plate; the temporary metal mask layer includes at least one metal layer, the material of which is selected from at least one of titanium, chromium, copper, silver, gold, aluminum, and molybdenum;

[0009] Pattern transfer and etching are performed on the temporary metal mask layer to define the first pattern region and the second pattern region;

[0010] The glass core plate is dry-etched in the second patterned area to form a first TGV hole;

[0011] The glass core plate is dry-etched in the first patterned area and the second patterned area to form a second TGV hole and deepen the depth of the first TGV hole;

[0012] Remove the temporary metal mask layer, metallize the inner walls of the first TGV hole and the second TGV hole to form a first conductive via and a second conductive via, and fabricate a first redistribution layer on the first surface. The first redistribution layer is electrically connected to the first conductive via and the second conductive via.

[0013] The second surface of the glass core plate is ground until the first conductive via is exposed; then, the glass core plate is dry-etched to form a cavity until the second conductive via is exposed; the dry etching is inductively coupled plasma etching, and the etching gas includes one or more of fluorine-containing gases, oxygen, and inert gases; the fluorine-containing gas is selected from at least one of carbon tetrafluoride, octafluorocyclobutane, trifluoromethane, and sulfur hexafluoride; the operating conditions for dry etching to form the cavity are: ICP source power 800-2500W, bias power 50-200W, and pressure 5-20mTorr;

[0014] A chip is provided and embedded in the cavity, wherein the bumps of the chip are thermo-bonded to the second conductive via, so that the chip is electrically connected to the second conductive via;

[0015] An insulating layer is formed in the gap between the chip and the cavity and on the second surface. Then, a second redistribution layer is fabricated on the insulating layer and the chip. The second redistribution layer is electrically connected to the first conductive via and the chip.

[0016] According to a method for fabricating a TGV glass substrate for embedded chips according to the present invention, the method performs pattern transfer and etching on a temporary metal mask layer. Utilizing the rigidity and etching resistance of the metal material, compared with traditional photoresist masks, deformation during the pattern transfer process can be significantly reduced, and the first pattern area (corresponding to the second TGV hole) and the second pattern area (corresponding to the first TGV hole) can be accurately defined, laying the foundation for the precise forming of the subsequent TGV holes. Then, step-by-step dry etching is used to control the size and depth of the TGV holes. Subsequently, grinding and dry etching are used in synergy to control the positional accuracy of the cavities. Thus, by using dry etching to fabricate TGV holes and cavities, problems such as damage or dimensional deviations to the substrate surface caused by mechanical processing, side etching caused by chemical agents, and microcracks or surface roughening caused by laser processing can be avoided, reducing glass substrate damage and improving long-term packaging stability. This method can reduce the difficulty of process implementation and improve process accuracy. Furthermore, by adjusting the size and distribution of the first and second pattern areas, different numbers and diameters of TGV conductive vias can be designed to meet the electrical connection requirements of high I / O chips; the cavity size can be adjusted according to the chip size to accommodate the embedding of different functional chips such as logic chips, memory chips, and optoelectronic devices, thus achieving heterogeneous integration.

[0017] In addition, the method for fabricating a TGV glass substrate with an embedded chip according to the present invention may also have the following additional technical features:

[0018] Optionally, the temporary metal mask layer includes a first metal sublayer and a second metal sublayer stacked sequentially, the first metal sublayer being adjacent to a first surface of the glass core, and the second metal sublayer being located on the side of the first metal sublayer away from the glass core.

[0019] Furthermore, the material of the first metal sublayer is selected from at least one of titanium, chromium, tantalum, and molybdenum, and the material of the second metal sublayer is selected from at least one of copper, silver, and gold.

[0020] More specifically, the first metal sublayer is a titanium layer, and the second metal sublayer is a copper layer.

[0021] Optionally, the step of performing pattern transfer and etching on the temporary metal mask layer to define the first pattern region and the second pattern region includes:

[0022] A first photosensitive medium layer is coated on the second metal sublayer. After the pattern transfer is completed, the second metal sublayer is etched to define the first pattern area.

[0023] The first photosensitive medium layer is removed, and a second photosensitive medium layer is coated on the first patterned area and the second metal sublayer. After the pattern transfer is completed, the first metal sublayer is etched to define the second patterned area.

[0024] Furthermore, after forming the first TGV hole, the second photosensitive medium layer is removed to expose the first metal sublayer. Then, the first metal sublayer is etched, and the glass core plate is dry-etched to form the second TGV hole and deepen the depth of the first TGV hole.

[0025] To achieve the above objectives, a second aspect of the present invention provides a TGV glass substrate for embedding a chip, which is fabricated using the above-described method; the TGV glass substrate comprises:

[0026] Glass core sheet, having opposing first and second surfaces;

[0027] A cavity is formed from the second surface within the glass core plate;

[0028] One or more first conductive vias penetrate the glass core and are exposed on the first surface and the second surface;

[0029] One or more second conductive vias penetrate the glass core and are exposed to the first surface and the cavity;

[0030] A chip is embedded in the cavity, the chip having one or more bumps formed on the surface of the chip, the bumps being bonded to the second conductive via.

[0031] An insulating layer is formed between the chip and the cavity, and on the second surface;

[0032] A first wiring layer is formed on the first surface and is electrically connected to the first conductive via and the second conductive via.

[0033] A second wiring layer is formed on the insulating layer and the chip, and is electrically connected to the chip and the first conductive via.

[0034] The TGV glass substrate for embedded chips according to the present invention achieves damage-free cavity processing through ICP dry etching, effectively avoiding problems such as substrate surface damage, dimensional deviations, side etching, microcracks, or surface roughening, thereby improving packaging density and long-term stability. Furthermore, the cavity size can be adjusted according to the chip size, accommodating the embedding of different functional chips such as logic chips, memory chips, and optoelectronic devices, achieving heterogeneous integration. Attached Figure Description

[0035] Figure 1 This is a schematic flowchart illustrating the method for fabricating a TGV glass substrate with an embedded chip according to an embodiment of the present invention.

[0036] Figures 2-11 This is a cross-sectional schematic diagram of the substrate for each step of the method for fabricating a TGV glass substrate with an embedded chip according to an embodiment of the present invention.

[0037] Label Explanation:

[0038] Glass core plate 100, first surface 100a, second surface 100b, first TGV hole 110, second TGV hole 120, cavity 130;

[0039] Temporary metal mask layer 200, first metal sublayer 210, second metal sublayer 220;

[0040] First photosensitive medium layer 310, second photosensitive medium layer 320;

[0041] First conductive via 410, second conductive via 420;

[0042] First wiring layer 500;

[0043] Chip 600;

[0044] Insulation layer 700;

[0045] Second wiring layer 800. Detailed Implementation

[0046] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0047] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0048] The embodiments described in this application provide a method for fabricating a TGV glass substrate with an embedded chip. Please refer to [link / reference]. Figure 1 The diagram shows the process flow of this manufacturing method, which includes the following steps:

[0049] S1: A glass core plate is provided, the glass core plate having opposing first and second surfaces;

[0050] S2: A temporary metal mask layer is formed on the first surface of the glass core plate; the temporary metal mask layer includes at least one metal layer, and the material of the metal layer is selected from at least one of titanium, chromium, copper, silver, gold, aluminum, and molybdenum;

[0051] S3: Perform pattern transfer and etching on the temporary metal mask layer to define the first pattern area and the second pattern area;

[0052] S4: The glass core plate is dry-etched in the second pattern area to form a first TGV hole;

[0053] S5: The glass core plate is dry-etched in the first patterned area and the second patterned area to form a second TGV hole and deepen the depth of the first TGV hole;

[0054] S6: Remove the temporary metal mask layer, metallize the inner wall of the first TGV hole and the inner wall of the second TGV hole to form a first conductive via and a second conductive via, and fabricate a first redistribution layer on the first surface, wherein the first redistribution layer is electrically connected to the first conductive via and the second conductive via.

[0055] S7: Grind the second surface of the glass core plate until the first conductive via is exposed; then dry-etch the glass core plate to form a cavity until the second conductive via is exposed; the dry etching is inductively coupled plasma etching, and the etching gas includes one or more of fluorine-containing gases, oxygen and inert gases; the fluorine-containing gas is selected from at least one of carbon tetrafluoride, octafluorocyclobutane, trifluoromethane and sulfur hexafluoride; the operating conditions for dry etching to form the cavity are: ICP source power 800-2500W, bias power 50-200W, pressure 5-20mTorr;

[0056] S8: Provide a chip and embed the chip in the cavity, wherein the bumps of the chip are thermo-bonded to the second conductive via, so that the chip is electrically connected to the second conductive via;

[0057] S9: An insulating layer is formed in the gap between the chip and the cavity and on the second surface. Then, a second redistribution layer is formed on the insulating layer and the chip. The second redistribution layer is electrically connected to the first conductive via and the chip.

[0058] This method first applies a temporary metal mask layer to the first surface of the glass core board, then performs pattern transfer and etching on the temporary metal mask layer. Utilizing the rigidity and etching resistance of the metal material, compared with traditional photoresist masks, deformation during the pattern transfer process can be significantly reduced, accurately defining the first pattern area (the area corresponding to the second TGV hole) and the second pattern area (the area corresponding to the first TGV hole), laying the foundation for the precise forming of the subsequent TGV holes. Then, step-by-step dry etching is used to control the size and depth of the TGV holes. Next, the TGV holes are metallized and the first redistribution layer is fabricated. Then, grinding and dry etching are used in combination to control the cavity position accuracy. Finally, the chip is embedded in the cavity.

[0059] Therefore, using dry etching to fabricate TGV vias and cavities avoids problems such as damage or dimensional deviations to the substrate surface caused by mechanical processing, lateral etching caused by chemical agents, and microcracks or surface roughening caused by laser processing. This reduces glass substrate damage and improves long-term packaging stability. This fabrication method can reduce the difficulty of process implementation and improve process precision. Furthermore, by adjusting the size and distribution of the first and second patterned areas, different numbers and diameters of TGV conductive vias can be designed to meet the electrical connection requirements of high I / O chips. The cavity size can be adjusted according to the chip size, accommodating the embedding of different functional chips such as logic chips, memory chips, and optoelectronic devices, achieving heterogeneous integration.

[0060] In the aforementioned fabrication method, if the cavity and the first TGV aperture are simultaneously fabricated using dry etching, and then the second TGV aperture is fabricated, the following issues arise: Before fabricating the cavity and the first TGV aperture using dry etching, windows need to be opened at corresponding positions on the glass core plate. Since the depths of the two are different, but the dry etching rates are the same, the first TGV aperture is not formed when the cavity is formed. In this case, it is impossible to close the window at the cavity and only allow dry etching of the first TGV area. Furthermore, due to the height difference between the cavity and the glass core plate, the windowing process cannot perform a secondary windowing at the bottom to expose the second TGV area, meaning the second TGV aperture cannot be fabricated. If the cavity is fabricated first, and then the first and second TGV apertures are fabricated in reverse order, the depths of the first and second TGV apertures are different. When the second TGV aperture is completed, it communicates with the cavity and penetrates the glass core plate, which can damage the equipment due to the ICP plasma beam. In addition, even if the ICP plasma does not damage the equipment, the first TGV hole and the second TGV hole need to undergo metallization, electroplating and other processes. Since the Cavity is connected to the second TGV hole, its bottom and sidewalls will also be covered with a metal layer, making it impossible to manufacture the TGV glass substrate for embedding the chip.

[0061] Specifically, please refer to Figures 2 to 11 This is a cross-sectional schematic diagram of the packaging substrate showing each step of the above-described method for fabricating a TGV glass substrate with an embedded chip.

[0062] First, refer to Figure 2 Step S1: A glass core plate 100 is provided, the glass core plate 100 having opposing first surfaces 100a and second surfaces 100b. The thickness of the glass core plate 100 can be 0.2-1mm, and the glass core plate 100 possesses both excellent heat resistance and extremely low dielectric loss factor (D). f It also has a high Young's modulus, is not limited in size, has low cost, strong mechanical stability, and excellent high-frequency electrical properties.

[0063] Next, refer to Figure 3Step S2 is performed: a temporary metal mask layer 200 is formed on the first surface 100a of the glass core plate 100; specifically, the temporary metal mask layer 200 includes at least one metal layer, that is, the temporary metal mask layer 200 can adopt a single-layer or multi-layer metal structure. The material of the metal layer is selected from at least one of titanium, chromium, copper, silver, gold, aluminum, and molybdenum.

[0064] More specifically, the temporary metal mask layer 200 includes a first metal sublayer 210 and a second metal sublayer 220 stacked sequentially. The first metal sublayer 210 is adjacent to the first surface 100a of the glass core plate 100, and the second metal sublayer 220 is located on the side of the first metal sublayer 210 away from the glass core plate 100. Each metal sublayer can be formed sequentially by physical vapor deposition.

[0065] Preferably, the material of the first metal sublayer 210 is selected from at least one of titanium, chromium, tantalum, and molybdenum, and the material of the second metal sublayer 220 is selected from at least one of copper, silver, and gold. For example, the first metal sublayer 210 adjacent to the glass core plate 100 can be titanium to enhance interfacial adhesion. Molybdenum can be used as the first metal sublayer 210 because it has good high-temperature resistance, a high melting point, and is not easily oxidized or volatilized at high temperatures, making it suitable for processes requiring high-temperature treatment. The second metal sublayer 220 away from the glass core plate 100 can be copper or silver to improve pattern transfer accuracy. In this embodiment, the first metal sublayer 210 is a titanium layer, and the second metal sublayer 220 is a copper layer. A PVD sputtered Ti / Cu layer can be used on the first surface 100a. Preferably, the thickness of the first metal sublayer 210 is 50-100 nm, and the specific value can be adjusted according to the etching selectivity and pattern fidelity requirements. The thickness of the second metal sublayer 220 is 200-600 nm. Thus, through the layered metal structure design, the high adhesion of the first metal sublayer 210 is used to ensure the bonding strength between the mask layer and the glass core plate 100, while the excellent pattern transfer characteristics of the second metal sublayer 220 are used to achieve high-precision pattern definition.

[0066] Then, refer to Figure 4Step S3 involves pattern transfer and etching on the temporary metal mask layer 200 to define the first and second pattern regions. Pattern transfer can be performed using photolithography. Specifically, a first photosensitive dielectric layer 310 can be coated on the second metal sub-layer 220. After pattern transfer, the second metal sub-layer 220 is etched to define the first pattern region. Then, the first photosensitive dielectric layer 310 is removed, and a second photosensitive dielectric layer 320 is coated on the first pattern region and the second metal sub-layer 220. After pattern transfer, the first metal sub-layer 210 is etched to define the second pattern region. More specifically, the first and second photosensitive dielectric layers 310 and 320 can be made of materials such as photoresist or photosensitive polyimide. Spin coating can be used. The etching process can be wet etching. When the second metal sublayer 220 is a copper layer, the wet etching solution can be ammonium persulfate solution or ferric chloride solution. When the first metal sublayer 210 is a titanium layer, the wet etching solution can be a mixed solution of hydrofluoric acid and nitric acid.

[0067] For example, a first photosensitive dielectric layer 310 is coated on the first surface 100a. A spin coater is used, first rotating at 500 rpm for 5-10 seconds, then at 1000-4000 rpm for 20-60 seconds to uniformly cover the glass with the photosensitive dielectric layer. The layer is then subjected to a staged temperature increase within the range of 50℃-110℃ for soft baking. After the photosensitive dielectric layer is semi-cured, exposure is performed using a photolithography machine. Photolithography machine types include exposure type, contact type, stepper type, scanning type, and immersion type. Subsequently, a 0.1-2.5 mol / L tetramethylammonium hydroxide (TMAH) solution is sprayed at a pressure of 0.1-0.3 MPa for 30-120 seconds to complete development and high-temperature curing at 180℃-350℃ for 60 minutes. Finally, copper flash etching is performed on the second metal sublayer 220. Figure 4 As shown.

[0068] After copper flash etching, the first photosensitive dielectric layer 310 can be removed using ICP dry etching. This ICP dry etching uses a gas combination including O2, Ar, and CF4, employing oxygen or a fluorine-based mixed gas to induce an oxidation reaction in the photosensitive dielectric layer and generate volatile products. The ICP source power is 800-1200W, the bias source power is 200-500W, and the gas flow rate is 50-200 sccm. By controlling the etching time to match the thickness of the photosensitive dielectric layer, precise removal is achieved, avoiding damage to the underlying material. Subsequently, the second photosensitive dielectric layer 320 is coated. After pattern transfer, the first metal sublayer 210 is etched to define the second patterned area, such as... Figure 5As shown. Therefore, by using a step-by-step coating method for the photosensitive dielectric layers, the pattern transfer and etching of the second metal sublayer 220 are first completed through the first photosensitive dielectric layer 310, and then the pattern transfer and etching of the first metal sublayer 210 are completed through the second photosensitive dielectric layer 320. This step-by-step processing method ensures precise definition of different pattern areas on the double-layer metal mask structure.

[0069] Then, as Figure 6 As shown, step S4 is performed: the glass core plate 100 is dry-etched in the second patterned area to form the first TGV hole 110. That is, the first metal sublayer 210 in the second patterned area has been etched away, and at this time, the glass is etched using ICP to form the first TGV hole 110 in the second patterned area. The gas combination includes fluorine-containing ions such as C4F8, CHF3, SF6, and Ar. These gases generate fluorine radicals that react with SiO2 to form volatile products, thus achieving etching. The ICP power is 800W-2500W, the bias power is 50W-200W, and the pressure is 5-20mTorr. The gas combination includes, but is not limited to, fluorine-containing gases such as CF4, CHF3, SF6, C4F8, and C5F8, as well as Ar and O2. The Ar flow rate is 20-80 sccm, the O2 flow rate is 0-5 sccm, the ratio of fluorine-containing gas flow rate to Ar flow rate is 1:1-2:1, and the total gas flow rate is 50-100 sccm. By adjusting the gas ratio and flow rate, the etching rate can be controlled to approximately 0.1-0.7 μm / min, thereby controlling the TGV depth by controlling the etching time.

[0070] Next, as Figure 7As shown, step S5 is performed: The glass core plate 100 in the first and second patterned regions is dry-etched to form the second TGV hole 120 and deepen the first TGV hole 110. Specifically, after forming the first TGV hole 110, the second photosensitive medium layer 320 is removed to expose the first metal sublayer 210. Then, the first metal sublayer 210 is etched, and the glass core plate 100 is dry-etched again to form the second TGV hole 120 and deepen the first TGV hole 110. That is, when the second photosensitive medium layer 320 is removed, the first metal sublayer 210 in the first patterned region is exposed. Etching the first metal sublayer 210 in the first patterned region at this time creates a window in the area of ​​the second TGV hole 120. The removal of the second photosensitive medium layer 320 can be done using ICP dry etching, similar to the removal of the first photosensitive medium layer 310. Then, the formation of the second TGV hole 120 and the deepening of the first TGV hole 110 are performed simultaneously. The depth of the second TGV hole 120 is half the depth of the first TGV hole 110. The diameters of the first TGV hole 110 and the second TGV hole 120 are 10-30 μm. In addition, the dry etching used to form the second TGV hole 120 is the same as the dry etching parameter conditions used to form the first TGV hole 110.

[0071] Then, as Figure 8 As shown, step S6 is performed: the temporary metal mask layer 200 is removed, and the inner walls of the first TGV hole 110 and the second TGV hole 120 are metallized to form the first conductive via 410 and the second conductive via 420. A first redistribution layer 500 is then fabricated on the first surface 100a, electrically connecting the first conductive via 410 and the second conductive via 420. It can be understood that removing the temporary metal mask layer 200 involves removing the remaining second metal sublayer 220 and the first metal sublayer 210, i.e., etching Ti / Cu. Subsequently, PVD metallization, copper / nickel / tin pillar plating, pattern transfer, and Ti / Cu etching are sequentially performed on the first surface 100a, the inner walls of the first TGV hole 110 and the second TGV hole 120 to complete the fabrication of the first conductive via 410, the second conductive via 420, and the first redistribution layer 500. Specifically, a Ti / Cu seed layer can be first deposited by PVD on the first surface 100a, the inner wall of the first TGV hole 110, and the inner wall of the second TGV hole 120. Then, a conductive layer is electroplated on the seed layer. After that, the conductive layer on the first surface 100a is patterned to form the circuit of the first redistribution layer 500. Finally, the excess conductive layer and seed layer are etched.

[0072] Next, as Figure 9As shown, step S7 is performed: the second surface 100b of the glass core plate 100 is ground until the first conductive via 410 is exposed; then, the glass core plate 100 is dry-etched to form a cavity 130 until the second conductive via 420 is exposed. Specifically, CMP is used to grind the glass on the second surface 100b until the first conductive via 410 is exposed. CMP is performed using existing technology and will not be described in detail here. Then, a photosensitive dielectric layer is coated on the second surface 100b, and the area to be etched into the cavity is exposed by pattern transfer. Finally, the glass core plate 100 is dry-etched until the second conductive via 420 is exposed to form the cavity 130. Specifically, the cavity parameters for fabricating a glass core plate 100 using ICP dry etching are as follows: ICP power 800W-2500W, bias power 50W-200W, pressure 5-20mTorr, and gas combinations including but not limited to fluorinated gases such as CF4, CHF3, SF6, C4F8, and C5F8, as well as Ar and O2. The Ar flow rate is 20-80 sccm, the O2 flow rate is 0-5 sccm, and the ratio of fluorinated gas flow rate to Ar flow rate is 1:1-2:1. This process forms... Figure 9 The cavity 130 is slightly larger than the size of the device to be embedded, so as to facilitate device placement within the cavity 130, and the cavity 130 can be adjusted according to changes in the size of the device to be embedded. In this embodiment, the size of the cavity 130 can be 6×6mm-100×100mm (length×width) and 100-500μm (depth). Common cavity fabrication processes include mechanical milling, chemical etching, and laser processing. Mechanical milling often results in damage to the substrate surface or dimensional deviations due to the use of mechanical milling cutters; chemical etching presents environmental pollution and process control issues, and the use of chemical agents can easily lead to impurity residues, lateral etching, and uneven etching. Residues may cause microvoids or stress concentrations, affecting the shape accuracy and structural integrity of the cavity; while laser processing offers high precision, the localized high temperatures during processing can easily cause glass melting, forming microcracks or increasing surface roughness, and the efficiency of laser processing is limited by laser power and focal length, making it difficult to handle thick substrates or complex structures. Based on the above analysis, traditional cavity fabrication processes are not suitable for glass materials. However, the ICP dry etching method of this application utilizes plasma bombardment of glass, which can achieve precise etching within ±1° of the cavity sidewall perpendicularity, avoiding the side etching phenomenon of wet chemical etching. Furthermore, it exhibits good uniformity, and the surface roughness can be controlled below 1 nm, which helps to reduce microcracks and stress concentration.

[0073] Finally, as Figure 10As shown, step S8 is performed: a chip 600 is provided and embedded in the cavity 130, and the chip 600 is electrically connected to the second conductive via 120. Specifically, when the chip 600 is placed in the cavity 130, the bumps 610 of the chip 600 are thermo-bonded to the second conductive via 120 to make the chip 600 electrically connected to the second conductive via 120; wherein, the bumps 610 (solder balls) of the chip 600 are pre-fabricated, and NCF glue is applied to the bottom surface of the chip 600 before placing the chip 600 into the cavity 130. The thermo-bonding can be performed by heating the glass core board 100 and the chip 600 to 150℃-200℃ using a TCB device to precisely align the chip 600 with the second conductive via 120 at the bottom of the cavity 130, with an alignment accuracy controlled at ±5μm. When the chip 600 comes into contact with the second conductive via 120, causing a pressure change, the chip 600 is heated to above 300°C to melt the solder balls, thereby completing the bonding.

[0074] Then, step S9 is performed: an insulating layer 700 is formed in the gap between the chip 600 and the cavity 130 and on the second surface 100b. A second redistribution layer 800 is then fabricated on the insulating layer 700 and the chip 600, electrically connecting the second redistribution layer 800 to the first conductive via 110 and the chip 600. The insulating layer 700 can be formed by filling the gap between the chip 600 and the cavity 130 with underfill using a dispensing machine, covering the second surface 100b with the underfill, and then curing. Next, the second redistribution layer 800 is fabricated on the second surface 100b through processes such as coating a photosensitive dielectric layer, pattern transfer, ICP etching of the underfill, PVD seed layer, electroplating of a conductive layer, and etching of Ti / Cu. Figure 11 As shown. The fabrication process for the second overlay layer 900 uses existing technology and will not be detailed here. The parameters for ICP etching underfill are: gas combination and flow rate: O2 (50-200 sccm) + CF4 (10-50 sccm) or SF6 (20-100 sccm), Ar (50-200 sccm), total flow rate 100-300 sccm, ICP power 300-1500W, bias power 20-100W, pressure 10-100 mTorr.

[0075] Thus, the fabrication of the TGV glass substrate with embedded chips is completed based on the above fabrication method.

[0076] like Figure 11As shown, the TGV glass substrate with the embedded chip includes a glass core plate 100 having opposing first surfaces 100a and second surfaces 100b; a cavity 130 is formed in the glass core plate 100 from the second surface 100b; one or more first conductive vias 110 penetrate the glass core plate 100 and are exposed to the first surface 100a and the second surface 100b; one or more second conductive vias 120 penetrate the glass core plate 100 and are exposed to the first surface 100a and the cavity 130; and a chip 600 is embedded in the cavity 130. 600 has one or more bumps 610 formed on the surface of chip 600, the bumps 610 being bonded to the second conductive via 120; an insulating layer 700 is formed between chip 600 and cavity 130, and on the second surface 100b; a first redistribution layer 500 is formed on the first surface 100a and electrically connected to the first conductive via 110 and the second conductive via 120; a second redistribution layer 800 is formed on the insulating layer 700 and chip 600, and electrically connected to chip 600 and the first conductive via 110.

[0077] Compared to existing technologies, this TGV glass substrate for embedded chips achieves damage-free cavity 130 processing through ICP dry etching, effectively avoiding problems such as substrate surface damage, dimensional deviations, side etching, microcracks, or surface roughening, thereby improving packaging density and long-term stability. Furthermore, the cavity 130 size can be adjusted according to chip size, accommodating the embedding of different functional chips such as logic chips, memory chips, and optoelectronic devices, achieving heterogeneous integration.

[0078] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0079] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0080] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0081] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0083] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for making a TGV glass substrate with embedded chips, characterized in that, The method comprises the following steps: providing a glass core plate having opposite first and second surfaces; forming a temporary metal mask layer on the first surface of the glass core plate; the temporary metal mask layer comprises at least one metal layer, and the material of the metal layer is selected from at least one of titanium, chromium, copper, silver, gold, aluminum and molybdenum; performing pattern transfer and etching on the temporary metal mask layer to define a first pattern area and a second pattern area; dry etching the glass core plate in the second pattern area to form a first TGV hole; dry etching the glass core plate in the first pattern area and the second pattern area to form a second TGV hole and deepen the first TGV hole; removing the temporary metal mask layer, and performing metalization on the inner wall of the first TGV hole and the inner wall of the second TGV hole to form a first conductive via and a second conductive via, and manufacturing a first redistribution layer on the first surface, the first redistribution layer being electrically connected to the first conductive via and the second conductive via; grinding the second surface of the glass core plate until the first conductive via is exposed; dry etching the glass core plate to form a cavity until the second conductive via is exposed; the dry etching is inductively coupled plasma etching, and the etching gas comprises one or a combination of fluorine-containing gas, oxygen and inert gas; the fluorine-containing gas is selected from at least one of carbon tetrafluoride, octafluorocyclobutane, trifluoromethane and sulfur hexafluoride; the operation conditions for forming the cavity by dry etching are as follows: ICP source power 800-2500 W, bias power 50-200 W, and pressure 5-20 mTorr; providing a chip and embedding the chip in the cavity, the bump of the chip being thermocompression bonded with the second conductive via to electrically connect the chip with the second conductive via; forming an insulating layer in the gap between the chip and the cavity and on the second surface, and then manufacturing a second redistribution layer on the insulating layer and the chip, the second redistribution layer being electrically connected to the first conductive via and the chip.

2. The method of claim 1, wherein the TGV glass substrate is a 0.7 mm thick Gorilla® glass substrate. The temporary metal mask layer comprises a first metal sub-layer and a second metal sub-layer stacked in sequence, the first metal sub-layer being adjacent to the first surface of the glass core plate, and the second metal sub-layer being located on the side of the first metal sub-layer away from the glass core plate.

3. The method of claim 2, wherein the TGV glass substrate is a 0.7 mm thick Gorilla® glass substrate. The material of the first metal sub-layer is selected from at least one of titanium, chromium, tantalum and molybdenum, and the material of the second metal sub-layer is selected from at least one of copper, silver and gold.

4. The method of claim 3, wherein the TGV glass substrate is a 0.7 mm thick Gorilla® glass substrate. The first metal sub-layer is a titanium layer, and the second metal sub-layer is a copper layer.

5. The method of claim 2, wherein the TGV glass substrate is a 0.7 mm thick Gorilla® glass substrate. The step of performing pattern transfer and etching on the temporary metal mask layer to define a first pattern area and a second pattern area comprises: coating a first photosensitive medium layer on the second metal sub-layer, and performing second metal sub-layer etching after completing pattern transfer to define a first pattern area; removing the first photosensitive medium layer, coating a second photosensitive medium layer on the first pattern area and the second metal sub-layer, and performing first metal sub-layer etching after completing pattern transfer to define a second pattern area.

6. The method of claim 5, wherein the TGV glass substrate is a 0.7 mm thick Gorilla® glass substrate. After forming the first TGV hole, the second photosensitive dielectric layer is removed to expose the first metal sub-layer, then the first metal sub-layer is etched, and the glass core plate is dry etched to form a second TGV hole and deepen the first TGV hole.

7. A TGV glass substrate with embedded chips, characterized by, The TGV glass substrate is prepared by the manufacturing method of any one of claims 1-6, and the TGV glass substrate comprises: a glass core plate having opposite first and second surfaces; a cavity formed in the glass core plate from the second surface; one or more first conductive vias extending through the glass core plate and exposed to the first and second surfaces; one or more second conductive vias extending through the glass core plate and exposed to the first surface and the cavity; a chip embedded in the cavity, the chip having one or more bumps formed on a surface of the chip, the bumps being bonded to the second conductive vias; an insulating layer formed between the chip and the cavity and on the second surface; a first redistribution layer formed on the first surface and electrically connected to the first and second conductive vias; a second redistribution layer formed on the insulating layer and the chip and electrically connected to the chip and the first conductive vias.

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