Method for selectively regulating and controlling pattern size through low-temperature ion implantation process

Abstract

The invention discloses a method for selectively regulating and controlling the size of a pattern through a low-temperature ion implantation process, and belongs to the technical field of integrated circuit manufacturing. Performing low-temperature ion implantation on the intermediate material to generate a modified layer on the vertical side wall of the non-hollow part of the intermediate film layer; selective growth is carried out through atomic layer deposition, a deposition layer covering the surface of the intermediate material is formed, the deposition layer forms an adjusted pattern structure, and the profile of the adjusted pattern structure is reduced relative to that of the intermediate pattern structure; part of the deposition layer is removed through wet etching, so that the upper part of the bottom film layer is exposed; performing thermal annealing treatment; and transferring the adjusted pattern structure to the bottom film layer through dry etching. According to the invention, the feature size of the pattern structure can be accurately controlled and reduced, the side wall of the pattern structure can obtain a flatter surface appearance without defects, and the performance of a semiconductor device can be improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a method for selectively controlling pattern size through a low-temperature ion implantation process. Background Technology

[0002] With the rapid development of CMOS integrated circuit technology, the critical dimension (CD) of semiconductor devices is continuously shrinking, requiring exposure wavelengths to evolve from ultraviolet (UV) and deep ultraviolet (DUV) to extreme ultraviolet (EUV). As patterned design layouts, three-dimensional structures (such as channels, trenches, and deep holes) continue to shrink and aspect ratios increase, high material selectivity, high precision in micro / nano structure fabrication, and high control over physical damage become increasingly important in advanced semiconductor structures such as FinFET / GAA transistors, high-performance MEMS / NEMS, silicon photonics devices, and ultra-precision optical components. Therefore, to meet the high requirements of high-efficiency, high-precision, and low-device chip fabrication and micro / nano devices, the fabrication process of advanced photolithography and etching technologies needs continuous improvement and optimization of high-precision micro / nano structure fabrication techniques. Simultaneously, the required technologies need to move from pattern fabrication to refining pattern contours and further shrinking feature sizes; this is a key element for 3-nanometer and below technology nodes.

[0003] In existing technologies, to reduce the line edge roughness (LER) of photomasks and improve the accuracy of pattern transfer during etching, the main approach is to optimize lithography and etching processes to reduce LER and improve the vertical accuracy of sidewall contours, sidewall flatness, and the miniaturization of critical dimensions / linewidths. For example, this involves using shorter wavelength light sources, higher precision lithography machines, finer photomasks, and reactive gases with higher selectivity and better etching capabilities. Furthermore, multiple exposures and etching processes can be used to gradually achieve the desired line fineness and pattern transfer accuracy. While existing solutions can reduce LER and improve sidewall contour control to some extent, these methods are often too costly, time-consuming, and inefficient, and cannot meet future demands for higher precision and lower costs. Moreover, these methods may be limited by physical constraints when fabricating and processing very fine lines and pattern contours, making it difficult to further improve precision and miniaturization. While atomic layer deposition (ALD) processes can currently reduce feature sizes, edge roughness and sidewall profile control / uniformity have not yet been effectively improved. Therefore, a new technical solution is urgently needed to optimize the edge roughness, sidewall profile accuracy, and precise adjustment of pattern profiles and aperture sizes in photomask / hard mask photolithography-etched channels, trenches, line patterns, and vias. Summary of the Invention

[0004] Based on the technical problems existing in the prior art, the present invention provides a method for selectively controlling pattern size through a low-temperature ion implantation process. The low-temperature ion implantation process changes the physical state or chemical properties of the material surface, thereby controlling the deposition rate of atomic layer deposition. This achieves a high-precision method for selective deposition, uniformity correction, and precise control of pattern outline size. It is used to solve the technical problems of inconsistent pattern shape and outline after photolithography / etching process with the original design, inability to effectively and accurately control feature size, inability to further miniaturize pattern outline size, and deterioration of sidewall surface roughness.

[0005] According to the technical solution of the present invention, the present invention provides a method for selectively controlling pattern size through a low-temperature ion implantation process, comprising the following steps:

[0006] Step S1: Obtain intermediate material; the intermediate material has a multilayer structure, including at least a bottom film layer, an intermediate film layer and a mask layer stacked sequentially from bottom to top; the intermediate material has an intermediate pattern structure, which is the mask layer and the hollowed-out part in the intermediate film layer, and the hollowed-out part in the mask layer corresponds to the hollowed-out part in the intermediate film layer.

[0007] Step S2: Low-temperature ion implantation is performed on the intermediate material to generate a modified layer on the vertical sidewall of the non-perforated portion of the intermediate film layer; wherein, the implantation direction of the low-temperature ion implantation is inclined implantation, and the implantation temperature of the low-temperature ion implantation is below 0°C.

[0008] Step S3: Selective growth is performed through atomic layer deposition to form a deposition layer covering the surface of the intermediate material. The deposition layer forms an adjusted pattern structure, and the outline of the adjusted pattern structure is smaller than that of the intermediate pattern structure. The thickness of the deposition layer on the surface of the modified layer is greater than the thickness of the deposition layer in the rest of the layer. The deposition layer on the surface of the modified layer reaches the set size and is uniform and flat.

[0009] Step S4: Remove part of the deposited layer above the mask layer and above the bottom film layer by wet etching, so that the bottom film layer is exposed between the vertical sidewalls of the deposited layer.

[0010] Step S5 involves repairing the bottom film layer, recrystallizing, and balancing stress through thermal annealing.

[0011] Step S6: The adjusted pattern structure is transferred to the bottom film layer by dry etching.

[0012] In some embodiments, the intermediate material in step S1 is obtained by the following steps: exposing a bottom film layer having a photoresist layer, a hard mask layer, and an intermediate film layer using a photolithography process, wherein the photoresist layer, hard mask layer, intermediate film layer, and bottom film layer are stacked sequentially from top to bottom; and then transferring the photoresist pattern structure to the intermediate film layer by an etching process to obtain the intermediate pattern structure.

[0013] In some embodiments, in step S1, the bottom film layer is a wafer or a thin film formed on a wafer; the intermediate pattern structure is a via, channel, trench or linear pattern structure.

[0014] In some embodiments, in step S1, the intermediate film layer is a monocrystalline silicon, polycrystalline silicon, or silicon dioxide thin film.

[0015] In some embodiments, in step S2, the angle of tilt implantation ranges from 5° to 50° relative to the vertical line of the bottom film layer toward the side closer to the vertical sidewall to be treated; and / or, the implantation temperature of low-temperature ion implantation is ≤-10°C.

[0016] In some embodiments, in step S2, the ion beam implantation species for cryogenic ion implantation includes one of argon ions, nitrogen ions, boron ions, helium ions, phosphorus ions, oxygen ions, fluorine ions, silicon ions, and germanium ions; the ion beam energy range is 50 eV to 10 keV; and the ion beam dose range is 5E13 atoms / cm. 2 ~5E16 atoms / cm 2Ion implantation depth ≤ 10 nm.

[0017] In some embodiments, in step S2, at least two cryogenic ion implantations at different implantation angles are performed to treat vertical sidewalls in at least two directions; during cryogenic ion implantation, the intermediate material is located on a stage in the ion implantation apparatus, and the stage drives the intermediate material on the stage to rotate to treat vertical sidewalls in different directions of the same intermediate material, with the implantation angle remaining unchanged before and after rotation.

[0018] In some embodiments, in step S3, the deposited layer is a nitride or an oxide.

[0019] In some embodiments, in step S3, the atomic layer deposition rate on the surface of the modified layer is ≥0.15 nm / cycle, and the atomic layer deposition rate of the remaining portion is ≤0.1 nm / cycle.

[0020] The width of the hollowed-out portion in the intermediate film layer of the intermediate pattern structure is ≥15nm, and the deviation is ≥±3nm; after adjustment, the width of the hollowed-out portion in the intermediate film layer of the intermediate pattern structure is ≤10nm, and the deviation is ≤±1nm.

[0021] In some embodiments, the aspect ratio of the hollow portion in the intermediate film layer of the adjusted pattern structure is ≥5:1; and / or, the surface roughness of the vertical sidewalls of the adjusted pattern structure is ≤0.5nm.

[0022] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0023] The present invention provides a method for selectively controlling pattern size through low-temperature ion implantation, enabling the refinement of pattern structures. By incident an ion beam at a low temperature and a specific angle onto the sidewall surface of the pattern structure, the material surface can be modified while avoiding excessive crystal damage. Selective growth of nitrides or oxides is then achieved through atomic layer deposition. The atomic layer deposition rate in the ion-implanted modified surface region is higher than in the unmodified region, thus allowing the pattern size in a specific region to reach the set feature size and exhibit high uniformity and a smooth sidewall surface profile. Therefore, the present invention can miniaturize the feature size of vias, channels, trenches, and linear patterns while meeting the requirement for higher pattern uniformity. It can also achieve a smoother and defect-free surface morphology on the sidewall surface of the pattern structure, precisely controlling and reducing the feature size of the pattern structure, thereby contributing to improved semiconductor device performance. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the method process from a top-down perspective according to the first embodiment of the present invention.

[0025] Figure 2 yes Figure 1 The schematic diagram of the method process from the cross-sectional perspective of the embodiment shown.

[0026] Figure 3 This is a schematic diagram of the method process from a top-down perspective according to the second embodiment of the present invention.

[0027] Figure 4 yes Figure 3 The schematic diagram of the method process from the cross-sectional perspective of the embodiment shown.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1. Bottom film layer; 2. Intermediate film layer; 3. Mask layer; 4. Intermediate pattern structure; 5. Modified layer; 6. Deposited layer; 7. Adjusted pattern structure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0031] It should also be noted that, for ease of description, only the parts relevant to the inventive point are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0032] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0033] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0034] While chip feature sizes have shrunk to a few nanometers, the critical dimensions of channels, trenches, line patterns, and vias, as well as line edge roughness (LER), do not decrease proportionally with the reduction in feature size. During the design and fabrication of photomask patterning, unevenness occurs on the sidewall surface contours of the photomask layer, a phenomenon known as line edge roughness (LER). This microstructural difference has an increasingly significant impact on device performance. Furthermore, as the patterned structure is transferred from the photomask / hard mask layer to the underlying thin film and the aspect ratio of the three-dimensional structure continues to increase, the etching accuracy of the material structure, the precision of the pattern contour, the fineness of the vertical sidewall contours, the flatness / smoothness of the structural surface, and the degree of removal of byproduct residues all have a high correlation and influence on the final patterned structure and device performance. For example, when the gate feature size of a CMOS field-effect transistor (MOSFET) is less than 100 nm, the sidewall line edge roughness of the gate can fluctuate within a range of 5 nm. Furthermore, during the patterning of nanostructures, radial inhomogeneities, uneven / non-perpendicular sidewall profiles, and the inability to further effectively shrink critical dimensions will all lead to significant changes in the effective conductive channel length of the device. This results in degraded or more volatile device performance, increased leakage current, increased contact resistance, decreased drive current, and changes in turn-on voltage (Vth). Therefore, the accuracy of sidewall profile morphology, the flatness of the structural surface, the elimination of LER (Leakage Reduction), and the precise and effective control of pattern profile dimensions are critical issues that urgently need to be addressed in chip manufacturing. Sidewall profile morphology, structural surface flatness, and LER mainly originate from the photolithography and etching processes, such as the diversity of polymer molecular structures, spatial imaging fluctuations, acidic diffusion of photoresist, production and preparation process conditions (such as coating thickness, drying temperature, exposure dose, and light intensity uniformity of the light source), etching selectivity, and by-product residues. If the LER of the photomask is uneven or exceeds specifications, low etching selectivity of the material, and incomplete removal of by-products can directly transfer to the wafer structure, causing serious impact and loss on chip performance.

[0035] To address the problems of the prior art, this invention provides a method for selectively controlling pattern size through a low-temperature ion implantation process. A typical embodiment includes the following steps: (1) exposing a wafer with photoresist, a hard mask, and a single-crystal silicon or polycrystalline silicon thin film using a photolithography process, and then transferring the photolithographic pattern structure to the underlying thin film through an etching process to obtain via, channel, trench, or line pattern structure; (2) performing low-temperature ion implantation on the shallow surface of the single-crystal silicon, polycrystalline silicon, or silicon dioxide thin film using a cold ion beam to modify the material surface; (3) selectively growing nitrides or oxides through atomic layer deposition to achieve a pattern in a specific area with a set characteristic size and a uniform and flat sidewall surface contour; (4) after atomic layer deposition, wet etching is required. (5) Remove the deposited layer on the upper surface and the bottom of the pattern structure by heat annealing; (6) Remove the excessive damage, recrystallize and balance the stress of the deposited film by heat annealing; (7) Transfer the miniaturized pattern structure to the lower film by dry etching to obtain miniaturized via, channel or trench pattern structure; This invention changes the physical state or chemical properties of the material surface by low temperature ion implantation process, thereby controlling the deposition rate of atomic layer deposition, thereby achieving a high-precision method for selective deposition, uniformity correction and precise control of pattern outline size, and is used to solve the technical problems of inconsistent pattern shape and outline with the original design pattern after photolithography / etching process, inability to effectively control feature size, inability to further miniaturize pattern outline size and deterioration of sidewall surface roughness.

[0036] Please see Figure 1 , Figure 2 The present invention provides a method for selectively controlling pattern size through a low-temperature ion implantation process, comprising the following steps.

[0037] Step S1: Obtain intermediate material; the intermediate material has a multi-layer structure, including at least a bottom film layer 1, an intermediate film layer 2 and a mask layer 3 stacked sequentially from bottom to top; the intermediate material has an intermediate pattern structure 4, which is the hollowed-out portion in the mask layer 3 and the intermediate film layer 2, and the hollowed-out portion in the mask layer 3 corresponds to the hollowed-out portion in the intermediate film layer 2.

[0038] Step S2: Low-temperature ion implantation is performed on the intermediate material to generate a modified layer 5 on the vertical sidewall of the non-perforated portion of the intermediate film layer 2; wherein the implantation direction of the low-temperature ion implantation is inclined implantation, and the implantation temperature of the low-temperature ion implantation is below 0°C.

[0039] In step S3, selective growth is performed by atomic layer deposition to form a deposition layer 6 covering the surface of the intermediate material. The deposition layer 6 forms an adjusted pattern structure 7, and the outline of the adjusted pattern structure 7 is reduced relative to the intermediate pattern structure 4. The thickness of the deposition layer 6 on the surface of the modified layer 5 is greater than the thickness of the deposition layer 6 in the rest of the area (i.e., the surface that has not undergone low-temperature ion implantation and does not have the modified layer 5). The deposition layer 6 on the surface of the modified layer 5 reaches the set size and is uniform and flat.

[0040] Step S4: Remove part of the deposited layer 6 above the mask layer 3 and above the bottom film layer 1 by wet etching, so that the bottom film layer 1 is exposed between the vertical sidewalls of the deposited layer 6.

[0041] Step S5 involves repairing the bottom film layer 1, recrystallizing, and balancing stress through thermal annealing.

[0042] Step S6: The adjusted pattern structure 7 is transferred to the bottom film layer 1 by dry etching.

[0043] The intermediate material in step S1, i.e., the material whose pattern structure has not yet achieved the expected effect, can be obtained using existing or similar processes. This invention is mainly used to achieve "refinement" of the pattern structure. Specifically, for example, the intermediate material in step S1 is obtained through the following steps: exposing the bottom film layer 1, which has a photoresist layer, a hard mask layer, and an intermediate film layer 2, using a photolithography process, wherein the photoresist layer, hard mask layer, intermediate film layer 2, and bottom film layer 1 are stacked sequentially from top to bottom; then transferring the photoresist pattern structure to the intermediate film layer 2 through an etching process to obtain the intermediate pattern structure 4.

[0044] The above method is a commonly used approach for obtaining patterned structures. In this method, after exposure, the photoresist layer forms a mask layer 3 with the desired pattern. Depending on the process, the mask layer 3 can be a hard mask layer or a combination of a photoresist layer and a hard mask layer. The mask layer 3 acts as a barrier to subsequent etching processes, allowing the patterned structure to be etched onto the intermediate film layer 2. Several similar methods for forming patterned structures exist, which will not be elaborated upon here.

[0045] More specifically, the bottom film layer 1 is, for example, a wafer or a thin film formed on a wafer. The intermediate film layer 2 is, for example, a monocrystalline silicon, polycrystalline silicon, or silicon dioxide thin film. The intermediate pattern structure 4 is, for example, a via, channel, trench, or line pattern structure, including combinations thereof, specifically designed according to the desired semiconductor device structure.

[0046] Step S2 involves using a tilted ion implantation process to modify the physical state or chemical properties of the vertical sidewall surface of the ion implantation pattern through shallow low-temperature ion implantation, thereby obtaining a modified layer 5. Because the ion beam is incident on the film sidewall surface at a low temperature and a specific angle, the material surface can be modified while avoiding excessive crystal damage. The modified layer 5 is selectively formed at specific locations, allowing for selective atomic layer deposition at those locations in subsequent steps. The low-temperature ion implantation modification process results in a faster atomic layer deposition rate at the treated locations, leading to a significantly increased deposition thickness compared to other locations. Without low-temperature ion implantation, the atomic layer deposition rate and thickness are uniform across all locations, lacking selective control. Low-temperature ion implantation ensures implantation precision and clearly defines the location of the modified layer 5. Preferably, the implantation temperature is ≤-10℃ for even better results.

[0047] More specifically, the angle of the tilted injection ranges from 5° to 50° relative to the vertical line of the bottom film layer 1, tilted towards the side closer to the vertical sidewall to be treated. For example... Figure 1 , Figure 2 As shown, when processing the vertical sidewall on the left side of the hollowed-out portion of the pattern structure (i.e., the vertical sidewall on the right side of the intermediate film layer 2), the injection direction indicated by the arrow is tilted to the left relative to the vertical direction of the bottom film layer 1 (i.e., the direction parallel to the vertical sidewall). Tilting refers to tilting along the injection direction (arrow direction), where the lower end of the arrow is closer to the vertical sidewall to be processed than the upper end. The specific angle of the tilted injection is set according to the situation to achieve the desired effect, such as completely irradiating the vertical sidewall to be processed. As a further explanation, the ion beam used for ion implantation is a strip-shaped ion beam, and the ion implantation is a scanning implantation. The intermediate material moves relative to the ion beam, generally in a direction parallel to the bottom film layer 1 and perpendicular to the length of the ion beam strip cross-section, so that the ion beam covers the entire area of ​​the intermediate material after scanning.

[0048] Preferably, in step S2, the ion beam implanted species of cryogenic ion implantation may include argon ions (Ar). + ), nitrogen ions (N) + Boron ions (B) + ), Helium ions (He) + ), Phosphate ions (P + ), oxygen ions (O + ), fluoride ions (F) + ), silicon ions (Si + germanium ions (Ge) +One of them. For cases where the ion beam implantation species are argon ions, nitrogen ions, boron ions, helium ions, phosphorus ions, oxygen ions, fluorine ions, silicon ions, and germanium ions, the ion beam energy range is 50 eV to 10 keV; the ion beam dose range is 5 E13 atoms / cm. 2 ~5E16 atoms / cm 2 Preferably, the ion implantation depth is ≤10nm, and only the shallow surface layer is modified.

[0049] As needed, in step S2, at least two cryogenic ion implantations at different implantation angles are performed to treat the vertical sidewalls in at least two directions. Preferably, during cryogenic ion implantation, the intermediate material is placed on a stage in the ion implantation equipment, such as an electrostatic chuck. The stage rotates the intermediate material on the stage to treat the vertical sidewalls of the same intermediate material in different directions, and the implantation angle remains unchanged before and after rotation. In conventional ion implantation equipment, the stage is usually movable, while the ion beam is adjusted and determined before implantation and is not adjusted again to ensure the stability of the ion beam during the implantation process. The vertical sidewalls of the patterned structure are vertical, and the angle of the ion beam tilt direction relative to the vertical direction remains unchanged. Therefore, the implantation angle remains unchanged before and after the stage and the intermediate material on it rotate. This method has high efficiency while ensuring parameters such as the tilted implantation angle, and no other adjustments are needed between cryogenic ion implantations at different implantation angles.

[0050] Step S3 primarily involves forming a deposition layer 6 through atomic layer deposition to increase the thickness at the location of the modified layer 5. This correspondingly reduces the size of the cutouts and flattens the vertical sidewalls, thus obtaining a patterned result (pattern structure) with a smaller feature size and ideal shape contour. The deposition layer 6 is, for example, a nitride or oxide. The atomic layer deposition rate on the surface of the modified layer 5 is significantly higher than that of the remaining portions. Specifically, for example, the atomic layer deposition rate on the surface of the modified layer 5 is ≥0.15 nm / cycle, while the atomic layer deposition rate of the remaining portions is ≤0.1 nm / cycle. In a typical embodiment, the width of the cutout portion in the intermediate film layer 2 of the intermediate pattern structure 4 is ≥15 nm with a deviation ≥±3 nm; the width of the cutout portion in the intermediate film layer 2 of the adjusted pattern structure 7 is ≤10 nm with a deviation ≤±1 nm, demonstrating that the feature size can be reduced and precisely controlled. In a typical embodiment, the aspect ratio (AR) of the hollow portion in the intermediate film layer 2 of the adjusted pattern structure 7 is ≥5:1, and further, for example, ≥10:1. This solution can better achieve a pattern structure with a high aspect ratio. At the same time, this solution can make the vertical sidewalls of the pattern structure flat. For example, the surface roughness of the vertical sidewalls of the adjusted pattern structure 7 is ≤0.5nm.

[0051] Step S4 involves removing a portion of the deposited layer 6 using wet etching to expose the bottom film layer 1, enabling subsequent etching of the bottom film layer 1. Atomic layer deposition forms the deposited layer 6 on all accessible surfaces of the intermediate material, including above the mask layer 3, on both sides of the cutout portion in the mask layer 3 and the intermediate film layer 2, and above the bottom film layer 1 corresponding to the cutout portion in the intermediate film layer 2. Wet etching is performed vertically from top to bottom, thereby removing the deposited layer 6 above the bottom film layer 1 (and a portion of the deposited layer 6 above the mask layer 3), while the vertical sidewalls of the deposited layer 6 remain essentially unchanged.

[0052] Step S5 involves thermal annealing to repair excessively damaged areas of the bottom film 1, perform surface repair, recrystallization, and balance the stress generated by the deposited thin film (deposited layer). The thermal annealing temperature is, for example, 200°C to 800°C.

[0053] Step S6 involves transferring the miniaturized patterned structure (adjusted patterned structure 7) to the lower bottom film layer 1 via dry etching to obtain a patterned structure of miniaturized vias, channels, or trenches. The dry etching is performed vertically, and the etching is blocked by the deposition layer 6 and the mask layer 3, thus obtaining a small-sized hollowed-out pattern on the bottom film layer 1. As a supplementary explanation, the low-temperature ion implantation process in step S2 may cause an amorphous layer to form in the intermediate film layer 2 within the modified layer 5, deeper than the surface. This amorphous layer can be recrystallized back to its original single-crystal or polycrystalline structure through the thermal annealing treatment in step S5.

[0054] The following description, in conjunction with specific embodiments, provides further details.

[0055] like Figure 1 , Figure 2 In the first embodiment shown, the initial intermediate pattern structure 4 is a circular via array structure with a diameter of approximately 50 nm. The vertical sidewalls are non-uniform, with a deviation (or uniformity) ≥ ±3 nm. During low-temperature ion implantation, the intermediate material is rotated 4 times, each time by 90°, for 4 implantations, or rotated 8 times, each time by 45°, for 8 implantations, thereby achieving uniform over-implantation in each orientation. The ion beam is tilted to the left, and the scanning direction is to the left. The adjusted pattern structure 7 is a highly uniform circular via array, with the via diameter reduced to ≤10 nm, the deviation reduced to ≤±1 nm, and the aspect ratio increased to ≥10:1.

[0056] like Figure 3 , Figure 4In the second embodiment shown, the initial intermediate pattern structure 4 is an arrangement of grooves, or a grid-like linear pattern. The longitudinal strip-shaped cutouts create multiple longitudinal non-cutout portions in the intermediate film layer 2. Low-temperature ion implantation is performed on the vertical sidewalls of these non-cutout portions, with the scanning direction during low-temperature ion implantation being left-right. The adjusted pattern structure 7 is a structure with narrower non-cutout portions.

[0057] In summary, the method of selectively controlling pattern size through low-temperature ion implantation of the present invention can refine the pattern structure. By incident an ion beam at a low temperature and a specific angle onto the sidewall surface of the pattern structure, the material surface can be modified and excessive crystal damage can be avoided. Then, selective growth of nitrides or oxides is carried out through atomic layer deposition. The atomic layer deposition rate of the surface region modified by ion implantation is greater than that of the unmodified region. This allows the pattern size of the specific region to reach the set feature size and present a highly uniform and flat sidewall surface profile. Therefore, the present invention can reduce the feature size of vias, channels, trenches and linear patterns and meet the requirement of higher pattern uniformity. It can also achieve a smoother and defect-free surface morphology on the sidewall surface of the pattern structure, and can accurately control and reduce the feature size of the pattern structure, thereby helping to improve the performance of semiconductor devices.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for selectively controlling pattern size using a low-temperature ion implantation process, characterized in that, Includes the following steps: Step S1: Obtain intermediate material; the intermediate material has a multilayer structure, including at least a bottom film layer (1), an intermediate film layer (2) and a mask layer (3) stacked sequentially from bottom to top; the intermediate material has an intermediate pattern structure (4), the intermediate pattern structure (4) is the hollowed-out part in the mask layer (3) and the intermediate film layer (2), and the hollowed-out part in the mask layer (3) corresponds to the hollowed-out part in the intermediate film layer (2); Step S2, perform low-temperature ion implantation on the intermediate material to generate a modified layer (5) on the vertical sidewall of the non-hollowed-out portion of the intermediate film layer (2); wherein, the implantation direction of the low-temperature ion implantation is inclined implantation, and the implantation temperature of the low-temperature ion implantation is below 0°C. Step S3: Selective growth is performed by atomic layer deposition to form a deposition layer (6) covering the surface of the intermediate material. The deposition layer (6) forms an adjusted pattern structure (7). The outline of the adjusted pattern structure (7) is smaller than that of the intermediate pattern structure (4). The thickness of the deposition layer (6) on the surface of the modified layer (5) is greater than the thickness of the other parts of the deposition layer (6). The deposition layer (6) on the surface of the modified layer (5) reaches the set size and is uniform and flat. Step S4: Remove part of the deposited layer (6) above the mask layer (3) and above the bottom film layer (1) by wet etching, so that the bottom film layer (1) is exposed between the vertical sidewalls of the deposited layer (6); Step S5: Repair the bottom film layer (1), recrystallize and balance stress through hot annealing; Step S6: The adjusted pattern structure (7) is transferred to the bottom film layer (1) by dry etching.

2. The method for selectively controlling pattern size using a low-temperature ion implantation process according to claim 1, characterized in that, The intermediate material in step S1 is obtained through the following steps: using photolithography, the bottom film layer (1) with photoresist layer, hard mask layer and intermediate film layer (2) is exposed, wherein the photoresist layer, hard mask layer, intermediate film layer (2) and bottom film layer (1) are stacked sequentially from top to bottom; then the photoresist pattern structure is transferred to the intermediate film layer (2) by etching process to obtain the intermediate pattern structure (4).

3. The method for selectively controlling pattern size using a low-temperature ion implantation process according to claim 1, characterized in that, In step S1, the bottom film layer (1) is a wafer or a thin film formed on a wafer; the intermediate pattern structure (4) is a via, channel, trench or linear pattern structure.

4. The method for selectively controlling pattern size using a low-temperature ion implantation process according to claim 1, characterized in that, In step S1, the intermediate film layer (2) is a single crystal silicon, polycrystalline silicon, or silicon dioxide thin film.

5. The method for selectively controlling pattern size using a low-temperature ion implantation process according to claim 1, characterized in that, In step S2, the angle of tilt implantation is 5° to 50° relative to the vertical line of the bottom film layer (1) towards the side closer to the vertical sidewall to be treated; and / or, the implantation temperature of low-temperature ion implantation is ≤-10℃.

6. The method for selectively controlling pattern size using a low-temperature ion implantation process according to claim 1, characterized in that, In step S2, the ion beam implantation species for cryogenic ion implantation includes one of the following: argon ions, nitrogen ions, boron ions, helium ions, phosphorus ions, oxygen ions, fluorine ions, silicon ions, and germanium ions; the ion beam energy range is 50 eV to 10 keV; and the ion beam dose range is 5 E13 atoms / cm. 2 ~5E16 atoms / cm 2 Ion implantation depth ≤ 10 nm.

7. The method for selectively controlling pattern size using a low-temperature ion implantation process according to any one of claims 1 to 6, characterized in that, In step S2, at least two cryogenic ion implantations at different implantation angles are performed to treat the vertical sidewalls in at least two directions. During cryogenic ion implantation, the intermediate material is located on a stage in the ion implantation equipment. The stage drives the intermediate material on the stage to rotate to treat the vertical sidewalls of the same intermediate material in different directions. The implantation angle remains unchanged before and after rotation.

8. The method for selectively controlling pattern size using a low-temperature ion implantation process according to any one of claims 1 to 6, characterized in that, In step S3, the deposited layer (6) is a nitride or an oxide.

9. The method for selectively controlling pattern size using a low-temperature ion implantation process according to any one of claims 1 to 6, characterized in that, In step S3, the atomic layer deposition rate on the surface of the modified layer (5) is ≥0.15 nm / cycle, and the atomic layer deposition rate of the remaining part is ≤0.1 nm / cycle; The width of the hollowed-out portion in the intermediate film layer (2) of the intermediate pattern structure (4) is ≥15nm and the deviation is ≥±3nm; the width of the hollowed-out portion in the intermediate film layer (2) of the adjusted pattern structure (7) is ≤10nm and the deviation is ≤±1nm.

10. The method for selectively controlling pattern size using a low-temperature ion implantation process according to any one of claims 1 to 6, characterized in that, The aspect ratio of the hollowed-out portion in the intermediate film layer (2) of the adjusted pattern structure (7) is ≥5:1; and / or the surface roughness of the vertical sidewall of the adjusted pattern structure (7) is ≤0.5nm.

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