Semiconductor packaging structure and semiconductor packaging method

Abstract

The invention provides a semiconductor packaging structure and a semiconductor packaging method, and the semiconductor packaging structure comprises a lead frame; the chip comprises a substrate, a groove is formed in one side, close to the lead frame, of the substrate, and an opening of the groove faces the lead frame; and the groove is filled with a part of the bonding piece, and the bonding piece is connected with the chip and the lead frame. According to the semiconductor device, the groove is formed in the side, close to the lead frame, of the substrate, so that the bonding piece is partially filled in the groove, the contact area of the chip and the bonding piece is increased, the thermal resistance between the chip and the lead frame is reduced, the reliability of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to a semiconductor packaging structure and a semiconductor packaging method. Background Technology

[0002] In semiconductor packaging manufacturing, the connection and mechanical support between the chip and external circuits mainly rely on the synergistic effect of the leadframe and the package. In related technologies, the chip substrate is typically directly bonded to the leadframe using conductive or insulating adhesives such as silver paste, with the chip's metal interconnect layer facing upwards. Electrical connections are achieved between the chip and the leadframe pins via metal bonding wires. However, this bonding method has high thermal resistance, leading to poor reliability of the semiconductor device and reduced lifespan. Summary of the Invention

[0003] This application provides a semiconductor packaging structure and a semiconductor packaging method, which increases the contact area between the chip and the bonding element, reduces the thermal resistance between the chip and the lead frame, improves the reliability of the semiconductor device, and extends its service life.

[0004] To address the aforementioned technical problems, this application provides a semiconductor packaging structure, comprising: a lead frame; a chip including a substrate, wherein a groove is formed on the substrate near the lead frame, and the opening of the groove faces the lead frame; and an adhesive, wherein a portion of the adhesive fills the groove and connects the chip and the lead frame.

[0005] In some embodiments, the chip further includes a metal interconnect layer disposed on the substrate; the substrate has a first surface and a second surface disposed opposite to each other, the metal interconnect layer being disposed on the second surface; the groove is recessed from the first surface in a direction pointing toward the second surface, and the groove terminates between the first surface and the second surface.

[0006] In some embodiments, the depth of the groove is greater than or equal to one-third of the thickness of the substrate, and less than the thickness of the substrate.

[0007] In some embodiments, the number of grooves is multiple; the multiple grooves are spaced apart from each other along a first direction perpendicular to the thickness direction of the substrate; or the multiple grooves form a mesh structure, including a first sub-groove extending along the first direction and a second sub-groove extending along a second direction, the first sub-groove and the second sub-groove communicating with each other; wherein the first direction and the second direction are perpendicular to the thickness direction of the substrate.

[0008] In some embodiments, the shortest vertical distance between the inner sidewall of the groove and the outer periphery of the substrate is greater than 10 μm.

[0009] In some embodiments, the number of grooves is multiple; each groove extends through two opposite sides of the substrate along a second direction; wherein the second direction is perpendicular to the thickness direction of the substrate and the first direction.

[0010] To address the aforementioned technical problems, this application also provides a semiconductor packaging method, comprising: providing a wafer on which a plurality of chips are formed, each chip including a substrate; forming a groove on the substrate of each chip near the lead frame; dicing the wafer to obtain the plurality of chips; and fixing each chip to the lead frame using an adhesive, wherein the opening of the groove faces the lead frame, a portion of the adhesive fills the groove, and connects the chip and the lead frame.

[0011] In some embodiments, the depth of the groove is greater than or equal to one-third of the thickness of the substrate, and less than the thickness of the substrate.

[0012] In some embodiments, the total area of ​​the plurality of grooves does not exceed 50% of the area of ​​the substrate.

[0013] In some embodiments, dicing the wafer to obtain a plurality of chips includes: the plurality of chips including a metal interconnect layer disposed on the substrate, dicing the wafer along a dicing track on the side of the wafer where the metal interconnect layer is disposed to obtain a plurality of chips; wherein the shortest vertical distance between the inner sidewall of the groove surrounding each chip and the dicing track is greater than 10 μm.

[0014] In some embodiments, the substrate is disposed on the side of the chip adjacent to the lead frame, and the metal interconnect layer is disposed on the side of the substrate opposite to the lead frame, and the metal interconnect layer is connected to the lead frame via leads.

[0015] Some embodiments of this application provide a semiconductor packaging structure including: a lead frame; a chip including a substrate, wherein a groove is formed on the substrate near the lead frame, and the opening of the groove faces the lead frame; and an adhesive, wherein a portion of the adhesive fills the groove and connects the chip and the lead frame. By forming a groove on the substrate near the lead frame, the adhesive portion fills the groove, increasing the contact area between the chip and the adhesive. On the one hand, this reduces the thermal resistance between the chip and the lead frame, improving heat dissipation performance; on the other hand, it enhances the connection strength and bonding force between the chip and the lead frame. Therefore, it can improve the reliability of the semiconductor device and extend its service life. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the semiconductor packaging structure provided in some embodiments of this application; Figure 2 This is a top view of a chip substrate with one side facing upwards, provided in some embodiments of this application, wherein a plurality of grooves are spaced apart from each other along a first direction and penetrate two opposite sides of the substrate along a second direction; Figure 3 This is a top view of a chip substrate with one side facing upwards, provided in some embodiments of this application, wherein multiple grooves are arranged in a mesh structure. Figure 4 This is a schematic diagram of the wafer structure provided in some embodiments of this application, wherein, Figure 1 The chips in a semiconductor packaging structure are obtained by cutting wafers; Figure 5 Flowcharts of semiconductor packaging methods provided for some embodiments of this application; and Figure 6 This is a cross-sectional schematic diagram of the wafer thickness direction provided for some embodiments of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] The terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified in some embodiments.

[0019] In the embodiments of this application, all directional indicators (such as up, down, left, right, front, back, top, bottom, etc.) are only used to explain the relative positional relationship and movement of each component in a specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0020] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0021] Unless otherwise defined, the term "approximately" as used in this application can be understood, in relation to numerical quantities or quantitative relationships, as a range of approximately ±15% of a certain value.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] To address the aforementioned technical problems, this application provides a semiconductor packaging structure. (See figure.) Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in some embodiments of this application. In some embodiments of this application, the semiconductor packaging structure 100 includes a package body 110, a chip 120, and a lead frame 130, with at least a portion of the chip 120 and the lead frame 130 encapsulated in the package body 110. The chip 120 is disposed on and electrically connected to the lead frame 130, so that the lead frame 130 serves to support the chip 120 and connect the chip 120 to external circuitry. In some embodiments, see... Figure 1 The metal interconnect layer 122 can be connected to the lead frame 130 via the lead wire 150 to achieve electrical connection between the chip 120 and the lead frame 130.

[0024] In some embodiments, the chip 120 includes a substrate 121 and a metal interconnect layer 122 disposed on the substrate 121. The substrate 121 is disposed adjacent to the lead frame 130. A recess 1211 is formed on the side of the substrate 121 near the lead frame 130, and the opening of the recess 1211 faces the lead frame 130. The metal interconnect layer 122 is disposed on the side of the substrate 121 opposite to the lead frame 130.

[0025] The semiconductor package structure 100 also includes an adhesive 140, which partially fills a groove 1211 and connects the substrate 121 of the chip 120 and the lead frame 130. In some embodiments of this application, a groove 1211 is formed on the side of the substrate 121 near the lead frame 130, allowing the adhesive 140 to partially fill the groove 1211. This increases the contact area between the chip 120 and the adhesive 140. On one hand, this reduces the thermal resistance between the chip 120 and the lead frame 130; by entering the groove 1211, the adhesive 140 can more easily dissipate heat from the chip, improving heat dissipation performance. On the other hand, it enhances the connection strength and bonding force between the chip 120 and the lead frame 130. Therefore, the reliability of the semiconductor device can be improved, and its lifespan extended. The adhesive component 140 can be made of thermally conductive adhesive, such as silver paste, copper paste, carbon-based conductive adhesive, or non-conductive adhesive such as epoxy resin or thermal grease, which can further improve the heat dissipation performance of the chip 120.

[0026] See Figure 1 In some embodiments, the substrate 121 has a first surface 1212 and a second surface 1213 disposed opposite to each other. A metal interconnect layer 122 is disposed on the second surface 1213 to support the metal interconnect layer 122 through the substrate 121. In some embodiments, the metal interconnect layer 122 includes active devices such as transistors and diodes, and integrates interconnect channels between different functional modules such as power distribution and signal transmission to complete signal processing, data transmission, and electrical functions within the chip 120.

[0027] The groove 1211 is recessed from the first surface 1212 in a direction pointing towards the second surface 1213, that is, the groove 1211 extends along the thickness direction of the substrate 121, and the groove 1211 terminates between the first surface 1212 and the second surface 1213. In other words, the groove 1211 does not penetrate the entire substrate 121 in the direction pointing from the first surface 1212 to the second surface 1213, ensuring that the surface of the groove 1211 away from its opening does not contact the metal interconnect layer 122. This reduces the impact or interference of the groove 1211 in the substrate 121 on the electrical structure of the metal interconnect layer 122. It is understood that in some embodiments, the substrate 121 has structures such as device doping regions and electrical isolation. The location of the groove 1211 avoids the device doping regions and electrical isolation structures in the substrate 121 to further reduce the impact or interference of the groove 1211 on the electrical structure of various regions in the chip 120.

[0028] In some embodiments, the depth of the groove 1211 is greater than or equal to one-third of the thickness of the substrate 121, and less than the thickness of the substrate 121. This enhances the stability and reliability of the connection between the substrate 121 and the lead frame 130, while minimizing the impact or interference of the groove 1211 on the electrical structure in the metal interconnect layer 122. In some embodiments, the depth of the groove 1211 can be set to one-third, one-half, two-thirds, etc., of the thickness of the substrate 121. In some embodiments, the thickness of the substrate 121 of the chip 120 before the packaging process is 100–300 μm, for example, 100 μm, 200 μm, 300 μm, etc. Correspondingly, the depth of the groove 1211 can be set to be greater than or equal to 33.3 μm and less than 100 μm, for example, 33.3 μm, 50 μm, 80 μm, etc.; or the depth of the groove 1211 can be set to be greater than or equal to 66.6 μm and less than 200 μm, for example, 70 μm, 110 μm, 180 μm, etc.; or the depth of the groove 1211 can be set to be greater than or equal to 100 μm and less than 300 μm, for example, 100 μm, 150 μm, 200 μm, etc.

[0029] See Figures 2-3 , Figure 2 This is a top view of a chip substrate with one side facing upwards, provided in some embodiments of this application, wherein a plurality of grooves are spaced apart from each other along a first direction and penetrate two opposite sides of the substrate along a second direction; Figure 3 This is a top view of a chip substrate with one side facing upwards, provided in some embodiments of this application, wherein multiple grooves are arranged in a cross-shaped mesh structure. In some embodiments, the number of grooves 1211 is multiple, for example, 2 or 3 (e.g., ...). Figure 2 As shown), 4 (as shown) Figure 3 (as shown), or four or more. This application does not impose a specific limit on the number of grooves 1211.

[0030] Further as Figure 2 As shown, in some embodiments, chip 120 has a first direction x perpendicular to the thickness direction of substrate 121 and a second direction y perpendicular to both the thickness direction of substrate 121 and the first direction x. A plurality of grooves 1211 extend along the second direction y and are parallel to and spaced apart from each other along the first direction x. In some embodiments, each groove 1211 may penetrate two opposite sides of substrate 121 along the second direction y, thereby increasing the contact area between chip 120 and lead frame 130, thereby improving the bonding strength between chip 120 and lead frame 130 and the overall heat dissipation performance of the semiconductor device.

[0031] In some embodiments, see Figure 3 Multiple grooves 1211 can also form a mesh structure. For example... Figure 3As shown, the plurality of grooves 1211 include a first sub-groove 03 extending along a first direction x and a second sub-groove 04 extending along a second direction y. The first sub-groove 03 and the second sub-groove 04 are interconnected. Figure 3 In the illustrated embodiment, there are multiple first sub-grooves 03 and second sub-grooves 04. The first sub-grooves 03 are arranged parallel to each other along the second direction y, and the second sub-grooves 04 are arranged parallel to each other along the first direction x. This allows the multiple grooves 1211 to intersect and form a mesh structure, further increasing the contact area between the chip 120 and the lead frame 130, and improving the bonding force and connection strength between the chip 120 and the lead frame 130 from multiple directions. Of course, in other embodiments, the number of first sub-grooves 03 and second sub-grooves 04 can also be one, with the first sub-grooves 03 and second sub-grooves 04 forming a cross structure.

[0032] In some embodiments, the first sub-groove 03 may penetrate the substrate 121 along the first direction x, and the second sub-groove 04 may penetrate the substrate 121 along the second direction y. Alternatively, the first sub-groove 03 and the second sub-groove 04 may be configured not to penetrate the two opposite sides of the substrate 121 in either the first direction x or the second direction y. Furthermore, In other embodiments, multiple grooves 1211 may be provided along the oblique direction of the chip 120, that is, the diagonal direction, according to different needs.

[0033] Continue as Figure 2 and Figure 3 As shown, in some embodiments, the plurality of grooves 1211 are elongated. Of course, in other embodiments, the plurality of grooves 1211 can also be set to other shapes, such as squares, circles, etc. This application does not impose specific limitations on the arrangement, specific structural settings, shape settings, and quantity settings of the grooves 1211.

[0034] See Figure 4 , Figure 4 This is a schematic diagram of the wafer structure provided in some embodiments of this application, wherein, Figure 1 In the semiconductor packaging structure, the chip is obtained by dicing a wafer. There are multiple chips 120a on the wafer 200, and the multiple chips 120a are arranged in an array. The dicing track 210 on the wafer 200 is arranged around the chip 120a. Figures 1-3The chip 120 shown is obtained by dicing a wafer 200 along the dicing track 210. In some embodiments, the groove 1211 is formed on the surface of the substrate 121 opposite to the metal interconnect layer 122 before dicing the wafer 200. Furthermore, on the wafer 200, the shortest vertical distance between the inner sidewall of the groove 1211 surrounding each chip 120a and the dicing track 210 is greater than 10 μm, for example, 12 μm, 15 μm, 20 μm, etc., thereby allowing for a reasonable setting of the groove 1211's location and reducing the impact of the groove 1211 on the wafer 200 dicing process. In some embodiments, the shortest vertical distance between the inner sidewall of the groove 1211 surrounding each chip 120a and the dicing track 210 is greater than 20 μm.

[0035] See further Figure 1 In some embodiments, by means of Figure 4 The wafer 200 shown can be diced to obtain a single chip 120. For a single chip 120, the shortest vertical distance between the inner sidewall 01 of the groove 1211 and the outer periphery 02 of the substrate 121 is greater than 10μm, such as 12μm, 15μm, 20μm, etc. This allows for the reasonable setting of the groove 1211, reducing the impact of the groove 1211 on the wafer 200 dicing process.

[0036] In some embodiments, the total area of ​​the plurality of grooves 1211 does not exceed 50% of the area of ​​the substrate 121, in order to mitigate the impact on the rigidity of the chip 120 when the grooves 1211 on the substrate 121 are relatively dense, thereby reducing the impact on the structural stability of the chip 120. In some embodiments, to alleviate the problem of low rigidity of the chip 120, when the substrate 121 is provided with a plurality of grooves 1211 along a certain direction, the distance between adjacent grooves 1211 is set to be equal to the width of the groove 1211. In some embodiments, the width of the plurality of grooves 1211 may be set to be equal; in other embodiments, the substrate 121 may be provided with a plurality of grooves 1211 with different widths, and the distance between adjacent grooves 1211 is not less than the minimum width among the widths of the plurality of grooves 1211, which is not limited here.

[0037] To address the aforementioned technical problems, this application also provides a semiconductor packaging method. See [link to relevant documentation]. Figure 5 , Figure 5 This is a flowchart illustrating a semiconductor packaging method provided for some embodiments of this application. In some embodiments, the semiconductor packaging method includes the following steps.

[0038] Step S1: Provide a wafer on which multiple chips are formed, and each chip includes a substrate.

[0039] Figure 6 This is a schematic cross-sectional view of the wafer in the thickness direction provided for some embodiments of this application. See also...Figure 4 and Figure 6 In step S1, a wafer 200 is provided, on which a plurality of chips 120a are arranged in an array. Each chip 120a includes a substrate 121a. In some embodiments, the wafer 200 further includes a dicing channel 210 arranged around the chip 120a.

[0040] Step S2: Create a groove on the substrate of each chip on the side near the lead frame.

[0041] See Figure 1 and Figure 6 For each chip (120, 120a), the substrate (121, 121a) has a first surface (1212, 1212a) and a second surface (1213, 1213a) disposed opposite to each other. See also Figure 6 In step S2, a groove 1211a is formed on the side of the substrate 121a of each chip 120a near the lead frame 130. The groove 1211a is recessed from the first surface 1212a in a direction pointing towards the second surface 1213a, and terminates between the first surface 1212a and the second surface 1213a. That is, the groove 1211a does not penetrate the entire substrate 121a in the direction from the first surface 1212a to the second surface 1213a, thereby reducing the impact or interference of the groove 121a in the substrate 121a on the electrical structure in the metal interconnect layer 122a. In some embodiments, the groove 1211a can be formed on the side of the substrate 121a near the lead frame 130 by means of laser cutting or the like. In other embodiments, the groove 1211a can also be formed in other ways, and there are no limitations here.

[0042] In some embodiments, the depth of the groove 1211a is greater than or equal to 1 / 3 of the thickness of the substrate 121a, and less than the thickness of the substrate 121a, thereby enhancing the stability and reliability of the subsequent connection between the substrate 121a and the lead frame 130. In some embodiments, the depth of the groove 1211a can be set to 1 / 3, 1 / 2, 2 / 3, etc., of the thickness of the substrate 121a. On the wafer 200, the shortest vertical distance between the inner sidewall 01 of the groove 1211a surrounding each chip 120a and the dicing track 210 is greater than 10 μm, for example, 12 μm, 15 μm, 20 μm, etc., thereby allowing for a reasonable setting of the groove 1211a's location and reducing the impact of the groove 1211a on the wafer 200 dicing process. In some embodiments, the shortest vertical distance between the inner sidewall 01 of the groove 1211a surrounding each chip 120a and the dicing track 210 is greater than 20 μm.

[0043] In some embodiments, the number of grooves 1211a is multiple. For example...Figure 2 As shown, in some embodiments, chip 120a has a first direction x perpendicular to the thickness direction of substrate 121a and a second direction y perpendicular to both the thickness direction of substrate 121a and the first direction x. A plurality of grooves 1211a extend along the second direction y and are parallel to and spaced apart from each other along the first direction x. Each groove 1211a can penetrate two opposite sides of substrate 121a along the second direction y, thereby increasing the contact area between subsequent chip 120a and lead frame 130, thereby improving the bonding strength between chip 120a and lead frame 130 and the overall heat dissipation performance of the semiconductor device.

[0044] In some embodiments, see Figure 3 Multiple grooves 1211a can also form a mesh structure. For example... Figure 3 As shown, the plurality of grooves 1211a include a first sub-groove 03a extending along a first direction x and a second sub-groove 04a extending along a second direction y. The first sub-groove 03a and the second sub-groove 04a are interconnected. Figure 3 In the illustrated embodiment, there are multiple first sub-grooves 03a and second sub-grooves 04a. The first sub-grooves 03a are arranged parallel to each other along the second direction y, and the second sub-grooves 04a are arranged parallel to each other along the first direction x. This allows the multiple grooves 1211a to intersect and form a mesh structure, further increasing the contact area between the subsequent chip 120a and the lead frame 130, and improving the bonding force and connection strength between the chip 120a and the lead frame 130 from multiple directions. Of course, in other embodiments, the number of first sub-grooves 03a and second sub-grooves 04a can also be one, with the first sub-grooves 03a and second sub-grooves 04a forming a cross structure.

[0045] Step S3: Cut the wafer to obtain multiple chips.

[0046] In step S3, wafer 200 is diced to obtain multiple such... Figures 1-3 The chip shown is 120.

[0047] In some embodiments, the plurality of chips 120a further include a metal interconnect layer 122a disposed on a substrate 121a. For example... Figure 1 and Figure 6As shown, metal interconnect layers (122, 122a) are disposed on the second surface (1213, 1213a) to support the metal interconnect layers (122, 122a) through the substrate (121, 121a). In some embodiments, the wafer 200 can be cut using a front-side dicing method (i.e., the side where the metal interconnect layer 122a is disposed), that is, the wafer 200 is cut along the dicing track 210 on the side where the metal interconnect layer 122a is disposed to obtain a plurality of chips 120. In other embodiments, the wafer 200 can also be cut using a back-side dicing method, that is, the wafer 200 is cut along the dicing track 210 on the side where the substrate 121a is disposed to obtain a plurality of chips 120, and there is no limitation herein.

[0048] In some embodiments, as described above, the depth of the groove 1211a is greater than or equal to one-third of the thickness of the substrate 121a, and less than the thickness of the substrate 121a. This structure further reduces the impact or interference of the groove 1211a on the electrical structure of the metal interconnect layer 122a. It is understood that in some embodiments, the substrate 121a contains structures such as device doping regions and electrical isolation. The groove 1211a is positioned to avoid these structures in the substrate 121a, further reducing the impact or interference of the groove 1211a on the electrical structure of various regions in the chip 120a.

[0049] See Figure 1 For a single chip 120 obtained after dicing, the shortest vertical distance between the inner sidewall 01 of the groove 1211 and the outer periphery 02 of the substrate 121 is greater than 10μm, such as 12μm, 15μm, 20μm, etc. This allows for the reasonable setting of the groove 1211 and reduces the impact of the groove 1211 on the wafer 200 dicing process.

[0050] In some embodiments, a groove 1211a can be first formed on the back side of the wafer 200, that is, on the side of the substrate 121a away from the metal interconnect layer 122a, by means of laser cutting or the like. Then, the wafer 200 is cut by front-side cutting (i.e., from the side where the metal interconnect layer 122a is provided), thereby obtaining multiple... Figures 1-3 The chip 120 is shown. In other embodiments, the recess 1211a and the wafer 200 can be formed and cut in other ways, which are not limited here.

[0051] Step S4: Fix each chip to the lead frame using an adhesive, wherein the opening of the groove faces the lead frame, the adhesive portion fills the groove, and connects the chip and the lead frame.

[0052] See Figure 1In step S4, each chip 120 obtained after dicing the wafer 200 is fixed to the lead frame 130 using an adhesive 140, and then encapsulated together in the package 110. The adhesive 140 partially fills the groove 1211 and connects the chip 120 and the lead frame 130. This increases the contact area between the chip 120 and the adhesive 140, which on the one hand reduces the thermal resistance between the chip 120 and the lead frame 130, improving heat dissipation performance; on the other hand, it enhances the connection strength and bonding force between the chip 120 and the lead frame 130. Therefore, it improves the reliability of the semiconductor device and extends its service life. The adhesive 140 can be made of thermally conductive adhesive, such as silver paste, copper paste, or carbon-based conductive adhesive, or it can be made of non-conductive adhesive such as epoxy resin or thermal grease, which further improves the heat dissipation performance of the chip 120.

[0053] In some embodiments, the substrate 121 of the chip 120 is disposed adjacent to the lead frame 130, and the opening of the recess 1211 faces the lead frame 130. A metal interconnect layer 122 is disposed on the side of the substrate 121 away from the lead frame 130, and the metal interconnect layer 122 is connected to the lead frame 130 through a lead 150 to realize the electrical connection between the chip 120 and the lead frame 130.

[0054] The semiconductor packaging structure 100 provided in this application includes a lead frame 130; a chip 120 including a substrate 121, on which a groove 1211 is formed near the lead frame 130, with the opening of the groove 1211 facing the lead frame 130; and an adhesive 140, a portion of which fills the groove 1211 and connects the chip 120 and the lead frame 130. By forming the groove 1211 on the substrate 121 near the lead frame 130, the adhesive 140 is partially filled into the groove 1211, increasing the contact area between the chip 120 and the adhesive 140. On the one hand, this reduces the thermal resistance between the chip 120 and the lead frame 130, improving heat dissipation performance; on the other hand, it enhances the connection strength and bonding force between the chip 120 and the lead frame 130. Therefore, it improves the reliability of the semiconductor device and extends its service life.

[0055] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A semiconductor package structure, comprising: The semiconductor package structure comprises: a lead frame; a chip comprising a substrate, a recess being formed on a side of the substrate close to the lead frame, and an opening of the recess facing the lead frame; and an adhesive, a part of the adhesive being filled in the recess and connecting the chip and the lead frame. The chip further comprises a metal interconnection layer disposed on the substrate.

2. The semiconductor package structure of claim 1, wherein, The substrate has a first surface and a second surface disposed oppositely, and the metal interconnection layer is disposed on the second surface. The recess is recessed from the first surface in a direction pointing to the second surface, and the recess is cut off between the first surface and the second surface. The depth of the recess is greater than or equal to 1 / 3 of the thickness of the substrate and less than the thickness of the substrate.

3. The semiconductor package structure of claim 2, wherein, 4. The semiconductor package structure according to claim 1, wherein the number of the recesses is plural; the plural recesses are disposed at intervals in a first direction perpendicular to the thickness direction of the substrate; or the plural recesses are in a mesh structure comprising first sub-recesses extending in a first direction and second sub-recesses extending in a second direction, the first sub-recesses and the second sub-recesses being in communication with each other; wherein the first direction and the second direction are perpendicular to the thickness direction of the substrate.

5. The semiconductor package structure according to claim 4, wherein a shortest vertical distance between an inner side wall of the recess and an outer periphery of the substrate is greater than 10 μm.

6. The semiconductor package structure according to claim 4, wherein a total area of the plural recesses is not more than 50% of an area of the substrate. the number of the recesses is plural; 7. The semiconductor package structure of claim 1, wherein, each of the recesses penetrates through two opposite sides of the substrate in a second direction; wherein the second direction is perpendicular to the thickness direction of the substrate and the first direction. The semiconductor package structure comprises:

8. A semiconductor packaging method, characterized by, providing a wafer, a plurality of chips being formed on the wafer, and each of the chips comprising a substrate; forming a recess on the substrate of each of the chips close to the lead frame; cutting the wafer to obtain the plural chips; and fixing each of the chips to a lead frame by an adhesive, wherein an opening of the recess faces the lead frame, a part of the adhesive is filled in the recess, and the adhesive connects the chip and the lead frame. The depth of the recess is greater than or equal to 1 / 3 of the thickness of the substrate and less than the thickness of the substrate. The cutting of the wafer to obtain the plural chips comprises:

9. The semiconductor packaging method of claim 8, wherein, the plural chips comprising a metal interconnection layer disposed on the substrate, the wafer being cut along a cutting path on a side of the wafer where the metal interconnection layer is disposed to obtain the plural chips; 10. The semiconductor packaging method of claim 8, wherein, wherein a shortest vertical distance between an inner side wall of the recess surrounding each of the chips and the cutting path is greater than 10 μm. The substrate is disposed on a side of the chip close to the lead frame, and the metal interconnection layer is disposed on a side of the substrate away from the lead frame, and the metal interconnection layer is connected to the lead frame by a lead. ​ 11. The semiconductor packaging method of claim 10, wherein, ​

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