Super junction semiconductor device
By employing monolithically integrated trench gate and planar gate structures in superjunction devices, the resistivity of the drift region and gate region is optimized, solving the problem of limited current conduction in existing superjunction devices and achieving higher current capability and lower energy loss.
Patent Information
- Application Number
- CN202380100835.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-02
- Publication Date
- 2026-03-10
AI Technical Summary
In existing superjunction devices, the resistivity of the drift region and gate region is not optimized, which restricts current conduction. Existing solutions have failed to effectively reduce the resistivity of the gate region.
Employing a monolithically integrated trench gate and planar gate structure, by forming a superjunction in the drift region, combining vertical and planar channels, multiple conductive channels are used to optimize the resistivity of the full-power device, reducing the resistivity of the drift and gate regions.
By optimizing resistivity, the current capability of the device is improved, making it suitable for power conversion systems with high blocking voltage, high current density, and high switching frequency, while reducing energy loss and total application cost.
Smart Images
Figure CN121647041A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power semiconductor technology, such as silicon, silicon carbide, gallium nitride, etc. This invention relates to a superjunction semiconductor device and a method for manufacturing such a superjunction semiconductor device. Background Technology
[0002] The superjunction (SJ) concept is widely used in many power semiconductor technologies, such as Si, SiC, and GaN. Realizing SJ power devices relies on forming two oppositely doped regions (called pillars) along a specific distance. Pillar formation is a technical challenge. Pillars can be formed through implantation (including multiple epitaxy and multiple implantation) or through trench refilling (including trench etching and epitaxial regrowth). To use SJ power semiconductor switching devices, the SJ feature needs to be connected to the gate to form the power device. All concepts of superjunction devices involve a structure containing both a gate and a drift region. A major drawback of existing superjunction devices is the unoptimized gate resistivity (i.e., current conduction). Existing approaches primarily focus on reducing the resistivity of the drift region through the SJ concept; however, this approach is not optimal because the current is also limited by the gate region resistivity. Summary of the Invention
[0003] The present invention provides a solution to overcome the above-mentioned limitations in superjunction devices caused by the non-optimal resistivity of the drift region and the gate region.
[0004] This invention provides a scheme for optimizing the resistivity of a superjunction device at full power. Furthermore, a silicon carbide (SiC) superjunction device with integrated trench and planar MOSFET gate is disclosed.
[0005] The above and other objectives are achieved through the features of the independent claim. Other implementations will be apparent from the dependent claims, the description, and the drawings.
[0006] Embodiments of the present invention provide a scheme for optimizing the resistivity of a full-power device by associating the SJ drift region with the gate region, which has better conductivity (and therefore lower resistivity) due to the use of multiple conductive channels.
[0007] The present invention provides a novel superjunction device formed by monolithic integration of a spacer-based gate, which includes a vertical channel and a planar channel, wherein the superjunction is formed in a drift region beneath the body of the planar MOSFET.
[0008] The solutions described below are applicable to any power conversion system or architecture using semiconductor power devices. These solutions are suitable for applications requiring high blocking voltages, high current densities, and high switching frequencies. They are applicable to inductive switching circuits. These solutions are applicable to all power electronic systems and are designed to reduce energy losses, application scale, and total cost of ownership.
[0009] Products to which the disclosed solutions can be applied include all power electronic products, particularly DC and AC converters used in photovoltaics, electric vehicles, chargers and on-board chargers, data centers, railways, telecommunications, servers, and other fields.
[0010] To describe the invention in detail, the following terms and symbols will be used: MOS (Metal Oxide Semiconductor) FET field-effect transistor MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) IGBT Insulated Gate Bipolar Junction Transistor SiC silicon carbide CSL Current Spreading Layer JFET junction field-effect transistor SBD Schottky barrier diode JSBD junction Schottky barrier diode SSF Shockley Stacking Fault BPD basal dislocation SJ Superjunction Effective device area: the area that conducts forward current; it is smaller than the total device area. Total device area: This can be understood as the chip (wafer) area; it includes the active area and all peripheral structures, such as edge termination regions, scribe lines (cut tracks), contact pads (e.g., gate contacts), etc. Forward current: The main current flowing through the device when it is in the on state. Edge termination region: A region extending beyond the active region, its function is to reduce the electric field outside the device. Source: A region in a MOSFET that is injected with majority carriers during the on-state. Drain: A region in a MOSFET that collects majority carriers during the on-state. Emitter: A region in an IGBT that injects majority carriers during the on-state. Collector: A region in an IGBT that collects majority carriers and injects minority carriers during the on-state. Majority carriers: Electron carriers (electrons or holes) that dominate forward current conduction; their density is much greater than that of minority carriers. Minority carriers: Electron carriers (electrons or holes) whose density is much lower than that of majority carriers. Gate: The voltage control region in a MOSFET or IGBT, used to switch the device between on and off states. Drift layer: A region in a MOSFET or IGBT that conducts current in the on-state and maintains the maximum applied voltage (blocking voltage) in the off-state. Channel: A region within the main body region of a MOSFET or the substrate region of an IGBT, into which electron carriers are injected from either the source or emitter, and its conduction is controlled by the gate. Main region: The region in a MOSFET with a doping type opposite to that of the source and drift layer, containing the channel and forming a pn junction with the drift layer. Substrate region: The region in the IGBT with a doping type opposite to that of the source and drift layer, containing the channel and forming a pn junction with the drift layer. JFET region: The region located between the body region or substrate region of the MOSFET or IGBT, respectively. CSL: A region located below the JFET region, its function is to disperse current to reduce on-resistance. SJ: The main idea behind superjunctions is to enhance the two-dimensional (2D) loss of the drift region (instead of 1D). As a result, voltage capability (breakdown voltage) is significantly increased, current capability (Rdson decrease) is increased, or epitaxial thickness (epitaxy cost) is reduced.
[0011] Superjunction devices include the following structures: a gate, such as a MOSFET, IGBT, etc. implemented in a planar, trench, or recessed trench configuration, a JFET with a JFET gate, or a diode without a gate; and a drift region, such as a vertical or lateral device containing alternating P-type and N-type regions (pillars).
[0012] According to a first aspect, the present invention relates to a superjunction semiconductor device having a monolithically integrated trench gate and a planar gate, the superjunction semiconductor device comprising: a substrate disposed on the bottom surface of the superjunction semiconductor device; a drift layer formed above the substrate; a buffer layer disposed on top of the substrate and below the drift layer; a vertical channel segment formed above the drift layer, the vertical channel segment including a current spreading layer, a body-body separation region, a mesa body region, and a mesa source region; a planar channel segment formed above the drift layer and below a trench, the trench being formed on both sides of the vertical channel segment, the planar channel segment including a stack of layers of the current spreading layer, the trench body region, and the trench source region; and a pillar region formed in the drift layer below the trench body region, the pillar region and the drift layer forming a superjunction.
[0013] This semiconductor device represents a novel superjunction device formed by monolithic integration of spacer-based gates, comprising vertical and planar channels, wherein the superjunction is formed in a drift region beneath the main trench region.
[0014] This enables maximizing the device's current capability by simultaneously reducing the resistance of the drift region (through the use of SJ) and the channel resistance (through the use of spacer-based gate modules to provide multiple channels).
[0015] In an exemplary implementation of the semiconductor device, the pillar region is placed side-by-side with the drift layer; the pillar region extends vertically from the trench body region into the drift layer. Therefore, the pillar region can help eliminate drift regions.
[0016] In one exemplary implementation of the semiconductor device, the pillar region is in electrical contact with the current spreading layer and the trench body region. Therefore, the pillar region supports enhanced 2D depletion of the drift region.
[0017] The following text combines Figure 1 The above implementation method will be further described.
[0018] In one exemplary implementation of a semiconductor device, the trench is formed along a first direction adjacent to the vertical channel segment above the buffer layer; wherein the trench includes a trench bottom and at least one trench sidewall, and the semiconductor device includes a body contact region formed along a second direction parallel to the bottom surface in the planar channel segment and the vertical channel segment, the body contact region being used to electrically connect the trench body region of the planar channel segment to the mesa body region of the vertical channel segment by metallization. This improves the integration of the trench gate and the planar gate with the superjunction.
[0019] The above implementation will be further described below without referring to any specific figures. Metallization is not shown in the figures.
[0020] In one exemplary implementation of a semiconductor device, the main contact region includes a first portion formed in the planar channel segment and a second portion formed in the vertical channel segment; wherein the first portion of the main contact region is separate from the second portion of the main contact region. Therefore, the main contact region can be implemented in two channel segments (the vertical channel segment and the planar channel segment), respectively. The main contact region can also be formed in a third dimension.
[0021] The following text combines Figure 2a , Figure 2b , Figure 3a and Figure 3b The above implementation method will be further described.
[0022] In one exemplary implementation of a semiconductor device, the first portion of the body contact region is self-aligned and injected via spacers on the trench body region. These self-alignment processing steps enable precise control of the body and are unaffected by unwanted misalignment, which improves device performance and reduces wafer performance variability.
[0023] The following text combines Figure 2a , Figure 2b , Figure 3a and Figure 3b The above implementation method will be further described.
[0024] In one exemplary implementation of the semiconductor device, the first portion of the body contact region extends to the at least one trench sidewall. Therefore, the contact between the trench sidewall and the first portion of the body contact region can be improved.
[0025] The following description of the above implementation method will not be accompanied by specific figures.
[0026] In one exemplary implementation of the semiconductor device, the first portion of the body contact region is spaced apart from the at least one trench sidewall. Therefore, the trench body region can fill the space between the first portion of the body contact region and the at least one trench sidewall, and different designs of this trench body region can be implemented.
[0027] The following text combines Figure 2a The above implementation method will be further described.
[0028] In one exemplary implementation of the semiconductor device, the first portion of the body contact region extends to the edge of the trench source region. This provides design flexibility for implementing the body contact region.
[0029] The following text combines Figure 2b The above implementation method will be further described.
[0030] In one exemplary implementation of the semiconductor device, the first portion of the body contact region is spaced apart from the edge of the trench source region. This also provides design flexibility in implementing the body contact region.
[0031] The following text combines Figure 3a and Figure 3b The above implementation method will be further described.
[0032] In one exemplary implementation of a semiconductor device, the first portion of the body contact region separates the trench source region into at least two portions. This provides design flexibility for implementing the body contact region.
[0033] The following text combines Figure 3a The above implementation method will be further described.
[0034] In one exemplary implementation of a semiconductor device, the first portion of the body contact region forms a strip parallel to the trench source region along the first direction. This also provides design flexibility for implementing the body contact region.
[0035] The following text combines Figure 4 and Figure 5a The above implementation method will be further described.
[0036] In one exemplary implementation of a semiconductor device, the first portion of the body contact region is formed discontinuously along the first direction. Therefore, different patterns can be formed within the body contact region.
[0037] The following text combines Figure 5b The above implementation method will be further described.
[0038] In one exemplary implementation of a semiconductor device, the pillar regions are self-aligned implanted in the drift layer via spacers. These self-alignment processing steps enable precise control of the body and are unaffected by unwanted misalignments, which improves device performance and reduces wafer performance variability.
[0039] The following text is in conjunction with the corresponding embodiment 3. Figure 6 The above implementation method will be further described.
[0040] In one exemplary implementation of the semiconductor device, the pillar region penetrates the drift layer and may or may not reach the buffer layer; or the pillar region penetrates both the drift layer and the buffer layer and may or may not reach the substrate. This allows for design flexibility. The pillar region can be formed according to design requirements. The size of the superjunction segment can be designed through the design of the pillar region.
[0041] The above implementation method corresponds to Example 4.
[0042] In one exemplary implementation of a semiconductor device, the width of the pillar region is designed to vary along a vertical direction of the semiconductor device, wherein the vertical direction is defined as running from the top surface of the semiconductor device to the bottom surface. This implementation can be designed such that the width of the pillar at the top portion is greater than its width at the bottom portion, or vice versa.
[0043] In one exemplary implementation of a semiconductor device, the pillar region is formed by multiple successive self-aligned injections through corresponding spacers in the drift layer.
[0044] The following text is in conjunction with the corresponding embodiment 3. Figure 7 The above implementation method will be further described.
[0045] According to a second aspect, the present invention relates to a method for manufacturing a superjunction semiconductor device, the method comprising: forming a mask in a wafer layer, the mask including a trench, the trench including a trench bottom and trench sidewalls; implanting a dopant into the trench to form a first dopant implantation region below the trench bottom; forming a spacer at the trench sidewalls; implanting a dopant into the trench, the trench sidewalls of the trench being covered by the spacer to form a second dopant implantation region below the first dopant implantation region; wherein the thickness of the spacer is designed such that the width of the second dopant diffusion region in the lateral direction matches the width of the first dopant diffusion layer in the lateral direction, wherein the second dopant diffusion layer is formed by diffusion or scattering of the second dopant implantation region in the lateral direction; wherein the first dopant diffusion layer is formed by diffusion or scattering of the first dopant implantation region in the lateral direction; wherein the first dopant implantation region and the second dopant implantation region together with the first dopant diffusion layer and the second dopant diffusion layer form a pillar region of the semiconductor device, wherein the pillar region formed in the wafer layer and the drift layer form a superjunction.
[0046] This method allows the fabrication of a semiconductor device representing a novel superjunction device, which can be monolithically integrated from spacer-based gates, including vertical and planar channels, wherein the superjunction is formed in a drift region below the main trench region.
[0047] It should be noted that dopant diffusion can also occur in the vertical direction (which will not be discussed further as it is not relevant to this invention).
[0048] The term "matching" here refers not only to alignment in the sense that the two dopant diffusion regions extend laterally such that their side surfaces lie on the same plane, but also to a design in which the first diffusion layer and the second diffusion layer have a predefined width relationship, i.e., the side surfaces of the first diffusion layer and the second diffusion layer are within a predetermined distance. In the embodiments shown below, designing this width relationship is an important aspect.
[0049] By using appropriate spacers, the lateral extension of the second dopant diffusion region can be efficiently matched with the lateral extension of the first dopant diffusion layer. Through this implantation and diffusion / scattering process, together with the spacers, the width of the diffusion layer can be optimally controlled or designed.
[0050] As mentioned above, dopant diffusion can also occur in the vertical direction, but since it is not further relevant to this invention, it will not be discussed further. It is understood that such vertical diffusion is also covered by this invention.
[0051] In one exemplary implementation of the method, the first dopant implantation region is formed by another spacer. Different spacer processes can be applied to improve the formation of the superjunction.
[0052] In one exemplary implementation of the method, the first dopant injection region is formed by a first self-aligned injection into the trench; the second dopant injection region is formed by a second self-aligned injection into the trench, the trench sidewalls being covered by the spacer.
[0053] As described above, these self-aligned implementations enable precise control of the host and are unaffected by unwanted misalignments, which improves device performance and reduces wafer performance variability.
[0054] In one exemplary implementation of the method, the method includes: removing the mask and the spacer, and forming another wafer layer on top of the first dopant implantation region; forming another mask in the second wafer layer, the other mask including a trench, the trench including a trench bottom and trench sidewalls; implanting dopant into the trench to form another first dopant implantation region below the trench bottom; forming another spacer at the trench sidewalls; implanting dopant into the trench, the trench sidewalls of the trench being covered by the other spacer to form another second dopant implantation region below the other first dopant implantation region; wherein the other spacer... The thickness is designed such that the width of the second dopant diffusion region in the lateral direction matches the width of the first dopant diffusion layer in the lateral direction, wherein the second dopant diffusion layer is formed by diffusion or scattering of the second dopant injection region in the lateral direction; wherein the first dopant diffusion layer is formed by diffusion or scattering of the first dopant injection region in the lateral direction; wherein the first dopant injection region and the second dopant injection region together with the first dopant diffusion layer and the second dopant diffusion layer form another portion of the pillar region of the semiconductor device.
[0055] The following text is in conjunction with the corresponding embodiment 3. Figure 6 The above implementation method will be further described. Attached Figure Description
[0056] Other embodiments of the present invention will be described in conjunction with the following drawings, wherein: Figure 1A schematic cross-section of the superjunction semiconductor device 100 provided in the first embodiment is shown; Figure 2a A 3D view of a superjunction semiconductor device 100 of a first variant having a main contact region 51, provided in the first embodiment, is shown. Figure 2b A 3D view of a superjunction semiconductor device 100 with a main contact region 51, provided in the first embodiment, is shown. Figure 3a A 3D view of a superjunction semiconductor device 100 with a main contact region 51, provided in the first embodiment, is shown. Figure 3b A 3D view of a superjunction semiconductor device 100 of a fourth variant having a main contact region 51, provided in the first embodiment, is shown. Figure 4 A schematic cross-section of the superjunction semiconductor device 100 provided in the second embodiment is shown; Figure 5a A 3D view of a superjunction semiconductor device 100 with a first variant having a main contact region 51, provided in the second embodiment, is shown. Figure 5b A 3D view of a superjunction semiconductor device 100 of a second variant having a main contact region 51, provided in the second embodiment, is shown. Figure 6 A schematic cross-section is shown illustrating the steps of a method for manufacturing a superjunction semiconductor device 100 provided in the third embodiment; Figure 7 A schematic cross-section is shown illustrating the implantation process of a method for manufacturing a superjunction semiconductor device 100 provided in the third embodiment. Detailed Implementation
[0057] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description, illustrating specific aspects in which the invention can be practiced. It should be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.
[0058] It should be understood that the statements relating to the described method can also apply to the corresponding device or system used to perform the method, and vice versa. For example, if a specific method step is described, the corresponding device may include units for performing the described method steps, even if such units are not illustrated or depicted in detail in the figures. Furthermore, it should be understood that, unless otherwise explicitly stated, features of the various exemplary aspects described herein can be combined with each other.
[0059] Figure 1 A schematic cross-section of the superjunction semiconductor device 100 provided in the first embodiment is shown.
[0060] The superjunction semiconductor device 100 is a device with monolithically integrated trench gate and planar gate.
[0061] The superjunction semiconductor device 100 includes: a substrate 1 disposed on the bottom surface 101 of the superjunction semiconductor device 100; a drift layer 3 formed above the substrate 1; a buffer layer 2 placed on top of the substrate 1 and below the drift layer 3; vertical channel segments 4, 7, 8, and 9 formed above the drift layer 3; planar channel segments 4, 5, and 6 formed above the drift layer 3 and below a trench 111, the trench 111 being formed on both sides of the vertical channel segments 4, 7, 8, and 9; and a pillar region 11.
[0062] Vertical channel sections 4, 7, 8, and 9 include current spread layer 4, body-body separation region 7, mesa body region 8, and mesa source region 9.
[0063] Planar channel segments 4, 5, and 6 consist of a stack of layers including a current spreading layer 4, a trench body region 5, and a trench source region 6.
[0064] The pillar region 11 is formed in the drift layer 3 below the main trench region 5. The pillar region 11 and the drift layer 3 form a superjunction 120.
[0065] The column region 11 can be placed side-by-side with the drift layer 3. The column region 11 extends vertically from the main trench region 5 into the drift layer 3, as shown below. Figure 1 As shown.
[0066] The column region 11 is the electrical contact current extension layer 4 and the trench body region 5.
[0067] The trench 111 may be formed along the first direction 104 next to the vertical channel segments 4, 7, 8, 9 above the buffer layer 2. The trench 111 includes a trench bottom 111a and at least one trench sidewall 111b.
[0068] The spacer gate region 10 may be formed in the trench 111, located above a portion of the trench body region 5 and the trench source region 6.
[0069] This first embodiment represents a vertical device.
[0070] Substrate 1, buffer layer 2, drift layer 3, current spreading layer 4, trench source region 6, body-body separation region 7, and mesa source region 9 can be of the first semiconductor doping type.
[0071] The trench body region 5 and the mesa body region 8 can be a second semiconductor doping type.
[0072] The connection between the main surface area 8 and the main groove area 5 can be made in the third dimension through the main contact area 51 (not shown in the figure).
[0073] In all implementations, the main contact region 51 is as deep as (or deeper than) the trench source region 6 to achieve contact with the trench main region 5.
[0074] The connection between the main body region 8 of the platform and the main body region 5 of the trench can also be implemented separately and performed in the third dimension (not shown in the figure). The main body region 8 of the platform can be connected through the second part of the main body contact region 52, while the main body region 5 of the trench can be connected through the first part of the main body contact region 51. In this case, region 52 needs to be as deep as (or deeper than) the source region 9 of the platform.
[0075] The connection of the main body area 5 of the trench (through the main body contact area 51) can be achieved as follows: Figure 2a , Figure 2b , Figure 3a and Figure 3b Implemented in the third dimension as indicated, wherein the subject contact region 51 can be implanted or regrown. The subject contact region 51 can be self-aligned to the trench edge, or spaced at a distance between 0 and the width of the trench region. The subject contact region 51 can be distributed (forming multiple regions) in the z-direction 104, wherein... Figure 2a , Figure 2b , Figure 3a and Figure 3b Only one of these multiple regions is shown in the z-direction 104. For simplicity, only one region is drawn in the figure.
[0076] The shape of the main contact area 51 is also arbitrary. It can also realize any other closed shape (circle, hexagon, triangle, rectangle, etc.) or any combination thereof.
[0077] In all cases, the main contact areas 51 and 52 can be made of metallized electrical contact (not shown in the figure for clarity).
[0078] The pillar region 11 of this SJ semiconductor device 100 can be self-aligned and implanted in the drift layer 3 via spacers, for example, as Figure 6 As shown. The column region 11 can penetrate the drift layer 3, reaching or not reaching the buffer layer 2, as... Figure 1 As shown. Alternatively, pillar region 11 may penetrate drift layer 3 and buffer layer 2, reaching or not reaching substrate 1 (not shown in the figure).
[0079] The width of the pillar region 11 can be designed to vary along the vertical direction of the semiconductor device 100, wherein the vertical direction is defined as from the top surface to the bottom surface of the semiconductor device 100.
[0080] The vertical direction can be tilted so that the width of the column at the top is greater than its width at the bottom, or vice versa.
[0081] The column region 11 can be formed by multiple consecutive self-aligned injections through corresponding spacers in the drift layer 3, for example, as... Figure 7 As shown.
[0082] Figure 2a A 3D view of a first variant of a superjunction semiconductor device 100 having a main contact region 51, provided in the first embodiment, is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown.
[0083] Semiconductor device 100 includes, as described above Figure 1 The main contact area 51 is formed in the planar channel segments 4, 5, 6 and the vertical channel segments 4, 7, 8, 9, for example along a second direction 107 parallel to the bottom surface 101. The main contact area 51 can be used to electrically connect the groove main area 5 of the planar channel segments 4, 5, 6 to the platform main area 8 of the vertical channel segments 4, 7, 8, 9 by metallization (not shown in the figure).
[0084] The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. For example... Figure 2a As shown, the first part 51 of the main body contact area 51 is separated from the second part 52 of the main body contact area 51.
[0085] The first portion 51 of the main contact area 51 can be self-aligned and implanted via a spacer on the grooved main area 5, for example, as described below. Figure 6 and Figure 7 As stated above.
[0086] A first portion 51 of the body contact area 51 is spaced apart from at least one trench sidewall 111b. In an alternative implementation (not shown), the first portion 51 of the body contact area 51 may extend to at least one trench sidewall 111b.
[0087] Figure 2b A 3D view of a superjunction semiconductor device 100 of a second variant having a main contact region 51, provided in the first embodiment, is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown.
[0088] As mentioned above Figure 2a The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. For example... Figure 2b As shown, the first part 51 of the main body contact area 51 is separated from the second part 52 of the main body contact area 51.
[0089] In this second variation, the first portion 51 of the main contact region 51 extends to the edge of the trench source region 6, and the first portion 51 of the main contact region 51 separates the trench source region 6 into at least two portions.
[0090] Figure 3a A 3D view of a third variant of a superjunction semiconductor device 100 having a main contact region 51, provided in the first embodiment, is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown.
[0091] As mentioned above Figure 2a The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. For example... Figure 3a As shown, the first part 51 of the main body contact area 51 is separated from the second part 52 of the main body contact area 51.
[0092] In this third variation, the first portion 51 of the main contact region 51 is spaced apart from the edge of the trench source region 6, but the first portion 51 of the main contact region 51 separates the trench source region 6 into at least two portions.
[0093] Figure 3b A 3D view of a fourth variant of a superjunction semiconductor device 100 having a main contact region 51, as provided in the first embodiment, is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown.
[0094] As mentioned above Figure 2a The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. For example... Figure 3b As shown, the first part 51 of the main body contact area 51 is separated from the second part 52 of the main body contact area 51.
[0095] In this fourth variation, the first portion 51 of the body contact region 51 is spaced apart from the edge of the trench source region 6, and the trench source region 6 is not divided into two or more portions by the first portion 51 of the body contact region 51.
[0096] Figure 4 A schematic cross-section of the superjunction semiconductor device 100 provided in the second embodiment is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown has a different shape in its connection to the trench body region 5, particularly the strip parallel to the trench source region 6.
[0097] As mentioned above Figure 2a The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. The first portion 51 of the main contact area 51 is separated from the second portion 52 of the main contact area 51 (e.g., Figure 5a and Figure 5b (As shown).
[0098] Figure 5a A 3D view of a superjunction semiconductor device 100 of a first variant having a main contact region 51, provided in a second embodiment, is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown.
[0099] As mentioned above Figure 2a The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. For example... Figure 5a As shown, the first part 51 of the main body contact area 51 is separated from the second part 52 of the main body contact area 51.
[0100] The first portion 51 of the main contact region 51 forms a strip parallel to the trench source region 6 along the first direction 104. The depth of the first portion of the main contact region 51 is greater than the depth of the trench source region 6, but less than the depth of the trench main region 5.
[0101] The first portion 51 of the main contact area 51 is formed continuously along the first direction 104.
[0102] Figure 5b A 3D view of a superjunction semiconductor device 100 of a second variant having a main contact region 51, provided in a second embodiment, is shown. The semiconductor device 100 corresponds to... Figure 1 The semiconductor device 100 shown.
[0103] As mentioned above Figure 2a The main contact area 51 includes a first portion 51 formed in the planar channel segments 4, 5, and 6, and a second portion 52 formed in the vertical channel segments 4, 7, 8, and 9. For example... Figure 5bAs shown, the first part 51 of the main body contact area 51 is separated from the second part 52 of the main body contact area 51.
[0104] The first portion 51 of the main contact area 51 forms a discontinuous strip along the first direction 104 parallel to the trench source region 6. (As described above...) Figure 5a The depth of the first part of the main contact area 51 is greater than the depth of the trench source region 6, but less than the depth of the trench main body region 5.
[0105] Figure 6 A schematic cross-section is shown illustrating the steps of a method for manufacturing a superjunction semiconductor device 100 provided in the third embodiment.
[0106] The method described above can produce the combination of the above. Figures 1 to 5b The superjunction semiconductor device 100 is described above.
[0107] The method, in conjunction with the first epitaxial layer, includes the following steps: A (601a) mask is formed in wafer layer 610, the mask including trench 111, the trench 111 including trench bottom 111a and trench sidewall 111b; Dopant (602a) is injected into trench 111 to form a first dopant injection region 5a below the bottom of trench 111a; Formation of the (603a) sedimentary layer; A spacer (604a) is formed at the trench sidewall 111b; a dopant (604a) is injected into the trench 111, the trench sidewall 111b of which is covered by the spacer, to form a second dopant injection region 5b below the first dopant injection region 5a.
[0108] The thickness of the spacer is designed such that the width of the second dopant diffusion region 5c in the lateral direction matches the width of the first dopant diffusion layer 5d in the lateral direction, wherein the second dopant diffusion layer 5c is formed by diffusion or scattering of the second dopant injection region 5b in the lateral direction; wherein the first dopant diffusion layer 5d is formed by diffusion or scattering of the first dopant injection region 5a in the lateral direction.
[0109] The first dopant implantation region 5a and the second dopant implantation region 5b, together with the first dopant diffusion layer 5d and the second dopant diffusion layer 5c, form the pillar region 11 of the semiconductor device 100, for example, as Figure 1 As shown, the pillar region 11 and the drift layer 3 formed in the wafer layer 610 form a superjunction 120, for example, as Figure 1 As shown.
[0110] It should be noted that dopant diffusion can also occur in the vertical direction (which will not be discussed further as it is not relevant to this invention).
[0111] The first dopant implantation region 5a can be formed by another spacer.
[0112] The first dopant implantation region 5a can be formed by performing a first self-aligned implantation into the trench 111; the second dopant implantation region 5b can be formed by performing a second self-aligned implantation into the trench 111, wherein the trench sidewall 111b of the trench 111 is covered by a spacer.
[0113] The method may be combined with a second epitaxial layer and includes the following further steps: Remove the mask and spacers, and form another wafer layer 611 on top of the first dopant implantation region 5a; Another mask (601b) is formed in the second wafer layer 611, the other mask including a trench 111, the trench 111 including a trench bottom 111a and trench sidewalls 111b, for example, as Figure 1 As shown; (602b) dopant is injected into trench 111 to form another first dopant injection region 5a below the bottom 111a of trench; Another sedimentary layer (603b) was formed; A (604b) spacer is formed at the trench sidewall 111b; a (604b) dopant is injected into the trench 111, the trench sidewall 111b of which is covered by another spacer to form another second dopant injection region 5b below another first dopant injection region 5a.
[0114] The thickness of the other spacer is designed such that the width of the other second dopant diffusion region 5c in the lateral direction matches the width of the other first dopant diffusion layer 5d in the lateral direction, wherein the other second dopant diffusion layer 5c is formed by diffusion or scattering of the other second dopant implantation region 5b in the lateral direction; wherein the other first dopant diffusion layer 5d is formed by diffusion or scattering of the other first dopant implantation region 5a in the lateral direction.
[0115] For example, another first dopant implantation region 5a and another second dopant implantation region 5b are formed together with another first dopant diffusion layer 5d and another second dopant diffusion layer 5c. Figure 1 Another portion of the pillar region 11 of the semiconductor device 100 shown.
[0116] In all the above embodiments, the pillar region 11 can be implemented by any manufacturing technique, such as (but not limited to): multiple implantation and multiple epitaxy, trench etching and filling, trench etching and sidewall implantation, or any combination thereof.
[0117] In particular, this invention proposes a novel method for manufacturing columns. It is based on epitaxy and injection through spacers: First epitaxial growth (e.g.) Figure 6 In the top portion shown, the epitaxial growth of a first thickness includes the following steps: Step 1 (Photolithography) 601a: In this step, a photolithographic mask is applied and developed to form an opening in the area on top of the semiconductor surface where the future SJ will be formed; Step 2 (Injection 1) 602a: Inject the first layer of SJ with one or more different doses and energies. Multiple injections may be used.
[0118] Step 3 (Layer Deposition) 603a: Deposit a layer in a conformal manner. The layer can be any material that can block the type of injection. Examples of such layers are dielectrics (e.g., oxides, nitrides, etc.), metals, alloys, etc.
[0119] Step 4.a (Layer Etching) 604a: Spacers are formed on the sidewalls of the trench by anisotropic etching (or a combination of anisotropic and isotropic etching) of the deposited layer. Step 4.b (Injection 2), 604a: The deeper portion of the SJ layer is self-aligned and injected into the spacer (the spacer acts as a mask). Multiple injections can be used.
[0120] Second epitaxial growth (e.g.) Figure 6 In the bottom portion (shown), the epitaxial growth of the second thickness includes the following steps: Step 1 (Photolithography), 601b: Same as Step 1 of the first epitaxy. The opening of the photolithographic mask is used as a parameter to determine the shape of the SJ. Figure 6 In the example shown, the mask opening is slightly widened (to accommodate the formation of the slanted SJ pillar). It should be noted that this is merely an example (other pillar shapes can be designed).
[0121] Step 2 (Injection 3), 602b: Inject the second layer of SJ with one or more different doses and energies. Multiple injectants can be used.
[0122] Step 3 (Layer Deposition), 603b: Deposit a layer in a conformal manner. The layer can be any material that can block the type of injection. Examples of such layers are dielectrics (e.g., oxides, nitrides, ...), metals, alloys, ... Adjust the thickness to form the desired column shape. Figure 6 The shape and size of the injected material are merely illustrative.
[0123] Step 4.a (Layer Etching), 604b: Spacers are formed on the sidewalls of the trench by anisotropic etching (or a combination of anisotropic and isotropic etching) of the deposited layer. Step 4.b (Injection 4), 604b: The deeper portion of the SJ layer is self-aligned and injected into the spacer (the spacer acts as a mask). Multiple injections can be used.
[0124] It should be noted that the thickness of the second epitaxial layer is adjusted such that the injection formed after the second epitaxy contacts the injection formed after the first epitaxy (to form a column).
[0125] It should be noted that, in Figure 6 In the (and related text) section, the width variation of the implanted layer forming the pillars of the SJ is not indicated (to simplify processing and avoid confusion). It must be understood that during the process flow, the implanted layer widens due to scattering effects (as in SiC) or diffusion (as in Si). The mask openings and spacer thicknesses are designed to account for this to achieve the desired pillar shape.
[0126] It should be noted that in the example given here, two epitaxies are arbitrarily selected, each with two injections (one via a mask and the other via a spacer). It must be understood that this is for illustrative purposes only: the number of epitaxies, the number of injections, the energy and dose of each injection, and the number of spacers are design parameters that can be selected based on the desired column shape.
[0127] The following text combines Figure 7 Here are some examples. Extremely large injection volumes can produce slanted column shapes, such as... Figure 7 As shown.
[0128] Figure 7 A schematic cross-section is shown illustrating the implantation process of a method for manufacturing a superjunction semiconductor device 100 provided in the third embodiment.
[0129] Figure 7 It shows the combination of the above text Figure 6 The steps described in the first epitaxial layer 610 and the second epitaxial layer 611 form a plurality of epitaxial layers.
[0130] In successful application, the above text is combined Figure 6 Following the steps described above, different shapes can be formed in the epitaxial layer.
[0131] For example, Figure 7Figure 701 shows multiple dopant implantation regions forming a pyramid shape, wherein the top of the pyramid is inverted, i.e., facing the bottom of the semiconductor device. Three epitaxial layers are present, with two dopant implantation regions formed in the first epitaxial layer, two dopant implantation regions formed in the second epitaxial layer, and three dopant implantation regions formed in the third epitaxial layer.
[0132] Figure 7 Figure 702 shows multiple dopant implantation regions forming a pyramid shape, with the top of the pyramid facing the top side of the semiconductor device. Three epitaxial layers are present: two dopant implantation regions are formed in the first epitaxial layer, two dopant implantation regions are formed in the second epitaxial layer, and three dopant implantation regions are formed in the third epitaxial layer.
[0133] Figure 7 Figure 703 shows multiple dopant implantation regions forming two pyramidal shapes with their tops facing each other. There are three epitaxial layers: two dopant implantation regions are formed in the first epitaxial layer, two dopant implantation regions are formed in the second epitaxial layer, and three dopant implantation regions are formed in the third epitaxial layer.
[0134] Figure 7 Figure 704 in the fourth section illustrates multiple dopant-implanted regions forming a pyramid shape, wherein the top of the pyramid is inverted. In contrast to Figure 701, there is an exemplary number of 11 epitaxial layers forming the dopant-implanted regions.
[0135] Figure 7 Figure 705 in the fifth section illustrates multiple dopant implantation regions forming a pyramid shape, with the top of the pyramid facing the top side of the semiconductor device. In contrast to Figure 702, there is an exemplary number of 11 epitaxial layers forming the dopant implantation regions.
[0136] Figure 7 Figure 706 in the document shows multiple dopant implantation regions forming a cuboid. There are three epitaxial layers: two dopant implantation regions are formed in the first epitaxial layer, two dopant implantation regions are formed in the second epitaxial layer, and three dopant implantation regions are formed in the third epitaxial layer.
[0137] Further embodiments will be described below.
[0138] According to the fourth embodiment, the pillar region 11 of all the above-mentioned superjunction semiconductor devices can be deep enough to reach the buffer layer 2, or penetrate the buffer layer 2, or reach the substrate 1, or penetrate the substrate 1.
[0139] According to the fifth embodiment, the pillar region 11 of all the superjunction semiconductor devices described above can have a variable width from top to bottom. For example, the pillar region 11 can be tilted such that the width of the pillar at the top is greater than its width at the bottom (or vice versa).
[0140] According to the sixth embodiment, the superjunction semiconductor device is a vertical device in which the doping type of the substrate 1 is opposite to the doping type of the drift layer 3. This device forms an IGBT structure.
[0141] According to the seventh embodiment, the superjunction semiconductor device is a complementary vertical device, wherein all semiconductor regions in the above embodiments are of the reverse doping type.
[0142] According to the eighth embodiment, the injection of the SJ column layer can be performed using any number of spacers (not limited to two). Each injection through a spacer can be a series of many sub-injections with different energies and / or doses.
[0143] According to the ninth embodiment, all previous embodiments may involve silicon, SiC, GaN, or Ga2O3.
[0144] According to the tenth embodiment, all previous embodiments may involve devices in which the depth of the current spreading layer 4 is less than that of the trench body region 5 or the trench source region 6.
[0145] In the embodiments of the present invention described above, the SJ is incorporated into a unique gate module, namely a planar gate and a trench gate. This enables the device's current capability to be maximized by simultaneously reducing the resistance of the drift region (through the use of the SJ) and the channel resistance (through the use of a spacer-based gate module to provide multiple channels).
[0146] In the embodiments of the present invention described above, the pillar extends below the body region of the planar MOSFET located within the trench region. This enables a direct and short path for collecting charge carriers during intense events (e.g., impact ionization).
[0147] In the embodiments of the present invention described above, the connection between the post and ground is naturally achieved through the body and contacts of the planar MOSFET body. This supports applying a ground potential to the post, thereby avoiding multiple grounding regions with potential differences.
[0148] In the embodiments of the present invention described above, the SJ column is formed by using multiple injections through spacers and combined with multiple epitaxial layers. This allows for better control over the column shape (e.g., straight, angled, etc.).
[0149] In the embodiments of the present invention described above, the space beneath the body of the planar MOSFET is used to implement SJ. This design does not result in an increase in area.
[0150] While certain features or aspects of the invention may have been disclosed in combination with only one of several implementations, such features or aspects may be combined with one or more other features or aspects of other implementations, provided that they are necessary or advantageous for any given or particular application. Furthermore, to a certain extent, the terms “comprising,” “having,” “having,” or other variations of these words are used in the detailed description or claims, and such terms, like the term “comprising,” are similar in meaning to indicate inclusion. Similarly, the terms “exemplarily” and “for example” are used only as examples and not as best or preferred. The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical contact or electrical contact, or whether they are not in direct contact with each other.
[0151] While specific aspects have been illustrated and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may replace the specific aspects shown and described without departing from the scope of the invention. This application is intended to cover any modifications or alterations to the specific aspects discussed herein.
[0152] Although the elements in the following claims are listed in a particular order using corresponding labels, these elements are not necessarily limited to being implemented in said particular order unless the formulation of the claims otherwise implies a particular order for implementing some or all of these elements.
[0153] Based on the above guidance, many alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, it will be readily apparent to those skilled in the art that the invention has many applications beyond those described herein. Although the invention has been described in conjunction with one or more specific embodiments, those skilled in the art will recognize that many changes can be made to the invention without departing from its scope. Therefore, it should be understood that the invention can be practiced in ways other than those specifically described herein, within the scope of the appended claims and their equivalents.
Claims
1. A super junction semiconductor device (100) with monolithically integrated trench gate and planar gate, characterized in that, The super junction semiconductor device (100) comprises: a substrate (1) arranged at a bottom surface (101) of the super junction semiconductor device (100); a drift layer (3) formed above the substrate (1); a buffer layer (2) placed on top of the substrate (1) and below the drift layer (3); a vertical channel segment (4, 7, 8, 9) formed above the drift layer (3), the vertical channel segment (4, 7, 8, 9) comprising a current spreading layer (4), a body- body separation region (7), a mesa body region (8), and a mesa source region (9); a planar channel segment (4, 5, 6) formed above the drift layer (3) and below a trench (111) formed on both sides of the vertical channel segment (4, 7, 8, 9), the planar channel segment (4, 5, 6) comprising a layer stack of the current spreading layer (4), a trench body region (5), and a trench source region (6); a pillar region (11) formed in the drift layer (3) below the trench body region (5), the pillar region (11) and the drift layer (3) forming a super junction (120).
2. The semiconductor device (100) according to claim 1, wherein the pillar region (11) is placed alongside the drift layer (3); the pillar region (11) extends vertically from the trench body region (5) into the drift layer (3).
3. The semiconductor device (100) according to claim 1 or 2, wherein the pillar region (11) electrically contacts the current spreading layer (4) and the trench body region (5).
4. The semiconductor device (100) according to any one of the preceding claims, wherein the trench (111) is formed alongside the vertical channel segment (4, 7, 8, 9) above the buffer layer (2) along a first direction (104); the trench (111) comprises a trench bottom (111a) and at least one trench sidewall (111b), the semiconductor device (100) comprising: a body contact region (51) formed in the planar channel segment (4, 5, 6) and in the vertical channel segment (4, 7, 8, 9) along a second direction (107) parallel to the bottom surface (101), the body contact region (51) for electrically connecting the trench body region (5) of the planar channel segment (4, 5, 6) with the mesa body region (8) of the vertical channel segment (4, 7, 8, 9) by metallization.
5. The semiconductor device (100) according to claim 4, wherein the body contact region (51) comprises a first portion (51) formed in the planar channel segment (4, 5, 6) and a second portion (52) formed in the vertical channel segment (4, 7, 8, 9); the first portion (51) of the body contact region (51) is separated from the second portion (52) of the body contact region (51).
6. The semiconductor device (100) according to claim 5, characterized in that the first portion (51) of the body contact region (51) is self-aligned implanted by spacers on the trench body region (5).
7. The semiconductor device (100) according to claim 5 or 6, characterized in that the first portion (51) of the body contact region (51) extends to the at least one trench sidewall (111b).
8. The semiconductor device (100) according to claim 5 or 6, characterized in that the first portion (51) of the body contact region (51) is spaced apart from the at least one trench sidewall (111b).
9. The semiconductor device (100) according to any one of claims 5, 6 or 7, characterized in that the first portion (51) of the body contact region (51) extends to an edge of the trench source region (6).
10. The semiconductor device (100) according to any one of claims 5, 6 or 7, characterized in that the first portion (51) of the body contact region (51) is spaced apart from an edge of the trench source region (6).
11. The semiconductor device (100) according to any one of claims 5, 6, 8 or 10, characterized in that the first portion (51) of the body contact region (51) separates the trench source region (6) into at least two portions.
12. The semiconductor device (100) according to claim 5 or 6, characterized in that the first portion (51) of the body contact region (51) forms a stripe parallel to the trench source region (6) along the first direction (104).
13. The semiconductor device (100) according to claim 5 or 6, characterized in that the first portion (51) of the body contact region (51) is formed in a discontinuous manner along the first direction (104).
14. The semiconductor device (100) according to any one of the preceding claims, characterized in that the pillar region (11) is self-aligned implanted in the drift layer (3) by spacers.
15. The semiconductor device (100) according to any one of the preceding claims, characterized in that the pillar region (11) penetrates the drift layer (3) to or not to the buffer layer (2); or the pillar region (11) penetrates the drift layer (3) and the buffer layer (2) to or not to the substrate (1).
16. The semiconductor device (100) according to any one of the preceding claims, characterized in that a width of the pillar region (11) is designed to vary along a vertical direction of the semiconductor device (100), wherein the vertical direction is defined from a top surface to a bottom surface of the semiconductor device (100).
17. The semiconductor device (100) according to any one of the preceding claims, characterized in that The pillar region (11) is formed by multiple successive self-aligned implantations through corresponding spacers in the drift layer (3).
18. A method for manufacturing a super junction semiconductor device (100), characterized by, The method comprises: forming a mask in a wafer layer (610), the mask comprising a trench (111), the trench (111) comprising a trench bottom (111a) and a trench sidewall (111b); implanting a dopant into the trench (111) to form a first dopant implantation region (5a) below the trench bottom (111a); forming a deposition layer; forming a spacer at the trench sidewall (111b); implanting a dopant into the trench (111), the trench sidewall (111b) of the trench (111) being covered by the spacer, to form a second dopant implantation region (5b) below the first dopant implantation region (5a); wherein the thickness of the spacer is designed to match a width of a second dopant diffusion region (5c) in a lateral direction with a width of a first dopant diffusion layer (5d) in the lateral direction, wherein the second dopant diffusion region (5c) is formed by diffusion or scattering of the second dopant implantation region (5b) in the lateral direction; wherein the first dopant diffusion layer (5d) is formed by diffusion or scattering of the first dopant implantation region (5a) in the lateral direction; wherein the first dopant implantation region (5a) and the second dopant implantation region (5b) together with the first dopant diffusion layer (5d) and the second dopant diffusion region (5c) form a pillar region (11) of the semiconductor device (100), wherein the pillar region (11) and the drift layer (3) formed in the wafer layer (610) form a super junction (120).
19. The method of claim 18, wherein the first dopant implantation region (5a) is formed by another spacer.
20. The method of claim 18 or 19, wherein the first dopant implantation region (5a) is formed by a first self-aligned implantation into the trench (111); the second dopant implantation region (5b) is formed by a second self-aligned implantation into the trench (111), the trench sidewall (111b) of the trench (111) being covered by the spacer.
21. The method of any one of claims 18-20, wherein, comprises: removing the mask and the spacer and forming another wafer layer (611) on top of the first dopant implantation region (5a); forming another mask in the second wafer layer (611), the another mask comprising a trench (111), the trench (111) comprising a trench bottom (111a) and a trench sidewall (111b); implanting a dopant into the trench (111) to form another first dopant implantation region (5a) below the trench bottom (111a); forming another deposition layer; forming another spacer at the trench sidewall (111b); injecting dopants into the trench (111) whose trench sidewall (111b) is covered by the other spacer to form another second dopant implantation region (5b) under the other first dopant implantation region (5a); wherein a thickness of the other spacer is designed to match a width of another second dopant diffusion region (5c) in a lateral direction with a width of another first dopant diffusion layer (5d) in the lateral direction, wherein the other second dopant diffusion layer (5c) is formed by diffusion or scattering of the other second dopant implantation region (5b) in the lateral direction; wherein the other first dopant diffusion layer (5d) is formed by diffusion or scattering of the other first dopant implantation region (5a) in the lateral direction; wherein the other first dopant implantation region (5a) and the other second dopant implantation region (5b) together with the other first dopant diffusion layer (5d) and the other second dopant diffusion layer (5c) form another portion of the pillar region (11) of the semiconductor device (100).