Light-emitting diode chip, preparation method thereof and display device

Abstract

The invention provides a light emitting diode chip, a preparation method thereof and a display device. The light emitting diode chip includes: a substrate; the light-emitting device comprises a substrate and at least two light-emitting structures arranged on the substrate, the at least two light-emitting structures are arranged at intervals, the at least two light-emitting structures are sequentially connected in series, and at least one light-emitting structure comprises a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first insulating layer, a current expansion layer and a first electrode which are arranged on the substrate and sequentially stacked; wherein at least one light-emitting structure comprises a first via hole located in the first insulating layer, the first electrode is electrically connected with the current expansion layer, and the current expansion layer is electrically connected with the second semiconductor layer through the first via hole; the orthographic projection of the first via hole on the substrate falls into the orthographic projection of the current expansion layer on the substrate, and the orthographic projection of the current expansion layer on the substrate falls into the orthographic projection of the second semiconductor layer on the substrate.

Description

Light-emitting diode chip, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a light emitting diode chip, a preparation method thereof, and a display device. Background Art

[0002] Light emitting diode (LED) technology has been developed for nearly three decades, and its application scope has continued to expand. For example, it can be used in the display field as a backlight source for display devices or as an LED display screen. With the development of technology, sub-millimeter light emitting diode (Mini Light Emitting Diode, Mini LED) has gradually become a research hotspot in the field of display technology. For example, Mini LED is driven by thin film transistor (TFT) technology, which has production capacity advantages, cost advantages, and backward compatibility with micro light emitting diode (Micro Light Emitting Diode, Micro LED), and has gradually become the mainstream research direction in the field of display technology. However, during use, because the current of Mini LED (μA level) is larger than the current of organic light-emitting diode (OLED) (nA level), the power consumption of TFT is large, resulting in high overall power consumption, which is not conducive to product promotion.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide a light emitting diode chip, a method for manufacturing the same, and a display device.

[0006] In one aspect, a light-emitting diode chip is provided, comprising: a substrate; and at least two light-emitting structures disposed on the substrate, wherein the orthographic projections of the at least two light-emitting structures on the substrate are spaced apart, and the at least two light-emitting structures are sequentially connected in series, wherein at least one of the light-emitting structures comprises: a first semiconductor layer disposed on the substrate; a light-emitting layer disposed on a side of the first semiconductor layer away from the substrate; a second semiconductor layer disposed on a side of the light-emitting layer away from the substrate; a first insulating layer disposed on a side of the second semiconductor layer away from the substrate; a current spreading layer disposed on a side of the first insulating layer away from the substrate; and a first electrode disposed on a side of the current spreading layer away from the substrate, wherein at least one of the light-emitting structures comprises a first via located in the first insulating layer, the first electrode being electrically connected to the current spreading layer, and the current spreading layer being electrically connected to the second semiconductor layer via the first via; and an orthographic projection of the first via on the substrate falling within the orthographic projection of the current spreading layer on the substrate, and the orthographic projection of the current spreading layer on the substrate falling within the orthographic projection of the second semiconductor layer on the substrate.

[0007] According to some exemplary embodiments, in the same light-emitting structure of at least one of the light-emitting structures, a plurality of first vias are provided in the first insulating layer, and the current spreading layer is electrically connected to the second semiconductor layer through the plurality of first vias; and the orthographic projections of the plurality of first vias on the substrate all fall within the orthographic projection of the current spreading layer on the substrate.

[0008] According to some exemplary embodiments, the light-emitting diode chip also includes a bridging conductive portion arranged on a side of the current spreading layer away from the substrate, the bridging conductive portion including a first part and a second part; and the at least two light-emitting structures include a first light-emitting structure and a second light-emitting structure that are adjacent, the first light-emitting structure and the second light-emitting structure being electrically connected through the bridging conductive portion, the first part of the bridging conductive portion being electrically connected to the second semiconductor layer of the first light-emitting structure, and the second part of the bridging conductive portion being electrically connected to the first semiconductor layer of the second light-emitting structure, wherein the orthographic projection of the first part of the bridging conductive portion on the substrate falls within the orthographic projection of the second semiconductor layer of the first light-emitting structure on the substrate, and the orthographic projection of the second part of the bridging conductive portion on the substrate falls within the orthographic projection of the first semiconductor layer of the second light-emitting structure on the substrate.

[0009] According to some exemplary embodiments, an orthographic projection of the first portion of the bridging conductive portion on the substrate at least partially overlaps with an orthographic projection of the current spreading layer of the first light emitting structure on the substrate.

[0010] According to some exemplary embodiments, an orthographic projection of the first via on the substrate at least partially overlaps with an orthographic projection of the first portion of the bridge conductive portion on the substrate.

[0011] According to some exemplary embodiments, an orthographic projection of at least one first via among the plurality of first vias on the substrate at least partially overlaps with an orthographic projection of the first portion of the bridge conductive portion on the substrate.

[0012] According to some exemplary embodiments, an orthographic projection of the first via on the substrate does not overlap with an orthographic projection of the first portion of the bridge conductive portion on the substrate.

[0013] According to some exemplary embodiments, the orthographic projection of the first portion of the bridging conductive portion on the substrate is spaced apart from the orthographic projection of the first via on the substrate, and the orthographic projection of a partial area of ​​the first portion of the bridging conductive portion on the substrate surrounds the orthographic projection of the first via on the substrate.

[0014] According to some exemplary embodiments, the light-emitting diode chip further includes a first reflective layer located between the first insulating layer and the current spreading layer, the light reflectivity of the first reflective layer is higher than the light reflectivity of the bridging conductive portion, and the orthographic projection of the first via on the substrate falls within the orthographic projection of the first reflective layer on the substrate.

[0015] According to some exemplary embodiments, the light emitting diode chip further includes a second reflective layer located on a side of the current spreading layer away from the substrate, and the second reflective layer includes a Bragg reflector.

[0016] According to some exemplary embodiments, the light-emitting diode chip further includes a second via hole in the second reflective layer, the first electrode is electrically connected to the current spreading layer through the second via hole, and an orthographic projection of the first via hole on the substrate falls within an orthographic projection of the second via hole on the substrate.

[0017] According to some exemplary embodiments, in at least one of the light-emitting structures, the orthographic projections of the plurality of first via holes on the substrate are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0018] According to some exemplary embodiments, in at least one of the light emitting structures, a ratio of an area of ​​an orthographic projection of the current spreading layer on the substrate to an area of ​​an orthographic projection of the second semiconductor layer on the substrate is less than 0.1.

[0019] According to some exemplary embodiments, in the same light-emitting structure of at least one of the light-emitting structures, the ratio of the area of ​​the orthographic projection of each of the multiple first vias on the substrate to the area of ​​the orthographic projection of the second semiconductor layer on the substrate is less than 0.1; and / or, in the same light-emitting structure of at least one of the light-emitting structures, the orthographic projection of the current spreading layer on the substrate basically coincides with the orthographic projection of the second semiconductor layer on the substrate.

[0020] According to some exemplary embodiments, the orthographic projection of the first via on the substrate is circular, the orthographic projection of a partial area of ​​the first portion of the bridging conductive portion on the substrate is annular, and the annular partial area of ​​the first portion of the bridging conductive portion is substantially concentric with the circular first via.

[0021] According to some exemplary embodiments, an orthographic projection of the first reflective layer on the substrate at least partially overlaps with an orthographic projection of the first portion of the bridge conductive portion on the substrate.

[0022] According to some exemplary embodiments, the light-emitting diode chip further includes a second electrode and a third via located in the second reflective layer, the second electrode being electrically connected to a first semiconductor layer of the light-emitting structure through the third via, and the orthographic projection of the third via on the substrate is spaced apart from the orthographic projection of the first via on the substrate.

[0023] According to some exemplary embodiments, the light-emitting diode chip includes three or more light-emitting structures, each of the light-emitting structures includes a first via hole located in the first insulating layer, the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; and the orthographic projection of the first via hole on the substrate falls within the orthographic projection of the current spreading layer on the substrate, and the orthographic projection of the current spreading layer on the substrate falls within the orthographic projection of the second semiconductor layer on the substrate.

[0024] In another aspect, a display device is provided, comprising the light emitting diode chip as described above.

[0025] On the other hand, a method for preparing a light-emitting diode chip is provided, wherein the preparation method includes: providing a substrate; and forming at least two light-emitting structures on the substrate, wherein the at least two light-emitting structures are arranged at intervals and are connected in series in sequence, wherein forming the at least two light-emitting structures on the substrate includes: forming a first semiconductor layer on the substrate; forming a light-emitting layer on a side of the first semiconductor layer away from the substrate; forming a second semiconductor layer on a side of the light-emitting layer away from the substrate; forming a first insulating layer on a side of the second semiconductor layer away from the substrate; forming a first via in the first insulating layer through a dry etching process; forming a current spreading layer on a side of the first insulating layer away from the substrate; and forming a first electrode on a side of the current spreading layer away from the substrate, wherein the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via; and an orthographic projection of the first via on the substrate falls within an orthographic projection of the current spreading layer on the substrate, and an orthographic projection of the current spreading layer on the substrate falls within an orthographic projection of the second semiconductor layer on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0027] FIG1A is a schematic cross-sectional view of a light emitting diode chip according to some exemplary embodiments of the present disclosure;

[0028] FIG1B is a cross-sectional schematic diagram of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure;

[0029] FIG. 1C is a plan view of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure.

[0030] FIG2 is a partially enlarged cross-sectional schematic diagram of a light emitting diode chip according to some exemplary embodiments of the present disclosure;

[0031] FIG3 is a schematic cross-sectional view of a light emitting diode chip according to some other exemplary embodiments of the present disclosure;

[0032] 4A is a cross-sectional view of a connection structure between a bridge conductive portion and a first light emitting structure according to some other exemplary embodiments of the present disclosure;

[0033] 4B is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to some other exemplary embodiments of the present disclosure;

[0034] FIG5 is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to further exemplary embodiments of the present disclosure;

[0035] FIG6 is a comparative plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to two exemplary embodiments of the present disclosure;

[0036] 7 is a cross-sectional view of a connection structure between a bridge conductive portion and a first light emitting structure according to further exemplary embodiments of the present disclosure;

[0037] FIG8 is a schematic diagram of a display device according to some exemplary embodiments of the present disclosure; and

[0038] 9A to 17A are schematic cross-sectional views of structures formed after some steps of a method for manufacturing a light emitting diode chip according to some exemplary embodiments of the present disclosure are performed;

[0039] 9B to 17B are schematic plan views of structures formed after some steps of a method for fabricating a light emitting diode chip according to some exemplary embodiments of the present disclosure are performed.

[0040] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0042] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0043] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0044] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0045] In this article, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED refers to inorganic light-emitting elements that are different from OLEDs. Specifically, inorganic light-emitting elements can include sub-millimeter light-emitting diodes (Mini LED) and micro light-emitting diodes (Micro LED). Sub-millimeter light-emitting diodes (Mini LEDs) refer to small light-emitting diodes with a grain size between Micro LEDs and traditional LEDs. Typically, the grain size of Mini LEDs can be between 100 and 300 microns.

[0046] Figure 1A is a cross-sectional schematic diagram of a light-emitting diode chip according to some exemplary embodiments of the present disclosure, Figure 1B is a cross-sectional schematic diagram of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure, and Figure 1C is a planar schematic diagram of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure.

[0047] Some exemplary embodiments of the present disclosure provide a light-emitting diode chip, a method for manufacturing the same, and a display device. Referring to Figures 1A, 1B, and 1C, the light-emitting diode chip includes a substrate 1 and at least two light-emitting structures 2 disposed on the substrate 1, the at least two light-emitting structures 2 being spaced apart and connected in series. In the embodiments of the present disclosure, the light-emitting diode chip may include multiple light-emitting structures connected in series, forming a high-voltage chip. This allows the line current to be reduced while the power consumption of the light-emitting diode remains essentially unchanged, thereby reducing the power consumption of the drive circuit and reducing the overall power consumption of the light-emitting diode chip.

[0048] Here, “at least two light-emitting structures 2 are arranged at an interval” means that the orthographic projections of the at least two light-emitting structures 2 on the substrate 1 are spaced apart from each other.

[0049] It should be noted that in the embodiments of the present disclosure, there is no particular limitation on the type of LED chip. For example, the LED chip may be a sub-millimeter LED, or a micro LED chip.

[0050] For example, the substrate 1 may be of various types and may be selected according to actual needs. For example, the substrate 1 may be a glass substrate, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, a silicon substrate, a silicon carbide substrate, or a sapphire substrate.

[0051] In an embodiment of the present disclosure, at least one light-emitting structure 2 includes: a first semiconductor layer 211 disposed on a substrate 1, a light-emitting layer 212 disposed on a side of the first semiconductor layer 211 away from the substrate 1, a second semiconductor layer 213 disposed on a side of the light-emitting layer 212 away from the substrate 1, a first insulating layer 214 disposed on a side of the second semiconductor layer 213 away from the substrate 1, a current spreading layer 215 disposed on a side of the first insulating layer 214 away from the substrate 1, and a first electrode 216 disposed on a side of the current spreading layer 215 away from the substrate 1. The inventors have found that using a small current to drive a light-emitting diode will result in a decrease in current density, which will correspondingly increase the degree of dispersion of the optical performance of the light-emitting diode chip itself. In an embodiment of the present disclosure, a current spreading layer is added to spread the current so that as many charges as possible (e.g., positive charges) can have a channel to the light-emitting layer so that they can recombine with negative charges injected from another semiconductor layer (e.g., an N-type layer) to emit light.

[0052] In an embodiment of the present disclosure, at least one light-emitting structure 2 includes a first via 217 located in the first insulating layer 214, the first electrode 216 is electrically connected to the current spreading layer 215, the current spreading layer 215 is electrically connected to the second semiconductor layer 213 through the first via 217, and the orthographic projection of the first via 217 on the substrate 1 falls within the orthographic projection of the current spreading layer 215 on the substrate 1, and the orthographic projection of the current spreading layer 215 on the substrate 1 falls within the orthographic projection of the second semiconductor layer 213 on the substrate 1.

[0053] For example, the current spreading layer 215 can be made of a transparent conductive material. In the actual manufacturing process, a transparent conductive material layer can be formed on the entire surface first, and then the transparent conductive material layer can be etched by a wet etching process to form the current spreading layer 215. The inventors have found through research that in the process of etching the transparent conductive material layer by a wet etching process, a lateral intrusion problem (i.e., a large amount of lateral etching) will occur, resulting in a large etching tolerance. For example, the etching tolerance on a single side reaches 5 microns. In this way, the minimum area of ​​the current spreading layer 215 is limited. For example, the minimum area of ​​the current spreading layer 215 is above 700 square microns. In the embodiment of the present disclosure, an insulating layer (such as the first insulating layer 214) is first made on the entire surface, and then the current spreading layer is evaporated after opening holes at the corresponding positions. Since a dry etching process is used to form vias in the insulating layer, the etching tolerance is small. For example, the etching tolerance on a single side is about 1 to 2 microns. The aperture of the via is the actual light-emitting area, which can reduce the actual light-emitting area to, for example, less than 300 square microns. This can further increase the current density and, accordingly, further improve the uniformity of the light-emitting diode chip at low grayscale.

[0054] In the embodiment of the present disclosure, by connecting at least two light-emitting structures 2 in series, the current in the light-emitting diode chip can be reduced when the same light-emitting intensity is achieved, and by providing the first insulating layer 214 and the first via 217, the actual light-emitting area of ​​the light-emitting diode chip can be reduced, thereby improving the current density of the light-emitting diode chip and optimizing the optical performance of the light-emitting diode chip.

[0055] 1B and 1C , a light-emitting diode chip according to an embodiment of the present disclosure may include a substrate 1 and at least two light-emitting structures 2 disposed on the substrate 1. For example, the substrate 1 may be a sapphire substrate, and the light-emitting structure 2 may include a first light-emitting structure 21 and a second light-emitting structure 22 connected in series.

[0056] For example, the first light-emitting structure 21 and the second light-emitting structure 22 emit light through the second electrode connected to the first semiconductor layer 211 of the second light-emitting structure 22 and the first electrode 216 connected to the second semiconductor layer 213 of the first light-emitting structure 21. The light-emitting diode chip can be any one of an R (red) chip, a G (green) chip, and a B (blue) chip.

[0057] It is understandable that the first light emitting structure 21 and the second light emitting structure 22 can be etched from a light emitting structure larger than the first light emitting structure 21. The first light emitting structure 21 can also be etched to obtain a sub-light emitting structure smaller than the first light emitting structure 21.

[0058] In the above embodiment, the light-emitting area of ​​the LED chip can be reduced by opening holes in the first insulating layer 214. In some embodiments, if the LED chip size is constant, only opening two holes to emit light will result in uneven light emission. Therefore, without reducing the operating current density of the LED chip, the LED chip can be etched to obtain more light-emitting structures 2.

[0059] According to an embodiment of the present disclosure, a light-emitting diode chip includes, for example, three or more light-emitting structures 2. Each light-emitting structure 2 includes a first via 217 located in a first insulating layer 214. The first electrode 216 is electrically connected to the current spreading layer 215. The current spreading layer 215 is electrically connected to the second semiconductor layer 213 through the first via 217. Furthermore, the orthographic projection of the first via 217 on the substrate 1 falls within the orthographic projection of the current spreading layer 215 on the substrate 1, and the orthographic projection of the current spreading layer 215 on the substrate 1 falls within the orthographic projection of the second semiconductor layer 213 on the substrate 1. The three or more light-emitting structures 2 have three or more first vias 217. The number of light-emitting structures 2 in the light-emitting diode chip can be adjusted according to actual needs to achieve uniform light emission.

[0060] FIG. 2 is a partially enlarged cross-sectional schematic diagram of a light emitting diode chip according to some exemplary embodiments of the present disclosure.

[0061] For example, as shown in Figure 2, the second light-emitting structure 22 includes: a first semiconductor layer 211 arranged on the substrate 1, a light-emitting layer 212 arranged on the side of the first semiconductor layer 211 away from the substrate 1, a second semiconductor layer 213 arranged on the side of the light-emitting layer 212 away from the substrate 1, a first insulating layer 214 arranged on the side of the second semiconductor layer 213 away from the substrate 1, and a current spreading layer 215 arranged on the side of the first insulating layer 214 away from the substrate 1.

[0062] For example, the first semiconductor layer 211 and the second semiconductor layer 213 can be an N-type layer and a P-type layer, respectively, or a P-type layer and an N-type layer, respectively. The light-emitting layer 212 is a quantum well layer. Under the action of current, positive charges are injected into the quantum well layer by the P-type layer, and negative charges are injected into the quantum well layer by the N-type layer. The positive and negative charges recombine in the quantum well layer to emit light.

[0063] According to an embodiment of the present disclosure, the light emitting layer 212 may include a multiple quantum well (MQW) structure, which may be a periodic structure in which gallium nitride (GaN) and indium gallium nitride (InGaN) are alternately arranged, but is not limited thereto.

[0064] For example, the first insulating layer 214 is a PV (polyvinyl) layer. The current spreading layer 215 is an ITO (Indium Tin Oxide) layer. The first insulating layer 214 covers the second semiconductor layer 213. Light emitted by the light-emitting layer 212 is transmitted upward through the first via 217 in the first insulating layer 214. The light-emitting area of ​​the light-emitting structure 2 can be controlled by controlling the size of the first via 217. This can increase the current density of the light-emitting diode chip during operation at low currents.

[0065] Since the current in the LED chip decreases, the current density of the LED chip during operation decreases, which increases the dispersion of the optical performance of the LED chip. To address this issue, the size of the individual light-emitting structures 2 in the LED chip can be reduced, thereby increasing the current density of the LED chip during operation at low currents and improving the uniformity of light emission.

[0066] For example, as shown in FIG1B , the size of the current spreading layer 215 can be controlled to control the light-emitting area of ​​the LED chip. In at least one light-emitting structure 2, the ratio of the area of ​​the orthographic projection of the current spreading layer 215 on the substrate 1 to the area of ​​the orthographic projection of the second semiconductor layer 213 on the substrate 1 is less than 0.1. The first insulating layer 214, for example, completely covers the second semiconductor layer 213, and the current spreading layer 215 is electrically connected to the second semiconductor layer 213 via a first via 217 in the first insulating layer 214. For example, the current spreading layer 215 only covers the first via 217 and does not cover the remaining portions of the first insulating layer 214 that do not have vias.

[0067] According to an embodiment of the present disclosure, as shown in FIG1A , the LED chip further includes, for example, a second reflective layer 220 located on a side of the current spreading layer 215 away from the substrate 1. The second reflective layer 220 includes a Bragg reflector. The second reflective layer 220 is used to enhance the brightness of the LED chip and to provide insulation and packaging for the PN junction.

[0068] Optionally, the second reflective layer 220 may be, for example, a distributed Bragg reflector (DBR) or a composite layer of a DBR and a photovoltaic (PV) layer. The DBR layer is a periodic structure formed by alternating two materials with different refractive indices, with the optical thickness of each alternating layer being one-quarter of the central reflection wavelength. In one example, the materials with different refractive indices forming the DBR layer may be silicon dioxide (SiO2) and titanium dioxide (TiO2), i.e., the DBR layer is formed by alternating silicon dioxide and titanium dioxide. In other examples, the materials with different refractive indices forming the DBR layer may be other materials.

[0069] According to an embodiment of the present disclosure, as shown in FIG1A , the light-emitting diode chip further includes, for example, a second via 221 located in the second reflective layer 220, and the first electrode 216 is electrically connected to the current spreading layer 215 via the second via 221. The current spreading layer 215 is in direct contact with the second semiconductor layer 213 via the first via 217, thereby achieving electrical connection. The first electrode 216 is electrically connected to the second semiconductor layer 213 via the current spreading layer 215.

[0070] According to an embodiment of the present disclosure, as shown in FIG1A , the light-emitting diode chip further includes, for example, a second electrode 222 and a third via 223 located in the second reflective layer 220. The second electrode 222 is electrically connected to the first semiconductor layer 211 of a light-emitting structure 2 through the third via 223. The orthographic projection of the third via 223 on the substrate 1 is spaced apart from the orthographic projection of the first via 217 on the substrate 1. The second electrode 222 is in direct contact with the first semiconductor layer 211 through the third via 223 to achieve electrical connection.

[0071] For example, the first electrode 216 and the second electrode 222 are respectively electrically connected to the first P-type layer and the first N-type layer between two adjacent independent light-emitting structures, and the second P-type layer and the second N-type layer between the two adjacent independent light-emitting structures are electrically connected through a metal part, thereby realizing a series electrical connection path between the two adjacent independent light-emitting structures, so that the two adjacent independent light-emitting structures emit light at the same current density.

[0072] In some exemplary embodiments of the present disclosure, the light-emitting diode chip may be a Mini LED chip. Mini LEDs can be driven using thin-film transistors like an active matrix, or can be driven using a driver IC like a passive matrix. For example, an LED backlight can be driven using a thin-film transistor. Specifically, Mini LED chips can be used in LCD display panels to form a display screen.

[0073] It should be noted that a rectangular frame is used in FIG1C to represent the LED chip, but it is understandable that the LED chip in the embodiment of the present disclosure is not limited to a rectangular shape, and may be other shapes such as a circle or a polygon.

[0074] According to an embodiment of the present disclosure, as shown in FIG1B , the LED chip further includes a bridging conductive portion 218 disposed on a side of the current spreading layer 215 away from the substrate 1. The bridging conductive portion 218 includes a first portion 2181 and a second portion 2182. At least two light-emitting structures 2 include adjacent first and second light-emitting structures 21 and 22. The first and second light-emitting structures 21 and 22 are electrically connected via the bridging conductive portion 218. The first portion 2181 of the bridging conductive portion 218 is electrically connected to the second semiconductor layer 213 of the second light-emitting structure 22, and the second portion 2182 of the bridging conductive portion 218 is electrically connected to the first semiconductor layer 211 of the first light-emitting structure 21. The first and second light-emitting structures 21 and 22 are independently luminous PN junctions. The bridging conductive portion 218 electrically connects the P-type layer and the N-type layer between the two adjacent independent light-emitting structures.

[0075] In an embodiment of the present disclosure, the orthographic projection of the first portion 2181 of the bridging conductive portion on the substrate 1 falls within the orthographic projection of the second semiconductor layer 213 of the first light-emitting structure on the substrate 1, and the orthographic projection of the second portion 2182 of the bridging conductive portion on the substrate 1 falls within the orthographic projection of the first semiconductor layer 211 of the second light-emitting structure on the substrate 1.

[0076] In the above embodiment, three or more light-emitting structures 2 can be obtained by etching the LED chip to achieve uniform light emission from the LED chip. Alternatively, multiple holes can be provided in one light-emitting structure 2 without increasing the number of light-emitting structures 2, thereby reducing the difficulty of the process.

[0077] FIG3 is a schematic cross-sectional view of a light emitting diode chip according to some other exemplary embodiments of the present disclosure.

[0078] According to an embodiment of the present disclosure, as shown in FIG3 , in the same light-emitting structure 2 of at least one light-emitting structure 2, a plurality of first vias 217 are provided in the first insulating layer 214, and the current spreading layer 215 is electrically connected to the second semiconductor layer 213 through the plurality of first vias 217. Furthermore, the orthographic projections of the plurality of first vias 217 on the substrate 1 all fall within the orthographic projection of the current spreading layer 215 on the substrate 1. Providing a plurality of first vias 217 in the first insulating layer 214 can disperse the current density in a single first via 217 relative to a single first via 217, thereby preventing the current spreading layer 215 in the first via 217 from being broken down due to excessive current density in a single first via 217, thereby improving the ESD (electro-static discharge) performance of the light-emitting diode chip. Furthermore, the plurality of first vias 217 also provide a plurality of light-emitting channels. When the plurality of first vias 217 are arranged in a certain manner, the light-emitting diode chip can achieve uniform light emission.

[0079] For example, as shown in FIG12B , the arrangement of the plurality of first vias 217 is as follows: in the same light-emitting structure 2 of at least one light-emitting structure 2, the orthographic projections of the plurality of first vias 217 on the substrate 1 are arranged in an array along a first direction and a second direction, where the first direction and the second direction intersect. The first direction and the second direction are, for example, orthogonal, and the rows and columns of the plurality of first vias 217 are arranged perpendicular to each other, thereby achieving uniform and uniform light emission from the light-emitting diode chip.

[0080] For example, in terms of connection, as shown in FIG3 , the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1 at least partially overlaps with the orthographic projection of the current spreading layer 215 of the first light-emitting structure 21 on the substrate 1. The first portion 2181 of the bridging conductive portion 218 is in direct contact with the current spreading layer 215, thereby achieving electrical connection between the bridging conductive portion 218 and the P-type layer of the first light-emitting structure 21.

[0081] For example, the orthographic projection of the first via 217 on the substrate 1 at least partially overlaps with the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1. The current spreading layer 215 is electrically connected to the second semiconductor layer 213 of the first light-emitting structure 21 through the first via 217. The first portion 2181 of the bridging conductive portion 218 is in direct contact with the current spreading layer 215 within the first via 217, and the first portion 2181 of the bridging conductive portion 218 at least partially covers the current spreading layer 215 within the first via 217. Because the charge transfer rate of the bridging conductive portion 218 is higher than that of the current spreading layer 215, the bridging conductive portion 218 covering the current spreading layer 215 within the first via 217 can promptly transfer charge in the current spreading layer 215 within the first via 217, reducing the accumulated charge in the current spreading layer 215 within the first via 217 and improving the ESD performance of the LED chip.

[0082] For example, the orthographic projection of at least one of the plurality of first vias 217 on the substrate 1 at least partially overlaps with the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1. When a plurality of first vias 217 are provided in the first insulating layer 214, the orthographic projection of at least one of the first vias 217 on the substrate 1 at least partially overlaps with the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1, thereby achieving electrical connection between the bridging conductive portion 218 and the second semiconductor layer 213.

[0083] For example, as shown in FIG3 , the orthographic projection of the first via 217 on the substrate 1 falls within the orthographic projection of the second via 221 on the substrate 1. When a plurality of first vias 217 are provided in the first insulating layer 214, the orthographic projection of at least one first via 217 on the substrate 1 falls within the orthographic projection of the second via 221 on the substrate 1, thereby achieving electrical connection between the first electrode 216 and the second semiconductor layer 213.

[0084] Figure 4A is a cross-sectional view of a connection structure between a bridge conductive portion and a first light emitting structure according to some other exemplary embodiments of the present disclosure. Figure 4B is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to some other exemplary embodiments of the present disclosure.

[0085] In some embodiments, because the bridge conductive portion 218 is formed directly after the current spreading layer 215, and its reflectivity is lower than that of the subsequently formed second reflective layer 220, the brightness of the LED chip may be reduced. To prevent this reduction in brightness of the LED chip, the first portion 2181 of the bridge conductive portion 218 may not cover the first via 217, thereby not blocking light from exiting the first via 217.

[0086] 4A and 4B , for example, the orthographic projection of the first via 217 on the substrate 1 does not overlap with the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1. The first portion 2181 of the bridging conductive portion 218 does not cover the first via 217 but directly contacts the current spreading layer 215 that is not in the first via 217, thereby achieving electrical connection.

[0087] In the above embodiment, providing multiple first via holes 217 in one light emitting structure 2 improves the light uniformity of the light emitting structure 2. To achieve a higher operating current density of the LED chip, the size of each first via hole 217 should be smaller than a size threshold.

[0088] For example, in the same light-emitting structure 2 of at least one light-emitting structure 2, the ratio of the area of ​​the orthographic projection of each of the plurality of first vias 217 on the substrate 1 to the area of ​​the orthographic projection of the second semiconductor layer 213 on the substrate 1 is less than 0.1. And / or, in the same light-emitting structure 2 of at least one light-emitting structure 2, the orthographic projection of the current spreading layer 215 on the substrate 1 substantially overlaps with the orthographic projection of the second semiconductor layer 213 on the substrate 1. Because the light-emitting structure 2 emits light through the first vias 217, the size of the current spreading layer 215 does not affect the light-emitting area. Therefore, the current spreading layer 215 and the second semiconductor layer 213 can be set to be substantially the same size, thereby achieving connection between the first portion 2181 of the bridging conductive portion 218 and the current spreading layer 215 while not covering the first vias 217. This avoids a decrease in the brightness of the LED chip due to the reflectivity of the bridging conductive portion 218 being lower than that of the subsequently fabricated second reflective layer 220.

[0089] In some embodiments, the first portion 2181 of the bridging conductive portion 218 does not cover the first via 217, thereby preventing a decrease in the brightness of the LED chip. Because the charge transfer rate of the bridging conductive portion 218 is greater than that of the current spreading layer 215, the shape of the bridging conductive portion 218 and the connection between the bridging conductive portion 218 and the current spreading layer 215 can be designed to reduce charge accumulation in the current spreading layer 215 due to the difference in charge transfer rates between the two, thereby improving the ESD performance of the LED chip.

[0090] FIG. 5 is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to further exemplary embodiments of the present disclosure.

[0091] According to an embodiment of the present disclosure, as shown in FIG5 , the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1 is spaced apart from the orthographic projection of the first via 217 on the substrate 1. Furthermore, the orthographic projection of a portion of the first portion 2181 of the bridging conductive portion 218 on the substrate 1 surrounds the orthographic projection of the first via 217 on the substrate 1. The first portion 2181 of the bridging conductive portion 218 does not cover the first via 217, but rather surrounds the first via 217. This allows for the timely transfer of charge within the current spreading layer 215 within the first via 217, reducing charge accumulation within the current spreading layer 215 and improving the ESD performance of the LED chip. Furthermore, the first portion 2181 of the bridging conductive portion 218 does not cover the first via 217, ensuring that the brightness of the LED chip does not decrease.

[0092] For example, as shown in FIG5 , the orthographic projection of the first via 217 on the substrate 1 is circular, and the orthographic projection of a portion of the first portion 2181 of the bridging conductive portion 218 on the substrate 1 is annular. The portion of the annular first portion 2181 of the bridging conductive portion 218 is substantially concentric with the circular first via 217. The first via 217 having a circular orthographic projection on the substrate 1, combined with the first portion 2181 of the bridging conductive portion 218 having an annular orthographic projection on the substrate 1, can achieve rapid charge transfer in the current spreading layer 215 within the first via 217.

[0093] It can be understood that the shape of the orthographic projection of the first via 217 on the substrate 1 can be other shapes besides a circle, such as a square, a diamond, an ellipse, etc., and the inner contour of the shape of the orthographic projection of the first part 2181 of the bridging conductive part 218 on the substrate 1 can also be other shapes corresponding to the shape of the orthographic projection of the first via 217 on the substrate 1.

[0094] FIG6 is a comparative plan view of connection structures between a bridge conductive portion and a first light emitting structure according to two exemplary embodiments of the present disclosure.

[0095] According to an embodiment of the present disclosure, as shown in FIG6 , in a scheme in which the first via 217 whose orthographic projection on the substrate 1 is circular is combined with the first portion 2181 of the bridging conductive portion 218 whose orthographic projection on the substrate 1 is annular, charges can be uniformly transferred from the four sides of the first via 217 to a partial area of ​​the first portion 2181 of the bridging conductive portion 218, and the charge transfer efficiency is better than the scheme in which charges are transferred from the first via 217 to the first portion 2181 of the bridging conductive portion 218 in a single direction.

[0096] In the above embodiment, the first portion 2181 of the bridging conductive portion 218 can be arranged not to cover the first via 217, thereby preventing a decrease in the brightness of the LED chip due to the reflectivity of the first portion 2181 of the bridging conductive portion 218 being lower than the reflectivity of the second reflective layer 220. Furthermore, a high-reflectivity metal layer can be provided below the first via 217 in the first via 217 to simultaneously ensure that the brightness of the LED chip is not reduced and improve the ESD performance of the LED chip.

[0097] FIG. 7 is a cross-sectional view of a connection structure between a bridge conductive portion and a first light emitting structure according to further exemplary embodiments of the present disclosure.

[0098] According to an embodiment of the present disclosure, as shown in Figure 7, the light-emitting diode chip further includes a first reflective layer 219 located between the first insulating layer 214 and the current spreading layer 215. The light reflectivity of the first reflective layer 219 is higher than the light reflectivity of the bridging conductive portion 218. The orthographic projection of the first via 217 on the substrate 1 falls within the orthographic projection of the first reflective layer 219 on the substrate 1.

[0099] For example, the first reflective layer 219 is made of high-reflectivity metallic silver. The first reflective layer 219 can effectively increase the charge accumulation area of ​​the current spreading layer 215 in the first via 217, increasing the radius from 8 microns to 10 microns, thereby improving the ESD performance of the LED chip.

[0100] For example, the orthographic projection of the first reflective layer 219 on the substrate 1 at least partially overlaps with the orthographic projection of the first portion 2181 of the bridging conductive portion 218 on the substrate 1. The first reflective layer 219 is disposed in the first via 217 and partially extends out of the first via 217, thereby covering the first via 217 while not covering the remaining portions of the first insulating layer 214 that are not exposed. The current spreading layer 215 covers the first reflective layer 219 and the first insulating layer 214 that does not cover the first reflective layer 219. The current spreading layer 215 covers the first reflective layer 219, thereby preventing migration of the first reflective layer 219. Because the light reflectivity of the first reflective layer 219 is greater than that of the bridging conductive portion 218, the first portion 2181 of the bridging conductive portion 218 can cover the first via 217, thereby improving the ESD performance of the LED chip.

[0101] Some exemplary embodiments of the present disclosure further provide a display device. FIG8 is a schematic diagram of a display device according to some exemplary embodiments of the present disclosure. Referring to FIG8 , the display device includes the above-mentioned light emitting diode chip.

[0102] The display device may be any product or component having a display function. For example, the display device may be a smart phone, a mobile phone, a navigation device, a television (TV), a car stereo, a laptop computer, a tablet computer, a portable multimedia player (PMP), a personal digital assistant (PDA), etc.

[0103] For example, in some Mini LED display modules using LED chips according to embodiments of the present disclosure, reducing the current in the LED chips can reduce the power consumption and cost of the Mini LED display modules. Furthermore, reducing the Cu thickness of the substrate reduces process difficulty. While maintaining the existing process difficulty, the use of high-voltage LED chips ensures the yield of the display module.

[0104] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned LED chip. These features and advantages can be referred to the above description of the LED chip and will not be repeated here.

[0105] Other exemplary embodiments of the present disclosure further provide a method for fabricating a light-emitting diode chip. Figures 9A to 17A are schematic cross-sectional views of structures formed after executing certain steps of the method for fabricating a light-emitting diode chip according to certain exemplary embodiments of the present disclosure. Figures 9B to 17B are schematic plan views of structures formed after executing certain steps of the method for fabricating a light-emitting diode chip according to certain exemplary embodiments of the present disclosure.

[0106] 9A to 17B , a method for fabricating a light-emitting diode chip includes providing a substrate 1, and forming at least two light-emitting structures 2 on the substrate 1, wherein the at least two light-emitting structures 2 are spaced apart and connected in series. Forming the at least two light-emitting structures 2 on the substrate 1 includes forming a first semiconductor layer 211 on the substrate 1, forming a light-emitting layer 212 on a side of the first semiconductor layer 211 away from the substrate 1, forming a second semiconductor layer 213 on a side of the light-emitting layer 212 away from the substrate 1, forming a first insulating layer 214 on a side of the second semiconductor layer 213 away from the substrate 1, forming a first via 217 in the first insulating layer 214 through a dry etching process, forming a current spreading layer 215 on a side of the first insulating layer 214 away from the substrate 1, and forming a first electrode 216 on a side of the current spreading layer 215 away from the substrate 1. The first electrode 216 is electrically connected to the current spreading layer 215, and the current spreading layer 215 is electrically connected to the second semiconductor layer 213 via the first via 217. The orthographic projection of the first via 217 on the substrate 1 falls within the orthographic projection of the current spreading layer 215 on the substrate 1 , and the orthographic projection of the current spreading layer 215 on the substrate 1 falls within the orthographic projection of the second semiconductor layer 213 on the substrate 1 .

[0107] For example, the various layers of the light-emitting diode chip can be prepared by using a metal-organic chemical vapor deposition (MOCVD) method combined with etching.

[0108] Specifically, referring to FIG. 9A and FIG. 9B , a first semiconductor layer 211 , a light emitting layer 212 , and a second semiconductor layer 213 are sequentially deposited on a substrate 1 to obtain a PN junction deposited on the substrate 1 .

[0109] 10A and 10B , the second semiconductor layer 213 and the light emitting layer 212 are etched to obtain basic shapes of the second semiconductor layer 213 and the light emitting layer 212 .

[0110] 11A and 11B , the first semiconductor layer 211 is further etched to obtain two independent PN junctions on the substrate 1 .

[0111] 12A and 12B , a first insulating layer 214 is deposited and etched on the second semiconductor layer 213 of each PN junction, and a plurality of first via holes 217 arranged in an array along the first direction and the second direction are etched on the first insulating layer 214 .

[0112] In the embodiment of the present disclosure, the light-emitting area of ​​the light-emitting structure 2 can be controlled by controlling the size of the first via 217. In this way, the current density of the light-emitting diode chip during operation can be improved under low current. Arranging multiple first vias 217 in the first insulating layer 214 relative to one first via 217 can disperse the current density in a single first via 217, avoid the current density in a single first via 217 being too high, and cause the current expansion layer 215 in the first via 217 to be broken down, thereby improving the ESD (Electro-Static discharge) performance of the light-emitting diode chip. In addition, the multiple first vias 217 also provide multiple light-emitting channels. When the multiple first vias 217 have a certain arrangement, the light-emitting diode chip can achieve a uniform light-emitting effect.

[0113] 13A and 13B , a current spreading layer 215 is evaporated on the first insulating layer 214 after the holes are opened, thereby obtaining a first light emitting structure 21 and a second light emitting structure 22 .

[0114] In the embodiment of the present disclosure, a current expansion layer 215 is added to expand the current so that as many charges as possible (e.g., positive charges) can pass from the second semiconductor layer 213 (e.g., P-type layer) to the light-emitting layer 212 so that they can recombine with the negative charges injected into the first semiconductor layer 211 (e.g., N-type layer) to emit light.

[0115] In particular, for example, the first insulating layer 214 is prepared by dry etching. After the first insulating layer 214 is prepared, a hole is opened in the first insulating layer 214 to obtain a first via 217. Then, the current spreading layer 215 is evaporated in the first via 217, thereby avoiding the side encroachment problem when preparing the current spreading layer 215 in the wet etching process. Because the first insulating layer 214 uses a dry etching process, the etching tolerance is small (for example, 1 to 2 μm on a single side), and the aperture of the first via 217 is the actual light-emitting area, the actual light-emitting area can be greatly reduced (for example, the light-emitting area is less than 300 μm2), thereby greatly improving the current density of the light-emitting diode chip during use and further improving the light uniformity of the light-emitting diode chip.

[0116] 14A and 14B , an insulating layer is deposited in the AA region.

[0117] 15A and 15B , a bridging conductive portion 218 is deposited in region BB. The insulating layer in region AA isolates the bridging conductive portion 218 in region BB from the first light-emitting structure 21. Furthermore, a first portion 2181 of the bridging conductive portion 218 contacts the current spreading layer 215 of the first light-emitting structure 21, electrically connecting the first portion 2181 of the bridging conductive portion 218 to the second semiconductor layer 213 of the first light-emitting structure 21. A second portion 2182 of the bridging conductive portion 218 contacts the first semiconductor layer 211 of the second light-emitting structure 22, electrically connecting the second portion 2182 of the bridging conductive portion 218 to the first semiconductor layer 211 of the second light-emitting structure 22. Thus, the bridging conductive portion 218 electrically connects the first light-emitting structure 21 and the second light-emitting structure 22 in series.

[0118] In the embodiment of the present disclosure, the first portion 2181 of the bridging conductive portion 218 may cover some of the plurality of first vias 217 or may not cover any of the first vias 217. The first portion 2181 of the bridging conductive portion 218 not covering the first vias 217 prevents a decrease in the brightness of the LED chip. By designing the shape of the bridging conductive portion 218 and the connection between the bridging conductive portion 218 and the current spreading layer 215, charge accumulation in the current spreading layer 215 caused by the difference in charge transfer rates between the two can be reduced, thereby improving the ESD performance of the LED chip.

[0119] In an embodiment of the present disclosure, the light-emitting diode chip may include a first light-emitting structure 21 and a second light-emitting structure 22 connected in series, that is, forming a high-voltage chip. In this way, the line current can be reduced while the power consumption of the light-emitting diode remains basically unchanged, thereby reducing the power consumption of the driving circuit, thereby reducing the overall power consumption of the light-emitting diode chip.

[0120] 16A and 16B , a second reflective layer 220 is deposited on the first and second light-emitting structures 21 and 22, which are electrically connected in series. The second reflective layer 220 is then etched to form a second via 221 connected to the current spreading layer 215 of the second light-emitting structure 22. Furthermore, the second reflective layer 220 is etched to form a third via 223 connected to the first semiconductor layer 211 of the first light-emitting structure 21. The second reflective layer 220 is used to enhance the brightness of the light-emitting diode chip and to provide insulation and packaging for the PN junction.

[0121] 17A and 17B , the first electrode 216 is deposited in the second via hole 221 , and the second electrode 222 is deposited in the third via hole 223 , thereby obtaining light emitting diode chips according to other embodiments of the present disclosure.

[0122] It should be noted that some steps of the above manufacturing method can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific operation sequence shown in the figure.

[0123] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0124] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A light-emitting diode chip, wherein: The light emitting diode chip comprises: substrate; and At least two light-emitting structures are provided on the substrate, wherein the orthographic projections of the at least two light-emitting structures on the substrate are spaced apart, and the at least two light-emitting structures are sequentially connected in series. Wherein, at least one of the light-emitting structures comprises: a first semiconductor layer disposed on the substrate; a light emitting layer disposed on a side of the first semiconductor layer away from the substrate; a second semiconductor layer disposed on a side of the light-emitting layer away from the substrate; a first insulating layer disposed on a side of the second semiconductor layer away from the substrate; a current spreading layer disposed on a side of the first insulating layer away from the substrate; and A first electrode is provided on a side of the current spreading layer away from the substrate, wherein at least one of the light emitting structures comprises a first via hole in the first insulating layer, the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; and The orthographic projection of the first via on the substrate falls within the orthographic projection of the current spreading layer on the substrate, and the orthographic projection of the current spreading layer on the substrate falls within the orthographic projection of the second semiconductor layer on the substrate.

2. The light-emitting diode chip according to claim 1, wherein: In at least one of the light-emitting structures, a plurality of first via holes are provided in the first insulating layer, and the current spreading layer is electrically connected to the second semiconductor layer through the plurality of first via holes; as well as The orthographic projections of the plurality of first vias on the substrate all fall within the orthographic projection of the current spreading layer on the substrate.

3. The light-emitting diode chip according to claim 1 or 2, wherein: The light emitting diode chip further includes a bridge conductive portion provided on a side of the current spreading layer away from the substrate, the bridge conductive portion including a first portion and a second portion; as well as The at least two light-emitting structures include a first light-emitting structure and a second light-emitting structure that are adjacent to each other, the first light-emitting structure and the second light-emitting structure being electrically connected via the bridging conductive portion, the first portion of the bridging conductive portion being electrically connected to the second semiconductor layer of the first light-emitting structure, and the second portion of the bridging conductive portion being electrically connected to the first semiconductor layer of the second light-emitting structure, wherein an orthographic projection of the first portion of the bridging conductive portion on the substrate falls within an orthographic projection of the second semiconductor layer of the first light-emitting structure on the substrate, and an orthographic projection of the second portion of the bridging conductive portion on the substrate falls within an orthographic projection of the first semiconductor layer of the second light-emitting structure on the substrate.

4. The light-emitting diode chip according to claim 3, wherein: An orthographic projection of a first portion of the bridging conductive portion on the substrate at least partially overlaps with an orthographic projection of a current spreading layer of the first light emitting structure on the substrate.

5. The light-emitting diode chip according to claim 1, wherein: An orthographic projection of the first via on the substrate at least partially overlaps with an orthographic projection of the first portion of the bridge conductive portion on the substrate. The light-emitting diode chip according to claim 2 , wherein: An orthographic projection of at least one first via hole among the plurality of first via holes on the substrate at least partially overlaps with an orthographic projection of the first portion of the bridge conductive portion on the substrate.

7. The light-emitting diode chip according to claim 1, wherein: An orthographic projection of the first via on the substrate does not overlap with an orthographic projection of the first portion of the bridging conductive portion on the substrate.

8. The light-emitting diode chip according to claim 7, wherein: The orthographic projection of the first portion of the bridging conductive portion on the substrate is spaced apart from the orthographic projection of the first via on the substrate, and the orthographic projection of a partial area of ​​the first portion of the bridging conductive portion on the substrate surrounds the orthographic projection of the first via on the substrate.

9. The light-emitting diode chip according to claim 5, 7 or 8, wherein: The light-emitting diode chip further includes a first reflective layer located between the first insulating layer and the current spreading layer, wherein the light reflectivity of the first reflective layer is higher than the light reflectivity of the bridging conductive portion, and the orthographic projection of the first via on the substrate falls within the orthographic projection of the first reflective layer on the substrate.

10. The light emitting diode chip according to any one of claims 1, 2 and 4-8, wherein: The light emitting diode chip further includes a second reflective layer located on a side of the current spreading layer away from the substrate, and the second reflective layer includes a Bragg reflector. The light-emitting diode chip according to claim 10 , wherein: The light-emitting diode chip further includes a second via hole in the second reflective layer, the first electrode is electrically connected to the current spreading layer through the second via hole, and the orthographic projection of the first via hole on the substrate falls within the orthographic projection of the second via hole on the substrate.

12. The light-emitting diode chip according to claim 2, wherein: In at least one of the light-emitting structures, the orthographic projections of the plurality of first via holes on the substrate are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

13. The light-emitting diode chip according to claim 1, wherein: In at least one of the light-emitting structures, a ratio of an area of ​​an orthographic projection of the current spreading layer on the substrate to an area of ​​an orthographic projection of the second semiconductor layer on the substrate is less than 0.

1.

14. The light-emitting diode chip according to claim 2, wherein: In at least one of the light-emitting structures, a ratio of an area of ​​an orthographic projection of each of the plurality of first via holes on the substrate to an area of ​​an orthographic projection of the second semiconductor layer on the substrate is less than 0.1; and / or, In at least one of the light-emitting structures, an orthographic projection of the current spreading layer on the substrate substantially coincides with an orthographic projection of the second semiconductor layer on the substrate.

15. The light-emitting diode chip according to claim 8, wherein The orthographic projection of the first via hole on the substrate is circular, and the orthographic projection of a partial area of ​​the first portion of the bridging conductive portion on the substrate is annular, which is substantially concentric with the circular first via hole.

16. The light-emitting diode chip according to claim 9, wherein: An orthographic projection of the first reflective layer on the substrate at least partially overlaps with an orthographic projection of the first portion of the bridge conductive portion on the substrate.

17. The light-emitting diode chip according to claim 11, wherein: The light-emitting diode chip also includes a second electrode and a third via located in the second reflective layer. The second electrode is electrically connected to the first semiconductor layer of the light-emitting structure through the third via. The orthographic projection of the third via on the substrate is spaced apart from the orthographic projection of the first via on the substrate.

18. The light-emitting diode chip according to claim 1, wherein: The light-emitting diode chip includes three or more light-emitting structures, each of the light-emitting structures includes a first via hole located in the first insulating layer, the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; and , the orthographic projection of the first via on the substrate falls within the orthographic projection of the current spreading layer on the substrate, and the orthographic projection of the current spreading layer on the substrate falls within the orthographic projection of the second semiconductor layer on the substrate.

19. A display device comprising the light emitting diode chip according to any one of claims 1 to 18.

20. A method for preparing a light emitting diode chip, wherein: The preparation method comprises: providing a substrate; and At least two light-emitting structures are formed on the substrate, the at least two light-emitting structures are spaced apart, and the at least two light-emitting structures are sequentially connected in series. Wherein, forming at least two light-emitting structures on the substrate includes: forming a first semiconductor layer on the substrate; forming a light-emitting layer on a side of the first semiconductor layer away from the substrate; forming a second semiconductor layer on a side of the light emitting layer away from the substrate; forming a first insulating layer on a side of the second semiconductor layer away from the substrate; forming a first via hole in the first insulating layer by a dry etching process; forming a current spreading layer on a side of the first insulating layer away from the substrate; and forming a first electrode on a side of the current spreading layer away from the substrate; wherein the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; and The orthographic projection of the first via on the substrate falls within the orthographic projection of the current spreading layer on the substrate, and the orthographic projection of the current spreading layer on the substrate falls within the orthographic projection of the second semiconductor layer on the substrate.

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