Wiring board, method for manufacturing wiring board, and electronic device

Abstract

The invention provides a wiring substrate, a method of manufacturing the same, and an electronic device. The wiring substrate includes: a substrate; and a plurality of pad groups located on the substrate, wherein each pad group comprises at least two pads. Two adjacent bonding pads in the first direction or the second direction in the at least two bonding pads are arranged at intervals, and the first direction intersects with the second direction. Each bonding pad comprises a plurality of edges, the plurality of edges comprise at least one selected edge and at least one non-selected edge, any bonding pad is adjacent to the other bonding pad along the first direction or the second direction, the selected edge of any bonding pad is the edge facing the other adjacent bonding pad in the plurality of edges, and the non-selected edge of any bonding pad is the edge facing the other adjacent bonding pad. The distance between the selected edge, facing the other adjacent bonding pad, of any bonding pad and the selected edge, facing the any bonding pad, of the other adjacent bonding pad is larger than or equal to 30 micrometers and smaller than 100 micrometers.

Description

Wiring substrate, manufacturing method thereof, and electronic device Technical Field

[0001] The present disclosure relates to the field of display technology, and more particularly to a wiring substrate, an electronic device including the wiring substrate, and a method for manufacturing the wiring substrate. Background Art

[0002] Display devices are generally divided into two categories: liquid crystal display devices and organic light-emitting diode display devices. Liquid crystal display devices are widely used due to their advantages such as lightness, good shock resistance, wide viewing angle, and high contrast. Liquid crystal display devices generally include a display panel and a backlight source. The backlight source is generally arranged on the non-display side of the display panel to provide light for the display operation of the display panel. Characteristics such as contrast, brightness uniformity, and stability of liquid crystal display devices are related to the structure and performance of the backlight source. In recent years, sub-millimeter light-emitting diodes (Mini-LEDs) have received widespread attention due to their excellent performance and are increasingly being used in backlight sources.

[0003] Summary of the Invention

[0004] According to one aspect of the present disclosure, a wiring substrate is provided, comprising: a substrate; a plurality of pad groups located on the substrate, each of the plurality of pad groups comprising at least two pads. Two pads adjacent to each other in a first direction or a second direction among the at least two pads are spaced apart, and the first direction intersects with the second direction. Each of the at least two pads comprises a plurality of edges, the plurality of edges comprising at least one selected edge and at least one non-selected edge, any one of the pads is adjacent to another pad along the first direction or the second direction, the selected edge of any one of the pads is an edge facing the adjacent other pad among the plurality of edges, and the spacing between the selected edge of any one of the pads facing the adjacent other pad and the selected edge of the adjacent other pad facing the any one of the pads is greater than or equal to 30 um and less than 100 um.

[0005] In some embodiments, the wiring substrate further comprises an insulating layer located on a side of the plurality of pad groups away from the substrate, wherein the insulating layer comprises a plurality of first openings, and any one of the plurality of first openings corresponds to one of the plurality of pad groups.

[0006] In some embodiments, any one of the multiple pad groups includes two pads spaced apart along the first direction or the second direction, and the positive projection of the non-selected side of each of the two pads on the substrate coincides with a partial outline of the positive projection of a corresponding first opening on the substrate.

[0007] In some embodiments, any one of the multiple pad groups includes four pads arranged in an array and spaced apart along the first direction and the second direction, and the non-selected edges of each of the four pads include at least one first non-selected edge, and the orthographic projection of the first non-selected edge on the substrate coincides with a partial outline of the orthographic projection of a corresponding first opening on the substrate.

[0008] In some embodiments, the non-selected side of each pad further includes a second non-selected side, and a minimum distance between an orthographic projection of the second non-selected side on the substrate and an outline of an orthographic projection of the corresponding first opening on the substrate is 30-50 um.

[0009] In some embodiments, any one of the multiple pad groups includes a plurality of pads spaced apart along the first direction or the second direction, the geometric centers of the plurality of pads are connected in sequence in a clockwise direction to form a convex polygon, and the non-selected edges of each of the multiple pads include at least one first non-selected edge, the orthographic projection of the first non-selected edge on the substrate coincides with a partial outline of the orthographic projection of a corresponding first opening on the substrate.

[0010] In some embodiments, the multiple pads include a first type of pads and a second type of pads, the selected edges of the first type of pads include a first selected edge and a second selected edge, the extension direction of the first selected edge and the extension direction of the second selected edge have an angle, the selected edges of the second type of pads include a third selected edge and a fourth selected edge, the extension direction of the third selected edge is parallel to the extension direction of the fourth selected edge.

[0011] In some embodiments, the first type of pad is spaced apart from two second type of pads in the first direction and the second direction respectively, and any pad adjacent to the second type of pad is spaced apart from the second type of pad along the first direction or the second direction.

[0012] In some embodiments, the non-selected side of each first type pad further includes a second non-selected side, and the minimum distance between the orthographic projection of the second non-selected side on the substrate and the outline of the orthographic projection of the corresponding first opening on the substrate is 30-50 um.

[0013] In some embodiments, the non-selected edge of each second-type pad also includes a third non-selected edge, the second-type pad is spaced apart from a first-type pad along the first direction, the spacing between the third non-selected edge of the second-type pad and the second selected edge of the first-type pad in the second direction is greater than 0 and less than or equal to 30um, and the second selected edge of the first-type pad is the selected edge of the second-type pad facing the first-type pad and spaced apart along the second direction.

[0014] In some embodiments, the non-selected edge of each second-type pad also includes a third non-selected edge, the second-type pad is spaced apart from a first-type pad along the second direction, the spacing between the third non-selected edge of the second-type pad and the first selected edge of the first-type pad in the first direction is greater than 0 and less than or equal to 30um, and the first selected edge of the first-type pad is the selected edge of the second-type pad facing the first-type pad and spaced apart along the first direction.

[0015] In some embodiments, no other film layer is disposed between the layer where the insulating layer is located and the layer where the plurality of pad groups are located.

[0016] According to another aspect of the present disclosure, an electronic device is provided, comprising the wiring substrate described in any of the foregoing embodiments and a plurality of electronic components. The plurality of electronic components are located on a side of the plurality of pad groups away from the substrate, any one of the plurality of electronic components corresponds to one of the plurality of pad groups, each of the plurality of electronic components includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and each pin of the electronic component is connected to a corresponding pad.

[0017] In some embodiments, a ratio of an area of ​​a surface of a pin of each electronic device facing the corresponding one of the pads to an area of ​​a surface of the corresponding one of the pads facing the pin is 0.4-1.0.

[0018] In some embodiments, the first orthographic projection of the pin of each electronic device on the substrate at least partially overlaps with the second orthographic projection of the corresponding pad on the substrate, and the area where the first orthographic projection overlaps with the second orthographic projection constitutes an overlapping area, and the ratio of the area of ​​the overlapping area to the area of ​​the second orthographic projection is greater than or equal to 39%.

[0019] In some embodiments, the insulating layer is located between the multiple pad groups and the multiple electronic devices, any one of the multiple electronic devices corresponds to a first opening among the multiple first openings of the insulating layer, the third orthographic projection of each electronic device on the substrate falls within the fourth orthographic projection of the corresponding first opening on the substrate, and the spacing between the outline of the third orthographic projection and the outline of the fourth orthographic projection is 20 to 40 μm.

[0020] According to another aspect of the present disclosure, a method for manufacturing an electronic device is provided, comprising: providing a substrate; forming a plurality of pad groups on the substrate, each of the plurality of pad groups including at least two pads; and securing a plurality of electronic devices to a side of the plurality of pad groups away from the substrate. Any one of the plurality of electronic devices corresponds to one of the plurality of pad groups, each of the plurality of electronic devices includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and each pin of the electronic device is connected to a corresponding pad.

[0021] In some embodiments, the step of forming a plurality of pad groups on the substrate includes: applying a conductive layer on the substrate, and patterning the conductive layer to form a plurality of signal lines; forming an insulating layer including a plurality of first openings on a side of the plurality of signal lines away from the substrate, and using the first openings to expose a portion of each of the plurality of signal lines to form the pads.

[0022] In some embodiments, the step of fixing multiple electronic devices on a side of the multiple pad groups away from the substrate includes: aligning each pin of the electronic device with the corresponding one of the pads so that the first orthographic projection of each pin of the electronic device on the substrate does not exceed the second orthographic projection of the corresponding one of the pads on the substrate; and soldering each pin of the electronic device to the corresponding one of the pads using solder.

[0023] In some embodiments, each pad group includes a plurality of pads spaced apart along the first direction or the second direction, the plurality of pads including a first type of pad, the first type of pad including a first selected side and a second selected side and a first non-selected side and a second non-selected side, the extension direction of the first selected side and the extension direction of the second selected side having an included angle, and the extension direction of the first non-selected side and the extension direction of the second non-selected side having an included angle. The step of aligning each pin of the electronic device with the corresponding pad includes: aligning the first selected side and the second selected side of each first type of pad with the first side and the second side of the corresponding pin in a direction perpendicular to the substrate, respectively, and aligning the orthographic projection of the first non-selected side and the second non-selected side of each first type of pad on the substrate with the orthographic projection of the third side and the fourth side of the corresponding pin on the substrate by 20 to 50 μm, respectively.

[0024] In some embodiments, the plurality of pads further include a second type of pad, the second type of pad including a third selected edge and a fourth selected edge and a first non-selected edge and a third non-selected edge, the third selected edge extending in a direction parallel to the fourth selected edge, and the first non-selected edge extending in a direction parallel to the third non-selected edge. The step of aligning each pin of the electronic device with the corresponding pad further includes: aligning the third selected edge and the fourth selected edge of each second type of pad with the fifth side edge and the sixth side edge of the corresponding pin in a direction perpendicular to the substrate, respectively, so that the orthographic projection of the third non-selected edge of each second type of pad on the substrate is 0 to 30 μm away from the orthographic projection of the seventh side edge of the corresponding pin on the substrate, and so that the orthographic projection of the first non-selected edge of each second type of pad on the substrate is 20 to 50 μm away from the orthographic projection of the eighth side edge of the corresponding pin on the substrate, and the third non-selected edge is closer to the center of the pad group than the first non-selected edge.

[0025] In some embodiments, each pad group includes a central area and a plurality of corner areas surrounding the central area, each of the plurality of corner areas is arranged with at least one first type pad and at least one second type pad. Before aligning each pin of the electronic device with the corresponding one of the pads, the method further includes: placing a mesh on a side of the plurality of pad groups away from the substrate on which they are located, the mesh including a plurality of second openings, any one of the plurality of second openings corresponding to one of the plurality of corner areas of the plurality of pad groups, the orthographic projection of each of the plurality of second openings on the substrate partially overlapping with the orthographic projection of at least one first type pad and at least one second type pad in the corresponding one of the corner areas on the substrate; printing flux on the surfaces of the first type pads and the second type pads away from the substrate through the second openings of the mesh; and removing the mesh. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] FIG1 shows a schematic planar structural diagram of a light-emitting substrate in the related art;

[0028] FIG2 is a schematic plan view showing a partial structure of a wiring substrate according to an embodiment of the present disclosure;

[0029] FIG3 shows another plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure;

[0030] FIG4 shows another schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure;

[0031] FIG5 shows another schematic plan view of a partial structure of a wiring substrate according to an embodiment of the present disclosure;

[0032] FIG6 shows the relative position relationship between the pad and the pin of the electronic device after welding in the related art;

[0033] FIG7 shows a block diagram of an electronic device according to an embodiment of the present disclosure;

[0034] FIG8 is a schematic cross-sectional view of a partial structure of an electronic device according to an embodiment of the present disclosure;

[0035] FIG9 is a schematic plan view showing a partial structure of an electronic device according to an embodiment of the present disclosure;

[0036] FIG10 shows another schematic plan view of a partial structure of an electronic device according to an embodiment of the present disclosure;

[0037] FIG11 shows the relative positional relationship between the pad and the pin of the electronic device after welding according to an embodiment of the present disclosure;

[0038] FIG12 shows another schematic plan view of a partial structure of an electronic device according to an embodiment of the present disclosure;

[0039] FIG13 is a schematic cross-sectional view of a partial structure of an electronic device according to an embodiment of the present disclosure;

[0040] FIG14 shows a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0041] FIG15 is a schematic structural diagram of a stencil used in a manufacturing process of the related art;

[0042] FIG16 shows another structural schematic diagram of a stencil used in a manufacturing process of the related art;

[0043] FIG17 shows a schematic structural diagram of a stencil used in a manufacturing process according to an embodiment of the present disclosure; and

[0044] FIG. 18 shows another schematic structural diagram of a stencil used in a manufacturing process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0046] FIG1 shows a light-emitting substrate 10 according to related art. This substrate 10 includes signal lines 16 and 17, a first insulating layer 14 positioned over the signal lines 16 and 17, a second insulating layer 15 positioned on the side of the first insulating layer 14 facing away from the signal lines 16 and 17, and light-emitting devices 13 positioned on the side of the second insulating layer 15 facing away from the first insulating layer 14. Each light-emitting device 13 includes two pins 12 facing the second insulating layer 15. The first insulating layer 14 includes an opening 141 at a location corresponding to each pin 12. The portion of the signal line 16 exposed by the opening 141 constitutes a solder pad 11-P, and the portion of the signal line 17 exposed by the opening 141 constitutes a solder pad 11-N. Except for solder pads 11-P and 11-N, the remainder of the signal lines 16 and 17 is covered by the first insulating layer 14, and the area between the two solder pads is also covered by the first insulating layer 14. The solder pad 11-P is connected to the corresponding pin 12 via solder, and the solder pad 11-N is connected to the corresponding pin 12 via solder. To increase the soldering area between the pads and pins 12, the boundaries of each of pads 11-P and 11-N are expanded relative to the boundaries of pins 12, so that the orthographic projection of each pin 12 on the substrate falls within the orthographic projection of the corresponding pad on the substrate. This outward expansion of the pad edges reduces the spacing L between adjacent pads. However, because a first insulating layer 14 is present between adjacent pads, this prevents pins 12 connected to pad 11-P from contacting adjacent pad 11-N, potentially causing a short circuit. Specifically, a pin 12 soldered to pad 11-P will not contact pad 11-N, and similarly, a pin 12 soldered to pad 11-N will not contact pad 11-P. Second insulating layer 15 includes an opening 151 at a location corresponding to each light-emitting device 13. The orthographic projections of both pads 11-P and 11-N, as well as the orthographic projections of light-emitting devices 13 on the substrate, fall within the orthographic projections of opening 151 on the substrate.

[0047] The first insulating layer 14 can be a single-layer structure or a multi-layer stacked structure. For example, the first insulating layer 14 can be a stacked structure of a passivation layer and an OC layer (Over Coating). The material of the passivation layer is an inorganic material, such as SiN, SiO, SiON, which can effectively block the invasion of water and oxygen into the light-emitting substrate 10; the material of the OC layer is usually an organic resin, which has good leveling properties and can be used as a flat layer. The patterning process accuracy of the first insulating layer 14 is relatively high, and its accuracy is usually on the order of several microns. The material of the second insulating layer 15 can be white ink, which has a relatively high reflectivity (for example, a reflectivity greater than 92%), and is therefore usually used as a reflective layer. Compared with the first insulating layer 14, the patterning process accuracy of the second insulating layer 15 is slightly lower, and its accuracy is usually above the order of hundreds of microns.

[0048] The inventors of the present application discovered that the light-emitting substrate 10 includes at least two insulating layers, which makes the light-emitting substrate 10 thicker, which is not conducive to the thinness of the backplane, and makes the process complicated and the production cost increased. In order to reduce the thickness of the backplane and reduce the production cost, the second insulating layer 15 can be directly used as both an insulating layer and a reflective layer; however, the inventors of the present application discovered that, due to the limitations of the material of the second insulating layer 15 and the patterning process accuracy, the area between two adjacent pads is no longer separated by an insulating layer, but is directly exposed by the opening 151 of the second insulating layer 15. If the design of uniformly expanding the boundaries of the pads in the related art is continued, when the spacing L between the two oppositely arranged sides of the two adjacent pads is too small, due to the lack of the obstruction of the first insulating layer 14, it is easy for the pin 12 soldered to one of the pads 11-P and 11-N to come into contact with the other of the pads 11-P and 11-N, thereby causing a short circuit.

[0049] Therefore, a new pad design needs to be proposed to avoid the short circuit problem.

[0050] An embodiment of the present disclosure provides a wiring substrate 100. The structure of the wiring substrate 100 can be described with reference to FIG2 . The wiring substrate 100 includes: a substrate (not shown); and a plurality of pad groups 102 located on the substrate, each pad group 102 including at least two pads. Two adjacent pads in a first direction D1 or a second direction D2 of the at least two pads are spaced apart from each other, with the first direction D1 intersecting the second direction D2. For example, the first direction D1 and the second direction D2 may be perpendicular to each other. Each pad includes multiple edges, including at least one selected edge 1021A and at least one non-selected edge 1021B. Any pad is adjacent to another pad along the first direction D1 or the second direction D2. The selected edge 1021A of any pad is the edge facing the adjacent pad among the multiple edges. The spacing T between the selected edge 1021A of any pad facing the adjacent pad and the selected edge 1021A of the adjacent pad facing the any pad is greater than or equal to 30 μm and less than 100 μm. For example, T can be 30 μm, 50 μm, 65 μm, 90 μm, 99 μm, etc. This spacing T is smaller than the value in the related art, in which the spacing between two oppositely disposed edges of two adjacent pads is greater than 100 μm.

[0051] It's important to note that during the manufacturing process, solder is applied to the pad surface to facilitate soldering to the pins. The lower limit of the spacing T is related to the accuracy of the solder application. For example, if the solder application accuracy is ±30 microns, the lower limit of T is 30 microns; if the solder application accuracy is ±50 microns, the lower limit of T is 50 microns. The solder application accuracy is also related to the size of the wiring substrate. For example, the solder application accuracy for a 32-inch wiring substrate can reach ±50 microns, while the solder application accuracy for a 16-inch wiring substrate can reach ±30 microns.

[0052] The following describes pad groups including different numbers of pads using several different examples.

[0053] FIG2 shows an example of a pad group 102 of a wiring substrate 100, in which each pad group 102 includes two pads 1021-P and 1021-N, which are respectively connected to two pins of a light-emitting element. Specifically, the two pads are spaced apart from each other along a first direction D1. Each of the two pads 1021-P and 1021-N includes four edges, which are a selected edge 1021A and non-selected edges 1021B, 1021C, and 1021D, respectively, that is, each pad includes one selected edge and three non-selected edges. As defined above, the "selected edge" needs to meet the following two conditions: first, the selected edge faces another adjacent pad, and second, the spacing T between the selected edge and the selected edge of another adjacent pad needs to be greater than or equal to 30 μm and less than 100 μm. Accordingly, if no other pad exists within 100 μm of a certain edge of the pad in the first direction D1 or the second direction D2, then that edge is a non-selected edge of the pad. In the example of FIG2 , edge 1021A of pad 1021-P is a selected edge because edge 1021A faces adjacent pad 1021-N, and a spacing T between edge 1021A and edge 1021A of adjacent pad 1021-N is greater than or equal to 30 μm and less than 100 μm. Edges 1021B, 1021C, and 1021D of pad 1021-P are non-selected edges because no other pad exists within 100 μm of edge 1021C in first direction D1 (edge ​​1021A of pad 1021-N is greater than 100 μm from non-selected edge 1021C of pad 1021-P), and no other pad exists within 100 μm of edges 1021B and 1021D in second direction D2. Similarly, edge 1021A of pad 1021-N is a selected edge, and edges 1021B, 1021C, and 1021D of pad 1021-N are non-selected edges. The spacing T between the selected side 1021A of the pad 1021-P and the selected side 1021A of the pad 1021-N is greater than or equal to 30um and less than 100um. For example, the spacing T can be 30um, 50um, 65um, 90um, 99um, etc.

[0054] It should be noted that although FIG2 shows that the four sides of each pad are all straight line segments, this is only a schematic example. In an alternative example, the four sides of each pad may also be composed of a plurality of broken line segments or curved line segments connected end to end. In another alternative example, some of the four sides of each pad may be straight line segments, and the remaining sides may be composed of a plurality of broken line segments or curved line segments connected end to end. It is understood that, when a certain side is composed of a plurality of broken line segments or curved line segments connected end to end, the angle between two adjacent broken line segments is not greater than 30°, and the angle between the tangent directions of two adjacent curved line segments is not greater than 30°; when a certain side is composed of a plurality of broken line segments or curved line segments connected end to end, the extension direction of the side is the direction of the line connecting the two endpoints of the side. It should be noted that, for the sake of simplicity, FIG2 only shows one pad group 102, and omits the other multiple pad groups 102 that are not shown.

[0055] As shown in FIG2 , the wiring substrate 100 further includes an insulating layer 105 located on a side of the pad group 102 away from the substrate. The insulating layer 105 includes a plurality of first openings 1051 , and any one of the plurality of first openings 1051 corresponds to one of the plurality of pad groups 102 . The material of the insulating layer 105 can be, for example, white ink. White ink has a high reflectivity, for example, a reflectivity greater than 92%, and thus has a reflective effect on the light emitted by the light-emitting element. No other intermediate film layer is provided between the layer where the insulating layer 105 is located and the layer where the plurality of pad groups 102 are located, that is, the insulating layer 105 is in direct contact with the signal lines where the respective pads are located.

[0056] Wiring substrate 100 also includes multiple signal lines located on the same layer as multiple pad groups 102. The portion of each signal line exposed by first opening 1051 constitutes pad 1021-P or 1021-N, as described above. That is, each pad is part of a corresponding signal line. FIG2 shows two signal lines 106 and 107. The portion of signal line 106 exposed by first opening 1051 serves as pad 1021-P, while the portion of signal line 107 exposed by first opening 1051 serves as pad 1021-N. Specifically, the portion of signal line 106 overlapping first opening 1051 defines the size and positions of the four sides of pad 1021-P, while the portion of signal line 107 overlapping first opening 1051 defines the size and positions of the four sides of pad 1021-N. As shown in FIG2 , the orthographic projection of each of the non-selected sides 1021B, 1021C, and 1021D of each pad onto the substrate partially overlaps with the orthographic projection of first opening 1051 onto the substrate. Signal line 106 also includes other portions covered by insulating layer 105, primarily used for transmitting electrical signals. Signal line 107 also includes other portions covered by insulating layer 105, primarily used for transmitting electrical signals. The orthographic projections of the remaining portions of signal line 106 excluding pad 1021-P and the remaining portions of signal line 107 excluding pad 1021-N on the substrate fall within the orthographic projection of the main body 1052 of insulating layer 105 on the substrate. "Main body 1052" here refers to the portion of insulating layer 105 excluding first opening 1051.

[0057] 1 , in the related art, the orthographic projection of the side 161 of the signal line 16 on the substrate and the partial contour of the orthographic projection of the opening 151 of the second insulating layer 15 on the substrate have a spacing D, and the orthographic projection of the side 161 of the signal line 16 on the substrate falls within the orthographic projection of the first insulating layer 14 on the substrate; the orthographic projections of the sides 171 and 172 of the signal line 17 on the substrate and the partial contour of the orthographic projection of the opening 151 of the second insulating layer 15 on the substrate both have a spacing D, and the orthographic projections of the sides 171 and 172 of the signal line 17 on the substrate fall within the orthographic projection of the first insulating layer 14 on the substrate. That is to say, although the orthographic projection of the side 161 of the signal line 16 on the substrate falls within the orthographic projection of the opening 151 on the substrate, the side 161 can be covered by the first insulating layer 14 located between the signal line 16 and the second insulating layer 15; similarly, although the orthographic projection of the side edges 171 and 172 of the signal line 17 on the substrate falls within the orthographic projection of the opening 151 on the substrate, the side edges 171 and 172 can be covered by the first insulating layer 14 located between the signal line 17 and the second insulating layer 15, so the first insulating layer 14 can prevent water, oxygen, etc. in the environment from invading the light-emitting substrate 10 along the sides of the signal lines 16 and 17.

[0058] However, if it is desired to achieve a thinner and lighter wiring substrate 100 and reduce production costs, the first insulating layer 14 is not provided. If the design scheme for the relative positional relationship between signal lines 16 and 17 and second insulating layer 15 in the related art is continued to be used, the side edges 161 of signal line 16 and the side edges 171 and 172 of signal line 17 will be directly exposed by the opening 151 of second insulating layer 15, allowing water and oxygen in the environment to intrude into the interior of the wiring substrate along the sides of the signal lines, corroding the signal lines and thus affecting the electrical performance of the signal lines. To at least address this technical problem, the inventors of this application have improved the relative positional relationship between the first opening 1051 of insulating layer 105 and signal lines 106 and 107. Specifically, as shown in FIG2 , the signal line 106 is, for example, a stripe-shaped structure including four sides, namely sides 1061, 1062, 1063, and 1064. At least the orthographic projections of the sides 1061, 1062, and 1063 on the substrate fall within the orthographic projection of the main portion 1052 of the insulating layer 105 on the substrate, i.e., the sides 1061, 1062, and 1063 are covered by the main portion 1052 of the insulating layer 105. Similarly, the signal line 107 is, for example, a stripe-shaped structure including four sides, namely sides 1071, 1072, 1073, and 1074. At least the orthographic projections of the sides 1071, 1072, and 1073 on the substrate fall within the orthographic projection of the main portion 1052 of the insulating layer 105 on the substrate, i.e., the sides 1071, 1072, and 1073 are covered by the main portion 1052 of the insulating layer 105. By using the main body 1052 of the insulating layer 105 to cover most of the side edges of the signal lines 106 and 107, water, oxygen, etc. in the environment can be effectively prevented from invading the interior of the wiring substrate 100 along the edges of the signal lines 106 and 107, thereby preventing the signal lines 106 and 107 from being corroded.

[0059] In the example of FIG. 2 , the arrangement of pads 1021-P and 1021-N is optimized so that the spacing T between two opposing selected edges 1021A of two adjacent pads is greater than or equal to 30 μm and less than 100 μm. This spacing T provides reasonable space for subsequent soldering to the pins of an electronic device. Without an insulating layer covering the gap between the two adjacent pads, this spacing T ensures that the pins do not contact other pads that should not be electrically connected, thereby preventing short circuits. For example, a pin connected to pad 1021-P does not contact pad 1021-N, and a pin connected to pad 1021-N does not contact pad 1021-P. Furthermore, this spacing T maximizes the surface area of ​​pads 1021-P and 1021-N facing the pins of the electronic device, while preventing short circuits. This increases the soldering area between pads 1021-P and 1021-N and reduces or even prevents solder joint defects such as cold solder joints caused by insufficient contact area.

[0060] Figure 3 shows another example of a pad group 202 of a wiring substrate 100. In this example, each pad group 202 includes four pads arranged in an array along a first direction D1 and a second direction D2 and spaced apart. These four pads are configured to connect to four pins of a driver chip, respectively. Specifically, as shown in Figure 3, the wiring substrate 100 also includes signal lines such as a PWR line, a cascade output line, a cascade input line, a GND line, and a signal channel line. The portion of the PWR line exposed by the first opening 1051 of the insulating layer 105 serves as a pad Pwr. The pad Pwr is connected to the power pin pwr of the driver chip, thereby transmitting the power voltage signal on the PWR line to the power pin pwr via the pad Pwr. The portion of the GND line exposed by the first opening 1051 of the insulating layer 105 serves as a pad Gnd. The pad Gnd is connected to the ground pin gnd of the driver chip, thereby transmitting the ground signal on the GND line to the ground pin gnd via the pad Gnd. One end of the signal channel line exposed by the first opening 1051 of the insulating layer 105 serves as a pad Out, which is connected to the output pin out of the driver chip. The other end of the signal channel line is connected to the light-emitting element. The side of the signal channel line is also connected to a cascade output line, which is connected to the pad Di of the next-level pad group, and the pad Di of the next-level pad group is connected to the address pin di of the next-level driver chip. Therefore, the output pin out is a multiplexed pin. It outputs a drive signal in one time period and transmits the drive signal to the light-emitting element via the signal channel line to cause the light-emitting element to emit light. It outputs a relay signal in another time period and transmits the relay signal to the address pin di of the next-level driver chip cascaded with the driver chip via the signal channel line and the cascade output line to serve as the address signal of the next-level driver chip. The portion of the cascade input line exposed by the first opening 1051 of the insulating layer 105 is used as a pad Di, which is connected to the address pin di of the driver chip. The cascade input line is usually connected to the pad Out of the previous level to receive the relay signal transmitted by the output pin out of the previous level, and transmit the relay signal to the address pin di of the driver chip as the address signal of the driver chip.

[0061] As shown in FIG3 , each pad group 202 includes four pads Pwr, Out, Di, and Gnd. Each of the four pads includes four edges, namely selected edges 2021A and 2021B and non-selected edges 2021C and 2021D. That is, each pad includes two selected edges and two non-selected edges. Taking pad Pwr as an example, selected edge 2021A of pad Pwr faces adjacent pad Out in a first direction D1, and the spacing T between selected edge 2021A of pad Pwr and selected edge 2021A of pad Out is greater than or equal to 30 μm and less than 100 μm; selected edge 2021B of pad Pwr faces adjacent pad Di in a second direction D2, and the spacing T between selected edge 2021B of pad Pwr and selected edge 2021B of pad Di is greater than or equal to 30 μm and less than 100 μm. No other pad exists within 100 μm of a non-selected edge 2021C of the pad Pwr in the second direction D2. For example, the spacing between the selected edge 2021B of the pad Di adjacent to the pad Pwr in the second direction D2 and the non-selected edge 2021C of the pad Pwr is greater than 100 μm. Furthermore, no other pad exists within 100 μm of a non-selected edge 2021D of the pad Pwr in the first direction D1. For example, the spacing between the selected edge 2021A of another pad Out adjacent to the pad Pwr in the first direction D1 and the non-selected edge 2021D of the pad Pwr is greater than 100 μm. At least one of the non-selected edges 2021C and 2021D is a first non-selected edge, and the orthographic projection of the first non-selected edge on the substrate coincides with a partial outline of the orthographic projection of the first opening 1051 on the substrate. In the example of FIG3 , non-selected edge 2021C is a first non-selected edge, whose orthographic projection onto the substrate coincides with a portion of the orthographic projection of first opening 1051 onto the substrate. Non-selected edge 2021D is a second non-selected edge, and the minimum distance between the orthographic projection of this second non-selected edge and the portion of the orthographic projection of first opening 1051 onto the substrate is T2, where T2 is 30 to 50 μm, for example, 30 μm, 40 μm, 50 μm, etc. In an alternative embodiment, non-selected edges 2021C and 2021D can both be first non-selected edges, and their orthographic projections onto the substrate coincide with a portion of the orthographic projection of first opening 1051 onto the substrate. In this case, there is no second non-selected edge among the non-selected edges of the pad.

[0062] In the example of FIG3 , the arrangement of the pads is optimized so that the spacing T between two selected, oppositely positioned edges 2021A or 2021B of two adjacent pads is greater than or equal to 30 μm and less than 100 μm. This spacing T provides reasonable space for subsequent soldering to the pins of the electronic device. Without an insulating layer covering the gap between the two adjacent pads, this spacing T, on the one hand, ensures that the pins do not contact other pads that should not be electrically connected, thereby preventing a short circuit. On the other hand, this spacing T also maximizes the surface area of ​​the pads facing the pins of the electronic device while avoiding short circuits, thereby increasing the soldering area between the pads and the pins, reducing or even preventing solder joint defects such as cold solder joints caused by insufficient contact area.

[0063] FIG4 shows another example of a pad group 302 of a wiring substrate 100. In this example, each pad group 302 includes twelve pads spaced apart along a first direction D1 or a second direction D2. The twelve pads are configured to be connected to the twelve pins of the driver chip, respectively. That is, the pad group 302 is used for a driver chip having twelve pins. Specifically, as shown in FIG4 , the wiring substrate 100 further includes a power output line, a data output line, a power input line, a data input line, a cascade input line, a cascade output line, a GND line (including a first tooth portion and a second tooth portion), a first signal channel line, a second signal channel line, a third signal channel line, and a fourth signal channel line. The portion of the power input line exposed by the first opening 1051 of the insulating layer 105 is used as a pad Vcc1. The pad Vcc1 is connected to the power pin vcc1 of the driver chip. Thus, the power voltage signal on the power input line can be transmitted to the power pin vcc1 via the pad Vcc1. The portion of the power output line exposed by the first opening 1051 of the insulating layer 105 serves as pad Vcc2. Pad Vcc2 is connected to the power pin Vcc2 of the driver chip. The power output line is typically connected to pad Vcc1 of the pad group 302 of the next-level device. Pads Vcc1 and Vcc2 are connected via a connecting wire K1, so that the power pins Vcc1 and Vcc2 of the driver chip receive the same voltage signal, and power pin Vcc2 can output a power signal to the power pin Vcc1 of the next-level driver chip via the power output line. It should be understood that the terms "power output line" and "power input line" are relative terms, named based on the signal flow direction of the power lines connected to the two power pins Vcc1 and Vcc2 of the same driver chip. That is, the power input line connected to the power pin Vcc1 of the current-level driver chip is also the power output line connected to the power pin Vcc2 of the previous-level driver chip; that is, the power output line connected to the power pin Vcc2 of the current-level driver chip is also the power input line connected to the power pin Vcc1 of the next-level driver chip. The portion of the data input line exposed by first opening 1051 of insulating layer 105 serves as pad Data1. Pad Data1 is connected to data pin Data1 of the driver chip, allowing the drive signal on the data input line to be transmitted to data pin Data1 via pad Data1. The portion of the data output line exposed by first opening 1051 of insulating layer 105 serves as pad Data2. Pad Data2 is connected to data pin Data2 of the driver chip. The data output line is typically connected to pad Data1 of pad group 302 at the next level. Pads Data1 and Data2 are connected to each other via connection line K2, allowing data pins Data1 and Data2 of the driver chip to receive the same drive signal. Data pin Data2 can then transmit the drive signal to data pin Data1 of the next-level driver chip via the data output line.It should be understood that the terms "data output line" and "data input line" are relative terms, named based on the signal flow directions of the signal lines connected to the two data pins, data1 and data2, of the same driver chip. Specifically, a data input line connected to data pin data1 of the current driver chip is also a data output line connected to data pin data2 of the previous driver chip; and a data output line connected to data pin data2 of the current driver chip is also a data input line connected to data pin data1 of the next driver chip. The portion of the first tooth of the GND line exposed by the first opening 1051 of the insulating layer 105 serves as a solder pad Gnd1, which is connected to the ground pin gnd1 of the driver chip. The portion of the second tooth of the GND line exposed by the first opening 1051 of the insulating layer 105 serves as a solder pad Gnd2, which is connected to the ground pin gnd2 of the driver chip. The first and second teeth of the GND line are connected to the main body of the GND line, and the main body forms an angle with the extension direction of the first and / or second teeth. Thus, the signal transmitted by the GND line can be transmitted to the ground pins gnd1 and gnd2 respectively via the first tooth portion and the second tooth portion. The portion of the cascade input line exposed by the first opening 1051 of the insulating layer 105 is used as a pad Di_in. The pad Di_in is connected to the address pin di_in of the driver chip. The cascade input line is usually connected to the pad Di_out of the previous level to receive the relay signal transmitted by the relay pin di_out of the previous level and transmit the relay signal to the address pin di_in of the driver chip as the address signal of the driver chip. The portion of the cascade output line exposed by the first opening 1051 of the insulating layer 105 is used as a pad Di_out. The pad Di_out is connected to the relay pin di_out of the driver chip. The cascade output line is connected to the pad Di_in of the next-level pad group. The relay pin di_out transmits the relay signal to the address pin di_in of the next-level driver chip cascaded with the driver chip via the cascade output line as the address signal of the next-level driver chip. The ends of the first, second, third, and fourth signal channel lines exposed by the first opening 1051 of the insulating layer 105 serve as pads Out1, Out2, Out3, and Out4, respectively. The other ends of the first, second, third, and fourth signal channel lines are connected to four light-emitting elements, respectively. The pads Out1 to Out4 are connected to the output pins out1 to out4 of the driver chip, respectively. Thus, a single driver chip can simultaneously control the emission of at least four light-emitting elements.

[0064] It should be noted that although FIG4 shows the arrangement of twelve pads, this is only an example. The positions of the pads in pad group 302 need to be adapted to the positions of the pins of the driver chip. When the pin positions of the driver chip change, the positions of the pads in pad group 302 also need to be changed accordingly.

[0065] As shown in Figure 4, the geometric centers of the twelve pads are connected in a clockwise direction to form a convex polygon. The textbook defines a "convex polygon" as: if any one of the sides of a polygon is infinitely extended in both directions to form a straight line, and the other sides are on the same side of this straight line, then the polygon is called a convex polygon. The twelve pads include first-class pads and second-class pads. The number of first-class pads is 4, namely Out1, Out4, Di_out, Di_in. This application uses the figure mark 3021 to represent the first-class pads. The number of second-class pads is 8, namely Out2, Out3, Gnd1, Gnd2, Vcc1, Vcc2, Data1, Data2. This application uses the figure mark 3022 to represent the second-class pads. Two second-class pads 3022 are arranged between two adjacent first-class pads 3021.

[0066] Each first-class pad 3021 includes four sides, namely selected sides 3021A and 3021B and unselected sides 3021C and 3021D. That is, each first-class pad 3021 includes two selected sides and two unselected sides. Taking the first-class pad Out1 in FIG4 as an example, the selected side 3021A of the first-class pad Out1 faces the adjacent second-class pad Vcc2 in the first direction D1, and the spacing T between the selected side 3021A of the first-class pad Out1 and the selected side 3022A of the second-class pad Vcc2 is greater than or equal to 30 μm and less than 100 μm. The selected side 3021B of the first-class pad Out1 faces the adjacent second-class pad Out2 in the second direction D2, and the spacing T between the selected side 3021B of the first-class pad Out1 and the selected side 3022B of the second-class pad Out2 is greater than or equal to 30 μm and less than 100 μm. The selected edge 3021A of the first type pad Out1 can be called a first selected edge, and the selected edge 3021B of the first type pad Out1 can be called a second selected edge. The extension directions of the first selected edge and the second selected edge have a certain angle, for example, the angle can be any angle greater than 0 degree and less than 180 degrees. There is no other pad within 100um of the non-selected edge 3021C of the first-type pad Out1 in the second direction D2, for example, the spacing between the selected edge 3022B of the second-type pad Out2 adjacent to the first-type pad Out1 in the second direction D2 and the non-selected edge 3021C of the first-type pad Out1 is greater than 100um; and there is no other pad within 100um of the non-selected edge 3021D of the first-type pad Out1 in the first direction D1, for example, the spacing between the selected edge 3022A of the second-type pad Vcc2 adjacent to the first-type pad Out1 in the first direction D1 and the non-selected edge 3021D of the first-type pad Out1 is greater than 100um.

[0067] At least one of the non-selected edges 3021C and 3021D is a first non-selected edge, whose orthographic projection onto the substrate coincides with a portion of the orthographic projection of the first opening 1051 onto the substrate. In the example of FIG4 , non-selected edge 3021C is a first non-selected edge, whose orthographic projection onto the substrate coincides with a portion of the orthographic projection of the first opening 1051 onto the substrate. Non-selected edge 3021D is a second non-selected edge, whose orthographic projection onto the substrate coincides with a portion of the orthographic projection of the first opening 1051 onto the substrate. The minimum spacing between the orthographic projection of the second non-selected edge and the orthographic projection of the first opening 1051 onto the substrate is T2, where T2 is 30 to 50 μm, for example, 30 μm, 40 μm, or 50 μm. In an alternative embodiment, both non-selected edges 3021C and 3021D may be first non-selected edges, whose orthographic projections onto the substrate coincide with a portion of the orthographic projection of the first opening 1051 onto the substrate. In this case, no second non-selected edge exists among the non-selected edges of the first-type pad 3021.

[0068] The arrangement of the four sides of any one of the other three first-type pads is the same as the arrangement of the four sides of the first-type pad Out1 described above, and for the sake of brevity, it will not be repeated here.

[0069] The eight second-type pads 3022 can be further divided into two categories. One category includes second-type pads 3022 spaced apart from the first-type pads 3021 along the first direction D1, such as pads Vcc1, Vcc2, Data1, and Data2. The other category includes second-type pads 3022 spaced apart from the first-type pads 3021 along the second direction D2, such as pads Out2, Out3, Gnd1, and Gnd2. Each of the eight second-type pads 3022 includes four edges: selected edges 3022A and 3022B, and unselected edges 3022C and 3022D. That is, each second-type pad 3022 includes two selected edges and two unselected edges. Taking the second-type pad Out2 in FIG4 as an example, the selected edge 3022A of the second-type pad Out2 faces the adjacent second-type pad Out3 in the second direction D2, and the spacing T between the selected edge 3022A of the second-type pad Out2 and the selected edge 3022B of the second-type pad Out3 is greater than or equal to 30 μm and less than 100 μm. The selected edge 3022B of the second-type pad Out2 faces the adjacent first-type pad Out1 in the second direction D2, and the spacing T between the selected edge 3022B of the second-type pad Out2 and the selected edge 3021B of the first-type pad Out1 is greater than or equal to 30 μm and less than 100 μm. The selected edge 3022A of the second-type pad Out2 can be referred to as the third selected edge, and the selected edge 3022B of the second-type pad Out2 can be referred to as the fourth selected edge. The extension directions of the third selected edge and the fourth selected edge are parallel to each other. Although the second-type pad Out2 has an adjacent second-type pad Gnd1 in the first direction D1, since the spacing S1 between the edge 3022C of the second-type pad Out2 and the edge of the adjacent second-type pad Gnd1 in the first direction D1 is greater than 100 μm, the edge 3022C of the second-type pad Out2 is a non-selected edge. Similarly, the edge 3022D of the second-type pad Out2 is also a non-selected edge. Similarly, for the second-type pad 3022 spaced apart from the first-type pad 3021 in the first direction D1, the selected edges are 3022A and 3022B, and the non-selected edges are 3022C and 3022D. Taking the second-type pad Vcc2 as an example, although the second-type pad Vcc2 has an adjacent second-type pad Vcc1 in the second direction D2, since the spacing S2 between the edge 3022C of the second-type pad Vcc2 and the edge of the adjacent second-type pad Vcc1 in the second direction D2 is greater than 100 μm, the edge 3022C of the second-type pad Vcc2 is a non-selected edge. Similarly, the edge 3022D of the second-type pad Vcc2 is also a non-selected edge.

[0070] Non-selected edge 3022D is a first non-selected edge, the orthographic projection of which on the substrate partially overlaps with the outline of the orthographic projection of first opening 1051 on the substrate. Non-selected edge 3022C is a third non-selected edge. Regarding second-type pads 3022 spaced apart from first-type pads 3021 along first direction D1, taking second-type pad Vcc2 as an example, a spacing T1 between third non-selected edge 3022C of second-type pad Vcc2 and second selected edge 3021B of first-type pad Out1 in second direction D2 is greater than 0 and less than or equal to 30 μm. Spacing T1 can be, for example, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc. Second selected edge 3021B is the selected edge of first-type pad Out1 that faces second-type pad Out2. For the second-type pad 3022 that is spaced apart from the first-type pad 3021 along the second direction D2, taking the second-type pad Out2 as an example, the distance T1 between the third non-selected edge 3022C of the second-type pad Out2 and the first selected edge 3021A of the first-type pad Out1 in the first direction D1 is greater than 0 and less than or equal to 30um. The distance T1 can be, for example, 5um, 10um, 15um, 20um, 25um, 30um, etc. The first selected edge 3021A is the selected edge of the first-type pad Out1 facing the second-type pad Vcc2.

[0071] As shown in FIG4 , each first-type pad 3021 is adjacent to two second-type pads 3022, and the spacing T between the selected edge of each first-type pad 3021 and the selected edge of the adjacent second-type pad 3022 is greater than 30 μm and less than 100 μm. The first-type pad 3021 is spaced apart from the two second-type pads 3022 in the first direction D1 and the second direction D2, respectively. Furthermore, any pad adjacent to a second-type pad 3022 is spaced apart from the second-type pad 3022 along the first direction D1 or the second direction D2.

[0072] It should be noted that although Figures 2 to 4 illustrate individual pad groups 102, 202, and 302, at least two of these groups may be included simultaneously in the wiring substrate 100. In one embodiment, the wiring substrate 100 includes multiple pad groups, some of which are pad groups 102, each of which has two pads 1021-P and 1021-N configured to connect to two pins of a light-emitting element, respectively; and other of which are pad groups 302, each of which has twelve pads configured to connect to twelve pins of a driver chip, respectively. In an alternative embodiment, the wiring substrate 100 includes a plurality of pad groups, some of which are pad groups 102, and the two pads 1021-P and 1021-N of each pad group 102 are configured to be respectively connected to the two pins of the light-emitting element; and other of which are pad groups 202, and the four pads of each pad group 202 are configured to be respectively connected to the four pins of the driving chip.

[0073] In the example of Figure 4, the pad layout is optimized so that the spacing T between two selected, oppositely positioned edges of two adjacent pads is greater than or equal to 30 μm and less than 100 μm. This spacing T provides reasonable space for subsequent soldering to the pins of the electronic device. Without an insulating layer covering the gap between the two adjacent pads, this spacing T ensures that the pins do not contact other pads that should not be electrically connected, thereby preventing a short circuit. Furthermore, this spacing T maximizes the surface area of ​​the pads facing the pins of the electronic device while avoiding short circuits, thereby increasing the soldering area between the pads and the pins, reducing or even preventing solder joint defects such as cold solder joints caused by insufficient contact area.

[0074] It should be noted that for any of the pad groups 102, 202, and 302, except that the spacing T between adjacent pads must meet the above requirements, the shapes, sizes, and areas of the multiple pads in the same pad group can be the same or different. The area of ​​each pad in the same pad group ranges from 8000 to 14400 μm. 2 , and the ratio of the areas of any two pads in the same pad group is in the range of 0.556 to 1.800. In one embodiment, the shapes, sizes, and areas of the pads in the same pad group can be adapted to the structural features of the corresponding pins of the connected electronic device. For example, each pad and the pin of the connected electronic device have similar shapes.

[0075] Referring to FIG5 , wiring substrate 100 may further include solder flux 109 located on the surfaces of the multiple pads in each pad group facing away from the substrate. FIG5 illustrates solder flux group 302 as an example. The solder flux 109 is primarily distributed in four regions, each region including one first-type solder pad 3021 and two second-type solder pads 3022. Within each region, the solder flux 109 is arranged on the surfaces of the first-type and second-type solder pads 3021, 3022 facing away from the substrate, as well as in the areas between adjacent first-type and second-type solder pads 3021, 3022. As shown in FIG5 , the orthographic projection of the solder flux 109 on the substrate does not overlap with the orthographic projection of the center area of ​​pad group 302 on the substrate. In other words, the solder flux 109 is not located in the center area of ​​pad group 302, and the multiple solder pads are not located in the center area of ​​pad group 302. This arrangement of the solder flux 109 depends on the shape of the openings in the stencil used in the manufacturing process. The structure of the stencil will be described in detail later and will not be elaborated on here.

[0076] The flux 109 can help and promote the welding of the pads and the pins in the reflow process, and also has the function of protecting and preventing oxidation. Since there is no pad set in the central area of ​​the pad group 302, there is no need to form the flux 109 in the central area. In the related art, a stencil is used to set the flux, and the opening of the stencil corresponds to the area where the entire pad group 302 is located. In this way, the flux 109 is not only formed on the surface of all the pads of the pad group that are away from the substrate, but also formed in the central area of ​​the pad group where no pads are set. When the pad group includes a large number of pads, the flux will remain in the central area of ​​the pad group and cannot be effectively discharged. This will cause the flux remaining in the central area to corrode the pad group and / or the pins connected to the pads. In contrast, in an embodiment of the present disclosure, the flux 109 is only arranged on the surface of the multiple pads of the pad group 302 facing away from the substrate and in the area between the adjacent first-type pads 3021 and second-type pads 3022, and is not arranged in the central area of ​​the pad group 302. Therefore, the flux 109 can be prevented from remaining in the central area of ​​the pad group 302, thereby preventing the flux 109 from corroding the pad group 302 and / or the corresponding pins connected to the various pads of the pad group 302.

[0077] FIG6 shows the relative positional relationship between each pad 11 in a pad group of a light-emitting substrate 10 and each pin 12 of a corresponding electronic device after soldering in the related art, wherein the size and shape of each pad 11 are substantially the same. Line B1B1' and line B2B2' in FIG6 are perpendicular to each other, and the dotted cross line formed by them represents the reference coordinate axis. The intersection of line B1B1' and line B2B2' can be understood as the geometric center of a pad group. Each pad 11 in a pad group is arranged in an array with the reference coordinate axis as the reference, wherein line B1B1' is parallel to the second direction D2, and line B2B2' is parallel to the first direction D1; multiple pins 12 of the electronic device are connected one-to-one with each pad 11 in the above pad group, and lines C1C1' and C2C2' are connected one-to-one. The intersection of lines C1C1' and C2C2' is perpendicular to each other, and can be understood as the geometric center of the electronic device soldered to the pad group. The multiple pins 12 of the electronic device are arranged in an array with the coordinate axis formed by the dotted cross line formed by lines C1C1' and C2C2' as the reference axis. The angle between line C1C1' and line B1B1' (i.e., second direction D2) is acute, and the angle between line C2C2' and line B2B2' (i.e., first direction D1) is acute. In other words, each pin 12 is deflected relative to the corresponding pad 11. The soldering process includes steps such as aligning the pins with the pads and soldering the pins to the pads. Ideally, after alignment of pin 12 and pad 11, pin 12 will be precisely soldered to the predetermined position of pad 11, i.e., the intersection of line B1B1' and line B2B2' substantially coincides with the intersection of line C1C1' and line C2C2', and the angle between line C1C1' and line B1B1' (i.e., second direction D2) is almost zero, and the angle between line C2C2' and line B2B2' (i.e., first direction D1) is almost zero; that is, pin 12 will not experience undesirable rotation and / or offset relative to pad 11. However, due to factors such as alignment accuracy and process deviations, in the actual soldering process, pin 12 soldered to pad 11 will inevitably experience a certain degree of rotation and offset relative to pad 11, as shown in FIG6 . Therefore, in the actual process, a certain degree of rotation and offset of pin 12 soldered to pad 11 is allowed. However, if the rotation and offset angle of pin 12 is too large, the contact area between pin 12 and pad 11 will fall below the required lower limit, resulting in insufficient solder joint overlap area between pin 12 and pad 11, causing solder joint defects such as cold solder joints, thereby affecting soldering yield. Compared to a driver chip with four pins, a driver chip with twelve pins is larger in size. At the same rotation angle, the relative offset of the edge pins of the driver chip will be significantly increased, resulting in an even greater lack of solder joint overlap area, which in turn is more likely to cause solder joint defects such as cold solder joints.

[0078] As shown in FIG6 , the related art increases the contact area between the pin 12 and the pad 11 by extending the four sides of each pad 11 outward relative to the four sides of the pin 12. For example, the length of each side of the pad 11 is extended by 15 μm relative to the length of the corresponding side of the pin 12. The outward extension design of each side of the pad 11 reduces the spacing between two adjacent pads 11. In particular, for the pads 11 in the first row of FIG6 , a portion of the orthographic projection of the side of the pin 12 in the first row and second column near the pad 11 in the first row and first column on the substrate substantially overlaps with a portion of the orthographic projection of the side of the pad 11 in the first row and first column near the pin 12 in the first row and second column on the substrate. A portion of the orthographic projection of the side of the pin 12 in the first row and third column near the pad 11 in the first row and second column on the substrate substantially overlaps with a portion of the orthographic projection of the side of the pad 11 in the first row and second column on the substrate near the pin 12 in the first row and third column on the substrate. When the light-emitting substrate 10 is provided with a first insulating layer 14 and a second insulating layer 15 at the same time, the first insulating layer 14 can be arranged in the area between two adjacent solder pads 11 to insulate the pin 12 from the adjacent solder pads 11. Then, even if the distance between the two adjacent solder pads 11 becomes smaller due to the outward expansion of the solder pad 11, it will basically not cause a short circuit problem between the pin 12 and the adjacent solder pad 11.

[0079] With respect to the wiring substrate 100 provided in the embodiment of the present disclosure, as mentioned above, in order to reduce the thickness of the wiring substrate 100 and reduce production costs, only one insulating layer 105 having both reflective and insulating functions is provided, and the first opening 1051 of the insulating layer 105 exposes portions of multiple signal lines to form multiple pads, so that there is no insulating layer spacing between adjacent pads. If the design scheme of each side of the pad of the related art is continued to be used in this application, the smaller spacing between adjacent pads will cause the pin to contact the adjacent pad, thereby generating a short circuit. In addition, since the first opening 1051 of the insulating layer 105 exposes each pad, if the area of ​​the pad is significantly larger than the area of ​​the pin due to the expansion, it means that the pad will have a larger non-welding surface area and the non-welding surface will be exposed by the first opening 1051, which can easily cause water and oxygen in the environment to invade the exposed non-welding surface of the pad 11, thereby increasing the risk of corrosion.

[0080] In view of this, an embodiment of the present disclosure provides an electronic device. FIG7 shows a block diagram of an electronic device 200, and FIG8 shows a cross-sectional schematic diagram of a partial structure of the electronic device 200. The structure of FIG8 can be obtained by cutting along the AA' line of FIG9. However, for the sake of simplicity, FIG9 omits structures such as the substrate 101 and multiple signal lines. Referring to FIG7-9, the electronic device 200 includes a wiring substrate 100 described in any of the previous embodiments and multiple electronic devices 103. The multiple electronic devices 103 are located on a side of the multiple pad groups away from the substrate, and any electronic device 103 in the multiple electronic devices 103 corresponds to one of the multiple pad groups. Each electronic device 103 includes a pin group 104, and the pin group 104 includes at least two pins 1041. Any pin of the at least two pins 1041 corresponds to one of the at least two pads, and the pin 1041 of each electronic device 103 is connected to a corresponding pad. The pad group can be any of the pad groups 102, 202, and 302 described in the previous embodiments. The electronic device 103 can include a light-emitting element and a driver chip. The light-emitting element can be a micro-light-emitting diode (Micro-LED) or a sub-millimeter light-emitting diode (Mini-LED) of the order of 100 microns or less. The driver chip can be used to provide a signal to the light-emitting element to cause the light-emitting element to emit light.

[0081] The electronic device 200 can be any suitable type of electronic device, such as a television, laptop computer, tablet computer, wearable display device, mobile phone, in-vehicle display, navigation device, e-book, digital photo frame, advertising light box, or any other product or component with a display function. In one embodiment, the electronic device 200 can be used as a backlight source for a liquid crystal display panel. In another embodiment, the electronic device 200 can be a liquid crystal display device, which can have more uniform backlight brightness and better display contrast.

[0082] FIG9 shows the relative positional relationship between the pins 1041 and the corresponding pads during the alignment process of the manufacturing process (before soldering). For the sake of simplicity, FIG9 omits structures such as multiple signal lines and the substrate 101. However, as previously described, the pads are obtained by exposing a portion of the signal lines through the first opening 1051 of the insulating layer 105. In FIG9, as an example, the pad group is the pad group 302 described in the previous embodiment, and the electronic device 103 is a driver chip 1031 having twelve pins 1041. As shown in FIG9, the driver chip 1031 includes four output pins out1, out2, out3, and out4, two power pins vcc1 and vcc2, two data pins data1 and data2, two ground pins gnd1 and gnd2, an address pin di_in, and a relay pin di_out. Each output pin can be connected to at least one light-emitting element (not shown), so one driver chip 1031 can drive at least four light-emitting elements. Compared to a solution where a driver chip has only one output pin, the number of driver chips 1031 can be reduced exponentially, significantly reducing the number of driver chips 1031 used and, in turn, lowering the cost of the electronic device 200. The address pin di_in is configured to receive an address signal, configure the address information of the driver chip 1031 based on the address signal, and generate a relay signal. The relay pin di_out is connected to the address pin di_in of the next-stage driver chip 1031 cascaded with the driver chip 1031 and is configured to output a relay signal as the address signal for the next-stage driver chip 1031. The data pins data1 and data2 are configured to receive drive data, which includes drive information and address verification information. The power pins vcc1 and vcc2 are configured to receive a power signal to provide the voltage required for the driver chip 1031 to operate, ensuring the normal operation of the driver chip 1031. The ground pins gnd1 and gnd2 are configured to receive a ground signal.

[0083] It should be noted that, although FIG9 shows the arrangement positions of the twelve pins 1041 of the driver chip 1031 , this is only an example, and the arrangement positions of the twelve pins of the driver chip 1031 can be flexibly changed according to specific needs.

[0084] As shown in FIG9 , the orthographic projection of each pin 1041 on the substrate does not exceed the orthographic projection of its corresponding pad on the substrate. As previously described, pad group 302 includes first-type pads 3021 and second-type pads 3022. First-type pads 3021 are soldered to pins out1, out4, di_out, and di_in, respectively, and second-type pads 3022 are soldered to pins out2, out3, gnd1, gnd2, vcc1, vcc2, data1, and data2, respectively.

[0085] As previously described, each first-type solder pad 3021 includes a first selected side 3021A, a second selected side 3021B, a first unselected side 3021C, and a second unselected side 3021D. The pin 1041 soldered to the first-type solder pad 3021 includes four sides. The upper right side of FIG9 is an enlarged schematic diagram of the output pin out1 and the corresponding first-type solder pad 3021 in the left figure. Taking pin out1 as an example, this pin includes a first side 1041A, a second side 1041B, a third side 1041C, and a fourth side 1041D. The other three pins out4, di_out, and di_in also include the same four sides. During alignment, taking pin out1 and the first type of pad 3021 (i.e., pad Out1) as an example, the first selected edge 3021A and the second selected edge 3021B of the first type of pad 3021 are aligned with the first side 1041A and the second side 1041B of the pin out1 in a direction perpendicular to the substrate, respectively. The orthographic projection of the first non-selected edge 3021C of the first type of pad 3021 on the substrate is D5 away from the orthographic projection of the third side 1041C of the pin out1 on the substrate. The orthographic projection of the second non-selected edge 3021D of the first type of pad 3021 on the substrate is D5 away from the orthographic projection of the fourth side 1041D of the pin out1 on the substrate. D5 is in the range of 20 to 50 μm, for example, it can be 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. In other words, for the first type of pad 3021, since there is an adjacent second type of pad 3022 within 100 μm of the first selected edge 3021A in the first direction D1, the first selected edge 3021A does not expand relative to the first side 1041A of the pin 1041; since there is an adjacent second type of pad 3022 within 100 μm of the second selected edge 3021B in the second direction D2, the second selected edge 3021B is not expanded relative to the second side 1041A of the pin out1. Pin 041B does not expand outward; since no adjacent pad exists within 100μm of the first non-selected edge 3021C in the second direction D2, the first non-selected edge 3021C can expand outward by a distance D5 relative to the third side 1041C of pin out1; since no adjacent pad exists within 100μm of the second non-selected edge 3021D in the first direction D1, the second non-selected edge 3021D can expand outward by a distance D5 relative to the fourth side 1041D of pin out1. The relative positional relationship between the other three pins, out4, di_out, and di_in, and their corresponding pads is the same as that between pin out1 and the first-type pad 3021, and is not further described for the sake of brevity.

[0086] By not designing the edges of the first-class pads 3021 with a spacing less than 100 μm from the adjacent pads (i.e., the selected edges 3021A and 3021B) to be expanded outward, it is possible to avoid a short circuit caused by the pins contacting other pads that should not have an electrical connection relationship due to the small spacing between the two adjacent pads; by expanding the edges of the first-class pads with a spacing greater than 100 μm from the adjacent pads (i.e., the non-selected edges 3021C and 3021D) outward by D5 relative to the sides of the pins, it is possible to maximize the surface area of ​​the first-class pads 3021 facing the pins while ensuring that short circuits are avoided, thereby increasing the welding contact area between the first-class pads 3021 and the pins, reducing or even avoiding welding defects such as cold solder joints caused by insufficient contact area between the pins and the first-class pads 3021, and thus improving the welding yield.

[0087] As previously described, each second-type pad 3022 includes a third selected side 3022A, a fourth selected side 3022B, a first unselected side 3022D, and a third unselected side 3022C. The pin 1041 corresponding to the second-type pad 3022 includes four sides. The lower right side of FIG9 is an enlarged schematic diagram of the output pin out2 and the second-type pad 3022 (i.e., pad Out2) soldered thereto. Taking pin out2 as an example, this pin includes a fifth side 1041E, a sixth side 1041F, a seventh side 1041G, and an eighth side 1041H. The other seven pins out3, gnd1, gnd2, vcc1, vcc2, data1, and data2 also include four sides. During alignment, the third selected edge 3022A and the fourth selected edge 3022B of the second type pad 3022 are aligned with the fifth side 1041E and the sixth side 1041F of the pin out2 in a direction perpendicular to the substrate, respectively. The orthographic projection of the first non-selected edge 3022D of the second type pad 3022 on the substrate is D3 away from the orthographic projection of the eighth side 1041H of the pin out2 on the substrate. D3 is in the range of 20 to 50 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm. m, 40μm, 45μm, 50μm, etc., the orthographic projection of the third non-selected edge 3022C of the second type of pad 3022 on the substrate is D4 away from the orthographic projection of the seventh side 1041G of the pin out2 on the substrate, and D4 is in the range of 0 to 30μm, for example, it can be 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, etc., the third non-selected edge 3022C of the second type of pad 3022 is closer to the center O of the pad group 302 than the first non-selected edge 3022D. In other words, for the second type pad 3022, since there is another adjacent second type pad 3022 within 100 μm of the third selected edge 3022A along the second direction D2, the third selected edge 3022A does not expand relative to the fifth side 1041E of the pin out2; since there is another adjacent first type pad 3021 within 100 μm of the fourth selected edge 3022B along the second direction D2, the fourth selected edge 3022B does not expand relative to the sixth side 1041E of the pin out2. 1041F does not expand outward; since there is no other adjacent pad within 100μm of the first non-selected edge 3022D along the first direction D1, the first non-selected edge 3022D can expand outward by a distance D3 relative to the eighth side 1041H of the pin out2; since there is no other adjacent pad within 100μm of the third non-selected edge 3022C along the first direction D1, the third non-selected edge 3022C can expand outward by a distance D4 relative to the seventh side 1041G of the pin out2.The relative position relationship of the other seven pins out3, gnd1, gnd2, vcc1, vcc2, data1, data2 and their corresponding pads is the same as the relative position relationship between the pin out2 and the second type of pad 3022, and will not be repeated for the sake of brevity.

[0088] By not designing the edges of the second-type pads 3022 with a spacing less than 100 μm from adjacent pads (i.e., the selected edges 3022A and 3022B) to be expanded outward, it is possible to avoid a short circuit caused by the pin contacting other pads that should not have an electrical connection relationship due to the small spacing between two adjacent pads; by designing the edges of the second-type pads 3022 with a spacing greater than 100 μm from adjacent pads (i.e., the non-selected edges 3022C and 3022D) to be expanded outward by D3 and D4 relative to the side edges of the pin, the surface area of ​​the second-type pads 3022 facing the pin can be maximized while ensuring that a short circuit is avoided, thereby increasing the welding contact area between the second-type pads 3022 and the pin, reducing or even avoiding welding defects such as cold solder joints caused by insufficient contact area between the pin and the second-type pads 3022, and thus improving the welding yield. Furthermore, since the third non-selected edge 3022C is closer to the center O of the pad group 302 relative to the first non-selected edge 3022D, the outward expansion distance D4 of the third non-selected edge 3022C relative to the seventh side 1041G of the pin can be smaller than the outward expansion distance D3 of the first non-selected edge 3022D relative to the eighth side 1041H of the pin, so that the distance between the two relatively arranged third non-selected edges 3022C of two adjacent second-type pads 3022 will not be too small.

[0089] As shown in FIG9 , the area of ​​the surface of each pin 1041 facing a corresponding pad is C1, and the range of C1 is 6400 to 12100 μm. 2 The area of ​​the surface of the corresponding pad facing the pin 1041 is C2, and the range of C2 is 8000~14400μm 2 , the ratio of C1 to C2 is 0.4 to 1.0, for example, the ratio of C1 to C2 can be 0.4, 0.6, 0.8, 1.0, etc.

[0090] As shown in FIG9 , the orthographic projection of the first non-selected side 3021C of the first-type pad 3021 on the substrate overlaps with the outline of the orthographic projection of the first opening 1051 of the insulating layer 105 on the substrate. The minimum distance between the orthographic projection of the second non-selected side 3021D of the first-type pad 3021 on the substrate and the outline of the orthographic projection of the first opening 1051 of the insulating layer 105 on the substrate is T2, and T2 ranges from 30 to 50 μm. For example, T2 can be 30 μm, 40 μm, 50 μm, etc. FIG10 is a variation of FIG9 . Except for the first-type pad 3021, the other structures of FIG10 are the same as those of FIG9 . In FIG10 , the orthographic projections of the first non-selected side 3021C and the second non-selected side 3021D of the first-type pad 3021 on the substrate overlap with the outline of the orthographic projection of the first opening 1051 of the insulating layer 105 on the substrate.

[0091] FIG11 illustrates the relative positional relationship between each pad in a pad group 302 of the electronic device 200 provided in an embodiment of the present disclosure (refer to FIG4 , including four first-type pads 3021 and eight second-type pads 3022) and each pin 1041 of the corresponding electronic device after soldering. Line E1E1′ and line E2E2′ in FIG11 are perpendicular to each other, and the dotted cross line formed by them represents the reference coordinate axis. The intersection of line E1E1′ and line E2E2′ can be understood as the geometric center of a pad group 302. Each pad in a pad group 302 is arranged in an array with reference to the reference coordinate axis, wherein line E1E1′ is parallel to the second direction D2, and line E2E2′ is parallel to the first direction D1. The multiple pins 1041 of the electronic device are connected to each pad in the above-mentioned pad group 302 in a one-to-one correspondence, and the line F1F1' and the line F2F2' are perpendicular to each other. The intersection of the line F1F1' and the line F2F2' can be understood as the geometric center of the electronic device soldered to the above-mentioned pad group 302, and the multiple pins 1041 of the electronic device are arranged in an array with the coordinate axis formed by the cross dotted line formed by the line F1F1' and the line F2F2' as the reference axis. The angle between the line F1F1' and the line E1E1' is an acute angle, and the angle between the line F2F2' and the line E2E2' is an acute angle. It can be seen that the pin 1041 has a certain rotation and offset relative to the first type of pad 3021 or the second type of pad 3022 of the pad group 302 (for example, the same angle as the rotation and offset in the related art shown in Figure 6). The rotation angle of the pin 1041 relative to the first-type solder pad 3021 or second-type solder pad 3022 to which it is connected is no greater than 3 degrees, and the offset dimension of the pin 1041 relative to the first-type solder pad 3021 or second-type solder pad 3022 to which it is connected is no greater than 36 microns. Under these rotation angles and offset dimensions, the contact area between the pin 1041 and the solder pads in the solder pad group meets the requirements, enabling a reliable connection between the two. As shown in FIG11 , the orthographic projection of each pin 1041 on the substrate is a first orthographic projection B1, and the orthographic projection of the solder pad 3021 or 3022 to which the pin 1041 is soldered on the substrate is a second orthographic projection B2. The first orthographic projection B1 and the second orthographic projection B2 at least partially overlap. The area where the first orthographic projection B1 and the second orthographic projection B2 overlap constitutes an overlapping region B3. The ratio of the area of ​​the overlapping region B3 to the area of ​​the second orthographic projection B2 is greater than or equal to 39%. In some embodiments, the ratio of the area of ​​the overlapping region B3 to the area of ​​the second orthographic projection B2 ranges from 39% to 100%, that is, the minimum value of the ratio of the area of ​​the overlapping region B3 to the area of ​​the second orthographic projection B2 is 39%, and the maximum value is 100%; for a pad group, the ratio of the minimum to the maximum area of ​​each overlapping region B3 is approximately 0.5.In contrast, in the related art, referring to FIG6 , the orthographic projection of each lead 12 on the substrate is a first orthographic projection A1, and the orthographic projection of the pad 11 to which the lead 12 is soldered is a second orthographic projection A2. The first orthographic projection A1 and the second orthographic projection A2 at least partially overlap to form an overlapping region A3. The ratio of the area of ​​the overlapping region A3 to the area of ​​the second orthographic projection A2 is greater than or equal to 31%. For a pad group, the minimum value of the ratio of the smallest to the largest area of ​​each overlapping region A3 is, for example, 0.25. Compared to the related art, the embodiments of the present disclosure, by separately designing the selected and unselected edges of the first-type solder pads 3021 and the second-type solder pads 3022 as described above, not only avoid the risk of short circuits, but also significantly increase the solder contact area between the pins 1041 and the first-type solder pads 3021 or the second-type solder pads 3022. This reduces or even prevents solder joint defects such as cold solder joints caused by insufficient contact area between the pins 1041 and the first-type solder pads 3021 or the second-type solder pads 3022, thereby helping to improve soldering yield. Furthermore, referring to FIG6 , in the related art, only four of the twelve solder pads 11 meet the requirement that the ratio of the area of ​​the overlap region A3 to the area of ​​the second orthographic projection A2 is greater than 40%. The ratio of the area of ​​the overlap region A3 to the area of ​​the second orthographic projection A2 for the other eight solder pads is significantly less than 40%. In particular, the solder pad 11 and the pin 12 located in the first row and fourth column have the smallest ratio of the area of ​​the overlap region A3 to the area of ​​the second orthographic projection A2, for example, less than 20%. In the example of FIG6 , the ratio of the area of ​​the overlap region A3 to the area of ​​the second orthographic projection A2 ranges from approximately 20% to 100%. In the embodiment of the present disclosure, referring to FIG11 , among the twelve solder pads, at least eleven solder pads satisfy a ratio of the area of ​​the overlap region B3 to the area of ​​the second orthographic projection B2 greater than 40%, and only one solder pad satisfies a ratio of the area of ​​the overlap region B3 to the area of ​​the second orthographic projection B2 slightly less than 40%. Therefore, compared to the related art, a greater number of solder pads satisfy a ratio of the area of ​​the overlap region B3 to the area of ​​the second orthographic projection B2 greater than 40%. This further ensures the soldering contact area between the pin 1041 and the first-type solder pad 3021 or the second-type solder pad 3022, avoids insufficient soldering contact area between the pin 1041 and the first-type solder pad 3021 or the second-type solder pad 3022, and thus helps further improve the soldering yield.

[0092] 8 , insulating layer 105 is located between multiple pad groups and multiple electronic devices 103, and any one of the multiple electronic devices 103 corresponds to one of the multiple first openings 1051 in insulating layer 105. In one embodiment, as shown in FIG9 , when the pad group is pad group 302 and the electronic device 103 is a driver chip 1031, insulating layer 105 is located between the multiple pad groups 302 and the multiple driver chips 1031, and any one of the multiple driver chips 1031 corresponds to one of the multiple first openings 1051 in insulating layer 105. The third orthographic projection of each driver chip 1031 on the substrate falls within the fourth orthographic projection of the corresponding first opening 1051 on the substrate, and the distance between the outline of the third orthographic projection and the outline of the fourth orthographic projection is D8, which can be 20 to 40 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, etc. The first opening 1051 of the insulating layer 105 is expanded D8 relative to the outer contour of the driver chip 1031, which can provide a certain redundancy to provide a tolerance range in the process, and can also limit the driver chip 1031 in the first direction D1 and the second direction D2 during the die bonding process. In another embodiment, as shown in FIG12 , when the pad group is a pad group 102 having two pads and the electronic device 103 is a light-emitting element 1032, the insulating layer 105 is positioned between the plurality of pad groups 102 and the plurality of light-emitting elements 1032, and any one of the plurality of light-emitting elements 1032 corresponds to one of the plurality of first openings 1051 in the insulating layer 105. The third orthographic projection of each light-emitting element 1032 on the substrate falls within the fourth orthographic projection of the corresponding first opening 1051 on the substrate, and the distance between the outline of the third orthographic projection and the outline of the fourth orthographic projection is D8, which can be 20 to 40 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, etc. The first openings 1051 in the insulating layer 105 are extended by D8 relative to the outer contour of the light-emitting element 1032 to provide a certain amount of redundancy, thereby limiting the light-emitting element 1032 in the first direction D1 and the second direction D2.

[0093] In some embodiments, in order to meet the reflection requirements, the thickness of the insulating layer 105 in the direction perpendicular to the substrate 101 is generally 50 to 60 μm to meet the reflection requirements; at the same time, since the first opening 1051 of the insulating layer 105 expands 20 to 40 μm relative to the outer contour of the electronic device 103, the insulating layer 105 can have a certain limiting effect on the electronic device 103 in the first direction D1 and the second direction D2, thereby avoiding the pins 1041 of the electronic device 103 from rotating and offsetting more relative to the pad during the solidification process, thereby increasing the contact area between the pins 1041 and the pad after reflow soldering, reducing or even avoiding poor soldering such as cold soldering. The first opening 1051 of the insulating layer 105 is expanded by 20 to 40 μm relative to the outer contour of the electronic device 103, which is an appropriate range. Because if the expansion size range is small, the pin 1041 will be limited in the amount of displacement that can be made during the solidification process, which may easily cause the local position of the electronic device 103 to contact the surface of the insulating layer 105 facing the electronic device 103, thereby causing the electronic device to tip over and making welding impossible; if the expansion is too large, the insulating layer 105 basically loses its limiting function, causing the pin 1041 of the electronic device 103 to rotate and / or deflect too much relative to the pad, which may easily lead to a reduction in the contact area between the pin 1041 and the pad, causing a cold solder joint, and may bring the risk of a short circuit between the pin 1041 and the adjacent pad.

[0094] The light emitting element 1032 may be a micro-LED or a sub-millimeter light emitting diode (Mini-LED) with a size of 100 microns or less. The driver chip 1031 may be used to provide a signal to the light emitting element 1032 to cause the light emitting element 1032 to emit light.

[0095] Figure 13 shows a schematic cross-sectional structure diagram of the electronic device 200. As shown in Figure 13, in addition to the substrate 101, the insulating layer 105, and the electronic device 103, the electronic device 200 may also include structures such as a support column 111, a diffuser 112, a wavelength conversion layer 113, a diffuser 114, and a composite film 115. The support column 111 is fixed on the insulating layer 105, which can provide a certain spatial spacing between the diffuser 112 and the insulating layer 105, thereby obtaining a certain light mixing distance and reducing or eliminating the lamp shadow produced by the light-emitting element. The diffuser 112 and the diffuser 114 can be used to further eliminate potential lamp shadows and improve the uniformity of the picture. The wavelength conversion layer 113 can, for example, convert the blue light emitted by the light-emitting element into white light. In some embodiments, the wavelength conversion layer 113 is a quantum dot film. The composite film 115 can be used to increase the brightness of the emitted light. The electronic components (such as light-emitting elements, driver chips, etc.) after welding are protected by packaging glue.

[0096] FIG14 shows a flow chart of a method 400 for manufacturing an electronic device, which is applicable to the electronic device described in any of the above embodiments. The method 400 includes the following steps:

[0097] S401: providing a substrate.

[0098] S402: forming a plurality of pad groups on a substrate, wherein each of the plurality of pad groups includes at least two pads.

[0099] S403: Fix a plurality of electronic devices on a side of a plurality of pad groups away from the substrate, wherein any one of the plurality of electronic devices corresponds to one of the plurality of pad groups, each of the plurality of electronic devices includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and each pin of the electronic device is connected to a corresponding pad.

[0100] Below, some process details involved in steps S401-S403 are described in detail.

[0101] S401: providing a substrate.

[0102] The substrate may be a flexible or rigid material, specifically, PEN resin, silicone resin, polyimide, glass, quartz, plastic, etc. The embodiments of the present disclosure do not limit the material of the substrate.

[0103] S402: forming a plurality of pad groups on a substrate, wherein each of the plurality of pad groups includes at least two pads.

[0104] Specifically, a conductive layer is formed on a substrate and patterned to form a plurality of signal lines. An insulating layer 105 including a plurality of first openings 1051 is formed on a side of the plurality of signal lines away from the substrate. The first openings 1051 expose a portion of each signal line to form a pad. The plurality of signal lines may include a power supply voltage signal line configured to provide a voltage to the light-emitting element 1032, a ground signal line configured to provide a ground voltage to the ground pin gnd of the driver chip, a transmission signal line configured to provide a data signal to the data pin data of the driver chip, and a power supply voltage signal line configured to provide a voltage to the power pin vcc of the driver chip. The pad group may be the pad groups 102, 202, or 302 described in the previous embodiments.

[0105] Between steps S402 and S403, a step of applying flux to the pins 1041 or pads is also included. The flux facilitates and promotes soldering between the pads and the pins during the subsequent reflow process, while also protecting and preventing oxidation. There are two main methods for applying flux. One method involves adhering and arranging several driver chips on a UV film, with the driver chip pins 1041 located on the side facing away from the UV film. The pins 1041 of all driver chips on the UV film are then dipped into a flux-filled groove, so that the surfaces of all pins 1041 facing away from the UV film are coated with flux. This method of applying flux is commonly referred to as a "flux dip process." Accordingly, solder can be applied to the surface of the pads facing the pins 1041. If the driver chip is a twelve-pin driver chip as described above, using this flux dip process will not only coat the surfaces of all pins 1041 facing away from the UV film with flux, but also the central area of ​​the driver chip's surface facing away from the UV film. The central area of ​​the driver chip does not have any pins 1041, so flux is not actually needed in this area. However, the flux dipping process causes flux to remain in the central area of ​​the driver chip and cannot be effectively discharged, causing the flux to corrode the pins of the driver chip and the pads connected to the pins.

[0106] Another method of applying flux is to use a mesh with openings, such as a stencil, to print flux onto the surface of each pad of the pad group facing the pin 1041. For example, a dipping method can be used to dip the solder onto the surface of the pin 1041 facing the pad. This method of applying flux is generally referred to as a "printed flux process."

[0107] There are two approaches to forming flux on multiple pads in a pad group using a printed flux process. One approach, as shown in FIG15 , involves providing a stencil 120 with an opening 122 at a location corresponding to each pad group. This opening 122 exposes all twelve pads 11 in the pad group and the central area of ​​the pad group. Flux is then printed onto the twelve pads 11 in each pad group and within the central area of ​​the pad group through the opening 122. However, this approach, similar to the flux dipping process, can result in flux residue in the central area of ​​the pad group where no pads 11 are located. Another approach, as shown in FIG16 , involves providing a stencil 220 with an opening 222 at a location corresponding to each pad 11 in the pad group. This opening 222 exposes a portion of the surface of the pad 11 facing the pin 1041. Flux is then printed onto the portion of the surface of each pad 11 facing the pin 1041 through the opening 222. Although this method can avoid printing flux into the center area of ​​the pad group, since the stencil 220 includes twelve openings 222 at positions corresponding to each pad group, and a large number of pad groups are provided on the light-emitting substrate, this will result in the entire stencil 220 having a correspondingly large number of openings 222. When the stencil 220 needs to be separated from the substrate after the flux printing is completed, the adhesion between the flux and the stencil 220 and / or the substrate will be significantly increased due to the large number of openings 222. In addition, the distance between two adjacent openings 222 corresponding to the same pad group is small, which will result in insufficient strength and reduced tension of the stencil 220, making it difficult to ensure the accuracy of removing the stencil 220 from the substrate. The reduced strength and tension will also accelerate the wear of the stencil 220 and shorten its lifespan.

[0108] In view of this, embodiments of the present disclosure provide an improved stencil to optimize the printing process of soldering flux.

[0109] As shown in Figure 17, when the pad group 202 includes four pads, the stencil 320 includes four second openings 322 at locations corresponding to each pad group 202. The orthographic projection of each opening 322 on the substrate falls within the orthographic projection of the corresponding pad on the substrate. Through the second openings 322, flux can be printed on the surface of each pad facing the pin 1041 without being printed on the center of the pad group 202. This prevents flux residue from remaining in the center of the pad group 202, further preventing flux corrosion of the individual pads of the pad group 202 and the corresponding pins of the electronic devices connected to each pad. The spacing D7 between the two opposing edges of two adjacent pads is relatively large, approximately 140 μm, while the spacing D6 between the two opposing outlines of two adjacent second openings 322 can be increased to 160 μm. This larger spacing D6 ensures that the stencil 320 has higher strength and tensile strength.

[0110] As shown in FIG18 , when the pad group is a pad group 302 including twelve pads, each pad group 302 includes a central region and four corner regions surrounding the central region. Each corner region is provided with one first-type pad 3021 and two second-type pads 3022. The stencil 420 includes a plurality of second openings 422. Each second opening 422 corresponds to one of the plurality of corner regions of the plurality of pad groups 302. The orthographic projection of each second opening 422 on the substrate partially overlaps with the orthographic projection of one first-type pad 3021 and two second-type pads 3022 within the corresponding corner region. That is, the stencil 420 includes four second openings 422 at locations corresponding to each pad group 302. In some embodiments, the second openings 422 are L-shaped, and each second opening 422 exposes at least one first-type pad 3021 and at least two second-type pads 3022 in the pad group 302. When the soldering flux is printed using the stencil 420 , the soldering flux is printed onto the surfaces of the first type soldering pads 3021 and the second type soldering pads 3022 facing away from the substrate through the second openings 422 of the stencil 420 . After printing is completed, the stencil 420 is removed.

[0111] Because the stencil 420 does not have an opening at the center of the corresponding pad group 302, the flux will not be printed in the center of the pad group 302, thereby preventing the flux from remaining in the center of the pad group 302, thereby preventing the flux from corroding the individual pads of the pad group 302 and the corresponding pins of the electronic devices connected to each pad. In the related art, the number of openings 222 of the stencil 220 at the position corresponding to each pad group is twelve; however, in the embodiment of the present disclosure, the number of second openings 422 of the stencil 420 at the position corresponding to each pad group 302 is reduced from twelve to four, thereby significantly improving the strength and tension of the stencil 420 compared to the strength and tension of the stencil 220. Furthermore, the reduction in the number of second openings 422 can effectively ensure the accuracy of the detachment of the stencil 420 from the substrate.

[0112] S403: Fixing a plurality of electronic devices on a side of the plurality of pad groups away from the substrate.

[0113] Specifically, this step may include: aligning each pin 1041 of the electronic device with a corresponding pad so that a first orthographic projection of each pin 1041 of the electronic device on the substrate does not extend beyond a second orthographic projection of the corresponding pad on the substrate; and soldering each pin 1041 of the electronic device to the corresponding pad using solder. Because the surface of the pin 1041 facing the pad has been dipped in solder containing tin in the aforementioned step, and the surface of the pad facing the pin 1041 has been printed with flux, during the reflow process between the pin and the pad, the tin in the solder and the surface material of the pad can form an intermetallic compound. Combined with the promoting effect of the flux, a reliable electrical connection can be achieved between the pin 1041 and the pad.

[0114] 9 , when the pad group is pad group 302 , the step of aligning each pin 1041 of the electronic device with a corresponding pad may include the following sub-steps:

[0115] The first selected edge 3021A and the second selected edge 3021B of each first-type solder pad 3021 are aligned with the first side edge 1041A and the second side edge 1041B of the corresponding pin 1041 in a direction perpendicular to the substrate, and the orthographic projection of the first non-selected edge 3021C of each first-type solder pad 3021 on the substrate is D5 away from the orthographic projection of the third side edge 1041C of the corresponding pin 1041 on the substrate, and the orthographic projection of the second non-selected edge 3021D of each first-type solder pad 3021 on the substrate is D5 away from the orthographic projection of the fourth side edge 1041D of the corresponding pin 1041 on the substrate, and D5 is in the range of 20 to 50 μm, for example, it can be 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. In addition, the third selected side 3022A and the fourth selected side 3022B of each second type pad 3022 are aligned with the fifth side 1041E and the sixth side 1041F of the corresponding lead 1041 in a direction perpendicular to the substrate, respectively, so that the orthographic projection of the first non-selected side 3022D of each second type pad 3022 on the substrate is at a distance D3 from the orthographic projection of the eighth side 1041H of the corresponding lead 1041 on the substrate, and D3 is within the range of 20 to 50 μm. The distance between the third non-selected side 3022C of each second-type pad 3022 and the orthographic projection of the seventh side 1041G of the corresponding pin 1041 on the substrate is D4, and D4 is in the range of 0 to 30 μm, for example, it can be 20 μm, 25 μm, 30 μm, 40 μm, 45 μm, 50 μm, etc., and the distance between the orthographic projection of the third non-selected side 3022C of each second-type pad 3022 on the substrate and the orthographic projection of the seventh side 1041G of the corresponding pin 1041 on the substrate is D4, and D4 is in the range of 0 to 30 μm, for example, it can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc.

[0116] By not designing the selected edges of the first-type solder pads 3021 and the second-type solder pads 3022 to be expanded relative to the side edges of the pins 1041, it is possible to avoid short circuits caused by contact between the pins 1041 and adjacent solder pads due to the small distance between adjacent solder pads; by designing the non-selected edges of the first-type solder pads 3021 and the second-type solder pads 3022 to be expanded relative to the side edges of the pins 1041 to a certain extent, it is possible to maximize the surface areas of the first-type solder pads 3021 and the second-type solder pads 3022 facing the pins 1041 while ensuring that short circuits are avoided, thereby increasing the welding contact area between the first-type solder pads 3021 and the second-type solder pads 3022 and the pins 1041, reducing or even avoiding welding defects such as cold solder joints caused by insufficient contact area between the pins 1041 and the first-type solder pads 3021 and the second-type solder pads 3022, thereby improving the welding yield.

[0117] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another area, layer or part. Therefore, the first element, component, area, layer or part discussed above can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0118] Spatially relative terms such as "row," "column," "under," "above," "left," "right," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary term "under" can encompass both orientations of above and below. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0119] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily need to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0120] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0121] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0122] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0123] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A wiring substrate, comprising: substrate; A plurality of pad groups are located on the substrate, each of the plurality of pad groups includes at least two pads; in, Two adjacent pads in the first direction or the second direction of the at least two pads are spaced apart, and the first direction intersects the second direction. Each of the at least two pads includes multiple edges, the multiple edges include at least one selected edge and at least one non-selected edge, any one pad is adjacent to the other pad along the first direction or the second direction, the selected edge of any one pad is the edge facing the adjacent other pad among the multiple edges, and the spacing between the selected edge of any one pad facing the adjacent other pad and the selected edge of the adjacent other pad facing the any one pad is greater than or equal to 30um and less than 100um.

2. The wiring substrate according to claim 1, further comprising an insulating layer located on a side of the plurality of pad groups away from the substrate, wherein The insulating layer includes a plurality of first openings, and any one of the plurality of first openings corresponds to one of the plurality of pad groups.

3. The wiring substrate according to claim 2, wherein Any one of the plurality of pad groups includes two pads spaced apart along the first direction or the second direction, and a positive projection of each of the two pads on the substrate coincides with a partial outline of a positive projection of a corresponding first opening on the substrate.

4. The wiring substrate according to claim 2, wherein Any one of the multiple pad groups includes four pads arranged in an array and spaced apart along the first direction and the second direction, and the non-selected sides of each of the four pads include at least one first non-selected side, and the orthographic projection of the first non-selected side on the substrate coincides with a partial outline of the orthographic projection of a corresponding first opening on the substrate.

5. The wiring substrate according to claim 4, wherein The non-selected sides of each pad further include a second non-selected side, and a minimum distance between an orthographic projection of the second non-selected side on the substrate and an outline of an orthographic projection of the corresponding first opening on the substrate is 30-50 um. The wiring substrate according to claim 2 , wherein: Any one of the multiple pad groups includes a plurality of pads spaced apart along the first direction or the second direction, the geometric centers of the multiple pads are connected in sequence in a clockwise direction to form a convex polygon, and the non-selected sides of each of the multiple pads include at least one first non-selected side, the orthographic projection of the first non-selected side on the substrate coincides with a partial outline of the orthographic projection of a corresponding first opening on the substrate.

7. The wiring substrate according to claim 6, wherein The multiple pads include a first type of pads and a second type of pads, the selected edges of the first type of pads include a first selected edge and a second selected edge, the extension direction of the first selected edge and the extension direction of the second selected edge have an angle, the selected edges of the second type of pads include a third selected edge and a fourth selected edge, the extension direction of the third selected edge and the extension direction of the fourth selected edge are parallel.

8. The wiring substrate according to claim 7, wherein The first type pad and two second type pads are spaced apart in the first direction and the second direction respectively, and any pad adjacent to the second type pad is spaced apart from the second type pad along the first direction or the second direction.

9. The wiring substrate according to claim 7 or 8, wherein: The non-selected sides of each first-type pad further include a second non-selected side, and the minimum distance between the orthographic projection of the second non-selected side on the substrate and the outline of the orthographic projection of the corresponding first opening on the substrate is 30-50 um.

10. The wiring substrate according to any one of claims 7 to 9, wherein: The non-selected edge of each second-type pad also includes a third non-selected edge. The second-type pad is spaced apart from a first-type pad along the first direction. The spacing between the third non-selected edge of the second-type pad and the second selected edge of the first-type pad in the second direction is greater than 0 and less than or equal to 30um. The second selected edge of the first-type pad is the selected edge of the second-type pad facing the first-type pad and spaced apart along the second direction.

11. The wiring substrate according to any one of claims 7 to 9, wherein: The non-selected edge of each second-type pad also includes a third non-selected edge. The second-type pad is spaced apart from a first-type pad along the second direction. The spacing between the third non-selected edge of the second-type pad and the first selected edge of the first-type pad in the first direction is greater than 0 and less than or equal to 30um. The first selected edge of the first-type pad is the selected edge of the second-type pad facing the first-type pad and spaced apart along the first direction.

12. The wiring substrate according to any one of claims 2 to 11, wherein: No other film layer is provided between the layer where the insulating layer is located and the layer where the plurality of pad groups are located.

13. An electronic device comprising the wiring substrate according to any one of claims 1 to 12 and a plurality of electronic devices, wherein: The multiple electronic devices are located on a side of the multiple pad groups away from the substrate, any one of the multiple electronic devices corresponds to one of the multiple pad groups, each of the multiple electronic devices includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and each pin of the electronic device is connected to a corresponding pad.

14. The electronic device according to claim 13, wherein: The ratio of the area of ​​the surface of the pin of each electronic device facing the corresponding one of the pads to the area of ​​the surface of the corresponding one of the pads facing the pin is 0.4-1.

0.

15. The electronic device according to claim 13 or 14, wherein: The first orthographic projection of the pin of each electronic device on the substrate at least partially overlaps with the second orthographic projection of the corresponding pad on the substrate, and the area where the first orthographic projection overlaps with the second orthographic projection constitutes an overlapping area, and the ratio of the area of ​​the overlapping area to the area of ​​the second orthographic projection is greater than or equal to 39%.

16. The electronic device according to any one of claims 13 to 15, wherein: The insulating layer is located between the multiple pad groups and the multiple electronic devices, any one of the multiple electronic devices corresponds to a first opening among the multiple first openings of the insulating layer, the third orthographic projection of each electronic device on the substrate falls within the fourth orthographic projection of the corresponding first opening on the substrate, and the spacing between the outline of the third orthographic projection and the outline of the fourth orthographic projection is 20 to 40 μm.

17. A method of manufacturing an electronic device, comprising: providing a substrate; forming a plurality of pad groups on the substrate, each of the plurality of pad groups including at least two pads; as well as fixing a plurality of electronic devices on a side of the plurality of pad groups away from the substrate, Among them, any one of the multiple electronic devices corresponds to one of the multiple pad groups, each of the multiple electronic devices includes at least two pins, any one of the at least two pins corresponds to one of the at least two pads, and each pin of the electronic device is connected to a corresponding pad.

18. The method according to claim 17, wherein: The step of forming a plurality of pad groups on the substrate comprises: applying a conductive layer on the substrate, and patterning the conductive layer to form a plurality of signal lines; An insulating layer including a plurality of first openings is formed on a side of the plurality of signal lines away from the substrate, and a portion of each of the plurality of signal lines is exposed through the first openings to form the pads.

19. The method according to claim 18, wherein The step of fixing a plurality of electronic devices on a side of the plurality of pad groups away from the substrate comprises: Aligning each pin of the electronic device with the corresponding pad so that a first orthographic projection of each pin of the electronic device on the substrate does not exceed a second orthographic projection of the corresponding pad on the substrate; Each pin of the electronic device is soldered to the corresponding one of the pads using solder.

20. The method according to claim 19, wherein Each pad group includes a plurality of pads spaced apart along the first direction or the second direction, the plurality of pads include first-type pads, the first-type pads include a first selected side and a second selected side and a first non-selected side and a second non-selected side, an extension direction of the first selected side and an extension direction of the second selected side have an included angle, and an extension direction of the first non-selected side and an extension direction of the second non-selected side have an included angle, The step of aligning each pin of the electronic device with the corresponding pad includes: The first selected edge and the second selected edge of each first-type solder pad are aligned with the first side edge and the second side edge of a corresponding pin in a direction perpendicular to the substrate, and the orthographic projections of the first non-selected edge and the second non-selected edge of each first-type solder pad on the substrate are 20 to 50 μm away from the orthographic projections of the third side edge and the fourth side edge of a corresponding pin on the substrate.

21. The method according to claim 20, wherein The plurality of pads further include a second type of pad, the second type of pad including a third selected side and a fourth selected side and a first non-selected side and a third non-selected side, an extension direction of the third selected side is parallel to an extension direction of the fourth selected side, and an extension direction of the first non-selected side is parallel to an extension direction of the third non-selected side, The step of aligning each pin of the electronic device with the corresponding pad further comprises: The third selected edge and the fourth selected edge of each second-type pad are respectively aligned with the fifth side edge and the sixth side edge of a corresponding pin in a direction perpendicular to the substrate, the orthographic projection of the third non-selected edge of each second-type pad on the substrate is 0 to 30 μm away from the orthographic projection of the seventh side edge of a corresponding pin on the substrate, and the orthographic projection of the first non-selected edge of each second-type pad on the substrate is 20 to 50 μm away from the orthographic projection of the eighth side edge of a corresponding pin on the substrate, and the third non-selected edge is closer to the center of the pad group than the first non-selected edge.

22. The method according to claim 21, wherein Each pad group includes a central area and a plurality of corner areas surrounding the central area, each of the plurality of corner areas is arranged with at least one first type pad and at least one second type pad. Before aligning each pin of the electronic device with the corresponding pad, the method further includes: placing a mesh on a side of the plurality of pad groups away from the substrate, the mesh comprising a plurality of second openings, any one of the plurality of second openings corresponding to one of the plurality of corner regions of the plurality of pad groups, an orthographic projection of each of the plurality of second openings on the substrate partially overlapping with an orthographic projection of at least one first-type pad and at least one second-type pad in a corresponding corner region on the substrate; Printing soldering flux onto the surfaces of the first type of pads and the second type of pads away from the substrate through the second opening of the stencil; Remove the stencil.

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