High-temperature pressure sensor and preparation method thereof

Abstract

The high-temperature pressure sensor comprises an SOI chip, isolation channels are formed in the side, close to an SOI device layer, of the surface of the SOI chip, the isolation channels sequentially penetrate through the SOI device layer, a buried oxide layer and part of a substrate layer and divide the surface of the SOI chip into a cavity area and a sealing end area, and every two adjacent isolation channels form a piezoresistor; the surface of the SOI wafer is sequentially covered with a first insulating layer, a second insulating layer, a passivation layer and a P-type doped polycrystalline silicon layer, and an electrode isolation channel and a second contact hole are formed in the surface of the SOI wafer; the bonding pad is formed on the surface of the polycrystalline silicon layer at a position corresponding to the second contact hole and is connected with the doping layer; borosilicate glass is bonded on the surface of the polycrystalline silicon layer and encloses a closed cavity in a cavity area, and a bonding pad is located in a glass through hole of the borosilicate glass; the metal pins are fixedly and electrically connected with the bonding pads through sintering and curing of the conductive silver paste. According to the design, the working temperature can be greatly improved, and failure is avoided.

Description

Technical Field

[0001] This invention relates to the field of sensors, and more particularly to a high-temperature pressure sensor and its fabrication method. Background Technology

[0002] High-temperature pressure sensors play a crucial role in applications such as pressure monitoring for aerospace engines, high-temperature hydraulic systems in aircraft, pressure monitoring for gas turbines, pressure monitoring in oil and gas exploration, and pressure monitoring for geothermal energy. These sensors operate in environments exceeding 125°C, requiring them to maintain excellent performance under these high-temperature conditions. Traditional pressure sensors are silicon-based, forming a PN junction between the piezoresistor and the substrate to isolate the piezoresistor and the pressure strain film. However, as temperature increases, the leakage current of the PN junction increases, leading to a deterioration in the performance of the high-temperature pressure sensor. At 125°C, the PN junction may even break down, causing the sensor to fail. Excessive temperatures can also cause fatigue at the solder joints of sensor components, leading to fatigue cracking of the lead bonding points.

[0003] Therefore, improved high-temperature pressure sensors often employ a thin-film SOI device layer doped and dry-etched as a piezoresistor, eliminating the PN junction. This ensures stable operation of the high-temperature pressure sensor above 125°C for extended periods, thereby improving its reliability. The piezoresistor fabrication involves completely etching away the thin-film SOI device layer to achieve full dielectric isolation, thus enabling stable operation at high temperatures. However, etching only the thin-film SOI device layer results in a small piezoresistive bump, typically less than 1µm, often leading to low sensitivity, poor temperature compensation, or low output voltage after compensation. Furthermore, the vacuum chamber is formed on a glass plate, requiring the etching of borosilicate glass, which is extremely difficult, resulting in a complex and costly manufacturing process.

[0004] For example, Chinese patent (publication number: CN117842924A) describes a high-temperature pressure sensor. The sensitive core adopts a glass-silicon-glass three-layer structure. An absolute pressure reference cavity is formed by opening a cavity between the cap borosilicate glass and the sensor chip sealing end face, which seals and protects the precision structure, realizing the design of a sensor that can withstand extreme high-temperature pressure for a long time. However, due to the extreme difficulty in preparing the absolute pressure reference cavity by etching the borosilicate glass, and the fact that the varistor formed by etching the thin-film SOI device layer has a protrusion height of only less than 1µm, the sensitivity is low, the temperature compensation effect is poor, or the output voltage is low after compensation.

[0005] Therefore, considering the aforementioned technical problems, it is necessary to propose a new technical solution. Summary of the Invention

[0006] To at least address one of the technical problems existing in the prior art, the present invention provides a high-temperature pressure sensor and its fabrication method. The specific technical solution is as follows: On one hand, the present invention provides a high-temperature pressure sensor, which includes: An SOI wafer, from bottom to top, includes a substrate layer, a buried oxide layer, and an SOI device layer. An isolation channel is formed on the surface of the SOI wafer near the SOI device layer. The isolation channel passes through the SOI device layer, the buried oxide layer, and part of the substrate layer in sequence. At least the SOI device layer is doped to form a doped layer. The surface area of ​​the SOI wafer is separated into a cavity region and a sealing end region by the isolation channel. Two adjacent isolation channels form a varistor, and the varistor is located in the cavity region. A first insulating layer covers the surface of the SOI wafer away from the substrate layer and the inner surface of the isolation channel; A second insulating layer covers the surface of the first insulating layer; A passivation layer is applied to the surface of the second insulating layer at a position corresponding to the sealing end area. An electrode isolation channel, a first contact hole, and a second contact hole are formed on the passivation layer. The electrode isolation channel passes through the passivation layer to the second insulating layer. The first contact hole passes through the passivation layer to connect with the second insulating layer. The second contact hole passes through the second insulating layer and the first insulating layer in sequence to connect with the doped layer. The first contact hole and the second contact hole correspond to each other. The first contact hole and the second contact hole are collectively referred to as contact holes. A polysilicon layer covers the surface of the passivation layer, the polysilicon layer is configured to be P-type doped, the second contact hole is filled with conductive doped polysilicon, and the sidewall of the first contact hole has doped polysilicon. The pads are formed on the surface of the polysilicon layer at positions corresponding to the first and second contact holes, and the pads are electrically connected to the doped layer. Borosilicate glass, wherein the borosilicate glass is bonded to the surface of a polycrystalline silicon layer, which encloses the cavity region into a closed cavity, and a through glass via is formed on the surface of the borosilicate glass at a position corresponding to the pad, and the pad is located inside the through glass via. A metal pin, wherein one end of the metal pin extends into a glass through-hole, the glass through-hole is filled with conductive silver paste, and the metal pin is fixedly electrically connected to the solder pad by sintering and curing the conductive silver paste.

[0007] As a preferred embodiment of the high-temperature pressure sensor described in this invention, a back cavity is formed on the surface of the substrate layer away from the buried oxide layer, and a back island is formed between two adjacent back cavities. The back cavities and the cavity regions are disposed opposite to each other on both sides of the substrate layer.

[0008] As a preferred embodiment of the high-temperature pressure sensor described in this invention, a portion of the substrate layer, the buried oxide layer, and a portion of the SOI device layer between the piezoresistor and the back cavity constitute a pressure strain film.

[0009] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the borosilicate glass anode is bonded and fixed to the surface of the polycrystalline silicon layer.

[0010] As a preferred embodiment of the high-temperature pressure sensor described in this invention, borosilicate glass is sealed above the cavity region, and the cavity is sealed as a vacuum chamber.

[0011] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the main body of the metal pin is Kovar alloy, and the surface of the Kovar alloy is plated with gold, nickel, silver or copper.

[0012] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the glass through-hole is a trapezoidal hole, with the inner diameter of the glass through-hole gradually decreasing from the side of the borosilicate glass closest to the pad towards the side furthest from the pad.

[0013] In a preferred embodiment of the high-temperature pressure sensor described in this invention, the first insulating layer is a silicon oxide thin film.

[0014] In a preferred embodiment of the high-temperature pressure sensor described in this invention, the second insulating layer is a silicon nitride thin film.

[0015] In a preferred embodiment of the high-temperature pressure sensor described in this invention, the passivation layer is a silicon oxide passivation layer.

[0016] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the passivation layer surface is polished to form a flat surface.

[0017] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the sealing end area is a sealing end, and the varistor and the sealing end form a Wheatstone bridge.

[0018] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the metal pins or pads are configured to extract the node voltages of the Wheatstone bridge.

[0019] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the conductive silver paste is configured to fix the metal pins to the pads by high-temperature sintering and curing.

[0020] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the high-temperature pressure sensor is a leadless package, and the pad is electrically connected to the varistor through the conductive doped polysilicon in the second contact hole.

[0021] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the side of the substrate surface away from the buried oxide layer is configured to be thinned before the back cavity is opened.

[0022] As a preferred embodiment of the high-temperature pressure sensor described in this invention, the passivation layer covers the surface of the second insulating layer and fills the isolation channel. The surface of the passivation layer is patterned to form an electrode isolation channel and a first contact hole. The position of the passivation layer surface exposed by the second insulating layer is further etched to form a second contact hole. The second contact hole sequentially penetrates the second insulating layer and the first insulating layer to connect with the doped layer.

[0023] On the one hand, the present invention also provides a method for manufacturing a high-temperature pressure sensor, specifically including the following steps: S1. Prepare a thin-film SOI wafer, which includes a substrate layer, a buried oxide layer, and an SOI device layer. S2 and SOI device layers are doped with concentrated boron through ion implantation or diffusion processes. S3. Pattern the surface of the SOI wafer near the SOI device layer and etch out multiple isolation channels. The multiple isolation channels divide the SOI wafer surface into varistors and sealing terminals. S4. A first insulating layer is deposited on the surface of the SOI device layer and the inner surface of the isolation channel; S5. A second insulating layer is deposited on the surface of the first insulating layer to form a second insulating layer; S6. A passivation layer is deposited on the surface of the second insulating layer. The surface of the passivation layer is patterned. An electrode isolation channel and a first contact hole are etched in the area corresponding to the sealing end area on the surface of the passivation layer. The electrode isolation channel and the first contact hole pass through the passivation layer and are connected to the second insulating layer. S7. Pattern the exposed surface of the second insulating layer on the passivation layer surface and etch to obtain the second contact hole. The second contact hole passes through the second insulating layer and the first insulating layer in sequence until it is connected to the doped layer. S8. A polycrystalline silicon layer is deposited and grown on the surface of the passivation layer, and the polycrystalline silicon layer is heavily doped with P-type through a doping process; then the surface of the polycrystalline silicon layer is patterned to remove the polycrystalline silicon layer in the cavity region and the electrode isolation channel. S9. Remove the passivation layer in the cavity area by wet etching; S10. A conductive metal film is sputtered onto the surface of the polysilicon layer to fill the first and second contact holes with conductive metal, and the conductive metal film is patterned to form pads on the surface of the polysilicon layer. S11. Prepare another piece of borosilicate glass; make through-holes on the surface of the borosilicate glass at positions corresponding to the first and second contact holes. After the through-holes are made, bond the borosilicate glass to the surface of the polycrystalline silicon layer. The borosilicate glass closes the cavity area into a closed cavity. The through-holes correspond to the second contact holes. S12. A metal pin is inserted into the glass through hole and filled with conductive silver paste. The conductive silver paste is sintered and cured to fix the metal pin to the pad and make an electrical connection. The metal pin is electrically interconnected with the varistor.

[0024] Compared with the prior art, the present invention has at least one or more of the following beneficial effects: This invention employs an SOI wafer design, in which the substrate layer and the SOI device layer are isolated by a buried oxide layer. The resistivity of silicon oxide in the buried oxide layer is much higher than that of silicon at high temperatures, which isolates the SOI device layer from the substrate layer, eliminating the PN junction between them. This avoids sensor failure caused by excessive leakage current due to the PN junction at high temperatures. Through this structural design, the high-temperature pressure sensor of this patent can operate at extremely high temperatures.

[0025] By etching the SOI device layer, buried oxide layer, and part of the substrate layer to form a varistor, the resulting varistor has increased protrusion and stress, thereby improving the output signal and reducing nonlinearity.

[0026] The passivation layer uses silicon oxide as a sacrificial layer and heavily doped polycrystalline silicon as the interface for anodic bonding. It cleverly utilizes the characteristic that polycrystalline silicon is not corroded by BOE (ammonium fluoride and hydrofluoric acid etching solution), realizing the structure release process at a very low cost, avoiding the corrosion of SOI wafers, and greatly simplifying the processing technology.

[0027] By filling the glass through-holes in borosilicate glass with conductive paste to fix the pads to the metal pins, the traditional wire bonding is replaced, thus avoiding the failure of the sensor due to the bonding point breaking caused by high temperature.

[0028] The sensor substrate is pressed on the back side, and the varistor is sealed and protected by the substrate layer, the first insulating layer, the second insulating layer and the borosilicate glass. This isolates the varistor from the working environment, making it less susceptible to external environmental interference, increasing its accuracy and extending the device's lifespan.

[0029] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0030] To more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 2 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 3 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 4 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 5 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 6 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 7 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 8 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 9 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 10 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 11 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 12 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 13 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 14 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 15 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 16 This is a cross-sectional structural schematic diagram of an embodiment of the high-temperature pressure sensor of the present invention; Figure 17 This is a top view of an embodiment of the high-temperature pressure sensor described in this invention.

[0032] Among them, 1-substrate layer, 2-buried oxide layer, 3-SOI device layer, 4-doped layer, 5-varistor, 6-sealing terminal, 7-isolation channel, 8-first insulating layer, 9-second insulating layer, 10-passivation layer, 11-electrode isolation channel, 12-first contact hole, 13-second contact hole, 14-polysilicon layer, 15-cavity, 16-pad, 17-borosilicate glass, 18-glass via, 19-pressure strain film, 20-back island, 21-back cavity, 22-metal pin, 23-conductive silver paste. Detailed Implementation

[0033] The embodiments of the present invention are described in detail below, providing a comprehensive overview and complete description of the technical solutions. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] Please see Figures 1-17 .like Figure 1-17 As shown, this invention provides a high-temperature pressure sensor to address the limitations of traditional pressure sensors in meeting operational requirements under high-temperature and extremely harsh environmental conditions. It includes: The SOI wafer comprises, from bottom to top, a substrate layer 1, a buried oxide layer 2, and an SOI device layer 3. An isolation channel 7 is formed on the surface of the SOI wafer near the SOI device layer 3. The isolation channel 7 passes through the SOI device layer 3, the buried oxide layer 2, and part of the substrate layer 1. At least the SOI device layer 3 is doped to form a doped layer 4. The surface area of ​​the SOI wafer is separated into a cavity region and a sealing end region by the isolation channel 7. Two adjacent isolation channels 7 form a varistor 5, and the varistor 5 is located in the cavity region. The first insulating layer 8 covers the surface of the SOI wafer away from the substrate layer 1 and the inner surface of the isolation channel 7; The second insulating layer 9 covers the surface of the first insulating layer 8; A passivation layer 10 covers the surface of the second insulating layer 9 at a position corresponding to the sealing end area. An electrode isolation channel 11, a first contact hole 12, and a second contact hole 13 are formed on the passivation layer 10. The electrode isolation channel 11 passes through the passivation layer 10 to the second insulating layer 9. The first contact hole 12 passes through the passivation layer to connect with the second insulating layer. The second contact hole 13 passes through the second insulating layer 9 and the first insulating layer 8 in sequence to connect with the doped layer 4. The first contact hole and the second contact hole correspond to each other. The first contact hole and the second contact hole are collectively referred to as contact holes. A polysilicon layer 14 covers the surface of the passivation layer 10. The polysilicon layer 14 is configured to be P-type doped. The second contact hole 13 is filled with conductive doped polysilicon, and the sidewall of the first contact hole has doped polysilicon. Pad 16 is formed on the surface of the polysilicon layer 14 at a position corresponding to the second contact hole 13, and pad 16 is connected to the doped layer 4; Borosilicate glass 17, wherein the borosilicate glass 17 is bonded to the surface of polycrystalline silicon layer 14, which surrounds the cavity region into a closed cavity 15, and a through glass via 18 is formed on the surface of the borosilicate glass 17 at a position corresponding to the pad, and the pad 16 is located in the glass via 18. Metal pin 22, one end of which extends into glass through hole 18, glass through hole 18 is filled with conductive silver paste 23, and metal pin 22 is fixedly electrically connected to pad 16 by sintering and solidifying conductive silver paste 23.

[0035] In a preferred embodiment, the surface of the SOI wafer is divided into a cavity region and a sealing end region, which are isolated by isolation channels 7. The sealing end region serves as the sealing end, and within the cavity region, varistors 5 are formed by adjacent isolation channels 7. In the example, multiple isolation channels 7 divide the surface of the SOI device layer 3 into four varistors 5 and four sealing ends 6, as shown below. Figure 17 As shown, four varistors 5 and four sealing terminals 6 are interconnected through substrate layer 1 to form a Wheatstone bridge. In this example, isolation channel 7 is configured to isolate the cavity region, the sealing terminal region, and other regions on the SOI wafer surface from each other.

[0036] Preferably, the varistor 5 and the sealing terminal 6 are interconnected through the substrate layer 1 to form a Wheatstone bridge.

[0037] Preferably, the SOI device layer 3 is formed into a doped layer 4 by p-type heavy doping, and the doped layer 4 is a heavy doped layer. In this example, the doping element of the doped layer 4 is boron.

[0038] In the example, substrate 1, buried oxide layer 2, and SOI device layer 3 are all configured to be heavily boron-doped by ion implantation or diffusion processes.

[0039] In the example, the SOI wafer is a P-type double-sided polished single-crystal silicon wafer.

[0040] Preferably, the first insulating layer 8 is a silicon oxide thin film. Preferably, the first insulating layer 8 is configured to be formed by chemical vapor deposition.

[0041] Preferably, the second insulating layer 9 is a silicon nitride thin film. Preferably, the second insulating layer 9 is formed on the surface of the first insulating layer 8 by chemical vapor deposition.

[0042] In a preferred embodiment, a back cavity 21 is formed on the surface of the substrate layer 1 away from the buried oxide layer 2. More preferably, back islands 20 are formed between two adjacent back cavities 21. Preferably, the back cavity 21 is disposed on both sides of the substrate layer 1 opposite to the cavity region.

[0043] Preferably, a portion of the substrate layer 1, the buried oxide layer, and a portion of the SOI device layer 3 between the varistor 5 and the back cavity 21 constitute a pressure strain film 19.

[0044] In a preferred embodiment, a passivation layer 10 covers the surface of the second insulating layer 9 and fills the isolation channel 7. The surface of the passivation layer 10 is patterned to form an electrode isolation channel 11 and a first contact hole 12. Further, a second contact hole 13 is formed by etching at the location where the passivation layer 10 exposes the second insulating layer 9. The second contact hole 13 sequentially penetrates the second insulating layer 9 and the first insulating layer 8 until it connects to the doped layer 4. In this example, the second contact hole 13 is formed by further opening a hole based on the first contact hole 12.

[0045] In the example, the first contact hole 12 and the second contact hole 13 together form a contact hole, which sequentially penetrates the passivation layer 10, the second insulating layer 9 and the first insulating layer 8 to connect with the doped layer 4.

[0046] The passivation layer 10 located in the cavity region is removed to form a recessed groove.

[0047] Preferably, a passivation layer 10 is formed on the surface of the second insulating layer 9 by physical vapor deposition.

[0048] Preferably, the passivation layer 10 is polished to form a flat surface for use in the bonding process.

[0049] Preferably, both the electrode isolation channel 11 and the first contact hole 12 are located in the sealing end region. Preferably, the electrode isolation channel 11 and the first contact hole 12 are formed on the surface of the passivation layer 10 by wet etching.

[0050] Preferably, the passivation layer 10 is exposed on the surface of the second insulating layer 9 and the second contact hole 13 is etched out by dry etching.

[0051] Preferably, the passivation layer 10 is a silicon oxide passivation layer.

[0052] In a preferred embodiment, a polysilicon layer 14 is covered on the surface of the SOI wafer near the passivation layer 10. The polysilicon layer 14 is configured to be p-type doped, and the surface of the polysilicon layer 14 is patterned to remove the polysilicon layer 14 in the cavity region and the electrode isolation channel 11. Preferably, after the surface of the polysilicon layer 14 is patterned, the passivation layer 10 in the cavity region is configured to be removed by wet etching to form a cavity 15. The passivation layer 10 in the cavity region includes the passivation layer 10 filled within the isolation channel 7.

[0053] Preferably, after the passivation layer 10 in the cavity region is removed, a conductive metal film is applied to the surface of the polysilicon layer 14, filling the first and second contact holes with conductive metal. A pad is formed on the surface of the polysilicon layer 14 at a position corresponding to the second contact hole 13 by metal stripping. The pad 16 is connected to the doped layer 4. More preferably, the conductive metal film is deposited on the surface of the polysilicon layer 14 by sputtering. More preferably, the high-temperature pressure sensor is a leadless package, and the pad 16 is electrically connected to the varistor 5 through the conductive metal and doped polysilicon within the second contact hole 13.

[0054] Preferably, a polysilicon layer 14 is grown on the surface of the SOI wafer near the passivation layer 10 by chemical vapor deposition. Preferably, the polysilicon layer 14 is configured to be heavily p-type doped by a doping process.

[0055] In a preferred embodiment, the borosilicate glass 17 is bonded and fixed to the surface of the polycrystalline silicon layer 14, which surrounds the cavity region into a closed cavity 15. A through glass via 18 is opened on the surface of the borosilicate glass 17 at the position corresponding to the pad, and the pad 16 is located in the through glass via 18.

[0056] Preferably, the borosilicate glass 17 and the polycrystalline silicon layer 14 are fixedly connected by anodic bonding.

[0057] Preferably, the borosilicate glass 17 is sealed above the cavity region, and the cavity 15 is sealed as a vacuum cavity.

[0058] Preferably, the borosilicate glass 17 is formed with glass through-holes 18 by a sandblasting process. More preferably, the glass through-holes 18 are trapezoidal holes, with the inner diameter of the glass through-holes 18 gradually decreasing from the side of the borosilicate glass 17 closest to the pad 16 toward the side furthest from the pad 16.

[0059] In the example, borosilicate glass 17 is borosilicate glass of model BF 33 or Pyrex 7740.

[0060] In a preferred embodiment, the metal pin 22 is electrically interconnected with the varistor 5.

[0061] Preferably, the main body of the metal pin 22 is Kovar alloy, and the surface of the Kovar alloy is plated with gold, nickel, silver or copper.

[0062] Preferably, the pad 16 is electrically interconnected with the varistor 5 and the package terminal 6 through conductive metal and doped polysilicon.

[0063] Preferably, the metal pins 22 or pads 16 are configured to draw the node voltages of the Wheatstone bridge. Specifically, the metal pins 22, the conductive metal and doped polysilicon in the second contact hole 13, the conductive silver paste 23 in the second contact hole 13, the pads 16, and the sealing terminals 6 are all electrically interconnected.

[0064] Preferably, the conductive silver paste 23 is configured to fix the metal pin 22 to the pad 16 by high-temperature sintering and curing.

[0065] This invention also provides a method for preparing a high-temperature pressure sensor, such as... Figure 1-16 As shown, the specific steps include the following: 1. Prepare a thin-film SOI wafer. The SOI wafer includes a substrate layer 1, a buried oxide layer 2, and an SOI device layer 3, such as... Figure 1 As shown; 2. The surface of SOI device layer 3 is doped with concentrated boron through ion implantation or diffusion processes. SOI device layer 3 is doped into doped layer 4, such as... Figure 2 As shown; preferably, the entire thin-film SOI sheet is doped with boron-permeable elements; 3. Pattern the surface of the SOI wafer closest to SOI device layer 3. Multiple isolation channels 7 are etched on the SOI wafer surface using a dry etching process. These isolation channels 7 divide the wafer into varistors 5 and sealing terminals 6. Figure 3 As shown; 4. A first insulating layer 8 is formed on the surface of SOI device layer 3 and the inner surface of isolation channel 7 by chemical vapor deposition, such as... Figure 4 As shown; 5. A second insulating layer 9 is formed on the surface of the first insulating layer 8 by chemical vapor deposition, such as... Figure 5 As shown; 6. A passivation layer 10 is formed on the surface of the second insulating layer 9 by physical vapor deposition, such as... Figure 6 As shown; the surface of the passivation layer 10 is patterned, and an electrode isolation channel 11 and a first contact hole 12 are etched in the area corresponding to the sealing end 6 on the surface of the passivation layer 10. The electrode isolation channel 11 and the first contact hole 12 pass through the passivation layer 10 and connect to the second insulating layer 9, as shown. Figure 8 As shown; 7. The surface of the exposed second insulating layer 9 on the passivation layer 10 is patterned by dry etching to obtain the second contact hole 13. The second contact hole 13 passes through the second insulating layer 9 and the first insulating layer 8 sequentially until it connects with the doped layer 4, as shown below. Figure 9 As shown; 8. A polysilicon layer 14 is grown on the surface of the passivation layer 10 by chemical vapor deposition, and the polysilicon layer 14 is heavily p-type doped by a doping process; then the surface of the polysilicon layer 14 is patterned, and the polysilicon layer 14 in the cavity region and electrode isolation channel 11 is removed by dry etching, such as... Figure 10 As shown; 9. The passivation layer 10 in the cavity region, including the passivation layer within the isolation channel 7, is removed by wet etching, forming a recessed groove in the cavity region, such as... Figure 11 As shown; 10. A conductive metal thin film is sputtered onto the surface of the polysilicon layer 14, filling the first contact hole 12 and the second contact hole 13 with conductive metal. The conductive metal thin film is then patterned to form pads 16 on the surface of the polysilicon layer. Figure 12 As shown; 11. Prepare another piece of borosilicate glass 17; make through-holes 18 on the surface of the borosilicate glass 17 at positions corresponding to the first contact hole 12 and the second contact hole 13. After the through-holes 18 are made, bond the borosilicate glass 17 to the surface of the polycrystalline silicon layer 14 by anodic bonding. The borosilicate glass 17 closes the recessed groove to form a cavity 15, as shown. Figure 13 As shown; 12. A metal pin 22 is inserted into the glass through-hole 18 and filled with conductive silver paste 23. The conductive silver paste 23 is sintered and cured to fix the metal pin 22 to the pad 16 for electrical connection. Figure 16 As shown, the metal pin 22 is electrically interconnected with the varistor 5.

[0066] Preferably, the metal pin 22 is electrically interconnected with the varistor 5, and the potential difference between the Wheatstone bridge nodes can be derived from the metal pin 22.

[0067] In a preferred embodiment, after the borosilicate glass 17 is bonded to the surface of the polycrystalline silicon layer 14, the surface of the substrate layer 1 away from the buried oxide layer 2 is patterned, that is, a back cavity 21 is formed on the surface of the substrate layer 1 away from the buried oxide layer 2 by deep silicon etching. Back islands 20 are formed between each pair of adjacent back cavities. The back islands 20 and back cavities 21 correspond to the cavity regions of the SOI wafer, such as... Figure 15 As shown.

[0068] In the example, the top layer of SOI device layer 3, buried oxide layer 2 and substrate layer 1 between varistor 5 and back cavity 21 constitutes a pressure strain film 19.

[0069] More preferably, before patterning the surface of substrate 1 away from buried oxide layer 2, the surface of substrate 1 away from buried oxide layer 2 is first thinned, such as... Figure 14 As shown, the thickness of substrate 1 is reduced.

[0070] Preferably, the thin-film SOI wafer is a double-sided polished P-type single-crystal silicon wafer.

[0071] In the example, the surface of layer 3 of the SOI device is doped with concentrated boron through ion implantation or diffusion processes, and the entire thin-film SOI wafer is fully doped to obtain a boron-doped SOI wafer.

[0072] Preferably, the varistor 5 and the sealing terminal 6 are interconnected through the substrate layer 1 to form a Wheatstone bridge. In the example, the varistor 5 and the sealing terminal 6 are isolated from the surrounding heavily doped SOI device layer 3 by isolation channels 7, and the varistor 5 and the sealing terminal 6 are interconnected through the substrate layer 1 to form a Wheatstone bridge. In the example, multiple isolation channels 7 divide the surface of the SOI device layer 3 into four varistor 5 and four sealing terminals 6, such as... Figure 17 As shown, four varistors 5 and four sealing terminals 6 are interconnected through the substrate layer 1 to form a Wheatstone bridge.

[0073] In the example, the varistor 5 includes an SOI device layer 3, a buried oxide layer 2, and a portion of the substrate layer 1 between two adjacent isolation channels 7.

[0074] In the example, the first insulating layer 8 is a silicon oxide thin film.

[0075] In the example, the second insulating layer 9 is a silicon nitride thin film.

[0076] Preferably, the passivation layer 10 is polished to form a smooth surface, such as... Figure 7 As shown. More preferably, the surface of the passivation layer 10 is formed into a highly flat plane by chemical mechanical polishing for use in the bonding process.

[0077] Preferably, the electrode isolation channel 11 and the first contact hole 12 are etched out by wet etching in the area corresponding to the sealing end 6 on the surface of the passivation layer 10.

[0078] In the example, borosilicate glass 17 is borosilicate glass of model BF 33 or Pyrex 7740.

[0079] Preferably, when the borosilicate glass 17 is bonded to the surface of the polycrystalline silicon layer 14, the borosilicate glass 17 seals the recessed groove to form a cavity 15, and the cavity 15 is a vacuum cavity.

[0080] The working principle of this invention is as follows: When the pressure to be measured is applied to the back of the SOI sheet, the pressure strain film deforms. The resistance of the piezoresistor 5 on the pressure strain film changes due to the strain of the pressure strain film. The change of the piezoresistor 5 is detected by detecting the potential difference between the nodes of the Wheatstone bridge. Since the output voltage of the Wheatstone bridge is proportional to the pressure to be measured, the magnitude of the pressure to be measured can be determined based on the magnitude of the output voltage.

[0081] Unless otherwise specified, the features described in the above embodiments or embodiments can be combined with each other in any way.

[0082] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0083] Although embodiments of the invention have been shown and described above, it is to be understood that these embodiments are exemplary, and it will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A high-temperature pressure sensor, characterized in that, It includes: The SOI wafer comprises, from bottom to top, a substrate layer (1), a buried oxide layer (2), and an SOI device layer (3). An isolation channel (7) is provided on the surface of the SOI wafer near the SOI device layer (3). The isolation channel (7) passes through the SOI device layer (3), the buried oxide layer (2), and part of the substrate layer (1) in sequence. At least the SOI device layer (3) is doped to form a doped layer (4). The surface area of ​​the SOI wafer is separated into a cavity area and a sealing end area by the isolation channel (7). Two adjacent isolation channels (7) form a varistor (5). The varistor (5) is located in the cavity area. A first insulating layer (8) covers the surface of the SOI wafer away from the substrate layer (1) and the inner surface of the isolation channel (7); The second insulating layer (9) covers the surface of the first insulating layer (8); A passivation layer (10) is provided on the surface of the second insulating layer (9) at the position corresponding to the sealing end area. An electrode isolation channel (11), a first contact hole (12) and a second contact hole (13) are provided on the passivation layer (10). The electrode isolation channel (11) passes through the passivation layer (10) to the second insulating layer (9). The first contact hole (12) passes through the passivation layer (10) to be connected to the second insulating layer (9). The second contact hole (13) passes through the second insulating layer (9) and the first insulating layer (8) in sequence to be connected to the doped layer (4). The first contact hole (12) and the second contact hole (13) correspond to each other. The first contact hole (12) and the second contact hole (13) are collectively referred to as contact holes. A polysilicon layer (14) covers the surface of the passivation layer (10), the polysilicon layer (14) is configured to be P-type doped, the second contact hole (13) is filled with conductive doped polysilicon, and the sidewall of the first contact hole has doped polysilicon. A pad (16) is formed on the surface of the polysilicon layer (14) at a position corresponding to the second contact hole (13), and the pad (16) is electrically connected to the doped layer (4); Borosilicate glass (17), wherein the borosilicate glass (17) is bonded to the surface of the polycrystalline silicon layer (14), which encloses the cavity region into a closed cavity (15), and a through glass via (18) is provided on the surface of the borosilicate glass (17) at the position corresponding to the pad, and the pad (16) is located in the through glass via (18). Metal pin (22), one end of which extends into glass through hole (18), glass through hole (18) is filled with conductive silver paste (23), and metal pin (22) is fixedly electrically connected to pad (16) by sintering and solidification of conductive silver paste (23).

2. The high-temperature pressure sensor according to claim 1, characterized in that, The substrate (1) has a back cavity (21) on the side surface away from the buried oxide layer (2), and a back island (20) is formed between two adjacent back cavities (21). The back cavities (21) are arranged opposite to the cavity area on both sides of the substrate (1).

3. The high-temperature pressure sensor according to claim 2, characterized in that, The partial substrate layer (1), buried oxide layer and partial SOI device layer between the varistor (5) and the back cavity (21) constitute a pressure strain film (19).

4. The high-temperature pressure sensor according to claim 1, characterized in that, Borosilicate glass (17) is anodicly bonded to the surface of polycrystalline silicon layer (14); and / or Borosilicate glass (17) is sealed above the cavity area, and the cavity (15) is sealed as a vacuum cavity.

5. The high-temperature pressure sensor according to claim 1, characterized in that, The main body of the metal pin (22) is Kovar alloy, and the surface of the Kovar alloy is plated with gold, nickel, silver or copper.

6. The high-temperature pressure sensor according to claim 1, characterized in that, The glass via (18) is a trapezoidal hole, with the inner diameter of the glass via (18) gradually decreasing from the side of the borosilicate glass (17) close to the pad (16) toward the direction away from the pad (16).

7. The high-temperature pressure sensor according to claim 1, characterized in that, The first insulating layer (8) is a silicon oxide thin film; and / or The second insulating layer (9) is a silicon nitride thin film; and / or The passivation layer (10) is a silicon oxide passivation layer; and / or The passivation layer (10) is polished to form a smooth surface.

8. The high-temperature pressure sensor according to claim 1, characterized in that, The sealing end area is the sealing end (6), and the varistor (5) and the sealing end (6) form a Wheatstone bridge; and / or The metal pins (22) or pads (16) are configured to draw the node voltages of the Wheatstone bridge.

9. The high-temperature pressure sensor according to claim 1, characterized in that, Conductive silver paste (23) is configured to fix the metal pin (22) to the pad (16) by high-temperature sintering and curing; and / or The high-temperature pressure sensor is a leadless package, and the pad (16) is electrically connected to the varistor (5) through the conductive doped polysilicon in the second contact hole (13).

10. A method for manufacturing a high-temperature pressure sensor as described in any one of claims 1-9, characterized in that, Specifically, the steps include the following: S1. Prepare a thin film SOI wafer, which includes a substrate layer (1), a buried oxide layer (2), and an SOI device layer (3). S2, SOI device layer (3) surface is doped with concentrated boron by ion implantation or diffusion process; S3. Pattern the surface of the SOI wafer close to the SOI device layer (3) and etch out multiple isolation channels (7). The multiple isolation channels (7) divide the SOI wafer surface into varistors (5) and sealing terminals (6). S4. A first insulating layer (8) is deposited on the surface of the SOI device layer (3) and the inner surface of the isolation channel (7); S5. A second insulating layer (9) is deposited on the surface of the first insulating layer (8); S6. A passivation layer (10) is deposited on the surface of the second insulating layer (9). The surface of the passivation layer (10) is patterned. An electrode isolation channel (11) and a first contact hole (12) are etched in the area corresponding to the sealing end area on the surface of the passivation layer (10). The electrode isolation channel (11) and the first contact hole (12) pass through the passivation layer (10) and are connected to the second insulating layer (9). S7. Pattern the exposed surface of the second insulating layer (9) on the surface of the passivation layer (10) and etch to obtain the second contact hole (13). The second contact hole (13) passes through the second insulating layer (9) and the first insulating layer (8) in sequence and is connected to the doped layer (4). S8. A polysilicon layer (14) is deposited and grown on the surface of the passivation layer (10), and the polysilicon layer (14) is heavily doped with P-type by a doping process; then the surface of the polysilicon layer (14) is patterned to remove the polysilicon layer (14) in the cavity region and the electrode isolation channel (11). S9. Remove the passivation layer in the cavity area by wet etching (10). S10. A conductive metal film is sputtered on the surface of the polysilicon layer (14) to fill the first contact hole (12) and the second contact hole (13) with conductive metal, and the conductive metal film is patterned to form a pad (16) on the surface of the polysilicon layer. S11. Prepare another piece of borosilicate glass (17); make a through glass hole (18) on the surface of the borosilicate glass (17) at the position corresponding to the first contact hole (12) and the second contact hole (13). After the glass through hole (18) is made, bond the borosilicate glass (17) to the surface of the polycrystalline silicon layer (14). The borosilicate glass (17) closes the cavity area into a closed cavity (15). The glass through hole (18) corresponds to the second contact hole (13). S12. A metal pin (22) is inserted into the glass through hole (18) and filled with conductive silver paste (23). The conductive silver paste (23) is sintered and solidified to fix the metal pin (22) to the pad (16) and make it electrically connected. The metal pin (22) is electrically interconnected with the varistor (5).

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