Method and system for testing short-circuit robustness of silicon carbide device degraded based on grid stress

Abstract

The invention relates to the technical field of reliability testing of semiconductor power devices, and discloses a short-circuit robustness testing method and system based on grid stress degradation of a silicon carbide device, and the method comprises the steps of pre-testing short circuit, grid stress application and post-testing short circuit are continuously executed under the same physical connection by configuring a coupling testing time sequence. The control unit cooperates with the driving unit to generate a static positive and negative bias and dynamic switch stress mode, and cooperates with the power loop auxiliary switch action to simulate different short circuit faults. A dynamic and static index correlation model is established to quantitatively evaluate robustness by collecting transient waveforms and measuring static parameters and calculating short-circuit energy integral, threshold voltage and drift distance of on resistance. According to the invention, the in-situ test of the aging and short-circuit characteristics of the device is realized, the contact resistance change and the loop parasitic parameter difference caused by the repeated disassembly and assembly of the device in the traditional discrete test are eliminated, and the change of the two short-circuit waveforms completely corresponds to the internal degradation of the device caused by the grid stress.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device reliability testing technology, specifically to a method and system for testing the short-circuit robustness of silicon carbide devices based on gate stress degradation. Background Technology

[0002] Silicon carbide (SiC) power MOSFETs have become core power devices in electric vehicles, photovoltaic inverters, and rail transportation due to their high voltage withstand capability, high switching speed, and high temperature resistance. However, limited by current material growth and device manufacturing processes, the gate oxide interface quality of SiC MOSFETs is relatively poor, making them susceptible to degradation phenomena such as threshold voltage drift under electrothermal stress during long-term operation. Furthermore, because SiC chips have higher power density and lower heat capacity, their short-circuit withstand time (SCWT) is typically significantly lower than that of comparable silicon-based devices, making short-circuit robustness a key reliability indicator restricting their widespread application.

[0003] In real-world applications, power devices often experience sudden short-circuit failures only after undergoing prolonged gate stress aging. Therefore, assessing the evolution of short-circuit robustness under gate degradation is crucial for predicting the device's safety throughout its entire lifecycle. However, existing testing technologies typically separate gate reliability testing (such as high-temperature gate bias (HTGB) testing) from dynamic short-circuit testing into two independent experimental stages. Traditional testing procedures require applying prolonged stress to the device on a dedicated aging device, and then, after the stress has dissipated, transferring the device to a short-circuit test platform for ultimate capability testing.

[0004] This discrete testing method has technical drawbacks. First, silicon carbide devices have extremely fast switching speeds and are highly sensitive to parasitic inductance and contact resistance in the test circuit. During device transfer between different devices, changes in contact state and differences in parasitic parameters are inevitably introduced. The turn-off current change rate of silicon carbide MOSFETs is extremely high, typically reaching 3-5 A / ns or even higher. This means that even minute differences in parasitic inductance in the circuit can be amplified into voltage overshoot by the extremely high turn-off current change rate. This external variable, not inherent to the device itself, severely interferes with the observation of the short-circuit current waveform, making it impossible to accurately distinguish whether changes in short-circuit characteristics stem from internal parameter drift caused by gate aging or from errors due to changes in the test environment, thus hindering accurate in-situ comparison. Second, existing short-circuit testing equipment is typically single-function, lacking flexible and precise gate control capabilities. It is difficult to simulate complex aging scenarios, including static bias and dynamic switching, during testing, and it cannot cover various fault types such as hard-switching short circuits and load-side short circuits.

[0005] Existing technologies mostly focus on the qualification of a single indicator, lacking a systematic approach to quantitatively establish the mapping relationship between the microscopic degradation of static parameters such as threshold voltage and on-resistance and the changes in macroscopic dynamic indicators such as short-circuit peak current and dissipated energy. This makes it difficult to deeply reveal the impact mechanism of aging on the safe operating area of ​​devices. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a method and system for testing the short-circuit robustness of silicon carbide devices based on gate stress degradation. This solves the problem in existing technologies where gate reliability stress testing and short-circuit limit capability testing are disconnected, making it impossible to evaluate the evolution of dynamic short-circuit characteristics and failure mechanisms of devices after gate degradation in situ under consistent parasitic parameter conditions.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] This invention proposes a testing method implemented through timing logic control within a unified hardware architecture. This method first relies on an integrated testing system that physically integrates timing control, gate drive modulation, and high-voltage power circuitry, eliminating the test environment differences caused by equipment replacement in traditional discrete testing. Based on this hardware foundation, the core of this invention lies in implementing a front-to-back coupling test logic through control units such as FPGAs. This means that while maintaining the physical connections and thermal state of the device under test (DUT) unchanged, a complete sequence of baseline short-circuit characterization, gate stress degradation, and final-state short-circuit characterization is continuously executed according to a specific timeline.

[0009] In terms of specific operation, this invention coordinates the actions of the gate drive unit and the power circuit unit by outputting programmable pulse signals through the control unit. Before applying stress, the system first controls the device under test (DUT) to short-circuit under a set bus voltage, capturing the transient waveform of the device at this time as a reference. Subsequently, the system seamlessly switches to stress application mode, using the voltage regulation module integrated inside the gate drive unit to inject a preset electrical stress into the gate of the DUT. This stress application is not a simple switching action, but rather a simulation of specific aging conditions faced by the device during long-term service. When the preset stress accumulation reaches the required level, the system automatically switches back to short-circuit test mode and triggers the short-circuit action again. Through this in-situ testing method, it can be ensured that there is no interference from other environmental variables between the two short-circuit tests, except for the degradation of gate characteristics.

[0010] Preferably, to comprehensively simulate different types of gate failure mechanisms, the gate drive unit in this method is configured to output various stress waveforms. For the positive bias temperature instability (PBTI) effect, the drive unit can lock the output to a constant DC level higher than the device threshold voltage through an internal positive voltage regulation circuit; for the negative bias temperature instability (NBTI) effect, it locks the output to a constant negative voltage level; for dynamic switching stress (GSS), the drive unit continuously flips the level according to a set high-frequency duty cycle. This flexible stress configuration allows the test method to adapt to the aging simulation needs of different application scenarios.

[0011] In one specific embodiment, the present invention can reproduce two typical short-circuit fault conditions. By controlling the on / off timing of the auxiliary switch in the power circuit, the system can simulate both a hard-switching short circuit caused by the device under test (DUT) being directly turned on under high voltage (Type I short circuit) and a sudden short circuit caused by a load-side fault during the DUT's conduction operation (Type II short circuit). This topology control capability ensures that the test data covers the main fault types that the device may encounter in actual applications.

[0012] Preferably, this invention emphasizes the precise controllability of the test timing. For the dynamic gate switching stress mode, the control logic strictly defines the time window between the short-circuit pulse and the stress pulse sequence, and avoids transient interference during mode switching by using preset delay parameters. Similarly, for the static bias stress mode, the system also ensures the precise connection between the DC bias application duration and the preceding and following short-circuit actions on the time axis through strict timing definitions.

[0013] Preferably, to ensure the accuracy of the test conditions, this method includes a calibration step for the hardware electrical parameters before the formal execution of the coupling sequence. This involves precise adjustment of the gate drive voltage level and matching adjustment of the gate resistance, thereby ensuring that the switching speed and driving capability of the device under test meet the experimentally preset boundary conditions.

[0014] Preferably, the data acquisition mechanism of this invention focuses on the synchronous recording of energy and waveform. Through coaxial shunts and differential probes arranged at key nodes in the power circuit, the system can simultaneously acquire high-bandwidth drain-source voltage, current, and gate signals. Based on this transient data, energy dissipation in a single short-circuit event can be directly quantified through integration, providing a data foundation for thermal failure analysis.

[0015] Preferably, to establish the link between microscopic parameter degradation and macroscopic fault tolerance, this method introduces static parameter scanning as an auxiliary means. At the beginning and end of the dynamic test sequence, a high-precision semiconductor parameter analyzer is used, and the threshold voltage and on-resistance of the device are extracted respectively under the safe condition of disconnecting the high-voltage main circuit. This step aims to capture the physical changes in the internal transistor structure of the device.

[0016] Preferably, based on the data collected above, this invention establishes a quantitative evaluation model. This model calculates the threshold voltage drift and the rate of change of on-resistance, and establishes a mapping relationship between these and the peak current change observed during short-circuit testing. This correlation analysis reveals how changes in the gate oxide interface states specifically affect the device's ability to limit short-circuit current, thereby achieving a dynamic evaluation of the device's short-circuit robustness.

[0017] Preferably, this method also integrates strict temperature field control. Throughout the entire test cycle, the case temperature of the device under test is maintained constant by an external temperature control device, ensuring that all changes in electrical parameters originate from internal device degradation caused by gate stress, rather than thermal drift caused by ambient temperature fluctuations, further improving the reliability of the evaluation results.

[0018] This invention provides a method and system for testing the short-circuit robustness of silicon carbide devices based on gate stress degradation. It has the following beneficial effects:

[0019] 1. This invention, by configuring the coupling test timing, continuously executes the pre-test short circuit, gate stress application, and post-test short circuit steps under the same physical connection and thermal equilibrium state, realizing in-situ testing of device aging and short circuit characteristics. This eliminates the contact resistance changes and loop parasitic parameter differences caused by multiple device disassembly and assembly in traditional discrete testing, ensuring that the changes in the short circuit waveforms before and after the test completely correspond to the internal device degradation caused by gate stress. This ensures the accuracy and consistency of data when evaluating the impact of gate aging on short circuit robustness.

[0020] 2. This invention utilizes the collaboration between the control unit and the programmable gate drive unit to flexibly generate various gate stress modes such as static positive and negative bias and dynamic switching. Combined with the timing control of the auxiliary switch in the power circuit, it covers the first and second types of short-circuit conditions. This enables the test method to fully reproduce the specific aging mechanisms and fault types that silicon carbide devices may face in different practical application scenarios, providing a more complete experimental condition coverage for device reliability screening.

[0021] 3. This invention establishes a correlation evaluation model between static parameter drift and dynamic short-circuit index changes. By quantitatively analyzing the mapping relationship between threshold voltage drift and on-resistance change rate with short-circuit peak current and dissipated energy, it reveals the specific impact mechanism of gate oxide interface state degradation on the device's short-circuit safe operating area. This overcomes the limitation of traditional testing that only focuses on a single failure point, and can quantitatively characterize the functional relationship between the degree of device performance degradation and the decrease in short-circuit tolerance, providing data support for predicting the safety of the device throughout its entire life cycle. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0023] Figure 2 A schematic diagram of the test preparation, drive adjustment and environmental control process of the present invention;

[0024] Figure 3 This is a schematic diagram of the data acquisition, calculation, and robustness evaluation logic flow of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] See attached document Figure 1 This invention provides a method and system for testing the short-circuit robustness of silicon carbide devices based on gate stress degradation. The testing system mainly includes a control unit, a gate drive unit, a power loop unit, and a measurement unit. The output terminal of the control unit is electrically connected to the signal input terminal of the gate drive unit, and the drive output terminal of the gate drive unit is electrically connected to the gates of multiple switching devices in the power loop unit. The probe of the measurement unit is connected to a key node of the power loop unit and transmits the acquired data to a host computer or oscilloscope for processing.

[0027] The control unit uses a Field-Programmable Gate Array (FPGA) as its core controller. Internally, the control unit stores preset coupling test timing logic, configured to generate multiple independent digital pulse signals. These signals include enable signals for controlling the on / off state of auxiliary switches and modulation signals for controlling the gate state of the device under test. The control unit connects to the gate drive unit via an electrically isolated digital interface to achieve electrical isolation between the low-voltage control side and the high-voltage power side.

[0028] Specifically, to suppress the coupling effect of high-frequency common-mode interference generated by the high-speed switching of silicon carbide devices on the control signal, optical fiber is preferably used as the signal transmission medium between the control unit and the gate drive unit. The output port of the control unit is connected to an optical transmitting module, which converts the electrical pulse signal into an optical signal; the input port of the gate drive unit is connected to an optical receiving module, which restores the received optical signal to an electrical signal. This optical fiber link provides electrical isolation up to kilovolts (kV) and cuts off the conduction path between the control-side ground loop and the power-side ground loop, ensuring that high voltage will not backflow to the control unit in the event of a short circuit or breakdown in the device under test.

[0029] The gate drive unit is responsible for converting the digital signal output from the control unit into the voltage level signal required to drive the power device. The gate drive unit integrates a positive voltage regulation module and a negative voltage regulation module. The positive voltage regulation module is configured to output an adjustable positive DC voltage to set the device's turn-on voltage or positive bias stress voltage. The negative voltage regulation module is configured to output an adjustable negative DC voltage to set the device's turn-off voltage or negative bias stress voltage. A gate resistor network, consisting of an on-gate resistor and a off-gate resistor, is connected in series in the output circuit of the gate drive unit to adjust the switching speed of the device under test.

[0030] The power loop unit constitutes the main current path of the test system. This power loop unit includes a high-voltage DC power supply, a DC bus capacitor, a first auxiliary switch, a second auxiliary switch, a load inductor, a device under test (DUT), and a coaxial shunt. The positive terminal of the high-voltage DC power supply is connected to the positive terminal of the DC bus capacitor, and the negative terminal is connected to the negative terminal of the DC bus capacitor and grounded. The collector of the first auxiliary switch is connected to the positive terminal of the DC bus capacitor. The emitter of the first auxiliary switch is connected via a wire to one end of the load inductor and one end of the second auxiliary switch. The other end of the load inductor and the other end of the second auxiliary switch are connected to the drain of the DUT. The source of the DUT is connected to the input of the coaxial shunt, and the output of the coaxial shunt is connected back to the negative terminal of the DC bus capacitor.

[0031] In terms of physical layout, the power circuit units are connected using a multilayer busbar technology. The positive and negative terminals of the DC bus capacitor are connected to the top and bottom copper plates of the multilayer busbar, respectively, with a polyimide insulating dielectric layer sandwiched between the two copper plates. The first auxiliary switch, the second auxiliary switch, and the device under test (DUT) are directly bolted to the multilayer busbar in a compact layout. This parallel-plate structure utilizes the proximity effect of high-frequency currents, causing the magnetic flux generated by the forward current path and the return current path to cancel each other out, thereby minimizing the total stray inductance of the circuit to the order of tens of nanohenries (nH). The low inductance design is crucial for capturing the true short-circuit current rise rate and preventing overvoltage breakdown during turn-off.

[0032] In this circuit topology, the first auxiliary switch acts as a high-side protection switch, controlling the connection and disconnection of the bus voltage. The second auxiliary switch is connected in parallel with the load inductor and configured as a bypass switch. During a Type II short-circuit test, the second auxiliary switch is turned on to short-circuit the load inductor. The parasitic inductance parameters present in the entire power loop affect the short-circuit transient process. According to Kirchhoff's voltage law, the voltage balance relationship of the power loop during the short circuit is as follows:

[0033] ;

[0034] in, This indicates the DC bus voltage value output by the high-voltage DC power supply; This represents the instantaneous voltage between the drain and source of the device under test. This represents the total stray inductance value of a power loop unit, including wire inductance and device package inductance. This represents the instantaneous value of the current flowing between the drain and source of the device under test; This represents the rate of change of short-circuit current over time. This represents the instantaneous voltage drop across the coaxial shunt.

[0035] The driving circuit formed by the gate driving unit and the gate of the device under test also follows Kirchhoff's voltage law, and its voltage balance relationship is shown in the following equation:

[0036] ;

[0037] in, This represents the instantaneous voltage between the gate and source of the device under test. This indicates the value of the drive source voltage output by the gate drive unit; This indicates the resistance value of the gate-on or gate-off resistor. This represents the instantaneous value of the gate current flowing through the gate circuit; This represents the total parasitic inductance of the drive circuit.

[0038] The measurement unit includes a high-bandwidth oscilloscope, a differential high-voltage probe, a differential voltage probe, and BNC signal lines connected to both ends of the coaxial shunt. The two inputs of the differential high-voltage probe are connected to the drain and source of the device under test (DUT), respectively, to acquire the drain-source voltage signal. The two inputs of the differential voltage probe are connected to the gate and source of the DUT, respectively, to acquire the gate-source voltage signal. The BNC signal lines transmit the voltage signal from the coaxial shunt to the high-bandwidth oscilloscope to characterize the drain-source current signal. Additionally, the system includes a temperature controller, whose heating element is in close contact with the heat sink of the DUT to regulate and maintain the DUT's case temperature.

[0039] See attached document Figure 2After completing the hardware construction and connection of the aforementioned test system, and before formally starting the dynamic coupling test sequence, a series of initialization settings and baseline parameter extractions need to be performed on the system to establish the test boundary conditions and the zero point for data comparison. Specifically, this involves:

[0040] Perform the drive parameter adjustment steps. Turn on the auxiliary power supply of the gate drive unit to put its internal control circuit into standby mode. Set the high-level voltage value of the drive output by adjusting the positive voltage regulator module.

[0041] For typical silicon carbide MOSFET devices, this high-level voltage is typically set between +15V and +V to ensure the device is in a sufficiently enhanced state during turn-on, reducing conduction losses. The low-level voltage of the drive output is set by adjusting the negative voltage regulator module. This low-level voltage is typically set between -2V and -5V to prevent false turn-on due to voltage oscillations caused by the Miller effect or stray inductance during turn-off.

[0042] In one specific embodiment, in order to verify the effectiveness of the test method proposed in this embodiment, a commercial 1200V / 40A silicon carbide planar gate MOSFET was selected as the device under test (DUT) for verification testing.

[0043] The test conditions are configured as follows:

[0044] DC bus voltage: set to 800V;

[0045] Drive voltage: set to -4V / +15V;

[0046] Ambient temperature: maintained at 175℃ by a temperature controller (simulating extreme junction temperature conditions).

[0047] Configure the coupling test timing in the control unit, set the gate stress mode to static positive bias stress (PBTI), the stress voltage to +22V, and the continuous stress application time to 60 minutes.

[0048] Using the testing system of this invention, the pre-test short-circuit waveform and post-test short-circuit waveform were recorded before and after stress application, and key dynamic and static parameters were extracted. The test results are compared in the table below, along with the analysis:

[0049] Table 1. Examples of comparison of dynamic and static parameters before and after gate stress

[0050] Key parameters and indicators Pre-test data Post-test data Change / Drift Threshold voltage 2.50V 2.15V -0.35V Short-circuit peak current 310A 338A +28A Single short circuit energy 0.49J 0.54J +0.05J

[0051] Data analysis and robustness assessment:

[0052] As can be seen from the above measured data, after experiencing high temperature and positive bias gate stress, the device under test exhibits obvious degradation characteristics:

[0053] Static parameter drift: The threshold voltage experienced a negative drift of 0.35V. This indicates that positive charges were trapped at the gate oxide interface or that the channel was more easily turned on due to changes in the interface state density.

[0054] Deterioration of dynamic short-circuit characteristics: Due to the negative drift of the threshold voltage, the effective value of the overdrive voltage of the device increases at the same gate drive voltage (+15V). This directly leads to a surge of 28A in the peak current in the subsequent short-circuit waveform.

[0055] Decreased short-circuit robustness: Increased short-circuit current increases the transient power and total energy dissipation that the device withstands in subsequent short-circuit events. This means the device is closer to the boundary of thermal failure, and its short-circuit withstand time (SCWT) is effectively shortened, resulting in reduced robustness.

[0056] Subsequently, based on the datasheet of the device under test and the preset switching speed requirements, the values ​​of the turn-on and turn-off gate resistors are physically replaced or adjusted. A smaller gate resistor value increases the charging and discharging current of the gate circuit, thereby improving the switching rate of the device, but may also lead to more severe voltage overshoot; a larger gate resistor value acts as a damper, suppressing oscillations. During the test preparation phase, the above driving parameters are verified using a double-pulse test method to ensure that the gate voltage waveform has no undervoltage or overvoltage phenomena, and that the switching transient process meets the test safety margin.

[0057] Perform the temperature control procedure. Fix the device under test (DUT) onto the heating platform of the temperature controller, or place the DUT inside an environmental test chamber. Under closed-loop control with feedback from a thermocouple or thermistor sensor, initiate the heating program to heat the DUT to the preset target case temperature. This target case temperature is typically set to the upper limit of the device's rated operating temperature to simulate the most severe thermal conditions.

[0058] During the heating process, the shell temperature is monitored in real time. When the temperature reaches the set value and the fluctuation within the preset time window is less than a specified threshold, the system is considered to have reached thermal equilibrium. In all subsequent static and dynamic tests, the temperature controller continues to operate to maintain this thermal equilibrium state, thereby eliminating the interference of ambient temperature fluctuations on the experimental data.

[0059] Perform the initial static parameter test procedure. With the high-voltage DC power supply disconnected and the power loop unit completely discharged and isolated from the DC bus capacitor, connect the Kelvin test fixture of the semiconductor parameter analyzer to the gate, source, and drain of the device under test.

[0060] The semiconductor parameter analyzer first executes the threshold voltage scanning mode: the drain-source voltage is fixed at a preset value, the gate-source voltage is scanned, the drain-source current is measured, and the gate-source voltage value corresponding to the drain-source current when the drain-source current reaches the preset judgment current is recorded as the initial threshold voltage.

[0061] Then, the on-resistance scanning mode is executed: the gate-source voltage is fixed at the high driving level, the drain-source voltage is scanned, the drain-source current is measured, and the ratio of drain-source voltage to drain-source current is calculated using Ohm's law and recorded as the initial on-resistance.

[0062] After completing the above tests, disconnect the semiconductor parameter analyzer, restore the high-voltage connection of the power circuit unit, and prepare to enter the dynamic coupling test phase.

[0063] See attached document Figure 1 This section details the core timing logic executed inside the control unit. This core timing logic is pre-programmed using the FPGA's hardware description language (such as Verilog or VHDL) to ensure seamless and precise timeline connection between the three stages of front-side short circuit, gate stress application, and back-side short circuit, without the need for manual intervention or hardware reconnection.

[0064] The control signal sequence output by the control unit is strictly divided into five consecutive intervals on the time axis: the initial short-circuit pulse interval, the first thermal relaxation delay interval, the stress loading interval, the second thermal relaxation delay interval, and the final short-circuit pulse interval.

[0065] First, the system enters the initial short-circuit pulse interval (corresponding to the pre-test short-circuit stage). During this stage, the control unit sends a closing command to the auxiliary switch in the power loop unit to establish a short-circuit path. After the loop state stabilizes, the control unit sends a single high-level pulse signal to the gate drive unit. The duration of this high-level pulse signal is defined as the short-circuit pulse width, typically set to the order of 1 microsecond to microsecond, with the specific value depending on the tolerance level of the device under test (DUT). During this period, the DUT instantly transitions from the off state to the short-circuit on state, enduring high voltage and high current surges. The control unit simultaneously outputs a trigger signal to the measurement unit to capture the reference waveform data during this transient process.

[0066] Immediately afterwards, the timing enters the first thermal relaxation delay interval. After the initial short-circuit pulse ends, the control unit forces the gate drive signal to remain in a low-level off state for a duration defined as follows: The purpose of setting this delay interval is to allow the internal junction temperature of the device under test (DUT) to drop back through the heat dissipation path after experiencing a short-circuit impact and reach thermal equilibrium with the case temperature and the ambient temperature set by the temperature controller. This process eliminates the temperature interference of the short-circuit self-heating effect on the subsequent stress application stage, ensuring that the starting temperature boundary conditions of the stress test are controllable.

[0067] Subsequently, the system automatically enters the stress loading interval (corresponding to the gate stress application stage). During this stage, the control unit switches the signal generation mode according to a pre-configured instruction set. Unlike the single-pulse triggering of the short-circuit stage, the control unit continuously outputs a level signal with specific characteristics during this stage, the duration of which is defined as... This duration is typically much longer than the short-circuit pulse width, ranging from a few seconds to thousands of hours, depending on the requirements of accelerated aging testing. Within this range, the high-voltage DC power supply to the power loop unit can be either kept connected (online stress) or disconnected via an auxiliary switch (offline stress) to isolate the high voltage from unintended interference with the gate aging process.

[0068] When the preset stress application time expires, the timing sequence enters the second thermal relaxation delay interval. The control unit immediately stops the output of the stress signal and clamps the gate drive signal to a low-level off state again. The duration is defined as follows: The second thermal relaxation delay interval is used not only to dissipate Joule heating that may be generated during stress application, but also to allow some recoverable trap charges in the gate oxide layer to be released, thereby filtering out permanent degradation features. Simultaneously, the control unit uses this time to send a reset command to the power circuit unit, re-establishing the high-voltage short-circuit readiness state.

[0069] During the stress loading and thermal relaxation delay periods, the control unit also monitors the gate leakage current signal or auxiliary power supply status fed back by the gate drive unit in real time. If the gate leakage current exceeds a preset safety threshold during the application of gate stress, it indicates that the gate oxide layer of the device under test has undergone irreversible hard breakdown failure. At this time, the protection logic inside the control unit will be triggered, immediately terminating subsequent timing, forcibly blocking all drive outputs, skipping the final short-circuit pulse interval, and directly issuing a device failure alarm to the operator. This active protection mechanism avoids the tube explosion accident that may be caused by performing a high-voltage short-circuit action again when the device has failed.

[0070] Finally, the final short-circuit pulse interval (corresponding to the post-test short-circuit stage) is entered. The control unit generates a single high-level pulse signal again, with its pulse width strictly equal to the initial short-circuit pulse width. The device under test (DUT) performs a short-circuit action again after experiencing gate degradation. At this time, the measurement unit is triggered again to record the transient waveform after aging. The entire coupling test sequence is now completed, the control unit stops outputting, and the system enters standby mode.

[0071] Throughout the timing execution process, the counters and state machines within the control unit operate synchronously with the system clock as the reference, ensuring that the time jitter during switching between each interval is less than nanoseconds, thus guaranteeing the repeatability of the test. Through this strict timing coupling, the device's aging process is embedded between two short-circuit tests, achieving true in-situ characteristic characterization.

[0072] See attached document Figure 1 This section details how the control unit, in conjunction with the gate drive unit, applies three different mechanisms of accelerated degradation stress to the physical gate port of the device under test within the stress loading range. The state machine within the control unit selects one of three modes—static positive bias, static negative bias, and dynamic switching stress—to execute based on a preset test scheme.

[0073] When the test scheme is configured in static positive bias stress mode (corresponding to the positive bias temperature instability PBTI test), the control unit locks its corresponding drive control pin to a continuous logic high level after entering the stress loading range. Upon receiving this high-level command, the gate drive unit controls its internal upper bridge push-pull circuit to conduct, applying the positive DC voltage set by the positive voltage regulator module to the gate of the device under test (DUT) via the gate-on resistor. In this mode, the timing logic within the control unit strictly follows the sequence of the first short-circuit pulse, the first thermal relaxation delay, a constant positive bias voltage of a preset duration, the second thermal relaxation delay, and the second short-circuit pulse. During the constant positive bias period, the channel of the DUT is in a strong inversion layer state, and the gate oxide layer is subjected to a constant positive electric field, prompting electrons to tunnel into the oxide layer traps, thereby simulating the aging state of the device under long-term conduction operation.

[0074] When the test scheme is configured in static negative bias stress mode (corresponding to negative bias temperature instability NBTI test), the control unit locks its drive control pin to a continuous logic low level after entering the stress loading range. The gate drive unit responds to this signal by turning on the lower bridge arm circuit, applying the negative DC voltage (e.g., -5V) set by the negative voltage regulator module to the gate of the device under test via the gate turn-off resistor.

[0075] At this time, the timing logic of the control unit is configured as follows: first short-circuit pulse, first thermal relaxation delay, constant negative bias voltage for a preset duration, second thermal relaxation delay, and second short-circuit pulse. This mode subjects the gate oxide layer to a reverse electric field, which is used to excite hole traps in the oxide layer and dissociate interface states, simulating the reliability degradation of the device in a long-term off state.

[0076] When the test scheme is configured in dynamic gate switching stress mode (corresponding to GSS test), the control unit activates its internal pulse width modulation (PWM) generator. The control unit generates a continuous high-frequency square wave signal based on the preset switching frequency and duty cycle. The gate drive unit follows this high-frequency square wave signal, driving the gate voltage of the device under test to rapidly switch between the high level set by the positive voltage regulation module and the low level set by the negative voltage regulation module.

[0077] In this mode, the timing logic of the control unit executes a sequence of the first short-circuit pulse, the first thermal relaxation delay, a preset number of gate switching stress pulses, the second thermal relaxation delay, and the second short-circuit pulse.

[0078] For the dynamic gate switching stress mode, the control unit precisely controls the total amount of stress applied through an internal pulse counter. When the number of pulses reaches a preset value, the counter overflows and interrupts, immediately stopping the PWM output and entering a delay phase. This dynamic gate switching stress mode utilizes the high-frequency charging and discharging process of the gate circuit parasitic inductance and input capacitance to subject the gate oxide layer to high-frequency voltage overshoot and oscillating stress, while simultaneously causing accumulated Joule heat in the internal gate resistance, thereby simulating gate fatigue failure under high-frequency hard switching conditions. During the execution of the above three modes, the power circuit unit always maintains a physical connection state, ensuring the instantaneity and stability of the test state switching.

[0079] In the pre-test short-circuit phase and post-test short-circuit phase of the above coupling test sequence, the control unit, according to the preset test requirements, precisely controls the conduction sequence of each switching device in the power circuit unit to physically reproduce the first type of short-circuit mode (hard switch short-circuit fault) or the second type of short-circuit mode (load short-circuit fault).

[0080] When executing the Type I short-circuit mode, the test simulates the condition where the device under test (DUT), under high bus voltage off-state, incorrectly receives a turn-on command and directly conducts to the short-circuit loop. The specific circuit operation flow is as follows:

[0081] The control unit outputs a high-level signal to the drive terminal of the first auxiliary switch, causing it to close, thereby connecting the high-voltage DC power supply and the DC bus capacitor to the main circuit.

[0082] The control unit controls the second auxiliary switch to be in the ON state, or the load inductor is directly shorted using a short-circuit busbar in the hardware connection. At this time, the device under test is in the OFF state, and its drain-source voltage is clamped to the DC bus voltage.

[0083] The control unit sends an enable pulse to the device under test (DUT). Since the load has been bypassed, the loop impedance consists only of the resistance of the coaxial shunt and the stray inductance of the loop. At the instant the channel of the DUT is formed, the drain-source current, excited by the bus voltage, rises rapidly at an extremely high rate of increase. At this moment, the DUT instantly enters the saturation region (active region), simultaneously experiencing high voltage and high current, resulting in huge transient power dissipation.

[0084] When executing the Type II short-circuit mode, the test simulates the condition where the device under test (DUT) is operating normally under rated load, and a sudden short-circuit fault occurs at the load end. The specific circuit operation flow is as follows:

[0085] The control unit controls the first auxiliary switch to turn on and the second auxiliary switch to turn off.

[0086] The control unit controls the device under test (DUT) to turn on normally. At this time, the current path flows sequentially through the first auxiliary switch, the load inductor, and the DUT. The DUT operates in the linear region, and the drain-source voltage is maintained at a low on-state voltage drop level. After the loop current reaches the preset rated load current value and stabilizes, the control unit suddenly sends a trigger signal to turn on the second auxiliary switch. The instant the second auxiliary switch turns on, it creates a low-impedance branch, bypassing the load inductor.

[0087] At the instant a Type II short-circuit fault occurs, because the inductive load is short-circuited, almost all of the DC bus voltage is applied across the stray inductance of the loop and the device under test (DUT). The DUT is forced to rapidly exit the low-dropout linear region and enter the high-dropout saturation region; this process is called desaturation.

[0088] During this period, the drain-source voltage surges from the on-state voltage drop to the bus voltage within nanoseconds, while the drain-source current further surges from the original load current to the short-circuit peak current. The control unit, by adjusting the on-time of the second auxiliary switch, can precisely control the initial phase and current reference at the time of a fault, thereby comprehensively evaluating the device's surge resistance during dynamic operation. In both modes, the coaxial shunt is located in the source loop of the device under test, ensuring complete capture of the full current waveform, including channel current and reverse recovery current.

[0089] See attached document Figure 3 This section details how, after completing the above coupling test timing, we can use the waveform data obtained by the measurement unit and the static parameters obtained by the semiconductor parameter analyzer to perform multi-dimensional quantitative analysis and evaluation.

[0090] First, high-precision acquisition of transient waveforms is performed. Under the synchronous triggering of the pre- and post-short-circuit phases in the control unit, a high-bandwidth oscilloscope records the critical electrical quantities in the system at a sampling rate of no less than 1 GS / s. Data acquired using voltage probes connected to both ends of the coaxial shunt is converted to the drain-source current signal using Ohm's law. Due to the extremely low parasitic inductance and high-frequency response of the coaxial shunt, this drain-source current signal can accurately reproduce nanosecond-level current rise edges and oscillation details. The drain-source voltage signal is then acquired using a differential high-voltage probe, which must possess a high common-mode rejection ratio (CMRR) to suppress common-mode interference generated during the high-speed switching of silicon carbide devices.

[0091] Based on the acquired transient waveform data, the measurement unit or host computer processing software performs numerical integration calculations of the short-circuit energy. For each short-circuit event, the short-circuit dissipation energy is obtained by integrating the instantaneous power over the short-circuit duration, as shown in the following formula:

[0092] ;

[0093] in, This indicates the moment when the short-circuit current begins to rise, and is usually defined as the moment when the gate voltage reaches the threshold voltage. This indicates the moment when the short-circuit turn-off process ends and the current drops back to zero. The drain-source current signal is obtained by converting Ohm's law; To acquire the drain-source voltage signal using a differential high-voltage probe.

[0094] Before performing the above integration calculation, the host computer processing software performs inter-channel time delay correction on the acquired raw waveform data. Due to inherent differences in physical length and transmission delay between the differential high-voltage probe and the signal line connecting the coaxial shunt, without correction, the voltage and current waveforms will be misaligned on the time axis, leading to significant errors in instantaneous power calculation. The correction process uses the oscilloscope's built-in calibration source signal to calibrate the transmission delay difference of each probe and performs correction before calculation. and The data array is shifted accordingly to ensure that the two are strictly aligned on a nanosecond-level time base.

[0095] Next, the final-state static parameters are extracted and the drift is calculated. After the dynamic test is completed and the device under test is allowed to cool to room temperature and reach thermal equilibrium, the final-state threshold voltage is measured again according to the static test procedure described in Part II. and final state on-resistance Then, its drift relative to the initial value is calculated:

[0096] ;

[0097] ;

[0098] in, This indicates the threshold voltage drift of the device under test after experiencing gate stress; This represents the initial threshold voltage measured when the device under test is in thermal equilibrium before the coupling test timing is started; This represents the final-state threshold voltage measured after the coupling test sequence ends and the system cools to the same thermal equilibrium state as the initial test. This indicates the percentage change in on-resistance of the device under test after experiencing gate stress. This represents the initial on-resistance measured before the coupling test timing sequence is started; This represents the final on-resistance measured after the coupling test timing sequence has ended.

[0099] Finally, a short-circuit robustness assessment based on parameter mapping is performed. The core of this step lies in establishing a mapping relationship between microscopic physical degradation and macroscopic dynamic performance. The system extracts the peak current from the previous short-circuit waveform and the peak current from the subsequent short-circuit waveform, calculating the degradation magnitude of the short-circuit capability. The assessment logic includes correlation analysis in the following three dimensions:

[0100] The first dimension is the analysis of the impact of threshold voltage drift on short-circuit current. If... A negative drift (typically caused by hole injection or positive charge trapping) leads to an increase in the overdrive voltage of the device at the same gate drive voltage. This results in a significantly higher peak current in the subsequent short-circuit waveform compared to the peak current extracted by the system from the preceding short-circuit waveform. This current increment means that the device will experience a greater thermal shock when a short circuit occurs after aging, reducing the short-circuit withstand time (SCWT) and indicating decreased robustness.

[0101] The second dimension is the analysis of the impact of changes in on-resistance on the thermal integrity of the device. If... A significant positive change typically indicates aging of the device's source lead bonding or metal layer remodeling. During a short circuit, this degradation manifests as increased impedance along the current path. While this may limit the peak short-circuit current, it exacerbates localized heat buildup and increases the risk of thermal escape.

[0102] The third dimension is the overall safe operating area (SOA) assessment. The system compares the calculated short-circuit energy with the critical breakdown energy specified in the device datasheet. If, after applying gate stress, the device does not experience catastrophic failure, but its subsequent short-circuit waveform shows obvious tailing current, a surge in gate leakage current, or irregular changes in turn-on delay time, then the device is determined to have failed in short-circuit robustness after gate stress degradation. Through the above mapping analysis, this invention achieves a shift from a single pass / fail criterion to a quantitative assessment of the degree of degradation and dynamic impact.

Claims

1. A short-circuit robustness test method for silicon carbide devices based on gate stress degradation, characterized in that, Includes the following steps: Step S1: Construct a test system, which includes a control unit, a gate drive unit, and a power loop unit; The power circuit unit includes a DC power supply, a first auxiliary switch, a second auxiliary switch, a device under test, and a current acquisition device for acquiring circuit current. The control unit is connected to the gate driving unit, and the gate driving unit is connected to the first auxiliary switch, the second auxiliary switch and the gate of the device under test, respectively. The power circuit unit adopts the following connection topology: the first auxiliary switch is connected in series between the DC power supply and the drain of the device under test, and is used to control the on / off of the bus voltage; the drain of the device under test is also connected in series with a load inductor; the second auxiliary switch is connected in parallel with the load inductor, and is used to bypass the load inductor. Step S2: Configure the coupling test timing in the control unit. The coupling test timing is defined as three stages executed sequentially under the same physical connection: the front-test short-circuit stage, the gate stress application stage, and the back-test short-circuit stage. Step S3: Start the test system, and the control unit outputs a pulse control signal according to the coupling test timing sequence; During the pre-test short-circuit phase, the device under test is controlled to perform a short-circuit action and the initial short-circuit transient waveform is recorded. During the gate stress application phase, the device under test is controlled to be under continuous gate electrical stress to simulate the aging and degradation process of the device. During the post-test short-circuit phase, the device under test is controlled to perform a short-circuit action again and the degraded short-circuit transient waveform is recorded. Step S4: Compare the initial short-circuit transient waveform with the degraded short-circuit transient waveform to evaluate the short-circuit robustness of the device under test after gate stress degradation.

2. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 1, characterized in that, In step S3, controlling the device under test to be in a continuous gate electrical stress state specifically includes: According to the coupling test timing configured in step S2, the gate driving unit is controlled to apply any one of the following gate stresses to the gate of the device under test: Static positive bias stress: The positive voltage regulation module in the gate drive unit is controlled to continuously output a constant positive bias voltage that is higher than the threshold voltage, corresponding to the positive bias temperature instability test; Static negative bias stress: The negative voltage regulation module in the gate drive unit is controlled to continuously output a constant negative bias voltage, corresponding to the negative bias temperature instability test. Dynamic gate switch stress: The gate drive unit is controlled to alternately output high-level voltage and low-level voltage at a preset frequency and duty cycle, corresponding to the gate switch stress test.

3. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 1, characterized in that, In the pre-test short-circuit stage and the post-test short-circuit stage of step S3, the short-circuit action performed by the device under test includes a first type of short-circuit mode or a second type of short-circuit mode. The execution process of the first type of short circuit mode is as follows: maintain the DC power supply output high voltage, control the first auxiliary switch or external load to be in a short circuit state, and then control the device under test to switch from the off state to the on state, so that the drain source current rises rapidly under the action of stray inductance. The execution process of the second type of short circuit mode is as follows: control the device under test to be in the conducting state and allow the rated load current to flow through it, then control the second auxiliary switch to be turned on and bypass the load, so that the voltage of the device under test is quickly restored to the bus voltage and the drain-source current surges.

4. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 2, characterized in that, When the dynamic gate switch stress mode is selected, the specific configuration logic of the coupling test timing in step S2 is as follows: Set the short-circuit pulse width duration, the total number of pulses in the stress application stage, the switching frequency, the duty cycle, and the delay time between each stage; The control unit generates control signals in the following order: first short-circuit pulse, first preset time delay, preset number of gate switching stress pulses, second preset time delay, and second short-circuit pulse.

5. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 2, characterized in that, When the static positive bias stress mode or the static negative bias stress mode is selected, the specific configuration logic of the coupling test timing in step S2 is as follows: Set the short-circuit pulse width duration, the duration of constant bias stress, and the delay time between each stage; The control unit generates control signals in the following order: first short-circuit pulse, first preset duration delay, constant DC bias voltage for preset duration, second preset duration delay, and second short-circuit pulse.

6. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 1, characterized in that, After constructing the test system in step S1 and before starting the test system in step S3, a drive parameter adjustment step is included, which specifically involves: Turn on the auxiliary power supply of the gate driving unit; Adjust the positive voltage regulation module and negative voltage regulation module inside the gate driving unit to set the high level value and low level value of the driving voltage; Adjust the resistance values ​​of the turn-on gate resistor and the turn-off gate resistor connected in series between the gate drive unit and the gate of the device under test, and set the switching rate of the device under test.

7. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 1, characterized in that, In step S3, recording the initial short-circuit transient waveform and the recorded degraded short-circuit transient waveform specifically includes: The current acquisition device is a coaxial shunt, which is connected in series between the source of the device under test and the negative terminal of the DC power supply. The voltage signal at both ends of the shunt is obtained by using a voltage probe connected to both ends of the coaxial shunt, and the voltage signal is converted into a drain-source current signal. The drain-source voltage signal is acquired using a differential high-voltage probe connected to the drain and source terminals of the device under test. The gate-source voltage signal is acquired using a differential voltage probe connected to the gate and source terminals of the device under test. Based on the collected drain-source voltage signal and drain-source current signal, the product over the short-circuit duration is integrated to calculate the dissipated energy of a single short-circuit event.

8. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 1, characterized in that, It also includes static parameter testing steps: After the test system is constructed in step S1 and before the test system is started in step S3, the device under test is scanned using a semiconductor parameter analyzer to obtain the initial threshold voltage and initial on-resistance. After step S3 is completed, once the device under test has cooled to room temperature, the semiconductor parameter analyzer is used again to perform a final-state static characteristic scan on the device under test to obtain the final-state threshold voltage and the final-state on-resistance. Specifically, during the initial static characteristic scan and the final static characteristic scan, the connection between the DC power supply and the power circuit unit is disconnected.

9. The short-circuit robustness test method for silicon carbide devices based on gate stress degradation according to claim 8, characterized in that, In step S4, the step of evaluating the short-circuit robustness of the device under test after gate stress degradation includes: Calculate the drift of the final threshold voltage relative to the initial threshold voltage; Calculate the rate of change of the final on-resistance relative to the initial on-resistance; A mapping relationship is established between the drift amount and the change in short-circuit peak current in the degraded short-circuit transient waveform to quantify the impact of static parameter degradation caused by gate stress on dynamic short-circuit withstand capability.

10. A short-circuit robustness testing system for silicon carbide devices based on gate stress degradation, characterized in that, include: The power loop unit is configured to provide a test environment for the device under test; The power circuit unit includes a DC power supply, a load inductor, a first auxiliary switch, a second auxiliary switch, a current acquisition device, and an interface for connecting the device under test. The first auxiliary switch is connected in series between the DC power supply and the device under test, and is configured to control the switching on and off of the bus voltage; the second auxiliary switch is connected in parallel with the load inductor, and is configured to control the bypass of the load inductor; the current acquisition device is configured to acquire the loop current flowing through the device under test. A gate driving unit is connected to the gates of the first auxiliary switch, the second auxiliary switch, and the device under test, respectively, and is configured to output a driving voltage signal to control the conduction and turn-off of each switching device; and the gate driving unit is configured with an adjustable positive voltage output module and a negative voltage output module for applying static bias stress or dynamic switching stress to the device under test. The control unit is communicatively connected to the gate driving unit and is configured to store and execute coupling test timing. The coupling test timing configuration is to control the gate drive unit and the power loop unit to continuously perform the following operations under the same physical connection: During the pre-test short-circuit phase, the device under test is controlled to perform a short-circuit action; During the gate stress application phase, the device under test is controlled to be in a continuous gate electrical stress state to simulate aging degradation. During the post-test short-circuit phase, the device under test is controlled to perform a short-circuit action again; The measurement unit, connected to a key node of the power loop unit, is configured to acquire the initial short-circuit transient waveform during the pre-test short-circuit phase and the degraded short-circuit transient waveform during the post-test short-circuit phase. The data processing unit is configured to receive waveform data collected by the measurement unit, calculate and compare the differences between two short-circuit waveforms, and evaluate the short-circuit robustness of the device under test.

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