Chip test system and test method integrated with temperature control

Abstract

The invention discloses an integrated temperature control chip test system and test method, and relates to the technical field of semiconductor test. The system comprises a supporting structure, a plurality of testing units and a plurality of single-chip microcomputers, the testing units are arranged on one side of the supporting structure and comprise mounting structures for mounting chips to be tested and testing circuit boards, heating and temperature sensing elements are integrated in the mounting structures, and the single-chip microcomputers are arranged on the other side of the supporting structure, connected with the testing units in a one-to-one correspondence mode and used for controlling temperature control loops. The supporting structure isolates the testing unit from the single-chip microcomputer in space, normal-temperature testing is carried out after the chip is installed, then heating is started, the temperature is controlled to a preset high temperature, then high-temperature testing is carried out, and the chip does not need to be moved in the whole process. According to the invention, normal temperature and high temperature tests are continuously and seamlessly carried out at the same test position, test scene switching is thoroughly avoided, the test efficiency and reliability are greatly improved, and independent parallel temperature control of multiple chips is supported.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a chip testing system and method with integrated temperature control. Background Technology

[0002] In the research, development, verification, mass production testing, and reliability assessment of semiconductor chips, especially memory chips (such as LPDDR), it is usually necessary to conduct functional and performance tests on the chips under different temperature environments. Among these, high-temperature environment testing is a key step in verifying the thermal reliability of the chips. Traditional high-temperature chip testing solutions typically employ two methods: one is to use a separate high-temperature test chamber, where the entire test board or chip that has completed room-temperature testing is moved into the test chamber for high-temperature testing; the other is to use a dedicated testing machine with a constant-temperature slot.

[0003] However, these existing technical solutions have significant drawbacks: First, they are inefficient. The physical transfer, reinstallation, connection, and temperature stabilization of chips or test boards between room temperature and high-temperature testing environments consume a considerable amount of time, severely slowing down the testing process. Second, they are cumbersome and prone to introducing risks. Frequent plugging and unplugging and movement can damage chip pins, test sockets, or connection interfaces, affecting test reliability and increasing costs. Finally, they lack equipment utilization and flexibility. Independent temperature control devices are often bulky, expensive, and difficult to implement parallel, independent temperature control testing of multiple chips under test.

[0004] Therefore, existing technologies suffer from technical problems such as disjointed testing processes, low efficiency, complex operation, and difficulty in achieving efficient parallel temperature control testing. Summary of the Invention

[0005] This invention provides a chip testing system with integrated temperature control, which solves the problems of low efficiency and cumbersome operation caused by the need to switch test scenarios in chip testing.

[0006] Firstly, a chip testing system with integrated temperature control is provided, comprising: Support structure; Multiple test units are set on one side of the support structure. Each test unit includes a mounting structure for mounting the chip under test and a test circuit board for testing the chip under test. Each mounting structure integrates a heating element and a temperature sensing element. Multiple microcontrollers are located on the other side of the support structure. Each microcontroller is electrically connected to the heating element and temperature sensing element of a test unit. The microcontroller is used to control the working state of the heating element according to the signal from the temperature sensing element. The support structure spatially isolates the test unit from the microcontroller.

[0007] Secondly, a chip testing method with integrated temperature control is provided, which is applied to the aforementioned chip testing system with integrated temperature control. The method includes: The chip under test is installed in the mounting structure of the test unit; With the heating element turned off, the chip under test is tested at room temperature using the test circuit board of the test unit. The microcontroller controls the heating element to turn on, heating the chip under test, and the temperature of the chip under test is collected in real time through the temperature sensing element. Based on the feedback from the temperature sensing element, the temperature of the chip under test is maintained within a preset high temperature range using a heating element. When the chip under test is within a preset high temperature range, a high temperature test is performed on the chip under test using a test circuit board. Among them, the room temperature test and the high temperature test are carried out continuously without the chip under test being moved or reinstalled.

[0008] The aforementioned chip testing system and method with integrated temperature control integrates heating and temperature sensing elements into the mounting structure of each test unit. This miniaturizes and distributes the functions traditionally reliant on external large-scale temperature control equipment, embedding them into each test site in a distributed manner. This physically eliminates the need for transporting the chip between room temperature and high-temperature testing environments. Secondly, the innovative layout of a support structure that spatially isolates the test unit and the microcontroller on opposite sides solves the thermal interference problem caused by integrated heating, ensuring stable operation of the control circuit and providing a reliable foundation for the aforementioned functional integration. Finally, the microcontroller independently controls each heating element based on temperature feedback, achieving precise and rapid closed-loop temperature adjustment at each test site. Therefore, after installation, the chip under test can continuously and automatically complete room temperature and high-temperature tests in the same location and with the same electrical connection state through circuit control alone. This eliminates the time spent on repeated installation, transportation, and waiting for temperature stabilization, allowing for seamless connection of the testing process and significantly improving testing efficiency and equipment utilization. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a chip testing system with integrated temperature control in one embodiment of the present invention.

[0011] Figure 2This is another structural schematic diagram of a chip testing system with integrated temperature control in one embodiment of the present invention.

[0012] Figure 3 This is a schematic diagram of the structure of a test unit in a chip testing system with integrated temperature control according to an embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram of the structure of an adapter board for a chip testing system with integrated temperature control, according to an embodiment of the present invention.

[0014] Figure 5 This is another schematic diagram of the adapter board of the chip testing system with integrated temperature control in one embodiment of the present invention.

[0015] Figure 6 This is a schematic diagram of the structure of the first fixture of a chip testing system with integrated temperature control in one embodiment of the present invention.

[0016] Figure 7 This is another structural schematic diagram of the first fixture of the chip testing system with integrated temperature control in one embodiment of the present invention.

[0017] Figure 8 This is a schematic diagram of the structure of the second fixture of a chip testing system with integrated temperature control in one embodiment of the present invention.

[0018] Figure 9 This is a schematic diagram of the clamping part of a chip testing system with integrated temperature control in one embodiment of the present invention.

[0019] Figure 10 This is a schematic flowchart of a chip testing method integrating temperature control in one embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Please see Figure 1 As shown, Figure 1 This is a schematic diagram of the integrated temperature control chip testing system provided in an embodiment of the present invention. The integrated temperature control chip testing system includes: a support structure 10, multiple testing units 20, and multiple microcontrollers 30.

[0022] Multiple test units 20 are disposed on one side of the support structure 10. Each test unit 20 includes a mounting structure 21 for mounting the chip under test and a test circuit board 22 for testing the chip under test. Each mounting structure 21 integrates a heating element (not shown in the figure) and a temperature sensing element (not shown in the figure). Multiple microcontrollers 30 are disposed on the other side of the support structure 10. Each microcontroller 30 is electrically connected to the heating element and temperature sensing element of one test unit 20. The microcontroller 30 is used to control the working state of the heating element according to the signal from the temperature sensing element. The support structure 10 spatially isolates the test units from the microcontrollers 30.

[0023] Specifically, the support structure 10 is the core skeleton of the system, preferably a plate-shaped component made of aluminum alloy or composite material. It not only provides mechanical support but, more importantly, isolates thermal management and electrical layout. Multiple test units 20 are detachably (e.g., by screw fastening) or fixedly mounted on the first surface 101 (defined as the front) of the support structure 10. Figure 1 As shown, these test units 20 can be arranged in a parallel array. Each test unit 20 is a fully functional test station, its core comprising two parts: first, a mounting structure 21, used for physically supporting and electrically connecting the second chip under test (such as a memory chip); second, a test circuit board 22, which integrates power conversion, signal conditioning circuitry, and a first chip (such as a high-performance SOC chip) serving as the test controller. The mounting structure 21 creatively integrates heating elements and temperature sensing elements. The heating element is preferably a high-temperature resistant thin-film heater or thick-film resistor, attached or embedded in the mounting structure 21 near the chip under test; the temperature sensing element is preferably a fast-responding miniature thermocouple or a high-precision digital temperature sensor (such as a PT100), its sensing end positioned to directly or indirectly sensitively reflect the temperature of the chip under test. On the second surface 102 of the support structure 10 (defined as the back surface, opposite to the first surface 101), multiple microcontrollers 30 are arranged in an array-like manner. The number of microcontrollers 30 strictly corresponds to the number of test units 20, and their positions correspond one-to-one. Each microcontroller 30 (such as ST's STM32 series) is connected to the heating element and temperature sensing element in its unique test unit 20 through a specially designed connecting line that passes through the support structure 10, forming an independent closed-loop temperature monitoring and control circuit.

[0024] In this embodiment, the support structure 10 is not a simple mounting backplate, but an actively designed component with clear thermal isolation and electrical partitioning functions. It centrally arranges all heat sources (i.e., the test unit 20 integrating heating elements) on one side, while centrally arranging all temperature-sensitive control cores (i.e., microcontrollers 30) on the other side. This layout fully utilizes the thermal resistance characteristics of the support structure 10's own material, effectively preventing the large-scale conduction of heat generated by the test unit 20 during high-temperature testing (e.g., 125°C) to the back side, thus providing a near-normal temperature, stable operating environment for precision electronic components such as the microcontroller 30. This completely solves the problem of control circuit thermal failure that inevitably arises when heating functions are directly integrated into the test position, and is the technological cornerstone of this solution. Each microcontroller 30 runs a dedicated PID control algorithm, dynamically adjusting the PWM duty cycle output to the heating element based on real-time feedback from the temperature sensing element, thereby enabling temperature control of the microenvironment of the chip under test with an accuracy of ±1°C.

[0025] This embodiment integrates heating and temperature sensing elements into the mounting structure of each test unit, miniaturizing and distributing functions that traditionally relied on large external temperature control equipment into each test site. This physically eliminates the need to transport the chip between room temperature and high temperature testing environments. Secondly, the innovative layout of a support structure that spatially isolates the test unit and the microcontroller on opposite sides solves the thermal interference problem caused by integrated heating, ensuring stable operation of the control circuit and providing a reliable foundation for the aforementioned functional integration. Finally, the microcontroller independently controls each heating element based on temperature feedback, achieving precise and rapid closed-loop temperature adjustment at each test site. Therefore, after installation, the chip under test can continuously and automatically complete room temperature and high temperature tests in the same location and with the same electrical connection state through circuit control alone. This eliminates the time spent on repeated installation, transportation, and waiting for temperature stabilization, allowing for seamless testing and significantly improving testing efficiency and equipment utilization.

[0026] Furthermore, based on the above embodiments, in other embodiments, such as Figure 1 As shown, the support structure 10 is also provided with multiple temperature display modules 40. Each temperature display module 40 is electrically connected to a temperature sensing element and is used to output and display the temperature of the chip under test.

[0027] Specifically, a temperature display module 40 is added to each test unit 20 on the first surface 101 of the support structure 10. This temperature display module 40 can be a small OLED display or a high-brightness LED digital tube embedded in the surface of the support structure 10. The input terminal of each temperature display module 40 is directly connected to the signal output terminal of the temperature sensing element within the corresponding test unit 20 via a wire, or connected to the serial communication interface of the corresponding microcontroller 30, to acquire the current temperature data in real time.

[0028] This embodiment provides localized, real-time visual temperature feedback through the temperature display module 40. Operators can intuitively and quickly confirm on-site whether the chip at each test site has reached the target temperature, whether the temperature is stable, or whether abnormal overheating has occurred, without relying on computer software monitoring. This greatly facilitates status inspection and debugging when multiple devices are operating in parallel, improving human-machine interaction efficiency and operational safety.

[0029] Furthermore, based on the above embodiments, in other embodiments, such as Figure 1 As shown, the support structure 10 is also equipped with multiple heating switch buttons 50. Each heating switch button 50 is electrically connected to a microcontroller 30 and is used to input heating commands to the microcontroller 30.

[0030] Specifically, a heating switch button 50 is added to each test unit 20 on the first surface 101 of the support structure 10. This button can be a physical self-locking button with an indicator light. The output of each heating switch button 50 is connected to a general purpose input / output (GPIO) pin of the corresponding microcontroller 30. Pressing the button sends a high / low level signal to the microcontroller 30, and the program of the microcontroller 30 can be configured to respond to the signal to start or stop the heating process, or to adjust the heating power level in manual mode.

[0031] This embodiment provides a convenient local control channel through the heating switch button 50. During equipment debugging, single-point testing, or emergency handling, the operator can perform quick operations directly in front of the equipment without operating the host computer software, enhancing the immediacy and convenience of system control. It also serves as a hardware emergency intervention method in addition to software control.

[0032] Furthermore, based on the above embodiments, in other embodiments, such as Figure 3 As shown, the mounting structure 21 includes an adapter plate 100, a first fixing member 200, a second fixing member 300, and a locking mechanism 400.

[0033] like Figure 4 and Figure 5As shown, the adapter board 100 has a first adapter surface 110 and a second adapter surface 120 facing each other. A first pin structure 111 is formed on the first adapter surface 110. The specific arrangement of the first pin structure 111 (such as the position, spacing, and number of pads or contacts) completely mirrors the pin (or solder ball) arrangement of the selected first chip (e.g., a high-performance 496-ball BGA packaged system-on-a-chip). At least one second pin structure 121 is formed on the second adapter surface 120, and its arrangement completely mirrors the pin arrangement of the second chip under test (e.g., a 315-ball packaged LPDDR memory chip). The first pin structure 111 and the second pin structure 121 are connected according to pre-designed electrical rules via conductive lines (such as copper traces, vias, and blind / buried vias) fabricated inside the adapter board 100, thereby "translating" the signal from the first chip and routing it to the second chip. For example, the high-current power supply pins (VDD, VDDQ) of the first chip are simultaneously connected to multiple power supply pins of two second chips in a star or mesh topology through the wide power plane inside the adapter board 100, ensuring power sharing and low impedance. This complex, asymmetrical pin-to-pin mapping enables a single physical adapter board 100 to perform logical "protocol conversion" and "signal routing" functions, which is the foundation for a single SoC to drive different packages or multiple memory chips.

[0034] The first fixing member 200 is made of an insulating material (such as PEEK engineering plastic) and is disposed on one side of the first adapter surface 110 of the adapter plate 100. The main function of the first fixing member 200 is to support and position the first chip. For example, it can be a base with a positioning frame to ensure that the first chip can be placed at a predetermined position relative to the first adapter surface 110.

[0035] The second fixing member 300, also made of insulating material, is disposed on one side of the second adapter surface 120 of the adapter plate 100. Its function is to support and position at least one second chip. For example, it can be a bracket with a receiving slot, allowing the second chip to be stably placed and aligned with the second pin structure 121 on the second adapter surface 120.

[0036] The locking mechanism 400 is mounted on the second fixing member 300. Its core function is to provide an operable and releasable mechanical clamping force. During operation, the locking mechanism 400 actuates, pressing and temporarily fixing the sequentially stacked first chip, adapter plate 100, and second chip along the thickness direction (i.e., the stacking direction) of the adapter plate 100. This clamping force forces the pins of the first chip into close contact with the first pin structure 111 on the first adapter surface 110, and simultaneously forces the pins of the second chip into close contact with the second pin structure 121 on the second adapter surface 120, thereby establishing a complete electrical connection path between the two originally independent chips. After testing, the locking mechanism 400 is operated to release the pressure, allowing for the non-destructive separation of the components and enabling complete reuse of the first chip and the adapter. The heating element and temperature sensing element are directly integrated into the locking mechanism 400, specifically located within its clamping section. This allows heating and temperature measurement to act directly on the chip carrier, maximizing efficiency.

[0037] This embodiment creatively constructs a signal conversion channel with heterogeneous pins by setting up an adapter board 100 with a first pin structure 111 and at least one second pin structure 121, and connecting the circuits inside. This allows first and second chips with different pin arrangements to communicate electrically directly, solving the fundamental problem of incompatibility testing between irregularly packaged chips. Secondly, through the stacked layout of "first fixing component 200 - adapter board 100 - second fixing component 300" and a detachable locking mechanism 400, the entire connection interface is mechanically and detachably press-fitted, replacing the soldering process required in traditional testing. This allows high-value first chips (such as test SOCs) to be safely and quickly reused for testing different second chips, greatly improving the utilization rate and testing flexibility of critical testing resources. Finally, through its integrated and compact design, the device integrates signal conversion, chip fixing, and electrical connection functions into a quickly detachable module, significantly simplifying the test preparation process, reducing operational complexity, and providing an efficient and universal hardware solution for chip R&D verification and production testing. Furthermore, it perfectly integrates three major functions: heterogeneous chip adaptation, detachable press-fit connection, and integrated temperature control. In particular, by integrating the temperature control element into the locking mechanism, it achieves the shortest distance transfer between the heat source and the chip under test, resulting in fast temperature control response and high accuracy.

[0038] Furthermore, based on the above embodiments, in other embodiments, such as Figure 4 and Figure 6As shown, the first adapter surface 110 is provided with a protrusion 112, and the first pin structure 111 is provided on the protrusion 112. The side of the first fixing member 200 facing the adapter plate 100 is provided with a first groove 210 that matches the protrusion 112. The first groove 210 is provided with a through hole 220. The through hole 220 is directly opposite the pin of the first chip. When the protrusion 112 is inserted into the first groove 210, the first pin structure 111 passes through the through hole 220 and abuts against the pin of the first chip.

[0039] Specifically, a protrusion 112 is specially formed on the first adapter surface 110 of the adapter board 100. This protrusion 112 can be a stepped area formed by controlling the PCB lamination thickness, or it can be an additionally soldered rigid frame. The first pin structure 111 is disposed on the top surface of this protrusion 112. Correspondingly, a first groove 210 is machined on the side of the first fixing member 200 facing the adapter board 100 (i.e., the upper surface). The shape and size of the first groove 210 are precisely matched with the protrusion 112, like a "mortise and tenon" structure. At the bottom of the first groove 210, a plurality of through holes 220 are provided. The positions of these through holes 220 are precisely designed to correspond one-to-one with the positions of the key pin clusters (or all pins) placed on the first chip pin surface below. During assembly, the protrusion 112 is aligned and snapped into the first groove 210. This action not only completes the precise horizontal alignment of the adapter plate 100 and the first fixing member 200, but more importantly, it enables the first pin structure 111 on the top surface of the protrusion 112 to pass through the through hole 220 and directly approach or contact the corresponding pin of the first chip located below the first fixing member 200.

[0040] This embodiment achieves mechanical pre-alignment between the adapter plate 100 and the first fixing member 200 through the cooperation of the "protrusion 112-first groove 210", avoiding blind assembly. The design of the "through hole 220" provides a precise "contact channel" for the first pin structure and the chip pin. This triple positioning structure (groove to protrusion 112, through hole 220 to chip pin) greatly improves the alignment accuracy and first-time assembly success rate between the high-density BGA packaged chip and the adapter plate 100, effectively preventing poor contact or short circuits caused by misalignment, and is a key mechanical design to ensure the reliability of the device.

[0041] Furthermore, based on the above embodiments, in other embodiments, such as Figure 7 As shown, the side of the first fixing member 200 facing away from the adapter plate 100 is provided with a second groove 230 that matches the first chip, and the through hole 220 passes through the first groove 210 and the second groove 230.

[0042] Specifically, a second groove 230 is machined on the side of the first fixing member 200 facing away from the adapter plate 100 (i.e., the lower surface). The shape and size of the second groove 230 match the package outline of the first chip, and are used to accommodate and limit the first chip. Crucially, the through hole 220 described in the above embodiment does not end at the bottom of the first groove 210, but extends downwards through the entire first fixing member 200, that is, it simultaneously penetrates the bottoms of the first groove 210 and the second groove 230. This allows the first groove 210 and the second groove 230 to communicate through the through hole 220. During assembly, the first chip is placed in the second groove 230. At this time, the pin surface of the first chip (the side facing the adapter plate 100) is exposed through the through hole 220. When the protrusion 112 of the adapter plate 100 (carrying the first pin structure 111) engages with the first groove 210 of the first fixing member 200, the first pin structure 111 can directly achieve spatial alignment and physical contact with the corresponding pins on the pin surface of the first chip below through these through holes 220.

[0043] This embodiment provides stable and precise primary positioning of the first chip through the second recess 230. The through hole 220 connects the dual recesses, creating a "vertical unobstructed contact channel" from the pin structure of the adapter board 100 to the chip pins. This structure ensures that regardless of the thickness of the first chip, as long as it is placed within the second recess 230, its pins can be accurately aligned with the upper first pin structure 111 through the through hole 220, simplifying assembly requirements and improving the adaptability of the device.

[0044] Furthermore, based on the above embodiments, in other embodiments, such as Figure 8 As shown, the second fixing member 300 is provided with at least one through slot 310 for mounting the second chip, and each through slot 310 is directly opposite a second pin structure 121.

[0045] Specifically, the second fixing member 300 is provided with at least one through slot 310. This through slot 310 is a through-hole extending vertically, and its horizontal cross-sectional shape and size are slightly larger than the package outline of the second chip, facilitating chip insertion and removal. The vertical projection of each through slot 310 completely coincides with or is included within the projection of a second pin structure 121 on the second adapter surface 120 of the adapter plate 100. That is, each through slot 310 faces an independent second pin structure 121 on the lower adapter plate 100. When testing is required, the second chip is placed into the corresponding through slot 310 with its pin face down. Due to the guiding and limiting effect of the through slot 310, the second chip is quickly placed in the correct position, with its pin face facing and approximately aligned with the lower second pin structure 121.

[0046] This embodiment provides an extremely simple and quick installation method for the second chip through the through-slot 310 structure, allowing operators to place the chip without precise alignment. Simultaneously, this structure clearly defines the correspondence between each second chip and a specific second pin structure 121 on the adapter board 100, making it particularly suitable for scenarios involving parallel testing of multiple identical or dissimilar chips (by setting multiple through-slots 310 and corresponding second pin structures 121), laying a physical foundation for improving test throughput.

[0047] Furthermore, based on the above embodiments, in other embodiments, such as Figure 3 As shown, the locking mechanism 400 includes a base 410 and a cover 420. One end of the base 410 is hinged to one end of the cover 420. The base 410 is disposed on the second fixing member 300. The base 410 is provided with a through hole facing the receiving area of ​​the second fixing member 300 for mounting the second chip. The cover 420 is provided with a pressing part 421. When the cover 420 is closed on the base 410, the pressing part 421 passes through the through hole and presses the second chip.

[0048] Specifically, the locking mechanism 400 includes a base 410 and a cover 420. The base 410 is fixedly mounted on the upper surface of the second fixing member 300 (the side facing away from the adapter plate 100). One end of the cover 420 is connected to one end of the base 410 via a hinge, allowing the cover 420 to open and close like a door. Through holes 411 are provided on the base 410. The positions of these through holes 411 correspond vertically to the receiving areas (e.g., the through slot 310 in embodiment four) on the second fixing member 300 for mounting the second chip. A pressing part 421 is provided on the inner side of the cover 420 (the side facing the base 410). In the basic form, this pressing part 421 can be a rigid pressure block that matches the shape of the back of the chip. During operation, after the second chip is placed into the second fixing member 300, the cover 420 is closed. The cover 420 rotates around the hinge until it covers the base 410. At this time, the pressing part 421 (pressing block) on the cover 420 passes through the through hole 411 on the base 410, extends into the receiving area (through groove 310) of the second fixing member 300, and directly presses against the back side (non-pin side) of the second chip. A set locking force can be applied and maintained by the locking mechanism 400 (such as a buckle or knob provided on the other side of the cover 420). This force is transmitted through the stacked components, ultimately ensuring that all electrical contact interfaces are stable and reliable.

[0049] This embodiment utilizes a hinged flip-top design, making the locking operation very intuitive and quick, similar to closing a box, greatly simplifying the testing personnel's workflow. The through-hole design provides a precise operating channel for the clamping part 421, avoiding interference with other components. This locking method is simple in structure, low in cost, and highly reliable, making it ideal for testing environments that require frequent chip replacements.

[0050] Furthermore, based on the above embodiments, in other embodiments, such as Figure 9 As shown, the pressing part 421 includes a pressing block 4210 and a plurality of independently movable pressing needles 4211. The pressing block 4210 is provided with a plurality of guide holes 4212 that match the pressing needles 4211. Each guide hole 4212 is provided with an elastic element 4213. The top end of the pressing needle 4211 is disposed in the guide hole 4212 and connected to the elastic element 4213. The bottom end of the pressing needle 4211 passes through the through hole and presses the second chip when the cover 420 is closed on the base 410.

[0051] Specifically, the clamping part 421 on the cover 420 is designed as a pressure-adaptive clamping assembly. This assembly includes a clamping block 4210 fixed to the cover 420 and multiple independently movable pressure pins 4211. Multiple guide holes 4212 are machined on the clamping block 4210, their arrangement corresponding to the back region of the second chip. An elastic element 4213, such as a miniature compression spring, is placed within each guide hole 4212. The upper end of each pressure pin 4211 is positioned within the corresponding guide hole 4212 and rests on or is connected to the lower end of the elastic element 4213. The pressure pins 4211 can slide independently in the vertical direction (clamping direction) under the constraint of the guide holes 4212. When the cover 420 is closed, the bottom ends of all pressure pins 4211 simultaneously contact the back of the second chip. If the back of the chip is uneven or has thickness variations, each pressure pin 4211 will independently compress its corresponding elastic element 4213 according to the height of its local area, resulting in different compression amounts. According to Hooke's Law (F=k·x), the pressure applied to the chip by each pressure pin 4211 is proportional to the compression amount of its corresponding spring. By designing a suitable spring stiffness (k value), the pressure applied by each pressure pin 4211 can be kept within a relatively uniform range within a certain range of compression variation.

[0052] Traditional monolithic pressure blocks can cause stress concentration at high points on the chip, while insufficient pressure may occur at low points. In this embodiment, multiple independent floating pressure pins 4211, in conjunction with elastic elements 4213, constitute a "distributed micro-pressure servo system" that can automatically adapt to and compensate for microscopic unevenness and macroscopic thickness differences in the chip, ensuring that the entire back surface of the second chip receives uniformly distributed positive pressure. This directly translates to uniformity of contact pressure between the chip pin surface and the adapter board 100, greatly improving the stability and consistency of the electrical connection. It is particularly suitable for long-term testing or multi-chip parallel testing where contact reliability requirements are extremely high.

[0053] Furthermore, based on the above embodiments, in other embodiments, the bottom end of the pressure needle 4211 is provided with a flexible contact head.

[0054] Specifically, a flexible contact head is provided at the bottom end of the pressure pin 4211, that is, the end that directly contacts the back side of the second chip. This flexible contact head can be made of silicone rubber, polyurethane, or other materials with appropriate elasticity and insulation properties.

[0055] The flexible contact head in this embodiment provides multiple layers of protection. First, its soft texture prevents the hard pressure pins from scratching or damaging the packaging material on the back of the chip. Second, the flexible material better conforms to the minute undulations of the chip surface, further improving the uniformity of pressure distribution. Finally, it provides additional cushioning to prevent damage to the chip from impacts caused by excessively rapid operation or overload during the locking process. This small improvement significantly enhances the safety and durability of the device.

[0056] Furthermore, based on the above embodiments, in other embodiments, a first conductive element (not shown in the figure) is provided between the first pin structure 111 and the first chip, and a second conductive element (not shown in the figure) is provided between the second pin structure 121 and the second chip.

[0057] In this embodiment, to ensure a good and stable electrical connection under compressed conditions, a first conductive element is sandwiched between the pins of the first chip and the first pin structure 111 on the first transition surface 110 of the adapter plate 100. Similarly, a second conductive element is sandwiched between the pins of the second chip and the second pin structure 121 on the second transition surface 120 of the adapter plate 100.

[0058] This embodiment offers a key advantage by introducing a specialized conductive component as the connection medium. It fills the microscopic gap between the chip pins and the pads of the adapter board 100, ensuring full contact even on surfaces that are not perfectly flat. The conductive component typically possesses a degree of elasticity or plasticity, capable of absorbing mechanical stress and dimensional changes caused by thermal expansion and contraction, maintaining connection stability. Most importantly, it enables a detachable electrical connection, a fundamental characteristic that distinguishes it from permanent soldering (such as reflow soldering), and forms the technological basis for enabling rapid chip replacement and device reuse.

[0059] Furthermore, based on the above embodiments, in other embodiments, both the first conductive element and the second conductive element are conductive adhesives.

[0060] Specifically, both the first and second conductive components are preferably conductive adhesives, and more specifically, anisotropic conductive adhesive films. The anisotropic conductive adhesive film contains uniformly dispersed micron-sized conductive particles, which are separated from each other in an uncompressed state. When placed between the chip pins and the pin structure of the adapter board 100 and subjected to appropriate heat and pressure, the adhesive softens and flows upon heating, and the conductive particles are compressed together in the vertical direction (Z-axis) to form a conductive path, thereby achieving electrical connection in this direction. In the horizontal direction (XY-axis), since the particles are not directionally compressed, the adhesive remains insulating, effectively preventing short circuits between adjacent pins.

[0061] This embodiment utilizes anisotropic conductive adhesive, a perfect material for solving high-density, detachable interconnects. Its "vertical conduction and lateral insulation" characteristics perfectly suit the connection requirements of array packages such as BGA. The connection achieved through thermoforming has advantages such as low contact resistance, high reliability, and good consistency. Furthermore, this connection is reversible under certain conditions (such as reheating), making chip removal possible. Therefore, the use of conductive adhesive not only achieves excellent electrical performance but also thoroughly implements the core design concept of "detachable" in this invention.

[0062] Figure 10 A schematic flowchart illustrating the chip testing method with integrated temperature control according to an embodiment of the present invention is shown. This chip testing method with integrated temperature control is applied to the chip testing system with integrated temperature control according to any of the above embodiments. Figure 10 As shown, the chip testing method with integrated temperature control includes: Step S1: Install the chip under test into the mounting structure of the test unit.

[0063] Step S2: With the heating element turned off, perform a room temperature test on the chip under test using the test circuit board of the test unit.

[0064] Step S3: Use a microcontroller to control the heating element to turn on, heat the chip under test, and collect the temperature of the chip under test in real time through a temperature sensing element.

[0065] Step S4: Based on the feedback from the temperature sensing element, the temperature of the chip under test is maintained within a preset high temperature range using a heating element.

[0066] Step S5: When the chip under test is within the preset high temperature range, use the test circuit board to perform a high temperature test on the chip under test.

[0067] Among them, the room temperature test and the high temperature test are carried out continuously without the chip under test being moved or reinstalled.

[0068] This embodiment integrates the traditionally segmented and discrete room temperature and high temperature testing processes into a continuous and automated unified process. The "install once, test throughout the temperature range" mode not only greatly improves the testing throughput, but also avoids mechanical wear and thermal fatigue of connectors or chips caused by repeated plugging and unplugging and temperature cycling, improving the consistency and reliability of test results, while reducing labor costs.

[0069] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A chip testing system with integrated temperature control, characterized in that, include: Support structure; Multiple test units are disposed on one side of the support structure. Each test unit includes a mounting structure for mounting the chip under test and a test circuit board for testing the chip under test. Each mounting structure integrates a heating element and a temperature sensing element. Multiple microcontrollers are disposed on the other side of the support structure. Each microcontroller is electrically connected to the heating element and temperature sensing element of a test unit. The microcontroller is used to control the working state of the heating element according to the signal of the temperature sensing element. The support structure spatially isolates the test unit from the microcontroller.

2. The chip testing system with integrated temperature control according to claim 1, characterized in that, The support structure is also equipped with multiple temperature display modules, each of which is electrically connected to a temperature sensing element to output and display the temperature of the chip under test.

3. The chip testing system with integrated temperature control according to claim 1, characterized in that, The support structure is also equipped with multiple heating switch buttons, each of which is electrically connected to a microcontroller and is used to input heating commands to the microcontroller.

4. The chip testing system with integrated temperature control according to claim 1, characterized in that, The mounting structure includes an adapter plate, a first fixing component, a second fixing component, and a locking mechanism; The adapter board has a first adapter surface and a second adapter surface arranged opposite to each other. The first adapter surface is provided with a first pin structure corresponding to the pin arrangement of the first chip, and the second adapter surface is provided with at least one second pin structure corresponding to the pin arrangement of the second chip. The first pin structure is electrically connected to the corresponding second pin structure through the internal circuit of the adapter board. A first fixing member is disposed on the first adapter surface and is used to install the first chip; A second fastener is disposed on the second adapter surface and is used to mount at least one of the second chips. A locking mechanism is provided on the second fixing member for detachably pressing and fixing the first chip, the adapter plate and the second chip along the thickness direction of the adapter plate, so that the first chip is electrically connected to the first pin structure and the second chip is electrically connected to the second pin structure. The heating element and the temperature sensing element are provided on the locking mechanism.

5. The chip testing system with integrated temperature control according to claim 4, characterized in that, The first adapter surface is provided with a protrusion, and the first pin structure is provided on the protrusion. The side of the first fixing member facing the adapter plate is provided with a first groove that matches the protrusion. The first groove is provided with a through hole, and the through hole is directly opposite the pin of the first chip. When the protrusion is inserted into the first groove, the first pin structure passes through the through hole and abuts against the pin of the first chip.

6. The chip testing system with integrated temperature control according to claim 5, characterized in that, The first fixing member has a second groove matching the first chip on the side facing away from the adapter plate, and the through hole passes through the first groove and the second groove.

7. The chip testing system with integrated temperature control according to claim 4, characterized in that, The second fastener is provided with at least one through slot for mounting the second chip, and each through slot is directly opposite a second pin structure.

8. The chip testing system with integrated temperature control according to claim 4, characterized in that, The locking mechanism includes a base and a cover. One end of the base is hinged to one end of the cover. The base is disposed on the second fixing member. The base has a through hole facing the receiving area of ​​the second fixing member for mounting the second chip. The cover has a pressing part. When the cover is closed on the base, the pressing part passes through the through hole and presses the second chip. The heating element and the temperature sensing element are disposed on the pressing part.

9. The chip testing system with integrated temperature control according to claim 4, characterized in that, A first conductive element is disposed between the first pin structure and the first chip, and a second conductive element is disposed between the second pin structure and the second chip. Both the first conductive element and the second conductive element are conductive adhesives.

10. A chip testing method with integrated temperature control, characterized in that, It is applied to the chip testing system with integrated temperature control as described in any one of claims 1-9, the method comprising: The chip under test is installed in the mounting structure of the test unit; With the heating element turned off, the chip under test is tested at room temperature using the test circuit board of the test unit; A microcontroller is used to control the heating element to turn on, thereby heating the chip under test, and the temperature of the chip under test is collected in real time by a temperature sensing element. Based on the feedback from the temperature sensing element, the heating element is used to maintain the temperature of the chip under test within a preset high temperature range; When the chip under test is within the preset high temperature range, the chip under test is subjected to high temperature testing using the test circuit board; The room temperature test and the high temperature test are performed continuously without the chip under test being moved or reinstalled.

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