Chip verification board test method, system, device, equipment, medium and product

Abstract

The invention discloses a chip verification board testing method, system, device and equipment, a medium and a product, relates to the technical field of hardware testing, is used for solving the problem that hardware detection is difficult to realize due to the fact that a traditional chip verification board is not provided with a main control chip and firmware, and is applied to testing main body equipment. The test main body equipment is connected with an upper computer and a port connecting device, the port connecting device is used for connecting a to-be-tested port of a target chip verification board, and the method comprises the following steps: receiving a configuration instruction issued by the upper computer to determine electrical characteristic information of the to-be-tested port, configuring a virtual test port corresponding to the to-be-tested port according to the electrical characteristic information, the virtual test port is matched with the to-be-tested port; receiving a test instruction issued by the upper computer, and executing a test operation corresponding to the test instruction on the to-be-tested port through the port connecting device by using the virtual test port to obtain test data of the to-be-tested port; and feeding back the test data to the upper computer for analysis and processing to obtain a test result of the to-be-tested port.

Description

Technical Field

[0001] This invention relates to the field of hardware testing technology, and in particular to a testing method for a chip verification board, as well as a testing system, apparatus, electronic device, computer-readable storage medium, and computer program product for a chip verification board. Background Technology

[0002] An EVB (Evaluation Board) is a circuit board specifically designed for testing and verifying the functionality of a chip. It can verify all or part of a chip's functions, ensuring its performance and stability in practical applications. It integrates the chip and its necessary peripheral circuits, interfaces, and connectors, primarily used to help developers quickly evaluate chip functionality and performance, accelerate prototyping, and reduce development risks. However, because the EVB itself lacks a main control chip and firmware, it is difficult to effectively perform hardware self-testing. If the EVB itself has problems, when using it to verify a newly fabricated chip, the problems of the new chip and the EVB will be coupled, making troubleshooting difficult and compromising the accuracy of the chip verification results.

[0003] Therefore, how to implement hardware testing of chip verification boards, ensure their qualification, and thus guarantee the accuracy of subsequent chip verification results is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a testing method for a chip verification board. This testing method can realize hardware testing of the chip verification board, ensure the qualification of the chip verification board, and thus ensure the accuracy of subsequent chip verification results. Another purpose of this invention is to provide a testing system, device, electronic device, computer-readable storage medium, and computer program product for a chip verification board, all of which have the above-mentioned beneficial effects.

[0005] In a first aspect, the present invention provides a testing method for a chip verification board, applied to a testing main device, wherein the testing main device is connected to a host computer and a port connection device, the port connection device being used to connect to the port to be tested on the target chip verification board, and the method includes: The system receives configuration instructions from the host computer, determines the electrical characteristics of the port under test based on the configuration instructions, and configures the virtual test port corresponding to the port under test based on the electrical characteristics, so that the virtual test port is compatible with the port under test. The system receives test commands from the host computer, uses the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device, and obtains the test data of the port under test. The test data is fed back to the host computer for analysis and processing to obtain the test results of the port under test, so as to realize the test of the target chip verification board.

[0006] The process includes determining the electrical characteristic information of the port under test according to the configuration instructions, and configuring the virtual test port corresponding to the port under test according to the electrical characteristic information, including: The electrical characteristic information of the port under test is determined according to the configuration instructions; the electrical characteristic information includes one or more combinations of IO type, IO level specification, and interface protocol; Configure the virtual test port corresponding to the port under test according to the electrical characteristic information; the configuration items of the virtual test port include one or more combinations of input buffer type, output buffer type, pull-up / pull-down resistor parameters, power supply parameters, and analog-to-digital conversion mode.

[0007] The process includes determining the electrical characteristic information of the port under test according to the configuration instructions, and configuring the virtual test port corresponding to the port under test according to the electrical characteristic information, including: The electrical characteristics of the port under test are determined according to the configuration instructions, and the preset configuration parameters of the virtual test port are determined according to the electrical characteristics. The manual configuration parameters of the virtual test port are determined according to the configuration instructions; Actual configuration parameters are generated based on the preset configuration parameters and the manually configured parameters, and the virtual test port is configured according to the actual configuration parameters.

[0008] Wherein, when the test command is a protocol verification command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: The master-slave mode of the port protocol corresponding to the port under test is determined according to the protocol verification command. In the master-slave mode, the virtual test port is used to perform protocol interaction with the port under test through the port connection device to obtain the protocol interaction result; The protocol interaction results are used as test data for the port under test.

[0009] Wherein, when the test command is a transmit / receive loopback verification command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: The transmit / receive loopback verification command controls the interconnection of the transmit and receive pins of the port under test to form a hardware link closed loop for the port under test. The test signal is sent to the port under test through the virtual test port and the feedback signal of the port under test is obtained. The comparison and analysis results of the test signal and the feedback signal are used as the test data of the port under test.

[0010] When the test command is a stress test command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: Determine the limiting parameters according to the pressure test command; According to the aforementioned limit parameters, preset test data is sent to the port under test via the port connection device using the virtual test port. During the transmission of the preset test data, the pressure resistance index data of the port under test is statistically analyzed according to the preset pressure resistance index. The pressure resistance index data are used as the test data for the port under test.

[0011] When the test command is an interference injection command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: The interference parameters are determined according to the interference injection command, and an interference signal is generated according to the interference parameters. The interference signal is injected into the port under test through the virtual test port via the port connection device. During the injection of the interference signal, the stability index data of the port under test are statistically analyzed according to the preset stability index. The stability index data are used as the test data for the port under test.

[0012] The test data is fed back to the host computer for analysis and processing to obtain the test results of the port under test, thereby realizing the testing of the target chip verification board, including: The test data is saved to a local log file; the local log file is used to store the test data of each functional port in the target chip verification board; When a log instruction is received from the host computer, the test data of the port to be tested is selected from the local log file according to the log instruction and fed back to the host computer for analysis and processing to obtain the test result of the port to be tested.

[0013] Secondly, the present invention also discloses a testing system for a chip verification board, including a host computer, a main testing device, and a port connection device. The main testing device is connected to the host computer and the port connection device respectively, and the port connection device is used to connect to the port to be tested of the target chip verification board. The main testing device is configured to receive configuration instructions from the host computer, determine the electrical characteristics of the port under test according to the configuration instructions, configure a virtual test port corresponding to the port under test according to the electrical characteristics, so that the virtual test port is compatible with the port under test; receive test instructions from the host computer, use the virtual test port to perform the test operation corresponding to the test instructions on the port under test through the port connection device, and obtain test data of the port under test; feed the test data back to the host computer for analysis and processing to obtain the test result of the port under test, so as to realize the testing of the target chip verification board.

[0014] The port connection device includes a probe and a standard port connector; When the port under test is equipped with a dedicated port connector, the port under test is connected to the standard port connector through the dedicated port connector, and the dedicated port connector is compatible with the standard port connector; When the port under test is not equipped with a dedicated port connector, the port under test is directly connected to the probe, and the probe is fixedly connected to the port under test through a pin header.

[0015] The number of probes is multiple, and the testing system also includes a mounting base for fixing the main testing device.

[0016] Thirdly, the present invention also discloses a testing device for a chip verification board, applied to a main testing device, wherein the main testing device is connected to a host computer and a port connection device, the port connection device being used to connect to the port to be tested on the target chip verification board, and the device comprising: The configuration module is used to receive configuration instructions from the host computer, determine the electrical characteristic information of the port under test according to the configuration instructions, and configure the virtual test port corresponding to the port under test according to the electrical characteristic information so that the virtual test port is compatible with the port under test. The testing module is used to receive test commands issued by the host computer, and use the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test; The analysis module is used to feed the test data back to the host computer for analysis and processing, and to obtain the test results of the port under test, so as to realize the test of the target chip verification board.

[0017] Fourthly, the present invention also discloses an electronic device, comprising: Memory, used to store computer programs; A processor, used to execute the computer program to implement the steps of the testing method for any of the chip verification boards described above.

[0018] Fifthly, the present invention also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the testing method for any of the chip verification boards described above.

[0019] In a sixth aspect, the present invention also discloses a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of any of the chip verification board testing methods described above.

[0020] This invention provides a testing method for a chip verification board, applied to a testing main device. The testing main device is connected to a host computer and a port connection device, the port connection device being used to connect to the port under test of the target chip verification board. The method includes: receiving a configuration command issued by the host computer; determining the electrical characteristic information of the port under test according to the configuration command; configuring a virtual test port corresponding to the port under test according to the electrical characteristic information, so that the virtual test port is compatible with the port under test; receiving a test command issued by the host computer; using the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device, obtaining test data of the port under test; and feeding back the test data to the host computer for analysis and processing, obtaining the test result of the port under test, thereby realizing the testing of the target chip verification board.

[0021] The present invention provides a testing system for a chip verification board, constructed by sequentially connecting port connection devices, a main testing device, and a host computer. This system is used to test the chip verification board. The port connection devices connect to the ports under test on the target chip verification board. The host computer issues configuration and test commands to control the main testing device to perform specific configuration and test operations. It also feeds back the test data of the ports under test on the target chip verification board to the host computer for aggregation and analysis, thus achieving the testing of the target chip verification board. Therefore, this technical solution realizes hardware testing of the chip verification board, effectively ensuring its qualification and thus guaranteeing the accuracy of subsequent chip verification based on the board.

[0022] The chip verification board testing system, apparatus, electronic equipment, computer-readable storage medium, and computer program product provided by this invention also have the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the prior art and the embodiments of the present invention, the accompanying drawings used in the description of the prior art and the embodiments of the present invention will be briefly introduced below. Of course, the accompanying drawings described below with respect to the embodiments of the present invention are only a part of the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort, and such other drawings also fall within the protection scope of the present invention.

[0024] Figure 1 This is a schematic diagram of the structure of a test system for a chip verification board provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating a testing method for a chip verification board provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a port configuration circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a functional verification circuit provided in an embodiment of the present invention; Figure 5 A schematic diagram of the structure of a test system for another chip verification board provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a test device for a chip verification board provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0025] The core of this invention is to provide a testing method for a chip verification board. This testing method can realize hardware testing of the chip verification board, ensure the qualification of the chip verification board, and thus ensure the accuracy of subsequent chip verification results. Another core aspect of this invention is to provide a testing system, device, electronic device, computer-readable storage medium, and computer program product for a chip verification board, all of which have the above-mentioned beneficial effects.

[0026] To provide a clearer and more complete description of the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be introduced below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] This invention provides a testing method for a chip verification board.

[0028] First, please refer to Figure 1 , Figure 1 This is a schematic diagram of a chip verification board testing system provided in an embodiment of the present invention. The chip verification board testing system mainly includes a host computer 100, a testing main device 200, and a port connection device 300. The testing main device 200 is connected to both the host computer 100 and the port connection device 300. The port connection device 300 is used to connect to the port to be tested on the target chip verification board, so as to use the chip verification board testing system to test the port to be tested on the target chip verification board, thereby realizing the testing of the target chip verification board.

[0029] For further information, please refer to [link / reference]. Figure 2 , Figure 2 This is a flowchart illustrating a testing method for a chip verification board provided in an embodiment of the present invention. This testing method for the chip verification board can be applied to… Figure 1 The test main equipment shown can be implemented in the following steps: S101 to S103.

[0030] S101: Receives configuration instructions from the host computer, determines the electrical characteristics of the port under test according to the configuration instructions, and configures the virtual test port corresponding to the port under test according to the electrical characteristics, so that the virtual test port is compatible with the port under test.

[0031] This step aims to perform port configuration operations. Specifically, after receiving the configuration command input by the technician, the host computer can send it to the main testing device, which then responds to the command and executes the corresponding port configuration operation. It should be noted that the port configuration operation here refers to configuring the virtual test port corresponding to the port under test on the target chip verification board, ensuring the virtual test port is compatible with the port under test, so that the main testing device can perform testing on the port under test through the virtual test port. Understandably, to ensure compatibility between the virtual test port and the port under test, the electrical characteristics of the port under test can be determined first, and then the corresponding virtual test port can be configured based on these characteristics. Furthermore, the target chip verification board is the chip verification board to be tested. By testing the various functional ports on the target chip verification board, hardware testing of the target chip verification board can be achieved. Therefore, the port under test can be any functional port on the target chip verification board. Different functional ports have different electrical characteristics, and therefore, the configuration of the virtual test port corresponding to different functional ports will also be different.

[0032] The process of determining the electrical characteristics of the port under test according to configuration instructions and configuring the virtual test port corresponding to the port under test according to the electrical characteristics information may include: determining the electrical characteristics of the port under test according to configuration instructions; the electrical characteristics information includes one or more combinations of IO type, IO level specification, and interface protocol; configuring the virtual test port corresponding to the port under test according to the electrical characteristics information; the configuration items of the virtual test port include one or more combinations of input buffer type, output buffer type, pull-up / pull-down resistor parameters, power supply parameters, and analog-to-digital conversion mode.

[0033] Specifically, I / O types can be used to configure input and output buffer types, I / O level specifications can be used to configure pull-up / pull-down resistor parameters and power supply parameters, and interface protocols can be used to configure analog-to-digital conversion modes. In one possible implementation, I / O types can include CMOS (Complementary Metal-Oxide-Semiconductor) or LVTTL (Low Voltage Transistor-Transistor Logic, the low-level version of TTL) inputs, push-pull, or open-drain outputs. Correspondingly, the input buffer type can be set to CMOS or LVTTL mode, and the output buffer type can be set to push-pull or open-drain mode. I / O level specifications can include various specifications such as 5V, 3.3V, 2.5V, 1.8V, 1.2V, and 1V for power supply parameter selection. Furthermore, to match port level requirements, pull-up / pull-down resistors can be further configured with pull-up mode, pull-down mode, and various impedance specifications. Interface protocols can include various types such as I2C (Inter-Integrated Circuit), SMBUS (System Management Bus), SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), and JTAG (Joint Test Action Group) to adapt to the needs of digital interface testing and analog signal processing.

[0034] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of a port configuration circuit provided in an embodiment of the present invention. The port configuration circuit is deployed on a test main device, and the test main device uses this port configuration circuit to effectively configure virtual test ports. Specifically, the port configuration circuit includes configuration circuits for multiple virtual test ports (port 1 to port x), which can be used to perform batch testing of the ports under test. The configuration circuit for each virtual test port mainly includes pull-up / pull-down resistors, level shifting devices, input / output buffers, and analog-to-digital converters (ADCs) / digital-to-analog converters (DACs), which can be used to configure the pull-up / pull-down resistor parameters, power supply parameters, input buffer type, output buffer type, and analog-to-digital conversion mode, respectively.

[0035] based on Figure 3The port configuration circuit shown takes UART serial port transceiver as an example. The UART serial port has RXD and TXD transmit and receive signal lines, and the required level is 3.3V. The configuration can be as follows: Port 1 is used to interconnect with the RXD signal line. The port switch is configured to the level conversion side, and no pull-up or pull-down resistors are configured. The input buffer is configured as CMOS input. Port 2 is used to interconnect with the TXD signal line. The port switch is configured to the level conversion side, and no pull-up or pull-down resistors are configured. The output buffer is configured as push-pull output.

[0036] In addition, when processing certain analog signals, the port switching switch (the multi-channel IO switching switch mentioned later) is configured on the ADC front end or DAC coupling side for analog signal sampling and analog signal driving. The analog signal sampling needs to be adjusted by the front-end analog circuit before entering the ADC for analog-to-digital conversion; the output of the analog signal driving needs to be coupled to the port, and the coupling method can be direct coupling, AC coupling, or other methods.

[0037] The process of determining the electrical characteristic information of the port under test according to the configuration instructions and configuring the virtual test port corresponding to the port under test according to the electrical characteristic information may include: determining the electrical characteristic information of the port under test according to the configuration instructions and determining the preset configuration parameters of the virtual test port according to the electrical characteristic information; determining the manual configuration parameters of the virtual test port according to the configuration instructions; generating the actual configuration parameters according to the preset configuration parameters and the manual configuration parameters, and configuring the virtual test port according to the actual configuration parameters.

[0038] To ensure accurate port configuration, virtual test ports can be configured based on the electrical characteristics of the port under test (UTD) and manually configured parameters. Specifically, a set of virtual test port configuration parameters (the preset configuration parameters) can be determined first based on the UTD's electrical characteristics. Then, a set of virtual test port configuration parameters (the manually configured parameters) can be determined based on the manually input data carried in the configuration command. Finally, the actual configuration parameters can be obtained by combining these two sets of parameters to configure the virtual test ports. For example, if the power parameters obtained based on the UTD's electrical characteristics differ from the power parameters specified by the technician for actual testing, the manually configured parameters should prevail. Furthermore, if the manually configured parameters are more comprehensive than the preset configuration parameters obtained based on the UTD's electrical characteristics, the preset configuration parameters can be supplemented using the manually configured parameters.

[0039] S102: Receives test commands from the host computer, uses the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device, and obtains the test data of the port under test.

[0040] This step aims to implement port testing operations. Specifically, after receiving the test command input by the technician, the host computer can send it to the main testing device. Alternatively, after receiving a configuration completion message from the main testing device, the host computer can send the test command to the main testing device, which then responds to the command and executes the corresponding test operation. It can be understood that when the main testing device performs port testing on the port under test, it utilizes the virtual test port configured based on S101 (software matching) and the port connection device (hardware connection) connected to the port under test to execute the test operation corresponding to the test command, thereby obtaining the test data of the port under test. Of course, for different ports under test, the main testing device will perform different test operations and obtain different test data. The following embodiments illustrate various testing functions that the main testing device can implement, including but not limited to protocol verification, transmit / receive loopback verification, stress testing, and interference injection.

[0041] Specifically, when the test command is a protocol verification command, the test operation corresponding to the test command is executed on the port under test through the port connection device using the virtual test port to obtain the test data of the port under test. This may include: determining the master-slave mode of the port protocol corresponding to the port under test according to the protocol verification command; in the master-slave mode, using the virtual test port to perform protocol interaction with the port under test through the port connection device to obtain the protocol interaction result; and using the protocol interaction result as the test data of the port under test.

[0042] Specifically, the test device can perform protocol verification on the target chip verification board. This involves testing the protocol interaction between the test device and the port under test (DUT) to verify the DUT's protocol. When the test device receives a protocol verification command, it first determines the master / slave mode of the port protocol corresponding to the DUT. This allows it to configure the master / slave mode between itself and the DUT. Specifically: if the DUT is to be the data initiator and the test device the data receiver for verification, the DUT can be configured as the master and the test device as the slave. Conversely, if the test device is to be the data initiator and the DUT as the data receiver, the test device can be configured as the master and the DUT as the slave. For example, if the DUT is an I2C Slave device (slave mode), the test device is configured as an I2C Master; if the DUT is a UART receiver (slave mode), the test device is configured as a UART transmitter (master mode). Therefore, in this master-slave mode, the protocol interaction result obtained by the test master device and the port under test is the protocol verification result of the port under test, which is also the test data of the current port under test. The protocol verification result of the port under test may include, but is not limited to, whether the test master device can successfully read and write data to the port under test, and whether the data read and write process conforms to the protocol timing requirements.

[0043] In the specific implementation process, the main testing device may include a main processor CPU and low-speed signal IP cores corresponding to each port protocol. The main processor CPU receives protocol verification instructions from the host computer to determine the port under test and then the port protocol corresponding to the port under test. After establishing a connection between the port connection device and the port under test, it can control the low-speed signal IP core corresponding to the port protocol to configure its working mode with the port under test, send test data (such as I2C read and write commands, UART character streams, etc.) to the port under test, and receive feedback signals from the port under test to complete the protocol interaction. Finally, the main processor CPU uploads the protocol interaction results to the host computer for summary and analysis.

[0044] Specifically, when the test command is a transmit / receive loopback verification command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test. This can include: controlling the interconnection of the transmit and receive pins of the port under test according to the transmit / receive loopback verification command to form a hardware link closed loop of the port under test; sending test signals to the port under test through the virtual test port through the port connection device and obtaining the feedback signal of the port under test; and using the comparison and analysis results of the test signal and the feedback signal as the test data of the port under test.

[0045] Specifically, the test equipment can perform loopback verification on the target chip verification board. This involves directly interconnecting the transmit and receive signal terminals (transmit / receive pins) of the port under test (DUT) to form a closed hardware link and verifying the consistency of the transmitted and received data. Therefore, when the test equipment receives a loopback verification command, it controls the interconnection of the transmit and receive pins of the DUT to form its corresponding closed hardware link. The test equipment then sends a test signal to the DUT, which, after passing through the closed hardware link, receives a feedback signal. If the two signals match, the loopback verification of the DUT has passed; otherwise, it has failed. Based on this, the comparison and analysis of the test signal and the feedback signal constitutes the loopback verification result of the DUT, i.e., the test data of the DUT. Furthermore, when the test signal and feedback signal are inconsistent and it is determined that the transmit / receive loopback verification of the port under test has failed, fault location can also be performed. The corresponding fault types may include pin configuration errors, switches not closed, etc., and can be uploaded to the host computer together.

[0046] In the specific implementation process, in addition to the main processor CPU and the low-speed signal IP cores corresponding to each port protocol, the main test equipment can also include a multi-channel I / O switch. The main processor CPU receives the transmit / receive loopback verification command sent by the host computer to determine the port under test. After establishing a connection between the port connection device and the port under test, the main processor CPU can control the multi-channel I / O switch to directly interconnect the transmit and receive pins of the port under test. For example, the TXD output pin and RXD input pin of the UART can be closed by a switch to form a hardware link closed loop. At this time, the main processor CPU controls the corresponding low-speed signal IP core to send test signals (such as specific characters of UART, high and low levels of GPIO, etc.) to the port under test and receives the feedback signal from the port under test. The consistency comparison between the two can obtain the transmit / receive loopback verification result of the port under test. Finally, the main processor CPU uploads the transmit / receive loopback verification result to the host computer for summary analysis.

[0047] When the test command is a pressure test command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test. This can include: determining the limit parameters according to the pressure test command; sending preset test data to the port under test through the virtual test port through the port connection device according to the limit parameters; during the transmission of the preset test data, statistically analyzing the pressure resistance index data of the port under test according to the preset pressure resistance index; and using each pressure resistance index data as the test data of the port under test.

[0048] Specifically, the main testing equipment can perform stress testing on the target chip verification board, that is, test the stress resistance performance of the port under test under extreme conditions. Upon receiving a stress test command, the main testing equipment first obtains the extreme parameters set for the stress test, such as the maximum communication rate of the protocol, the maximum I / O toggle frequency, and the test duration. Then, under the extreme conditions corresponding to these parameters, the main testing equipment sends preset test data to the port under test, such as continuously sending read / write commands at the highest rate for the I2C interface and toggling high / low levels at the maximum frequency for the GPIO interface. Simultaneously, it collects various stress resistance indicators of the port under test during the transmission process, such as data transmission success rate, bit error rate, and whether the link is interrupted, thus obtaining the stress test result of the port under test, i.e., the test data. Furthermore, it can analyze the collected stress resistance indicators, such as whether the bit error rate is below a preset threshold. Similarly, if the stress test of the port under test fails, fault location can be performed and the results uploaded to the host computer.

[0049] In the specific implementation process, the main processor CPU receives stress test commands from the host computer to determine the port under test and its limit parameters. After establishing a connection between the port connection device and the port under test, the main processor CPU first configures the low-speed signal IP core and the multiplexer switch based on either "protocol verification" or "transmit / receive loopback verification": if it is an interactive stress test between the interface under test and the target chip verification board, the protocol verification configuration is used; if it is a stress test of the interface under test's own link, the transmit / receive loopback verification configuration is used. Furthermore, the main processor CPU controls the corresponding low-speed signal IP core to send preset test data to the port under test according to the limit parameters, and continuously records various stress resistance indicators of the port under test during data transmission. This data is then uploaded to the host computer as the stress test result for the port under test for summary analysis.

[0050] Specifically, when the test command is an interference injection command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test. This can include: determining interference parameters according to the interference injection command, generating interference signals according to the interference parameters; injecting interference signals into the port under test through the virtual test port through the port connection device; during the interference signal injection process, statistically analyzing the stability index data of the port under test according to preset stability indicators; and using the stability index data as the test data of the port under test.

[0051] Specifically, the main testing equipment can perform interference injection on the target chip verification board, that is, inject interference signals into the port under test to verify its anti-interference capability. Based on this, when the main testing equipment receives an interference injection command, it can first determine the interference parameters (such as interference type, interference intensity, injection duration, etc.) to generate the corresponding interference signal, and then inject this interference signal into the port under test. Simultaneously, it monitors various stability indicators of the port under test after interference injection, such as whether data transmission is normal, whether the interface reports errors, and whether the function is interrupted, thus obtaining the interference injection result of the port under test, which is the test data of the port under test.

[0052] In the specific implementation process, the main processor CPU receives the interference injection command from the host computer to determine the port under test and the interference parameters. After establishing a connection between the port connection device and the port under test, the main processor CPU first controls the multiplexer switch to configure to... Figure 3 The DAC coupling side of the port configuration circuit is shown. At the same time, according to the interference parameters, the interference signal generated by the DAC is injected into the port under test. Various stability index data of the port under test are continuously recorded during the interference injection process. The interference injection result of the port under test is then uploaded to the host computer for summary analysis.

[0053] To perform the above functional tests, please refer to... Figure 4 , Figure 4 This is a schematic diagram of a functional verification circuit provided in an embodiment of the present invention. The functional verification circuit is deployed on the main testing equipment and... Figure 3 The port configuration circuit shown is connected to the main testing equipment, which uses this functional verification circuit to perform various functional tests on the port under test. Specifically, the functional verification circuit includes a main processor CPU connected to the host computer and the analog-to-digital converter / digital-to-analog converter in the port configuration circuit, low-speed signal IP cores corresponding to each port protocol connected to the input / output of the port configuration circuit, and multiplexer switches connected to the input / output of the port configuration circuit. Both the low-speed signal IP cores corresponding to each port protocol and the multiplexer switches are connected to the main processor CPU. Therefore, the main processor CPU can perform the aforementioned functional tests on the port under test by controlling the low-speed signal IP cores and multiplexer switches corresponding to each port protocol.

[0054] S103: Feeds the test data back to the host computer for analysis and processing to obtain the test results of the port under test, so as to realize the test of the target chip verification board.

[0055] This step aims to summarize and analyze the test data of the port under test to obtain the test results. By combining the test results of all ports under test on the target chip verification board, the target chip verification board can be tested, and the final test result can be obtained. The summary and analysis of the test data of the port under test can be performed by a host computer; that is, after the main testing device obtains the test data of the port under test, it uploads it to the host computer for summary and analysis.

[0056] The process of feeding back test data to a host computer for analysis and processing to obtain the test results of the port under test, thereby enabling the testing of the target chip verification board, may include: saving test data to a local log file; the local log file is used to store the test data of each functional port in the target chip verification board; when a log instruction is received from the host computer, the test data of the port under test is selected from the local log file according to the log instruction and fed back to the host computer for analysis and processing to obtain the test results of the port under test.

[0057] Specifically, a log file, or local log file, can be created in the local storage space of the main testing device to store the test data of all functional ports during the testing process of the target chip verification board. When the main testing device receives the log instruction from the host computer, it can select the test data of the port to be tested or the test data of all functional ports in the local log file according to the log instruction and upload it to the host computer for summary analysis to obtain the test results of the port to be tested on the target chip verification board or the overall test results of the target chip verification board.

[0058] As can be seen, the chip verification board testing method provided in this embodiment of the invention constructs a chip verification board testing system by sequentially connecting a port connection device, a testing main device, and a host computer. This system is used to test the chip verification board. The port connection device connects to the port under test on the target chip verification board, and the host computer issues configuration and test commands to control the testing main device to execute specific configuration and test operations. It also feeds back the test data of the port under test on the target chip verification board to the host computer for aggregation and analysis, thereby achieving the testing of the target chip verification board. Therefore, this technical solution realizes hardware testing of the chip verification board, effectively ensuring its qualification and thus guaranteeing the accuracy of subsequent chip verification based on the chip verification board.

[0059] This invention provides a testing system for a chip verification board.

[0060] like Figure 1As shown, the chip verification board testing system provided in this embodiment of the invention may include a host computer 100, a testing main device 200, and a port connection device 300. The testing main device 200 is connected to the host computer 100 and the port connection device 300 respectively. The port connection device 300 is used to connect to the port to be tested of the target chip verification board. The main testing device 200 is used to receive configuration instructions from the host computer 100, determine the electrical characteristics of the port under test according to the configuration instructions, configure the virtual test port corresponding to the port under test according to the electrical characteristics, so that the virtual test port is compatible with the port under test; receive test instructions from the host computer 100, use the virtual test port to perform the test operation corresponding to the test instructions through the port connection device 300, and obtain the test data of the port under test; feed the test data back to the host computer 100 for analysis and processing, and obtain the test results of the port under test, so as to realize the test of the target chip verification board.

[0061] The port connection device 300 may include a probe and a standard port connector. When the port under test is equipped with a dedicated port connector, the port under test is connected to the standard port connector through the dedicated port connector, and the dedicated port connector is compatible with the standard port connector. When the port under test is not equipped with a dedicated port connector, the port under test is directly connected to the probe, and the probe is fixedly connected to the port under test through a pin header.

[0062] The number of probes can be multiple, and the testing system may also include a mounting base for fixing the main testing device 200.

[0063] For example, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of a test system for another chip verification board provided in an embodiment of the present invention. It mainly includes multiple probes, a main test device, and a host computer. The main test device primarily includes a port configuration circuit. Figure 3 ), Functional verification circuit ( Figure 4 The system includes an interaction module, which can be the interaction port of the main testing device for connecting to a host computer. This module enables functions such as uploading and displaying test data and distributing and controlling scripts. A test system based on this chip verification board can then perform the testing functions of the chip verification board.

[0064] As can be seen, the chip verification board testing system provided in this embodiment of the invention constructs a chip verification board testing system by sequentially connecting port connection devices, a main testing device, and a host computer. This system is used to test the chip verification board. The port connection devices are used to connect to the ports under test of the target chip verification board. The host computer is used to issue configuration and test commands to control the main testing device to execute specific configuration and test operations, and to feed back the test data of the ports under test of the target chip verification board to the host computer for summary and analysis, thereby achieving the testing of the target chip verification board. Therefore, this technical solution realizes hardware testing of the chip verification board, effectively ensuring the qualification of the chip verification board, and thus ensuring the accuracy of subsequent chip verification based on this chip verification board.

[0065] This invention provides a testing device for a chip verification board.

[0066] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a testing device for a chip verification board provided by the present invention. The testing device is applied to a main testing unit, which is connected to a host computer and a port connection device. The port connection device is used to connect to the port to be tested on the target chip verification board. The testing device for the chip verification board may include: Configuration module 1 is used to receive configuration instructions from the host computer, determine the electrical characteristic information of the port under test according to the configuration instructions, and configure the virtual test port corresponding to the port under test according to the electrical characteristic information so that the virtual test port is compatible with the port under test. Test module 2 is used to receive test commands issued by the host computer, and use the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test; Analysis module 3 is used to feed the test data back to the host computer for analysis and processing, and obtain the test results of the port under test, so as to realize the test of the target chip verification board.

[0067] As can be seen, the chip verification board testing device provided in this embodiment of the invention constructs a chip verification board testing system by sequentially connecting a port connection device, a main testing device, and a host computer. This system is used to test the chip verification board. The port connection device connects to the port under test on the target chip verification board, and the host computer issues configuration and test commands to control the main testing device to execute specific configuration and test operations. It also feeds back the test data of the port under test on the target chip verification board to the host computer for aggregation and analysis, thereby achieving the testing of the target chip verification board. Therefore, this technical solution realizes hardware testing of the chip verification board, effectively ensuring its qualification and thus guaranteeing the accuracy of subsequent chip verification based on the chip verification board.

[0068] In one embodiment of the present invention, the configuration module 1 can be specifically used to determine the electrical characteristic information of the port under test according to the configuration instructions; the electrical characteristic information includes one or more combinations of IO type, IO level specification, and interface protocol; configure the virtual test port corresponding to the port under test according to the electrical characteristic information; the configuration items of the virtual test port include one or more combinations of input buffer type, output buffer type, pull-up / pull-down resistor parameters, power supply parameters, and analog-to-digital conversion mode.

[0069] In one embodiment of the present invention, the configuration module 1 is specifically used to determine the electrical characteristic information of the port under test according to the configuration instruction, and determine the preset configuration parameters of the virtual test port according to the electrical characteristic information; determine the manual configuration parameters of the virtual test port according to the configuration instruction; generate the actual configuration parameters according to the preset configuration parameters and the manual configuration parameters, and configure the virtual test port according to the actual configuration parameters.

[0070] In one embodiment of the present invention, when the test instruction is a protocol verification instruction, the test module 2 can be specifically used to determine the master-slave mode of the port protocol corresponding to the port under test according to the protocol verification instruction; in the master-slave mode, the virtual test port is used to perform protocol interaction with the port under test through the port connection device to obtain the protocol interaction result; and the protocol interaction result is used as the test data of the port under test.

[0071] In one embodiment of the present invention, when the test command is a transmit / receive loopback verification command, the test module 2 can be specifically used to control the interconnection of the transmit and receive pins of the port under test according to the transmit / receive loopback verification command to form a hardware link closed loop of the port under test; use a virtual test port to send a test signal to the port under test through a port connection device, and obtain the feedback signal of the port under test; and use the comparison and analysis results of the test signal and the feedback signal as the test data of the port under test.

[0072] In one embodiment of the present invention, when the test instruction is a pressure test instruction, the test module 2 can be specifically used to determine the limit parameters according to the pressure test instruction; according to the limit parameters, use a virtual test port to send preset test data to the port under test through a port connection device; during the transmission of the preset test data, statistically analyze the pressure resistance index data of the port under test according to the preset pressure resistance index; and use each pressure resistance index data as the test data of the port under test.

[0073] In one embodiment of the present invention, when the test instruction is an interference injection instruction, the test module 2 can be specifically used to determine interference parameters according to the interference injection instruction, generate interference signals according to the interference parameters, inject interference signals into the port under test through a port connection device using a virtual test port, and during the injection of interference signals, statistically analyze the stability index data of the port under test according to a preset stability index, and use each stability index data as the test data of the port under test.

[0074] In one embodiment of the present invention, the analysis module 3 described above can be specifically used to save test data to a local log file; the local log file is used to store test data of each functional port in the target chip verification board; when a log instruction is received from the host computer, the test data of the port to be tested is selected in the local log file according to the log instruction and fed back to the host computer for analysis and processing to obtain the test result of the port to be tested.

[0075] For a description of the apparatus provided in the embodiments of the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0076] This invention provides an electronic device.

[0077] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device provided by the present invention. The electronic device may include: Memory 11 is used to store computer programs; The processor 10 is configured to execute computer programs to implement the steps of any of the chip verification board testing methods described above.

[0078] like Figure 7 The diagram shows the structural composition of an electronic device, which may include a processor 10, a memory 11, a communication interface 12, and a communication bus 13. The processor 10, memory 11, and communication interface 12 all communicate with each other through the communication bus 13.

[0079] In this embodiment of the invention, the processor 10 may be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field-programmable gate array, or other programmable logic devices.

[0080] The processor 10 can call the program stored in the memory 11. Specifically, the processor 10 can execute the operations in the embodiment of the chip verification board test method.

[0081] The memory 11 is used to store one or more programs, which may include program code and computer operation instructions. In this embodiment of the invention, the memory 11 stores at least a program for performing the following functions: receiving configuration instructions from a host computer, determining the electrical characteristic information of the port under test according to the configuration instructions, configuring a virtual test port corresponding to the port under test according to the electrical characteristic information, so that the virtual test port is compatible with the port under test; receiving test instructions from a host computer, using the virtual test port to perform the test operation corresponding to the test instructions on the port under test through the port connection device, and obtaining the test data of the port under test; feeding back the test data to the host computer for analysis and processing, and obtaining the test result of the port under test, so as to realize the test of the target chip verification board.

[0082] In one possible implementation, the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created during use.

[0083] In addition, memory 11 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.

[0084] Communication interface 12 can be an interface for the communication module, used to connect with other devices or systems.

[0085] Of course, it should be noted that, Figure 7 The structure shown does not constitute a limitation on the electronic device in the embodiments of the present invention. In practical applications, the electronic device may include more than Figure 7 More or fewer components as shown, or combinations of certain components.

[0086] This invention provides a computer-readable storage medium.

[0087] The computer-readable storage medium provided in this embodiment of the invention stores a computer program, which, when executed by a processor, can implement the steps of any of the chip verification board testing methods described above.

[0088] The computer-readable storage medium can be any available medium that a computer can store, or a data storage device such as a server or data center that integrates one or more available media. For example, it can be any medium that can store computer program code, such as magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives).

[0089] For a description of the computer-readable storage medium provided in the embodiments of the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0090] This invention provides a computer program product.

[0091] The computer program product provided in this embodiment of the invention includes a computer program / instruction. When the computer program / instruction is executed by a processor, it can implement the steps of any of the chip verification board testing methods described above.

[0092] Specifically, in the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.

[0093] The computer program product may include one or more computer programs / instructions, which, when loaded and executed on a computer, can generate all or part of the processes or functions described in the embodiments of the present invention. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line, etc.) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0094] For a description of the computer program product provided in the embodiments of the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0095] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0096] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0097] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0098] The technical solution provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A testing method for a chip verification board, characterized in that, The method is applied to a main testing device, which is connected to a host computer and a port connection device, wherein the port connection device is used to connect to the port under test of the target chip verification board. The method includes: The system receives configuration instructions from the host computer, determines the electrical characteristics of the port under test based on the configuration instructions, and configures the virtual test port corresponding to the port under test based on the electrical characteristics, so that the virtual test port is compatible with the port under test. The system receives test commands from the host computer, uses the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device, and obtains the test data of the port under test. The test data is fed back to the host computer for analysis and processing to obtain the test results of the port under test, so as to realize the test of the target chip verification board.

2. The testing method for the chip verification board according to claim 1, characterized in that, The electrical characteristic information of the port under test is determined according to the configuration instructions, and the virtual test port corresponding to the port under test is configured according to the electrical characteristic information, including: The electrical characteristic information of the port under test is determined according to the configuration instructions; the electrical characteristic information includes one or more combinations of IO type, IO level specification, and interface protocol; Configure the virtual test port corresponding to the port under test according to the electrical characteristic information; the configuration items of the virtual test port include one or more combinations of input buffer type, output buffer type, pull-up / pull-down resistor parameters, power supply parameters, and analog-to-digital conversion mode.

3. The testing method for the chip verification board according to claim 1, characterized in that, The electrical characteristic information of the port under test is determined according to the configuration instructions, and the virtual test port corresponding to the port under test is configured according to the electrical characteristic information, including: The electrical characteristics of the port under test are determined according to the configuration instructions, and the preset configuration parameters of the virtual test port are determined according to the electrical characteristics. The manual configuration parameters of the virtual test port are determined according to the configuration instructions; Actual configuration parameters are generated based on the preset configuration parameters and the manually configured parameters, and the virtual test port is configured according to the actual configuration parameters.

4. The testing method for the chip verification board according to claim 1, characterized in that, When the test command is a protocol verification command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: The master-slave mode of the port protocol corresponding to the port under test is determined according to the protocol verification command. In the master-slave mode, the virtual test port is used to perform protocol interaction with the port under test through the port connection device to obtain the protocol interaction result; The protocol interaction results are used as test data for the port under test.

5. The testing method for the chip verification board according to claim 1, characterized in that, When the test command is a transmit / receive loopback verification command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: The transmit / receive loopback verification command controls the interconnection of the transmit and receive pins of the port under test to form a hardware link closed loop for the port under test. The test signal is sent to the port under test through the virtual test port and the feedback signal of the port under test is obtained. The comparison and analysis results of the test signal and the feedback signal are used as the test data of the port under test.

6. The testing method for the chip verification board according to claim 1, characterized in that, When the test command is a stress test command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: Determine the limiting parameters according to the pressure test command; According to the aforementioned limit parameters, preset test data is sent to the port under test via the port connection device using the virtual test port. During the transmission of the preset test data, the pressure resistance index data of the port under test is statistically analyzed according to the preset pressure resistance index. The pressure resistance index data are used as the test data for the port under test.

7. The testing method for the chip verification board according to claim 1, characterized in that, When the test command is an interference injection command, the virtual test port is used to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test, including: The interference parameters are determined according to the interference injection command, and an interference signal is generated according to the interference parameters. The interference signal is injected into the port under test through the virtual test port via the port connection device. During the injection of the interference signal, the stability index data of the port under test are statistically analyzed according to the preset stability index. The stability index data are used as the test data for the port under test.

8. The testing method for the chip verification board according to claim 1, characterized in that, The test data is fed back to the host computer for analysis and processing to obtain the test results of the port under test, thereby realizing the testing of the target chip verification board, including: The test data is saved to a local log file; the local log file is used to store the test data of each functional port in the target chip verification board; When a log instruction is received from the host computer, the test data of the port to be tested is selected from the local log file according to the log instruction and fed back to the host computer for analysis and processing to obtain the test result of the port to be tested.

9. A testing system for a chip verification board, characterized in that, It includes a host computer, a main testing device, and a port connection device. The main testing device is connected to the host computer and the port connection device, respectively. The port connection device is used to connect to the port under test of the target chip verification board. The main testing device is used to receive configuration instructions from the host computer, determine the electrical characteristics of the port under test according to the configuration instructions, configure a virtual test port corresponding to the port under test according to the electrical characteristics, so that the virtual test port is compatible with the port under test; receive test instructions from the host computer, and use the virtual test port to perform the test operation corresponding to the test instructions on the port under test through the port connection device to obtain the test data of the port under test; The test data is fed back to the host computer for analysis and processing to obtain the test results of the port under test, so as to realize the test of the target chip verification board.

10. The testing system for the chip verification board according to claim 9, characterized in that, The port connection device includes probes and a standard port connector; When the port under test is equipped with a dedicated port connector, the port under test is connected to the standard port connector through the dedicated port connector, and the dedicated port connector is compatible with the standard port connector; When the port under test is not equipped with a dedicated port connector, the port under test is directly connected to the probe, and the probe is fixedly connected to the port under test through a pin header.

11. The testing system for the chip verification board according to claim 10, characterized in that, The number of probes is multiple, and the testing system also includes a mounting base for fixing the main testing device.

12. A testing device for a chip verification board, characterized in that, The device is applied to a main testing device, which is connected to a host computer and a port connection device, respectively. The port connection device is used to connect to the port under test of the target chip verification board. The device includes: The configuration module is used to receive configuration instructions from the host computer, determine the electrical characteristic information of the port under test according to the configuration instructions, and configure the virtual test port corresponding to the port under test according to the electrical characteristic information so that the virtual test port is compatible with the port under test. The testing module is used to receive test commands issued by the host computer, and use the virtual test port to perform the test operation corresponding to the test command on the port under test through the port connection device to obtain the test data of the port under test; The analysis module is used to feed the test data back to the host computer for analysis and processing, and to obtain the test results of the port under test, so as to realize the test of the target chip verification board.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the test method for the chip verification board as described in any one of claims 1 to 8.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the test method for the chip verification board as described in any one of claims 1 to 8.

15. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the testing method for the chip verification board according to any one of claims 1 to 8.

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