Data processing method and system based on data stream architecture

Abstract

The invention discloses a data processing method and system based on a data stream architecture, and relates to the field of computer system architecture design. Comprising the steps of 1, creating a data stream architecture accelerator used for executing acceleration of tridiagonal matrix solving in data processing, 2, when the data stream architecture accelerator is used for executing acceleration of tridiagonal matrix solving in data processing, the data stream architecture accelerator runs in a host machine, input data is issued to a global memory of the accelerator according to a calculation task, and the acceleration is executed. A firmware program of the computing core is initialized, the firmware program is used for loading a corresponding kernel program, the kernel program is used for executing a corresponding task load, a data load kernel program is used for initiating a read-write request to carry out data handling, and a computing load kernel program is used for consuming input data, executing a corresponding algorithm and generating output data; the calculation load kernel program comprises transposition distribution, forward elimination and backward substitution, specification and de-reconstruction, various kernel programs are issued to a calculation core of the data stream architecture accelerator in real time and are scheduled and executed, and a calculation result is retrieved from a global memory of the accelerator after the execution is finished.

Description

Technical Field

[0001] This invention discloses a data processing method and system based on a data flow architecture, which relates to the field of computer system architecture design. Background Technology

[0002] With the development of modern applications such as machine learning and high-performance computing, the scale of computational data continues to grow. To cope with the demands of large-scale data transmission and parallel processing, various heterogeneous acceleration devices have emerged. Acceleration devices integrate a large number of energy-efficient processing units, enabling them to efficiently handle data-intensive or computationally intensive tasks. General-purpose processor cores can offload such computational tasks to corresponding acceleration units to achieve speedup, and free up the general-purpose processor cores to handle other logically complex control tasks.

[0003] A tridiagonal matrix is ​​a special type of sparse square matrix where all non-zero elements are concentrated along the main diagonal, one upper diagonal, and one lower diagonal, with the remaining elements being zero. Tridiagonal matrices are widely used in scientific and engineering computing and have significant potential applications in machine learning and data mining. However, existing systems still suffer from low computational efficiency and inefficient memory and bandwidth utilization when processing tridiagonal matrices. Summary of the Invention

[0004] This invention addresses the problems of existing technologies by providing a data processing method and system based on a data flow architecture. Compared with existing CPU and GPU algorithms, it has higher computing speed, memory and bandwidth utilization, and can significantly improve computing efficiency and reduce energy consumption.

[0005] The specific solution proposed in this invention is as follows:

[0006] This invention also provides a data processing method based on a data flow architecture, comprising:

[0007] Step 1: Create a dataflow architecture accelerator to speed up the solution of tridiagonal matrices in data processing.

[0008] The dataflow architecture accelerator includes a computing core, a storage core, global memory, and an on-chip network. The computing core consists of a data workload unit, a computing workload unit, and local memory.

[0009] The data payload unit connects to the on-chip network and the local memory of the computing core it resides in. It executes the data payload kernel program and initiates read / write requests to the on-chip network.

[0010] The computational load unit is connected to local memory and is used to execute the computational load kernel program.

[0011] Local memory is used to store firmware programs, kernel programs, and local data.

[0012] The storage core connects to the on-chip network and global memory, acts as the global memory controller, and responds to read and write requests from the computing cores.

[0013] Global memory is used to store input / output data and necessary intermediate results, while on-chip networks are used to connect the various computing cores and storage cores.

[0014] Step 2: When accelerating tridiagonal matrix solving in data processing using a dataflow architecture accelerator, the dataflow architecture accelerator runs on the host machine. It sends input data to the accelerator's global memory based on the computation task, initializes the firmware of the computation core, and loads the corresponding kernel program. The kernel program executes the corresponding task load. The data load kernel program initiates read / write requests for data transfer, while the computation load kernel program consumes input data, executes the corresponding algorithm, and generates output data. The computation load kernel program includes transpose distribution, forward elimination and backward substitution, reduction, and deconstruction.

[0015] The various kernel programs are sent to the computing core of the dataflow architecture accelerator in real time and scheduled for execution. After execution, the computing results are retrieved from the global memory of the accelerator.

[0016] Furthermore, in step 1 of the data processing method based on a data flow architecture, when creating the data flow architecture accelerator, the data load unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V G extensions, and connected to the on-chip network and the local memory of the computing core through a handshake protocol bus interface.

[0017] The computational workload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V GCV, ZFH, ZVFH, and ZFBF extensions to support various logical operations. The computational workload unit is connected to local memory via a handshake protocol bus interface.

[0018] Local memory is implemented based on SRAM, connected to the processor core via a bus interface, and located close to the workload unit of the computing core in the layout. It has memory access speeds comparable to the computing core and is used to store firmware programs, kernel programs, and local data.

[0019] The storage core is implemented based on a DDR controller and connects to the on-chip network and global memory.

[0020] Furthermore, in step 2 of the data processing method based on a data flow architecture, when initializing the firmware program of the computing core, if the firmware program is used to load the data load kernel program, then the data load kernel program, when the data load unit initiates a read request, moves the data in the memory of other nodes on the on-chip network to the local memory; when it initiates a write request, it moves the data in the local memory to the memory of other nodes on the on-chip network.

[0021] Furthermore, in step 2 of the data processing method based on a data flow architecture, the transpose distribution kernel program and the corresponding data transport kernel program are sent to a specified location in the local memory of the computing core, and the computing parameters are sent to the specified parameter locations, notifying the computing load unit to execute the corresponding computing load core program.

[0022] Simultaneously, the forward elimination and backward substitution kernel programs, along with their corresponding data transport kernel programs, are sent to another specified location within the computation core, and the computation parameters are sent to another specified parameter location.

[0023] Once the computation core detects that it has completed the transpose distribution computation task, it immediately schedules the computation core to execute the forward elimination and backward substitution kernel programs, while simultaneously distributing the reduction kernel program, the corresponding data transfer kernel program, and the computation parameters in parallel.

[0024] After detecting that the computing core has completed the forward elimination and backward substitution computation tasks, the computing core is immediately scheduled to execute the reduction kernel program. At the same time, the deconstruction kernel program, the corresponding data transfer kernel program, and the computation parameters are issued in parallel.

[0025] Once the computation core has completed the reduction computation task, the computation core is immediately scheduled to execute the de-reconstruction kernel program. Once the computation core has completed the de-reconstruction computation task, the computation result is retrieved from global memory.

[0026] The present invention also provides a data processing system based on a data flow architecture, including a data flow architecture accelerator, which is used to accelerate the solution of tridiagonal matrices in data processing.

[0027] The dataflow architecture accelerator includes a computing core, a storage core, global memory, and an on-chip network. The computing core consists of a data workload unit, a computing workload unit, and local memory.

[0028] The data payload unit connects to the on-chip network and the local memory of the computing core it resides in. It executes the data payload kernel program and initiates read / write requests to the on-chip network.

[0029] The computational load unit is connected to local memory and is used to execute the computational load kernel program.

[0030] Local memory is used to store firmware programs, kernel programs, and local data.

[0031] The storage core connects to the on-chip network and global memory, acts as the global memory controller, and responds to read and write requests from the computing cores.

[0032] Global memory is used to store input / output data and necessary intermediate results, while on-chip networks are used to connect the various computing cores and storage cores.

[0033] When using a dataflow architecture accelerator to accelerate tridiagonal matrix solving in data processing, the accelerator runs on the host machine. Input data is sent to the accelerator's global memory according to the computation task, and the firmware of the computation core is initialized. The firmware loads the corresponding kernel program, which executes the corresponding task load. The data load kernel program initiates read / write requests to move data, while the computation load kernel program consumes the input data, executes the corresponding algorithm, and generates output data. The computation load kernel program includes transpose distribution, forward elimination and backward substitution, reduction, and deconstruction.

[0034] The various kernel programs are sent to the computing core of the dataflow architecture accelerator in real time and scheduled for execution. After execution, the computing results are retrieved from the global memory of the accelerator.

[0035] Furthermore, the data load unit of the data processing system based on a dataflow architecture is a processor implemented using the RISC-V instruction set, supports RISC-V G extensions, and connects to the on-chip network and the local memory of the computing core via a handshake protocol bus interface.

[0036] The computational workload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V GCV, ZFH, ZVFH, and ZFBF extensions to support various logical operations. The computational workload unit is connected to local memory via a handshake protocol bus interface.

[0037] Local memory is implemented based on SRAM, connected to the processor core via a bus interface, and located close to the workload unit of the computing core in the layout. It has memory access speeds comparable to the computing core and is used to store firmware programs, kernel programs, and local data.

[0038] The storage core is implemented based on a DDR controller and connects to the on-chip network and global memory.

[0039] Furthermore, when the firmware program of the data flow architecture accelerator of the data processing system based on the data flow architecture initializes the computing core, if the firmware program is used to load the data load kernel program, then the data load kernel program, when the data load unit initiates a read request, moves the data in the memory of other nodes on the on-chip network to the local memory; when it initiates a write request, it moves the data in the local memory to the memory of other nodes on the on-chip network.

[0040] Furthermore, the data processing system based on a dataflow architecture runs a dataflow architecture accelerator, distributes the transpose distribution kernel program and the corresponding data transport kernel program to a specified location in the local memory of the computing core, distributes the computing parameters to the specified parameter location, and notifies the computing load unit to execute the corresponding computing load core program.

[0041] Simultaneously, the forward elimination and backward substitution kernel programs, along with their corresponding data transport kernel programs, are sent to another specified location within the computation core, and the computation parameters are sent to another specified parameter location.

[0042] Once the computation core detects that it has completed the transpose distribution computation task, it immediately schedules the computation core to execute the forward elimination and backward substitution kernel programs, while simultaneously distributing the reduction kernel program, the corresponding data transfer kernel program, and the computation parameters in parallel.

[0043] After detecting that the computing core has completed the forward elimination and backward substitution computation tasks, the computing core is immediately scheduled to execute the reduction kernel program. At the same time, the deconstruction kernel program, the corresponding data transfer kernel program, and the computation parameters are issued in parallel.

[0044] Once the computation core has completed the reduction computation task, the computation core is immediately scheduled to execute the de-reconstruction kernel program. Once the computation core has completed the de-reconstruction computation task, the computation result is retrieved from global memory.

[0045] The advantages of this invention are:

[0046] By utilizing a dataflow architecture accelerator based on on-chip networks, a parallel algorithm solver for tridiagonal matrices is implemented. Compared with traditional CPU and GPU algorithms, it has higher computing speed, memory and bandwidth utilization, which can significantly improve computing efficiency and reduce energy consumption. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0048] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0049] Example 1

[0050] This invention also provides a data processing method based on a data flow architecture, comprising:

[0051] Step 1: Create a dataflow architecture accelerator to speed up the solution of tridiagonal matrices in data processing.

[0052] The dataflow architecture accelerator includes a computing core, a storage core, global memory, and an on-chip network. The computing core consists of a data workload unit, a computing workload unit, and local memory.

[0053] The data payload unit connects to the on-chip network and the local memory of the computing core it resides in. It executes the data payload kernel program and initiates read / write requests to the on-chip network.

[0054] The computational load unit is connected to local memory and is used to execute the computational load kernel program.

[0055] Local memory is used to store firmware programs, kernel programs, and local data.

[0056] The storage core connects to the on-chip network and global memory, acts as the global memory controller, and responds to read and write requests from the computing cores.

[0057] Global memory is used to store input and output data and necessary intermediate results, while on-chip network is used to connect various computing cores and storage cores.

[0058] When creating the dataflow architecture accelerator, the data payload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V G extensions, and connected to the on-chip network and the local memory of the computing core via a handshake protocol bus interface.

[0059] The computational workload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V GCV, ZFH, ZVFH, and ZFBF extensions to support various logical operations. The computational workload unit is connected to local memory via a handshake protocol bus interface.

[0060] Local memory is implemented based on SRAM, connected to the processor core via a bus interface, and located close to the workload unit of the computing core in the layout. It has memory access speeds comparable to the computing core and is used to store firmware programs, kernel programs, and local data.

[0061] The storage core is implemented based on a DDR controller and connects to the on-chip network and global memory.

[0062] Step 2: When accelerating tridiagonal matrix solving in data processing using a dataflow architecture accelerator, the dataflow architecture accelerator runs on the host machine. It sends input data to the accelerator's global memory according to the computation task and initializes the firmware of the computation core. The firmware is used to load the corresponding kernel program.

[0063] If the firmware program is used to load the data payload kernel program, the data payload kernel program is used to move data from the memory of other nodes on the on-chip network to local memory when the data payload unit initiates a read request; and to move data from local memory to the memory of other nodes on the on-chip network when it initiates a write request.

[0064] The kernel program is used to execute the corresponding task workload. The data workload kernel program initiates read and write requests to move data, while the computation workload kernel program consumes input data, executes the corresponding algorithm, and generates output data. The computation workload kernel program includes transpose dispatch, forward elimination and backward substitution, reduction, and deconstruction.

[0065] The various kernel programs are sent to the computing core of the dataflow architecture accelerator in real time and scheduled for execution. After execution, the computing results are retrieved from the global memory of the accelerator.

[0066] The process involves sending the transpose distribution kernel program and the corresponding data transport kernel program to a specified location in the local memory of the computing core, sending the computing parameters to the specified parameter location, and notifying the computing load unit to execute the corresponding computing load kernel program. For example, in distributed GPU computing, transpose distribution requires dividing the matrix into blocks and transposing and allocating them across nodes to optimize memory access locality and reduce cross-node communication overhead.

[0067] Simultaneously, the forward elimination and backward substitution kernel programs, along with their corresponding data transport kernel programs, are sent to another designated location within the computational core. Computational parameters are also sent to another designated parameter location. Forward elimination, a method for solving linear equations, involves transforming the coefficient matrix into an upper triangular matrix through row operations while simultaneously manipulating the right-hand vectors to obtain intermediate results. Backward substitution refers to solving for the unknowns by substituting back from the last row upwards; both are computational processes.

[0068] After detecting that the computing core has completed the transpose distribution computing task, the computing core is immediately scheduled to execute the forward elimination and backward substitution kernel programs. At the same time, the reduction kernel program, the corresponding data transfer kernel program and computing parameters are distributed in parallel. The reduction computing refers to the operation of merging data scattered in multiple computing units such as CPU threads and GPU thread bundles into a single result, such as summation, finding the maximum value, finding the average value, etc.

[0069] After detecting that the computing core has completed the forward elimination and backward substitution calculation tasks, the computing core is immediately scheduled to execute the reduction kernel program. At the same time, the deconstruction kernel program, the corresponding data transfer kernel program, and the calculation parameters are issued in parallel. In numerical computation, deconstruction refers to the process of reconstructing a high-precision solution based on intermediate results such as coarse mesh solutions and low-precision approximations.

[0070] Once the computation core has completed the reduction computation task, the computation core is immediately scheduled to execute the de-reconstruction kernel program. Once the computation core has completed the de-reconstruction computation task, the computation result is retrieved from global memory.

[0071] Example 2

[0072] The present invention also provides a data processing system based on a data flow architecture, including a data flow architecture accelerator, which is used to accelerate the solution of tridiagonal matrices in data processing.

[0073] The dataflow architecture accelerator includes a computing core, a storage core, global memory, and an on-chip network. The computing core consists of a data workload unit, a computing workload unit, and local memory.

[0074] The data payload unit connects to the on-chip network and the local memory of the computing core it resides in. It executes the data payload kernel program and initiates read / write requests to the on-chip network.

[0075] The computational load unit is connected to local memory and is used to execute the computational load kernel program.

[0076] Local memory is used to store firmware programs, kernel programs, and local data.

[0077] The storage core connects to the on-chip network and global memory, acts as the global memory controller, and responds to read and write requests from the computing cores.

[0078] Global memory is used to store input / output data and necessary intermediate results, while on-chip networks are used to connect the various computing cores and storage cores.

[0079] When using a dataflow architecture accelerator to accelerate tridiagonal matrix solving in data processing, the accelerator runs on the host machine. Input data is sent to the accelerator's global memory according to the computation task, and the firmware of the computation core is initialized. The firmware loads the corresponding kernel program, which executes the corresponding task load. The data load kernel program initiates read / write requests to move data, while the computation load kernel program consumes the input data, executes the corresponding algorithm, and generates output data. The computation load kernel program includes transpose distribution, forward elimination and backward substitution, reduction, and deconstruction.

[0080] The various kernel programs are sent to the computing core of the dataflow architecture accelerator in real time and scheduled for execution. After execution, the computing results are retrieved from the global memory of the accelerator.

[0081] The information interaction and execution of readable programs by the accelerators in the above system are based on the same concept as the method embodiments of the present invention, and the specific details can be found in the descriptions in the method embodiments of the present invention, and will not be repeated here.

[0082] Similarly, the system of the present invention utilizes a dataflow architecture accelerator based on on-chip network to implement a parallel algorithm solver for tridiagonal matrices. Compared with traditional CPU and GPU algorithms, it has higher computing speed, memory and bandwidth utilization, which can significantly improve computing efficiency and reduce energy consumption.

[0083] It should be noted that not all steps and modules in the above processes and system structures are mandatory; some steps or modules can be omitted as needed. The execution order of each step is not fixed and can be adjusted as required. The system structures described in the above embodiments can be physical or logical structures. That is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities, or they may be jointly implemented by certain components in multiple independent devices.

[0084] The above-described embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention. The scope of protection of the present invention is defined by the claims.

Claims

1. A data processing method based on a dataflow architecture, characterized by: include: Step 1: Create a dataflow architecture accelerator to speed up the solution of tridiagonal matrices in data processing. The dataflow architecture accelerator includes a computing core, a storage core, global memory, and an on-chip network. The computing core consists of a data workload unit, a computing workload unit, and local memory. The data payload unit connects to the on-chip network and the local memory of the computing core it resides in. It executes the data payload kernel program and initiates read / write requests to the on-chip network. The computational load unit is connected to local memory and is used to execute the computational load kernel program. Local memory is used to store firmware programs, kernel programs, and local data. The storage core connects to the on-chip network and global memory, acts as the global memory controller, and responds to read and write requests from the computing cores. Global memory is used to store input / output data and necessary intermediate results, while on-chip networks are used to connect the various computing cores and storage cores. Step 2: When accelerating tridiagonal matrix solving in data processing using a dataflow architecture accelerator, the dataflow architecture accelerator runs on the host machine. It sends input data to the accelerator's global memory based on the computation task, initializes the firmware of the computation core, and loads the corresponding kernel program. The kernel program executes the corresponding task load. The data load kernel program initiates read / write requests for data transfer, while the computation load kernel program consumes input data, executes the corresponding algorithm, and generates output data. The computation load kernel program includes transpose distribution, forward elimination and backward substitution, reduction, and deconstruction. The various kernel programs are sent to the computing core of the dataflow architecture accelerator in real time and scheduled for execution. After execution, the computing results are retrieved from the global memory of the accelerator.

2. The data processing method based on a data flow architecture according to claim 1, characterized in that: In step 1, when creating the dataflow architecture accelerator, the data payload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V G extensions, and connected to the on-chip network and the local memory of the computing core via a handshake protocol bus interface. The computational workload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V GCV, ZFH, ZVFH, and ZFBF extensions to support various logical operations. The computational workload unit is connected to local memory via a handshake protocol bus interface. Local memory is implemented based on SRAM, connected to the processor core via a bus interface, and located close to the workload unit of the computing core in the layout. It has memory access speeds comparable to the computing core and is used to store firmware programs, kernel programs, and local data. The storage core is implemented based on a DDR controller and connects to the on-chip network and global memory.

3. The data processing method based on a dataflow architecture according to claim 1, characterized in that: In step 2, when initializing the firmware of the computing core, if the firmware is used to load the data payload kernel program, then the data payload kernel program, when the data payload unit initiates a read request, moves the data in the memory of other nodes on the on-chip network to the local memory; when it initiates a write request, it moves the data in the local memory to the memory of other nodes on the on-chip network.

4. The data processing method based on a data flow architecture according to claim 1, characterized in that: In step 2, the transpose distribution kernel program and the corresponding data transport kernel program are sent to a specified location in the local memory of the computing core, and the computing parameters are sent to the specified parameter locations. The computing load unit is then notified to execute the corresponding computing load core program. Simultaneously, the forward elimination and backward substitution kernel programs, along with their corresponding data transport kernel programs, are sent to another specified location within the computation core, and the computation parameters are sent to another specified parameter location. Once the computation core detects that it has completed the transpose distribution computation task, it immediately schedules the computation core to execute the forward elimination and backward substitution kernel programs, while simultaneously distributing the reduction kernel program, the corresponding data transfer kernel program, and the computation parameters in parallel. After detecting that the computing core has completed the forward elimination and backward substitution computation tasks, the computing core is immediately scheduled to execute the reduction kernel program. At the same time, the deconstruction kernel program, the corresponding data transfer kernel program, and the computation parameters are issued in parallel. Once the computation core has completed the reduction computation task, the computation core is immediately scheduled to execute the de-reconstruction kernel program. Once the computation core has completed the de-reconstruction computation task, the computation result is retrieved from global memory.

5. A data processing system based on a dataflow architecture, characterized by: This includes a dataflow architecture accelerator used to accelerate tridiagonal matrix solving in data processing. The dataflow architecture accelerator includes a computing core, a storage core, global memory, and an on-chip network. The computing core consists of a data workload unit, a computing workload unit, and local memory. The data payload unit connects to the on-chip network and the local memory of the computing core it resides in. It executes the data payload kernel program and initiates read / write requests to the on-chip network. The computational load unit is connected to local memory and is used to execute the computational load kernel program. Local memory is used to store firmware programs, kernel programs, and local data. The storage core connects to the on-chip network and global memory, acts as the global memory controller, and responds to read and write requests from the computing cores. Global memory is used to store input / output data and necessary intermediate results, while on-chip networks are used to connect the various computing cores and storage cores. When using a dataflow architecture accelerator to accelerate tridiagonal matrix solving in data processing, the accelerator runs on the host machine. Input data is sent to the accelerator's global memory according to the computation task, and the firmware of the computation core is initialized. The firmware loads the corresponding kernel program, which executes the corresponding task load. The data load kernel program initiates read / write requests to move data, while the computation load kernel program consumes the input data, executes the corresponding algorithm, and generates output data. The computation load kernel program includes transpose distribution, forward elimination and backward substitution, reduction, and deconstruction. The various kernel programs are sent to the computing core of the dataflow architecture accelerator in real time and scheduled for execution. After execution, the computing results are retrieved from the global memory of the accelerator.

6. A data processing system based on a dataflow architecture according to claim 5, characterized in that the data... The workload unit is a processor implemented based on the RISC-V instruction set, supports RISC-V G extensions, and connects to the on-chip network and the local memory of the computing core via a handshake protocol bus interface. The computational workload unit is a processor implemented based on the RISC-V instruction set, supporting RISC-V GCV, ZFH, ZVFH, and ZFBF extensions to support various logical operations. The computational workload unit is connected to local memory via a handshake protocol bus interface. Local memory is implemented based on SRAM, connected to the processor core via a bus interface, and located close to the workload unit of the computing core in the layout. It has memory access speeds comparable to the computing core and is used to store firmware programs, kernel programs, and local data. The storage core is implemented based on a DDR controller and connects to the on-chip network and global memory.

7. A data processing system based on a dataflow architecture according to claim 5, characterized in that: When the firmware of the computing core is initialized by the dataflow architecture accelerator, if the firmware is used to load the data payload kernel program, then the data payload kernel program, when the data payload unit initiates a read request, moves the data in the memory of other nodes on the on-chip network to the local memory; when it initiates a write request, it moves the data in the local memory to the memory of other nodes on the on-chip network.

8. A data processing system based on a dataflow architecture according to claim 5, characterized in that: The data processing system runs a dataflow architecture accelerator, which distributes the transpose kernel program and the corresponding data transport kernel program to a specified location in the local memory of the computing core, and distributes the computing parameters to the specified parameter locations, notifying the computing load unit to execute the corresponding computing load core program. Simultaneously, the forward elimination and backward substitution kernel programs, along with their corresponding data transport kernel programs, are sent to another specified location within the computation core, and the computation parameters are sent to another specified parameter location. Once the computation core detects that it has completed the transpose distribution computation task, it immediately schedules the computation core to execute the forward elimination and backward substitution kernel programs, while simultaneously distributing the reduction kernel program, the corresponding data transfer kernel program, and the computation parameters in parallel. After detecting that the computing core has completed the forward elimination and backward substitution computation tasks, the computing core is immediately scheduled to execute the reduction kernel program. At the same time, the deconstruction kernel program, the corresponding data transfer kernel program, and the computation parameters are issued in parallel. Once the computation core has completed the reduction computation task, the computation core is immediately scheduled to execute the de-reconstruction kernel program. Once the computation core has completed the de-reconstruction computation task, the computation result is retrieved from global memory.

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