Error injection and fault-tolerant testing system in memory chip ft testing

Abstract

The application relates to the technical field of semiconductor testing, and particularly discloses an error injection and fault-tolerant test system in FT testing of a storage chip. The system comprises a test control host, a programmable error injection module, a protocol state monitoring module, a multi-dimensional response analysis module and a test scene generation engine. Through cooperative work, the system can automatically generate and inject error sequences, non-invasively monitor the internal state of a protocol, and perform timing, logic and statistical analysis, so that automatic, high-intensity stress testing and comprehensive evaluation of the fault-tolerant capability of a chip are realized. The system forms a closed-loop system of the programmable error injection module and the test scene generation engine, and realizes automatic stress testing of a high intensity and high concurrency of a fault-tolerant protocol of a storage chip.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing technology, specifically relating to an error injection and fault tolerance testing system in the FT test of memory chips. Background Technology

[0002] In the field of semiconductor testing technology, final testing of memory chips is a crucial step in ensuring their factory quality and reliability. Fault tolerance testing aims to verify the correct response and recovery capabilities of the complex fault tolerance protocols integrated within the chip when encountering various errors, and is the core of evaluating chip robustness.

[0003] The core objective of fault-tolerant testing technology for memory chips is to systematically evaluate the effectiveness of the chip's built-in error detection, correction, and recovery mechanisms by simulating various failure scenarios. This fault-tolerant testing technology is crucial for ensuring data integrity and system stability in complex application environments.

[0004] In existing technologies, simulation testing of complex on-chip fault-tolerant protocols typically employs limited, targeted test cases. This fails to exhaust all interactions of the protocol state machine under abnormal, concurrent, and extreme stress conditions, making it difficult to expose deep-seated logical defects such as deadlocks, livelocks, or performance cliffs. This testing method, based on pre-defined scenarios, has limited coverage and cannot effectively simulate random, concurrent, and complex error injection sequences in real-world operating environments, resulting in insufficient sufficiency and depth of testing.

[0005] Therefore, in the final testing phase of memory chips, how to build a test system that can comprehensively and efficiently stimulate and verify the extreme capabilities of its fault tolerance protocol has become an urgent technical problem to be solved. Summary of the Invention

[0006] This invention provides an error injection and fault tolerance testing system for FT testing of memory chips, in order to solve the problems of limited coverage of fault tolerance protocol testing in the prior art, inability to effectively simulate real complex concurrent error scenarios, and difficulty in exposing deep-seated logical defects.

[0007] The technical solution of this invention is an error injection and fault tolerance testing system for memory chip FT testing. This system includes a test control host, a programmable error injection module, a protocol status monitoring module, a multi-dimensional response analysis module, and a test scenario generation engine. The test control host, as the central scheduling and decision-making core of the system, is responsible for coordinating the collaborative work of each module and executing the final test judgment. The programmable error injection module is physically connected to the test interface of the memory chip under test and is used to inject preset types of electrical or logical errors in real time and accurately during chip operation according to the received injection instructions.

[0008] The protocol status monitoring module connects to a pre-defined debug bus or status register inside the memory chip under test via a high-speed probe. This allows for real-time capture and recording of state machine transitions, error flag changes, and critical control signal levels within the fault-tolerant protocol. The multi-dimensional response analysis module connects to both the protocol status monitoring module and the test control host, enabling in-depth timing, logic, and statistical analysis of the captured protocol response data. The test scenario generation engine, integrated into the test control host, automatically generates and dynamically schedules complex concurrent error injection test sequences based on a predefined error model library and protocol specifications.

[0009] Furthermore, the programmable error injection module includes a precise timing unit, an error type library unit, and a physical layer driver unit. The precise timing unit receives injection timing parameters from the test scenario generation engine; these parameters are accurate to the nanosecond level and are used to control the absolute timing and duration of the error injection. The error type library unit stores various predefined error models, including but not limited to single-bit flip errors, multi-bit burst errors, address line sticking errors, command decoding errors, power supply glitches, and clock jitter simulations. The physical layer driver unit generates corresponding abnormal voltage, current, or digital signal waveforms based on the selected error model and timing parameters, and selectively applies them to designated pins or internal access paths of the chip under test via a multiplexer.

[0010] Furthermore, the protocol status monitoring module is implemented based on non-intrusive tracking technology. This module includes a high-speed sampling circuit, protocol parsing logic, and a real-time stream buffer. The high-speed sampling circuit synchronously samples parallel data on the debug bus at a frequency several times higher than the main clock of the chip under test. The protocol parsing logic incorporates the state transition table and signal definitions of the fault-tolerant protocol under test, enabling real-time decoding of the sampled raw data stream into readable state names, event identifiers, and data values. The real-time stream buffer adopts a first-in-first-out (FIFO) structure to temporarily store the decoded protocol activity trajectory and pushes it to the multi-dimensional response analysis module in a streaming manner.

[0011] Furthermore, the multi-dimensional response analysis module includes a timing violation detection submodule, a logical consistency verification submodule, and a statistical performance analysis submodule. The timing violation detection submodule compares the response timing captured by the protocol state monitoring module with the protocol timing specifications pre-stored in the test control host to detect whether indicators such as state recovery time and error acknowledgment delay exceed limits. The logical consistency verification submodule verifies the legality of the monitored actual state transition sequence based on the standard finite state machine model of the fault-tolerant protocol, and specifically detects the existence of undefined state transitions, deadlock (infinite loop state), and error handling states that cannot be exited (deadlock state). The statistical performance analysis submodule aggregates and calculates various response time, error correction rate, and protocol overhead data collected from multiple tests, generates a statistical distribution chart, and identifies performance cliffs—the sharp deterioration of performance indicators when the error rate or concurrency exceeds a certain threshold.

[0012] Furthermore, the core of the test scenario generation engine is a sequence generator based on constraint randomization. The sequence generator's workflow is as follows: First, it selects multiple basic error types from an error model library as seeds. Next, it randomly generates the injection time point, duration, location, and intensity parameters for each error type. This randomization process is subject to a set of predefined constraints, including but not limited to the minimum time interval between errors, the inability of mutually exclusive error types to occur simultaneously, and the requirement that the error intensity must not exceed the chip's physical damage threshold. Then, the sequence generator arranges and combines multiple such random error instances chronologically to form complex test scenarios containing both concurrent and sequential errors. Finally, the generation engine attaches the expected correct protocol response sequence to each scenario as a crucial reference for subsequent analysis and comparison.

[0013] Furthermore, the test scenario generation engine integrates an adaptive feedback learning unit. This unit receives test result data from the multi-dimensional response analysis module, particularly those scenario features that expose protocol defects or are at performance limits. The adaptive feedback learning unit employs a coverage-based optimization algorithm. Specifically, the system maintains a coverage table of protocol states and transitions, recording states and edges triggered by the tested scenarios. After analyzing new test results, the algorithm prioritizes generating error combinations that can trigger uncovered states or transitions, while simultaneously increasing error pattern mutations near discovered defective scenarios, thereby guiding the test to evolve deeper into unexplored or high-risk areas.

[0014] Furthermore, the overall test process executed by the test control host is as follows: The test control host initializes the entire system and loads the protocol description file of the chip under test. The test scenario generation engine generates the first concurrent error injection test sequence and sends it to the programmable error injection module. The test control host commands the chip under test to start executing the standard workload. During chip operation, the programmable error injection module injects errors at precise times according to the sequence. Simultaneously, the protocol status monitoring module captures the internal activities of the protocol throughout the process. After injection, the multi-dimensional response analysis module analyzes the response data and reports the results to the test control host. The test control host determines whether the behavior of the fault-tolerant protocol in this test scenario meets expectations based on the analysis results. The test scenario generation engine generates the next test sequence based on coverage and feedback information. This cycle continues until the preset test duration or protocol status coverage target is reached.

[0015] Furthermore, the system also includes a comprehensive test result reporting unit. This unit summarizes the execution results of all test scenarios and generates a comprehensive test report that includes a protocol state coverage matrix, a list of timing violations, detailed logs of logical defects, statistical performance charts, and a final fault tolerance level assessment.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] 1. This invention achieves high-intensity, high-concurrency automated stress testing of memory chip fault-tolerant protocols by constructing a closed-loop system consisting of a programmable error injection module and a test scenario generation engine. The system can generate random concurrent error sequences far exceeding the scope of manual design, effectively simulating complex fault scenarios in harsh real-world environments. This greatly improves the sufficiency and depth of testing, and can more reliably expose deep-seated boundary condition defects and concurrent interaction problems in the protocol design.

[0018] 2. This invention, through the collaboration of a protocol status monitoring module and a multi-dimensional response analysis module, achieves non-intrusive, fine-grained observation and multi-dimensional in-depth analysis of the internal behavior of fault-tolerant protocols. It can not only verify functional correctness but also accurately quantify timing compliance, detect deadlocks and livelocks in the logic state machine, and identify statistical performance cliffs. This provides a comprehensive qualitative and quantitative assessment of the chip's fault tolerance capabilities, offering a solid data foundation for chip reliability assessment.

[0019] 3. This invention enables the testing process to have intelligent evolution capabilities through the adaptive feedback learning unit integrated in the test scenario generation engine. Based on historical test coverage and defect discovery information, the system can dynamically adjust the test scenario generation strategy, proactively explore untested protocol state spaces and defect-prone areas, thereby approaching the test completeness target with higher efficiency. This overcomes the shortcomings of traditional random testing, which is characterized by high blindness and low efficiency, and maximizes test effectiveness with limited testing resources. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention;

[0021] Figure 2 This is a schematic diagram of the core principle framework of the test scenario generation engine based on constraint randomization and adaptive feedback in this invention.

[0022] Figure 3 This is a logical flowchart of the collaborative operation of programmable error injection, protocol status monitoring, and multi-dimensional response analysis in this invention.

[0023] Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow between the test control host, the programmable error injection module and the chip under test in this invention;

[0024] Figure 5 This is a schematic diagram illustrating the technical effect of the adaptive feedback learning unit in this invention guiding the test scenario to evolve towards an uncovered protocol state. Detailed Implementation

[0025] Example 1: The overall architecture of the fault injection and fault tolerance testing system for memory chip FT testing proposed in this invention is as follows: Figure 1 As shown in the attached diagram. This system consists of five core components: a test control host, a programmable error injection module, a protocol status monitoring module, a multi-dimensional response analysis module, and a test scenario generation engine. These modules work closely together via a high-speed data bus and control signal lines, forming a closed-loop, adaptive, and high-precision fault-tolerant verification platform. The following will be discussed in conjunction with the attached diagram. Figure 1 To be continued Figure 5 The internal structure, working principle, interaction logic, and specific implementation details of each component of the system are explained layer by layer.

[0026] As the central scheduling and decision-making core of the entire system, the test control host undertakes key functions such as initialization configuration, task distribution, result judgment, and report generation. During the test startup phase, the test control host loads the protocol description file of the memory chip under test. This file, in a structured format, defines in detail the state machine model, legal state transition rules, key signal timing constraints, error handling procedures, and expected response behaviors of the fault-tolerant protocol. The protocol description file is typically written using Extended Markup Language (Extended Markup Language) or a subset of a dedicated hardware description language, and includes fields such as a list of state names, state transition conditions, input event sets, output action definitions, and timeout threshold parameters. After parsing the protocol description file, the test control host distributes its internal representation to the protocol state monitoring module for building real-time parsing logic and to the multi-dimensional response analysis module for establishing a golden reference benchmark. Furthermore, the test control host is also responsible for setting global test parameters, including the maximum test duration, target protocol state coverage, maximum number of concurrent errors, and physical damage safety threshold.

[0027] The interaction between the test control host and the programmable error injection module is as follows: Figure 4 As shown, the test control host sends a sequence of injection instructions accurate to the nanosecond level to the programmable error injection module via a high-speed serial control link. This injection instruction sequence is dynamically generated by the test scenario generation engine and includes the type identifier, target pin or internal path address, injection start timestamp, duration, and strength parameters for each error instance. Upon receiving the instruction, the programmable error injection module immediately enters a standby state and, driven by a local high-precision clock synchronization unit, triggers the error injection operation at the specified time.

[0028] The programmable error injection module consists of three internal structures: a precise timing unit, an error type library unit, and a physical layer driver unit. The precise timing unit employs a phase-locked loop (PLL)-based delay-locked loop structure, integrating a sub-nanosecond resolution digital delay line. This unit receives injection timing parameters from the test control host and converts them into a precise trigger signal in the local clock domain. For example, if the master clock frequency is 500 MHz and the injection command requires an error to be injected at 1023.7 nanoseconds, the precise timing unit will calculate the corresponding number of clock cycles and the remaining delay, and output the trigger pulse after precise delay via the digital delay line. This exposure protocol design ensures that the absolute accuracy of the error injection timing is better than 0.1 nanoseconds, far exceeding the microsecond-level accuracy of traditional general-purpose test equipment.

[0029] The error type library unit is embedded in the programmable error injection module in read-only memory and pre-stores 12 basic error models. These include single-bit flip errors, used to simulate soft errors caused by cosmic rays; multi-bit burst errors, simulating ionization effects in localized areas; address line sticking errors, characterized by a certain address line being constantly high or low; command decoding errors, causing the chip to misjudge the operation type by tampering with the encoded bits on the command bus; power supply glitches, superimposed with brief voltage spikes or drops on the VDD or VSS pins; and clock jitter simulation, superimposed with random or periodic phase disturbances on the clock input pins. Each error model is associated with a set of adjustable parameters, such as the bit position of the single-bit flip, the length and start position of the multi-bit burst, and the amplitude and duration of the power supply glitches. The error type library unit supports dynamic updates via the test control host, allowing users to customize new error models according to specific chip architectures or application scenarios.

[0030] The physical layer driver unit serves as the physical interface between the programmable error injection module and the memory chip under test (MDT). This unit comprises a set of high-bandwidth, high-slew-rate analog / digital hybrid driver circuits, each corresponding to a programmable error injection channel. Upon receiving the error model and parameters selected by the error type library unit, the physical layer driver unit generates the corresponding abnormal signal waveform. For example, for a single-bit flip error, the driver unit outputs an inverted pulse with a width of one master clock cycle on the specified data line; for power supply glitch simulation, the driver unit superimposes a square wave pulse with an amplitude of ±0.5 volts and a duration of 5 nanoseconds onto the power supply pin through a low-impedance buffer. All driver channels are equipped with multiplexed switch arrays, which can be selectively connected to external pins of the DDT or accessed via probes to internal access paths according to the injection command. The switching time of the multiplexed switches is less than 0.5 nanoseconds, ensuring that the error injection process does not introduce additional timing uncertainties.

[0031] Simultaneously with error injection, the protocol status monitoring module non-intrusively captures the operational status of the fault-tolerant protocol within the tested memory chip in real time. This module is implemented based on a pre-defined debug bus or dedicated status register set within the chip; these hardware resources are reserved during the chip design phase to support mass production testing and field diagnostics. The protocol status monitoring module is physically connected to the debug bus via a high-frequency probe array with a probe bandwidth of at least 10 GHz to ensure signal integrity. Figure 1 As shown, the protocol status monitoring module includes three sub-units: a high-speed sampling circuit, protocol parsing logic, and a real-time stream buffer.

[0032] The high-speed sampling circuit employs a parallel time-interleaved architecture, consisting of eight independent sample-and-hold amplifiers, each operating at a frequency four times the main clock frequency of the chip under test (DUT). For example, if the DUT's main clock frequency is 1 GHz, the effective sampling rate of the high-speed sampling circuit is 4 GHz, with a sampling interval of 0.25 nanoseconds. This high-speed sampling circuit synchronously samples the 32-bit parallel status signal on the debug bus and sends the raw sampled data to the protocol parsing logic. The protocol parsing logic is a configurable hardware state machine, internally containing the state transition table of the fault-tolerant protocol under test. This state transition table is loaded by the test control host during the initialization phase and includes the encoding of all legal states, the triggering conditions for state transitions, and the output actions accompanying the transitions. The protocol parsing logic compares the sampled data stream with the state transition table in real time, decoding the raw binary stream into human-readable state names and key data values. The decoded protocol activity trace is written to the real-time stream buffer in a structured record format.

[0033] The real-time streaming buffer employs a first-in, first-out (FIFO) queue structure with a depth of 65,536 records. Each record includes a timestamp, status name, event identifier, relevant data fields, and a checksum. The buffer pushes data to the multi-dimensional response analysis module in a streaming manner via a high-speed serial link, ensuring no data loss occurs under high-concurrency error injection scenarios. When the buffer approaches full capacity, the protocol status monitoring module sends a flow control signal to the test control host, which can temporarily reduce the error injection rate to maintain system stability.

[0034] The multi-dimensional response analysis module receives the protocol activity trajectory stream from the protocol status monitoring module and performs three levels of in-depth analysis: timing violation detection, logical consistency verification, and statistical performance analysis. The internal structure of this multi-dimensional response analysis module is as follows: Figure 3 As shown, its workflow and the functions of each sub-module are described below.

[0035] The timing violation detection submodule maintains the protocol timing specification database, which is loaded by the test control host during the initialization phase. This database contains the legal ranges for various key timing indicators. For example, the maximum delay from error detection to entering the recovery state is 100 nanoseconds, the minimum interval from ECC error correction completion to normal read / write recovery is 50 nanoseconds, and the maximum timeout threshold for the retry mechanism is 1 microsecond. The timing violation detection submodule traverses the protocol activity trajectory stream, extracts the time intervals between adjacent events, and compares them with the thresholds in the specification database. If any time interval is found to exceed the specified range, a violation event is recorded, including the violation type, occurrence time, involved state, deviation of the actual value from the threshold, and a violation alarm signal is generated. All violation events are summarized in the test result comprehensive reporting unit to form a timing violation list.

[0036] The core of the logic consistency verification submodule is the protocol state machine simulator. This simulator loads a finite state machine model identical to the chip under test and is driven by the same input event stream as the protocol state monitoring module. The simulator outputs the expected next state each clock cycle, and the logic consistency verification submodule compares this expected state with the actual state captured by the protocol state monitoring module cycle by cycle. If they are inconsistent, it is determined to be a logic inconsistency event. Furthermore, this submodule specifically deploys deadlock and livelock detection algorithms. Deadlock detection is achieved by identifying whether there are unexitable loop paths in the "error handling state": if the system stays in an error handling state for more than a preset threshold without any state transition, it is marked as a potential deadlock. Livelock detection is achieved by analyzing the entropy value of the state transition sequence: if the system oscillates at high frequency between several states and cannot enter a stable state, it is determined to be a livelock. All logic inconsistencies, deadlocks, and livelock events are recorded in detail, including complete state transition sequences, loop paths, dwell times, etc., forming a detailed logic defect log.

[0037] The statistical performance analysis submodule aggregates and calculates response data collected during multiple test runs. Its input data includes recovery time after each error injection, ECC error correction success rate, protocol overhead, and number of retries. This submodule employs a sliding window mechanism to model the relationship between independent variables such as the number of concurrent errors and error intensity and the aforementioned performance metrics. Specifically, this submodule implements a performance cliff identification algorithm: when the error rate or concurrency increases in increments of 1, if the degradation of a performance metric exceeds three times the standard deviation of the previous interval, a performance cliff is identified, and the location of the cliff point is recorded. This information is crucial for assessing the chip's reliability boundary under extreme conditions.

[0038] The test scenario generation engine is the core driving force for this system to achieve intelligent and efficient testing. Its internal architecture is as follows: Figure 2 As shown. This test scenario generation engine is integrated into the test control host and consists of two parts: a sequence generator based on constraint randomization and an adaptive feedback learning unit. The workflow of the sequence generator is as follows: First, k basic error types are randomly selected from the error type library, where k is an integer between 1 and the preset maximum concurrency; then, a four-dimensional parameter vector is generated for each error type: injection time point. , in 0 to Evenly distributed within the range, Maximum duration and duration of a single test , in 1 to Values ​​and positions within each clock cycle Randomly selected based on the chip pin mapping table, intensity parameters Within a safety threshold range, samples are collected using a Gaussian distribution; a set of hard constraints are applied to filter the generated parameter vectors, including: the time interval between any two erroneous injections must be greater than the minimum safety interval Δ. Mutually exclusive error types cannot coexist in the same scenario; all intensity parameters must satisfy | |≤ _max; Arranges the error instances that pass the constraint check in chronological order to form a concurrent error injection test sequence, and attaches the expected correct response sequence generated by the protocol state machine simulator as a gold reference.

[0039] Adaptive feedback learning units such as Figure 5 As shown, its goal is to guide the test towards an uncovered protocol state space. The adaptive feedback learning unit maintains a coverage table of protocol states and transitions, where each entry corresponds to a state or state transition edge, initially set to uncovered. After each test, the multi-dimensional response analysis module feeds back all states and transition edges triggered in this test to the adaptive feedback learning unit. This unit updates the coverage table and calculates the current coverage rate. If the coverage rate does not reach the target, an optimization algorithm is initiated: identifying all uncovered states or transition edges; then analyzing the characteristics of discovered defective scenarios; subsequently, when generating new test scenarios, prioritizing error type combinations that can trigger uncovered items, and performing parameter mutations near known defective scenarios. This process concentrates test resources on high-value areas, improving test efficiency. For example, if a test finds that the combination of "address line sticking + clock jitter" causes deadlock under specific timing conditions, subsequent scenarios will systematically explore variations with different sticking bits, different jitter frequencies, and different time offsets based on this combination to fully expose the boundary conditions of the defect.

[0040] The entire system's testing process is centrally scheduled by the test control host, with the following specific steps: First, the system powers on and performs a self-test, with each module initializing. Second, the test control host loads the protocol description file and test configuration parameters of the chip under test. Third, the test scenario generation engine generates the first concurrent error injection test sequence and sends it to the programmable error injection module. Fourth, the test control host sends a start command to the chip under test, initiating the execution of its standard workload. Fifth, during chip operation, the programmable error injection module injects errors at precise moments according to the sequence. Sixth, the protocol status monitoring module captures all internal protocol activities and pushes the decoded trajectory stream to the multi-dimensional response analysis module. Seventh, after injection, the multi-dimensional response analysis module performs three-level analysis and reports the results to the test control host. Eighth, the test control host determines whether the behavior of the fault-tolerant protocol in this test scenario meets expectations based on the analysis results. Ninth, the test scenario generation engine generates the next test sequence based on coverage and feedback information. Tenth, steps four through nine are repeated until the preset test duration or protocol status coverage target is reached.

[0041] After testing, the comprehensive test results reporting unit automatically summarizes the execution results of all test scenarios and generates a comprehensive test report. This comprehensive test report includes the following: a protocol state coverage matrix, displaying the coverage of each state and transition edge in heatmap form; a timing violation list, listing all out-of-limit events and their detailed parameters; detailed logic defect logs, including the complete context of deadlocks, livelocks, and illegal state transitions; statistical performance charts, showing the trends of recovery time, error correction rate, and other indicators as error concurrency changes, and marking performance cliff points; and a final fault tolerance level assessment, providing a quantitative rating based on preset scoring rules. This comprehensive test report provides chip design teams with clear improvement directions and also provides reliable acceptance criteria for mass production quality control.

[0042] In summary, this embodiment achieves unprecedented in-depth verification capabilities for memory chip fault-tolerant protocols by constructing a highly integrated, closed-loop feedback, and multi-dimensional analysis testing system. The system can not only simulate complex concurrent fault scenarios in the real world, but also perform fine-grained observation and quantitative evaluation of the protocol's internal behavior, thereby effectively intercepting potential reliability risks before chip mass production.

[0043] Example 2: Based on Example 1, this example enhances the system to meet the specific testing requirements of high-bandwidth memory. The enhancements are mainly reflected in the architecture upgrades of the physical layer driver unit of the programmable error injection module and the high-speed sampling circuit of the protocol status monitoring module.

[0044] High-bandwidth memories typically employ a multi-channel parallel architecture, with each channel achieving data rates exceeding 20 gigabits per second, and signal integrity demands extremely high testing accuracy. In this embodiment, the physical layer driver unit adopts a distributed injection architecture, deploying miniature error injection units near each memory channel. Each miniature unit includes an independent precise timing unit, a subset of error type libraries, and a physical layer driver sub-circuit, synchronized with the clock of the corresponding channel via a local phase-locked loop. This design avoids delays and distortions introduced by long-distance signal transmission, ensuring that the injection accuracy of single-bit flip errors remains within 0.05 nanoseconds at a data rate of 20 gigabits per second. The physical layer driver sub-circuit employs differential signal driving technology, capable of accurately simulating specific error types such as common-mode noise and differential skew on high-speed serial links, which is impossible with traditional single-ended injection.

[0045] The high-speed sampling circuit of the protocol status monitoring module has also been upgraded to a channelized parallel sampling architecture. Each storage channel is equipped with a dedicated sample-and-hold amplifier, increasing the sampling rate to 80 GHz to meet the Nyquist sampling theorem requirement of 20 gigabits per second. Sampled data is transmitted to the central protocol parsing logic via on-chip optical interconnect technology, significantly reducing crosstalk and latency caused by electrical interconnects. The state machine model within the protocol parsing logic has also been customized and extended for the specific fault-tolerant protocol of high-bandwidth memory, enabling it to identify and decode more complex protocol states, such as "channel equalization adjustment in progress" and "dynamic voltage scaling recovery."

[0046] The constraint library of the test scenario generation engine has been updated to include physical layer constraints for high-bandwidth memories, such as "multiple channels within the same physical bank cannot be injected with power glitches simultaneously" and "error injection on the two signal lines of a differential pair must maintain common-mode consistency." The adaptive feedback learning unit has also enhanced its ability to monitor and analyze physical layer eye diagram parameters. When an increase in bit error rate due to eye diagram closure is detected, it will prioritize generating error combinations that exacerbate signal degradation to accelerate the exposure of the limits of the physical layer fault tolerance mechanism.

[0047] Through the above enhancements, this embodiment can effectively address the FT test challenges of next-generation high-bandwidth memories, ensuring that its fault tolerance under extreme signal integrity conditions is fully verified.

Claims

1. A fault injection and fault tolerance testing system for memory chip FT testing, characterized in that, include: The test control host, as the central scheduling and decision-making core of the system, is used to coordinate the collaborative work of various modules and execute the final test judgment. The programmable error injection module is physically connected to the test interface of the memory chip under test. It is used to inject preset types of electrical or logical errors in real time and accurately during chip operation according to the received injection instructions. The protocol status monitoring module is connected to the pre-set debugging bus or status register inside the memory chip under test via a high-speed probe. It is used to capture and record in real time the transitions of the internal state machine of the fault-tolerant protocol, the changes of the error flag bit, and the level of key control signals. The multi-dimensional response analysis module is connected to the protocol status monitoring module and the test control host for in-depth analysis of the captured protocol response data in terms of timing, logic and statistics. The test scenario generation engine, integrated within the test control host, is used to automatically generate and dynamically schedule complex concurrent error injection test sequences based on a predefined error model library and protocol specifications. The programmable error injection module includes a timing precision timing unit, an error type library unit, and a physical layer driver unit; The precise timing unit is used to receive injection timing parameters from the test scenario generation engine. These injection timing parameters are accurate to the nanosecond level to control the absolute timing and duration of error injection. The error type library unit is used to store various predefined error models, including single-bit flip error, multi-bit burst error, address line sticking error, command decoding error, power supply glitch simulation, and clock jitter simulation. The physical layer driving unit is used to generate corresponding abnormal voltage, current or digital signal waveforms according to the selected error model and timing parameters, and selectively apply them to designated pins or internal access paths of the chip under test through a multiplexer switch. The protocol status monitoring module includes a high-speed sampling circuit, protocol parsing logic, and a real-time stream buffer. The high-speed sampling circuit is used to synchronously sample parallel data on the debug bus at a frequency several times higher than the main clock of the chip under test. The protocol parsing logic has a built-in state transition table and signal definition of the fault-tolerant protocol under test, which is used to decode the sampled raw data stream into readable state names, event identifiers and data values ​​in real time. The real-time stream buffer adopts a first-in-first-out structure to temporarily store the decoded protocol activity trajectory and push it to the multi-dimensional response analysis module in a streaming manner. The multi-dimensional response analysis module includes a timing violation detection submodule, a logical consistency verification submodule, and a statistical performance analysis submodule. The timing violation detection submodule is used to compare the response timing captured by the protocol status monitoring module with the protocol timing specification pre-stored in the test control host to detect whether the status recovery time and error confirmation delay indicators exceed the limits. The logical consistency verification submodule is used to verify whether the monitored actual state transition sequence is legal according to the standard finite state machine model of the fault-tolerant protocol, and to detect whether there are undefined state transitions, livelocks, and deadlocks. The statistical performance analysis submodule is used to aggregate and calculate various response times, error correction rates, and protocol overhead data collected from multiple tests, generate statistical distribution charts, and identify performance cliffs. The core of the test scenario generation engine is a sequence generator based on constraint randomization. The sequence generator works as follows: it selects multiple basic error types from the error model library as seeds; For each error type, the injection time point, duration, location of action, and intensity parameters are randomly generated. These random generation processes are subject to a set of predefined constraints. The sequence generator arranges and combines multiple random error instances according to a timeline to form a complex test scenario that includes concurrency and sequence errors; The generation engine appends the expected correct protocol response sequence to each scenario; The test scenario generation engine also integrates an adaptive feedback learning unit; The adaptive feedback learning unit is used to receive test result data from the multi-dimensional response analysis module and employ a coverage-based optimization algorithm. The specific process of the coverage-based optimization algorithm is as follows: the system maintains a coverage table of protocol states and transitions, recording the states and edges that have been triggered by the tested scenarios; After analyzing the new test results, the algorithm prioritizes generating error combinations that can trigger uncovered states or transitions, while also increasing error pattern variations near the already discovered defective scenarios. The overall test process executed by the test control host is as follows: The test control host initializes the entire system and loads the protocol description file of the chip under test; The test scenario generation engine generates the first concurrent error injection test sequence and sends it to the programmable error injection module; The test control host commands the chip under test to begin executing a standard workload. During chip operation, the programmable error injection module injects errors at precise moments according to a sequence. The protocol status monitoring module captures all internal protocol activities throughout the entire process; After injection, the multi-dimensional response analysis module analyzes the response data and reports the results to the test control host; The test control host determines whether the behavior of the fault tolerance protocol in the test scenario meets expectations based on the analysis results. The test scenario generation engine generates the next test sequence based on coverage and feedback information; This cycle continues until the preset test duration or protocol status coverage target is reached.

2. The error injection and fault tolerance testing system for memory chip FT testing according to claim 1, characterized in that, The predefined constraints include the minimum time interval between errors, the inability of mutually exclusive error types to occur simultaneously, and the requirement that the error intensity must not exceed the physical damage threshold of the chip.

3. The error injection and fault tolerance testing system for memory chip FT testing according to claim 2, characterized in that, The system also includes a comprehensive test result reporting unit; The test result comprehensive reporting unit is used to summarize the execution results of all test scenarios and generate a comprehensive test report including a protocol state coverage matrix, a timing violation list, detailed logs of logical defects, statistical performance charts, and a final fault tolerance level assessment.

4. The error injection and fault tolerance testing system for memory chip FT testing according to claim 3, characterized in that, The precise timing unit adopts a phase-locked loop-based delay-locked loop structure, which integrates a digital delay line with sub-nanosecond resolution to convert the injected timing parameters into a precise trigger signal in the local clock domain.

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