Inversion method and circuit, processing method, device and circuit, sensor and terminal

Abstract

The invention discloses a matrix inversion method, a matrix inversion circuit, a signal processing method, a signal processing device, an integrated circuit, an electromagnetic wave sensor and terminal equipment, which can realize El Mitt matrix inversion. The El Matrix inversion circuit is used for performing inversion on an El Matrix A. The El Matrix inversion circuit comprises a Cholesky decomposition circuit used for calculating a lower triangular matrix L to enable LLH to be equal to A, and LH is conjugate transpose of L; and the triangular matrix inversion circuit is used for calculating the inverse L-1 of the lower triangular matrix L, and the product of the conjugate transpose of the L-1 and the L-1 is the inverse of the El matrix A.

Description

Technical Field

[0001] This article relates to, but is not limited to, signal processing technology, particularly a matrix inversion method, matrix inversion circuit, signal processing method, signal processing device, integrated circuit, electromagnetic wave sensor, and terminal equipment. Background Technology

[0002] In the fields of communications and radar, many algorithms require matrix inversion, and most of these matrices are positive definite Hermitian matrices. Existing methods for calculating matrix inversion include Gaussian elimination, LU decomposition, and iterative methods, but these methods are computationally complex and have high hardware implementation costs. Summary of the Invention

[0003] This application provides a matrix inversion method, a matrix inversion circuit, a signal processing method, a signal processing device, an integrated circuit, an electromagnetic wave sensor, and a terminal device, which can realize Hermitian matrix inversion.

[0004] On one hand, embodiments of this disclosure provide a Hermitian matrix inversion circuit for inverting a Hermitian matrix A, comprising: Cholesky decomposition circuit, used to calculate the lower triangular matrix L to make LL H =A, where L H This is the conjugate transpose of L; A triangular matrix inverse circuit is used to calculate the inverse L of the lower triangular matrix L. -1 The L -1 The conjugate transpose of L -1 The product of these is the inverse of the Hermitian matrix A.

[0005] In an exemplary embodiment, the Cholesky decomposition circuit is a circuit array composed of multiple circuit units, and the Cholesky decomposition circuit includes the following circuit units: for calculating A = A - |P| 2 The C circuit unit is used to calculate A = A - PQ*, the D circuit unit is used to calculate P = AQ, and the E circuit unit is used to calculate P = 1 / A. 1 / 2 And Q=1 / A 1 / 2 The F circuit unit, wherein the C circuit unit is connected to the D circuit unit, the E circuit unit and the F circuit unit respectively, the D circuit unit is connected to the E circuit unit, and the E circuit unit is connected to the F circuit unit. The triangular array inversion circuit is a circuit array composed of multiple circuit units. The triangular array inversion circuit includes the following circuit units: a G circuit unit for calculating Q=PB, an H circuit unit for calculating B=B-PQ, and an I circuit unit for storing data and outputting the data with a one-cycle delay. The G circuit unit is connected to the H circuit unit and the I circuit unit respectively, and the H circuit unit is connected to the I circuit unit.

[0006] In an exemplary embodiment, the Cholesky decomposition circuit includes: Two or more C circuit units are used to calculate A = A - |P| 2 It includes: an A-value input port for inputting data A; a P-value input port for inputting data P; and an A-value output port for outputting the calculation result A = A - |P|. 2 The Q-value output port is used to output Q=P. One or more D circuit units are used to calculate A = A - PQ*, including: an A-value input port for inputting data A; a P-value input port for inputting data P; a Q-value input port for inputting data Q; an A-value output port for outputting the calculation result A = A - PQ*, ** represents the complex conjugate; a P-value output port for outputting data P, i.e., the data P input through the P-value input port; and a Q-value output port for outputting data Q, i.e., the data Q input through the Q-value input port. Two or more E circuit units are used to calculate P=AQ, including: an A value input port for inputting data A; a Q value input port for inputting data Q; a P value output port for outputting the calculation result P=AQ; and a Q value output port for outputting data Q, which is the data Q input through the Q value input port. An F circuit unit is used to calculate P=1 / A. 1 / 2 And Q=1 / A 1 / 2 It includes: an A-value input port for inputting data A; and a P-value output port for outputting the calculation result P=1 / A. 1 / 2 The Q-value output port is used to output the calculation result Q=1 / A. 1 / 2 ; The C circuit unit, D circuit unit, E circuit unit and E circuit unit form a grid connection. When connected, the A value output port is connected to the A value input port, the P value output port is connected to the P value input port, and the Q value output port is connected to the Q value input port.

[0007] In an exemplary embodiment, the Cholesky decomposition circuit includes: 4 C circuit units, 3 D circuit units, 3 E circuit units, and 1 F circuit unit, wherein: The A-value input port of the first C circuit unit is the first input port of the Cholesky decomposition circuit. The first C circuit unit, the second C circuit unit, and the third C circuit unit are connected in sequence. The A-value output port of the first C circuit unit is connected to the A-value input port of the second C circuit unit, the A-value output port of the second C circuit unit is connected to the A-value input port of the third C circuit unit, the A-value output port of the third C circuit unit is connected to the A-value input port of the F circuit unit, and the P-value output port of the F circuit unit is the first output port of the Cholesky decomposition circuit. The A-value input port of the first D circuit unit is the second input port of the Cholesky decomposition circuit. The A-value output port of the first D circuit unit is connected to the A-value input port of the second D circuit unit. The P-value output port of the first D circuit unit is connected to the P-value input port of the first C circuit unit. The Q-value input port of the first D circuit unit is connected to the Q-value output port of the second C circuit unit. The P-value output port of the second D circuit unit is connected to the P-value input port of the second C circuit unit. The Q-value input port of the second D circuit unit is connected to the Q-value output port of the third C circuit unit. The A-value input port of the third D circuit unit is the third input port of the Cholesky decomposition circuit. The P-value output port of the third D circuit unit is connected to the P-value input port of the first D circuit unit. The Q-value input port of the third D circuit unit is connected to the Q-value output port of the second D circuit unit. The Q-value output port of circuit unit F is connected to the Q-value input port of circuit unit E. The P-value output port of circuit unit E is connected to the P-value input port of circuit unit C. The P-value output port of circuit unit E is the second output port of the Cholesky decomposition circuit. The A-value input port of circuit unit E is connected to the A-value output port of circuit unit D. The Q-value output port of circuit unit E is connected to the Q-value input port of circuit unit E. The P-value output port of circuit unit E is connected to the P-value input port of circuit unit D. The P-value output port of circuit unit E is the third output port of the Cholesky decomposition circuit. The A-value input port of circuit unit E is connected to the A-value output port of circuit unit D. The Q-value output port of circuit unit E is connected to the Q-value input port of circuit unit E. The P-value output port of circuit unit E is connected to the P-value input port of circuit unit D. The P-value output port of circuit unit E is the fourth output port of the Cholesky decomposition circuit. The A-value input port of circuit unit E is the third input port of the Cholesky decomposition circuit.

[0008] The Cholesky decomposition circuit described above can perform Cholesky decomposition of Hermitian matrices in 4 dimensions and below.

[0009] In an exemplary embodiment, the triangular array inversion circuit includes: Two or more G circuit units are used to calculate Q=PB, including: a P-value input port for inputting data P; a B-value input port for inputting data B; a Q-value output port for outputting the calculation result Q=PB; and a P-value output port for outputting data P. Three or more H circuit units are used to calculate B=B-PQ, including: a P-value input port for inputting data P; a B-value input port for inputting data B; a Q-value input port for inputting data Q; a B-value output port for outputting the calculation result B=B-PQ; a P-value output port for outputting data P, i.e., the data P input through the P-value input port; and a Q-value output port for outputting data Q, i.e., the data Q input through the Q-value input port. An I-circuit unit is used to store data and output it with a one-cycle delay. It includes a P-value input port for inputting data P and a Q-value output port for outputting Q=P. The G circuit unit, H circuit unit, and I circuit unit form a grid connection. When connected, the P-value output port is connected to the P-value input port, the B-value output port is connected to the B-value input port, and the Q-value output port is connected to the Q-value input port.

[0010] In an exemplary embodiment, the triangular array inversion circuit includes: 3 G circuit units, 6 H circuit units, and 1 I circuit unit, wherein: The P-value input port of the first G circuit unit is the first input port of the triangular array inversion circuit. The first G circuit unit, the second G circuit unit, and the third G circuit unit are connected in sequence. The P-value output port of the first G circuit unit is connected to the P-value input port of the second G circuit unit, the P-value output port of the second G circuit unit is connected to the P-value input port of the third G circuit unit, and the P-value output port of the third G circuit unit is connected to the P-value input port of the I circuit unit. The P-value input port of the first H circuit unit is the second input port of the triangular array inversion circuit. The P-value output port of the first H circuit unit is connected to the P-value input port of the second H circuit unit. The B-value output port of the first H circuit unit is connected to the B-value input port of the first G circuit unit. The Q-value input port of the first H circuit unit is connected to the Q-value output port of the second G circuit unit. The P-value output port of the second H circuit unit is connected to the P-value input port of the third H circuit unit. The B-value output port of the second H circuit unit is connected to the B-value input port of the second G circuit unit. The Q-value input port of the second H circuit unit is connected to the Q-value output port of the third G circuit unit. The B-value output port of the third H circuit unit is connected to the B-value input port of the third G circuit unit. The Q-value input port of the third H circuit unit is connected to the Q-value output port of the I circuit unit. The Q-value output port of the first G circuit unit is the fourth output port of the triangular array inversion circuit, the Q-value output port of the second G circuit unit is the third output port of the triangular array inversion circuit, the Q-value output port of the third G circuit unit is the second output port of the triangular array inversion circuit, and the Q-value output port of the I circuit unit is the first output port of the triangular array inversion circuit. The P-value input port of the fourth H circuit unit is the third input port of the triangular array inversion circuit. The P-value output port of the fourth H circuit unit is connected to the P-value input port of the fifth H circuit unit. The B-value output port of the fourth H circuit unit is connected to the B-value input port of the first H circuit unit. The Q-value input port of the fourth H circuit unit is connected to the Q-value output port of the second H circuit unit. The B-value output port of the fifth H circuit unit is connected to the B-value input port of the second H circuit unit. The Q-value input port of the fifth H circuit unit is connected to the Q-value output port of the third H circuit unit. The P-value input port of the sixth H circuit unit is the fourth input port of the triangular array inversion circuit. The B-value output port of the sixth H circuit unit is connected to the B-value input port of the fourth H circuit unit. The Q-value input port of the sixth H circuit unit is connected to the Q-value output port of the fifth H circuit unit.

[0011] The above-mentioned triangular matrix inversion circuit can realize the inversion of lower triangular matrices of 4 dimensions and below.

[0012] In an exemplary embodiment, the Cholesky decomposition circuit is connected to the triangular array inversion circuit via a delay unit, so that the output data of the Cholesky decomposition circuit matches the input timing of the triangular array inversion circuit.

[0013] In an exemplary embodiment, the Hermitian matrix inversion circuit is used to process multiple Hermitian matrices or multiple positive definite Hermitian matrices in parallel.

[0014] In an exemplary embodiment, the Hermitian matrix inversion circuit further includes a processing unit and a storage unit, wherein: The processing unit is used to, when it is determined that two or more Hermitian matrices to be processed have the same element, cause the storage unit to store the same element and the intermediate calculation result of the same element, so as to improve the processing speed of the Hermitian matrix.

[0015] On the other hand, this disclosure also provides a Hermitian matrix inversion circuit for inverting a Hermitian matrix A, comprising: Given multiple n-dimensional Hermitian matrices A1, A2, ... A kAll matrices share a common submatrix. The Hermitian matrix inversion circuit processes the multiple Hermitian matrices in parallel. After inputting the first matrix A1, the Hermitian matrix inversion circuit stores the intermediate calculation results of the common submatrix. For A2, ..., A... k When processing the matrix, the stored intermediate calculation results are used for calculation.

[0016] For two Hermitian moments with identical submatrices, the intermediate results of their submatrices are the same when they are processed. Therefore, they can be directly used in subsequent calculations, or directly output when they do not need to be used in calculations. Alternatively, this part can be stored and directly used for the same elements in the next matrix, with the intermediate calculation result being the same. In an exemplary embodiment, for A2,…A k The Hermitian matrix inversion circuit outputs elements that differ from the A1 matrix output. In other words, it can output only the parts of the result that differ from the A1 matrix.

[0017] On the other hand, this disclosure also provides a method for inverting a Hermitian matrix, used to invert a Hermitian matrix A, the method comprising: Obtain the lower triangular matrix L, where the product of the conjugate transpose of the triangular matrix L and the triangular matrix L is equivalent to the Hermitian matrix A; Obtain the inverse L of the lower triangular matrix L. -1 ;as well as Based on the L -1 The conjugate transpose of L -1 The inverse of the Hermitian matrix A is obtained.

[0018] In an exemplary embodiment, the Hermitian inversion circuit of any of the foregoing embodiments can be used to obtain the lower triangular matrix L and the inverse L of the lower triangular matrix L. -1 .

[0019] In an exemplary embodiment, elements of two or more Hermitian matrices are input alternately according to a pre-configured timing sequence, so that the Hermitian matrix inversion circuit processes the two or more Hermitian matrices in parallel. By utilizing the idle periods during single-matrix processing to achieve parallel processing, the circuit utilization and matrix inversion processing efficiency are improved.

[0020] In an exemplary embodiment, when it is determined that two or more Hermit matrices to be processed have the same element, the same element and the intermediate processing result of the same element are stored to improve the processing speed of the Hermit matrices.

[0021] On the other hand, this disclosure also provides a method for radar signal processing, the method including: when processing echo signals, performing at least one step of deblurring, achieving super-resolution, angle estimation, and target tracking based on the method of inverting the Hermitian matrix using a lower triangular matrix.

[0022] In an exemplary embodiment, the method of inverting the Hermitian matrix using the lower triangular matrix includes: using the Hermitian inversion circuit or method described in any of the foregoing embodiments to obtain the lower triangular matrix and the inverse of the lower triangular matrix.

[0023] In another aspect, embodiments of this disclosure also provide a radar signal processing device, including an M4INV computing engine unit, wherein the M4INV computing engine unit includes an Hermitian inversion circuit as described in any of the preceding embodiments.

[0024] In another aspect, embodiments of this disclosure also provide an integrated circuit, comprising: a signal transmitting module configured for electromagnetic waves for target detection; a signal receiving module configured for receiving echoes formed by reflection and / or scattering of the electromagnetic waves; and a processing module configured for processing the echo signals to achieve target detection; wherein at least the processing module includes the Hermitian inversion circuit described in any of the foregoing embodiments.

[0025] In an exemplary embodiment, the integrated circuit may be a millimeter-wave chip or a sensor chip.

[0026] In another aspect, embodiments of this disclosure also provide an electromagnetic wave sensor, comprising: a carrier; the aforementioned integrated circuit disposed on the carrier; an antenna disposed on the carrier, or the antenna and the integrated circuit are integrated into a single device disposed on the carrier; wherein the integrated circuit is connected to the antenna and is used to transmit the electromagnetic wave signal and / or receive the echo signal.

[0027] In another aspect, embodiments of this disclosure also provide a terminal device, including: a device body; and an electromagnetic wave sensor as described above disposed on the device body; wherein the electromagnetic wave sensor is used for target detection and / or communication to provide reference information to the operation of the device body.

[0028] The Hermite matrix inversion circuit of the present disclosure can achieve efficient Hermite matrix inversion and has a simple circuit structure.

[0029] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0031] Figure 1 A schematic diagram of a radar system that can be used in embodiments of this disclosure is shown; Figure 2 A schematic diagram of another radar system that can be used in this embodiment is shown; Figure 3 This is a waveform diagram of a detection signal transmitted by a radar system based on FMCW. Figure 4A This is a schematic diagram of a signal processing device that can be used in embodiments of this disclosure; Figure 4B This is a schematic diagram of another signal processing device structure that can be used in embodiments of this disclosure; Figure 5 A schematic diagram illustrating the process of inverting an Hermitian matrix; Figures 6A to 6D This is a schematic diagram of the circuit units in the Cholesky decomposition circuit array according to an embodiment of this disclosure; Figure 7 This is a schematic diagram of a 4D Cholesky decomposition circuit array according to an embodiment of the present disclosure; Figure 8 for Figure 7 The timing diagram of the Cholesky decomposition circuit array is shown below. Figures 9A to 9C This is a schematic diagram of the circuit elements in the triangular array inversion circuit of this embodiment of the present disclosure; Figure 10 This is a schematic diagram of a 4D triangular array inversion circuit array according to an embodiment of the present disclosure; Figure 11 for Figure 10 The timing diagram of the triangular array inversion circuit array is shown below. Figure 12 This is a schematic diagram showing the connection between the Cholesky decomposition circuit array and the triangular array inversion circuit in an embodiment of this disclosure; Figure 13 This is a timing diagram of the Cholesky decomposition circuit array during matrix parallel processing in Embodiment 3 of this disclosure; Figure 14 This is a timing diagram of the triangular matrix inversion circuit array during matrix parallel processing in Embodiment 3 of this disclosure; Figure 15 In this embodiment of the disclosure, the A matrix and L are recorded using a memory mode. -1 A schematic diagram of a matrix; Figure 16 This is a schematic diagram of the circuit structure for implementing Hermitian matrix inversion using a non-array structure according to an embodiment of this disclosure. Detailed Implementation

[0032] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0033] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0034] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0035] Figure 1A radar system 100 applicable to embodiments of this disclosure is illustrated, taking a frequency-modulated continuous wave (FMCW) millimeter-wave radar as an example. The radar system 100 includes a radio frequency (RF) chip 110, a transmitting antenna 120, a receiving antenna 130, and a main processing chip 140. The RF chip 110 is configured to generate a detection signal and transmit it through a transmitting antenna array. The detection signal can be an FMCW electromagnetic wave signal. Multiple transmitting antennas 120 are connected to the RF chip 110 and can form a transmitting antenna array, configured to transmit the detection signal. Multiple receiving antennas 130 are configured to receive the echo signal formed by the detection signal reflected by a target (i.e., the object being detected or the target object, hereinafter referred to as the target). The main processing chip 140 is connected to the receiving antenna array and the RF chip 110, configured to process the echo signal obtained by the receiving antenna array to obtain information such as the target's distance, velocity, and angle. In one example, the transmitting antenna 121 and the receiving antenna 131 can be integrated with the RF chip 110 to form an RF transceiver chip, which, together with the main processing chip 140, constitutes a radar signal transceiver processing system. In another example, the RF chip 110 and the main processing chip 140 can be integrated into a single SoC (System on Chip) chip, enabling the transmission, reception, and processing of RF signals with a single chip. The transmitting and receiving antennas can also be integrated with this SoC chip to form an AiP (Antenna in Package) chip or an AoC (Antenna on Chip) chip structure, etc.

[0036] The integrated or separate radio frequency chip 110 and main processing chip 140 constitute the integrated circuit in the radar system. This integrated circuit, transmitting antenna, and receiving antenna can be mounted on a carrier, together forming an electromagnetic wave sensor. This electromagnetic wave sensor can be installed inside a vehicle cabin, for example, one or more on the roof. Each electromagnetic wave sensor can be used to detect one or two rows of seats in the cabin. When using the electromagnetic wave sensor for Child Residue Detection (CPD), the region of interest can be set to the area where the person is most likely to be seated and the area on the floor. A distance range can be preset based on the distance from the seat and floor to the electromagnetic wave sensor. Distance cells within the preset distance range in the range-dimensional FFT (1D-FFT), Doppler-dimensional (i.e., velocity-dimensional) FFT (2D-FFT), or range-Doppler image are used as the distance cells of interest for corresponding processing.

[0037] Figure 2Another radar system that can be used in this embodiment is shown. It includes a transmitting antenna 11, a power amplifier 21, a signal generator 23, a receiving antenna 13, a low-noise amplifier 31, a mixer 33, an analog-to-digital converter (ADC) module 41, and a digital signal processing module 51. The signal generator 23 can be a millimeter-wave generator implemented with an oscillator. The detection signal generated by the signal generator 23 is amplified by the power amplifier 21 and then transmitted through one or more transmitting antennas 11. Radar systems typically transmit a series of chirps in frames. The detection signal transmitted by an FMCW-based radar system can use... Figure 3 The sawtooth waveform shown includes multiple chirp signals per frame. Each chirp signal includes an up-modulation band, a down-modulation band, and a frequency hold band. The period of each chirp signal is Tc. The signal transmission channel of the radar system consists of devices such as a signal generator 23 and a power amplifier 21.

[0038] The detection signal is reflected and / or refracted by the target to form an echo signal. The receiving antenna 13 amplifies the received echo signal through a low-noise amplifier 31, and then mixes it with the corresponding local oscillator signal in a mixer 33 to obtain an intermediate frequency (IF) signal. There are usually multiple receiving antennas 13. The signal channel of the radar system is composed of components such as the low-noise amplifier 31 and the mixer 33. The IF signal is sent to the analog-to-digital converter (ADC) 41 for sampling, and the resulting digital signal is further processed in the digital signal processing module 51. This includes performing range-dimensional FFT and Doppler-dimensional (i.e., velocity-dimensional) FFT to obtain the range-Doppler spectrum, or RD spectrum, of the digital signal. Based on the RD spectrum, the target's range, velocity, and direction of arrival are detected to achieve target judgment, location, and identification. Digital signal processing can also include windowing, clustering, digital beamforming (DBF), etc.

[0039] Figure 4A and Figure 4B A signal processing apparatus that can be used in this embodiment is shown, which may be located, for example, in [location missing]. Figure 1 The main processing chip 140 of the radar system shown, or located in Figure 2 The digital signal processing module 51 of the radar system shown.

[0040] The signal processing device may include a processor buffer (PBUF) module and a pool of computational resources consisting of multiple computing engine units, such as... Figure 4A and Figure 4BThe RSP combo engines in the computing resource pool include a PBUF (Processor Buffer Memory) storage module and an address controller. When performing radar signal processing, the computing resource pool reuses the PBUF storage medium based on the memory addresses generated by the address controller to perform radar signal processing (including post-processing of radar signals), thereby enabling flexible and customized radar tasks. Simultaneously, when the computing engines in the computing resource pool perform read / write operations on the processor cache, they can also perform operations such as data transposition, splitting, merging, and filtering based on the coordination of read / write operations. This serves as part of the execution of radar signal processing or as data connection between different signal processing operations.

[0041] like Figure 4A and Figure 4B As shown, the signal processing device includes RSP Combo Engines and a Processor Buffer (PBUF) module. The RSP Combo Engines include multiple computing engine units, and the PBUF module includes a PBUF storage medium (Processor Buffer) and an address controller. At least two computing engine units can perform read and / or write operations on the PBUF storage medium based on the storage address generated by the address controller, through a shared (or reused) approach. This allows them to perform at least one of the following operations: signal calculation, spectrum analysis, and data manipulation, thereby realizing corresponding radar signal processing operations and enabling flexible and customized radar tasks. During read / write operations on the PBUF storage medium, the computing engines can also perform operations such as data transposition, splitting, merging, and filtering, serving as part of the execution body in radar signal processing or as data connection between different signal processing operations. Optionally, the multiple computing engine units included in the RSP Combo Engines can share a set of PBUFIO access permissions to enable sequential operation of the combo engines.

[0042] In some optional embodiments, the RSP combination engine may include at least one of the following: Fast Fourier Transform (FFT) computation engine unit (R8FFT in the figure represents 8 parallel FFT), multiply-accumulate (MAC) computation engine unit (M4MAC in the figure represents 4 parallel MAC), inversion (INV) computation engine unit (M4INV in the figure represents 4 parallel INV), spatial variant apodization (SVA) computation engine unit, PeakHist computation engine unit, constant false alarm rate (CFAR) computation engine unit, detection (DET) engine unit, SIFT engine unit, remap engine unit, and data movement engine unit. Among them, the FFT calculation engine unit, MAC calculation engine unit, INV calculation engine unit, and SVA calculation engine unit can be used to implement signal calculation operations related to radar signal processing; the PeakHist calculation engine unit, CFAR calculation engine unit, and DET engine unit can be used to implement spectrum analysis operations in signal processing; and the SIFT engine unit, REMAP engine unit, and MOVE engine unit can be used to perform data manipulation on radar signals.

[0043] The SVA computing engine unit is designed for operations with large data requirements. It integrates dedicated storage media to perform large-data-demand operations such as large FFT calculations, including range-dimensional FFT, Doppler-dimensional FFT, Spatial Variant Apodization (SVA), and Chirp Quality Recovery (CQR) signal recovery in radar signal processing. This dedicated storage media unit typically meets computational needs by utilizing its integrated storage medium, without sharing or reusing the PBUF storage medium. Optionally, the SVA computing engine unit may have dedicated PBUF IO access permissions, allowing it to operate in parallel with other computing engine units included in the RSP combined engine. Optionally, to implement operations such as FFT processing, corresponding window coefficient modules can be configured to handle windowing operations like FFT.

[0044] In some alternative embodiments, such as Figure 4A and Figure 4B As shown, based on the application dimension of the computing engine units, the signal processing device may include a signal computation engine module, a spectrum analysis engine module, a data manipulation engine module, and a processor buffer (PBUF) module. That is, the signal computation engine module, spectrum analysis engine module, and data manipulation engine module may each include at least one computing engine unit. Similarly, the processor buffer (PBUF) module includes a PBUF storage medium (Processor Buffer Memory) and an address generator (Address Controller). At least two computing engine units in the engine module can perform read and / or write operations on the PBUF storage medium based on the storage address generated by the address generator, through a shared (or reused) method, to perform at least one of the operations such as signal computation, spectrum analysis, and data processing, thereby realizing the corresponding radar signal processing operations and achieving various flexible and customized radar tasks. When the computing engine performs read / write operations on the PBUF storage medium, it can also perform operations such as data transposition, splitting, merging, and filtering based on the cooperation of read / write operations, serving as part of the execution body in radar signal processing or as data connection between different signal processing operations.

[0045] In some optional embodiments, the computing engine units included in the spectrum analysis engine module and the data operation engine module in this application embodiment share or reuse the PBUF storage medium in this application embodiment, while the computing engine units included in the signal computing engine module can partially share or reuse the PBUF storage medium in this application embodiment.

[0046] The signal calculation engine module included in this embodiment, or the related calculation engine unit used for signal calculation, can be configured to handle raw (radar) signal processing tasks, such as FFT processing, matrix multiplication, and matrix inversion. Correspondingly, the spectrum analysis engine module or the related calculation engine unit used for spectrum analysis can be configured to handle the analysis of the signal spectrum (such as the power domain), for example, it can be used for operations such as searching for maximums / minimums and order statistics. The data manipulation engine module or the related calculation engine unit used for data processing can be configured to handle data manipulation related tasks, such as selecting data words from a vector, antenna remapping, and data copying.

[0047] In some alternative embodiments, such as Figure 4A and Figure 4BThe signal processing engine module shown includes processing engine units that can be used for operations on signal data types, and are also compatible with logical data types or integer data types. For example, the R8FFT computation engine unit in the signal computation engine module can be used for channel domain Fast Fourier Transforms (FFTs) and convolutions, while also being compatible with handling larger FFT computations; the M4MAC computation engine unit can be used to perform multiply-accumulate (MAC) operations in linear algebra, supporting operations including matrix-matrix dot (MMD), matrix-vector dot / addition (MVX, where X represents dot or addition), and vector-vector dot / addition (VVX), or simultaneously supporting operations including vector-vector dot (VVD), matrix-vector dot (MVD), and matrix-matrix dot (MMD); the M4INV computation engine unit can be used for the Cholesky inversion of Hermitian matrices, for real signals (real The SVA computational engine unit can also handle the inversion of symmetric matrices, such as the Jacobian matrix in a Kalman filter. It provides an advanced nonlinear variable-coefficient FIR filter designed to process FFT results. By employing nonlinear techniques, it effectively reduces sidelobes, improves sidelobe suppression, and maintains signal resolution.

[0048] For example, in relatively complex algorithm or signal processing flows, it may be necessary for the output of one computing engine unit to be used as the input of another computing engine unit. For instance, the matrix output obtained by the M4INV computing engine unit can be used as input to the M4MAC computing engine unit to perform multiplication operations in the corresponding algorithm or signal processing, while the vector output generated by the M4MAC computing engine unit can be used as input for the execution of the R8FFT computing engine unit.

[0049] like Figure 4A and Figure 4B As shown, the spectrum analysis engine module can be configured as a component for processing and analyzing radar signals, and may include PeakHist computing engine unit, CFAR (Constant False AlarmRate Engine) computing engine unit, and DET (Detection Engine) engine unit, etc.

[0050] The PeaknHist computational engine unit can be configured as a pseudo-order statistic engine, approximating the nth ranked data point in a batch of data, thus reducing a list of vectors to a list of words. The CFAR computational engine unit can be configured to process log power vectors, enabling operations such as sliding windowing, noise estimation, and comparison. For example, it can perform noise estimation based on a one-dimensional sliding window, label log vectors using noise information, and identify points of interest in noisy scenes. The DET engine unit can be configured to pick words of interest from log powermaps, and can include the COND branch and the IDX branch. The COND branch can be configured to perform threshold comparisons and local maximum conditions, parse tags generated by other engine units (such as the CFAR computing engine unit), and return data as a map with updated tags. The IDX branch can be configured to return indices of the detected words.

[0051] In some alternative embodiments, such as Figure 4A and Figure 4B As shown, the data processing engine module (datamanipulation) can be configured to move data in a specified manner, and may include engine units such as SIFT, REMAP, and MOVE. The SIFT engine unit can be configured to collect data indicated by indices from ordered data blocks, and the collected data is configured for batch processing by other engine units.

[0052] The REMAP engine unit can be configured to manipulate data in an encoded manner, inserting zeros or removing invalid data (squeezing bubble words out of data in an encoded manner). This REMAP engine unit can be configured as a preprocessing operation for the R8FFT computation engine unit, or it can be configured to process sparse matrices, etc. The MOVE engine unit can be configured to move data from one location to another within the PBUF (Processing Buffer) module; that is, it can be configured to perform data transfer operations. It can also be configured to be used in conjunction with the address generator (or address controller) in the PBUF module to achieve more complex data operations.

[0053] like Figure 4A and Figure 4B As shown, based on the requirements of radar signal processing, the signal processing device may also include a Direct Memory Access (DMA) module. This DMA module can be configured to work with the PBUF module to perform at least one of the following operations: data transfer, data transpose, data conversion, and data compression. Simultaneously, the DMA module is also configured to connect to a storage module (such as Static Random Access Memory, SRAM) for storing radar digital signals. This allows it to independently access the radar signal to be processed from the storage module and output the processed radar signal to the storage module for storage. In other words, the DMA module is responsible for data transfer between the SRAM and PBUF modules, and during this process, it can also be configured to perform operations such as data compression and format conversion.

[0054] Optionally, during radar signal processing, the processor cache (PBUF) module can be used as a memory structure in the radar signal processing device. It can serve as a cache for storage modules (such as SRAM). Due to its high throughput and dedicated address generator, it can effectively improve the performance and efficiency of the entire system's signal processing.

[0055] For example, compared to DMA, the PBUF module offers higher throughput, effectively supporting parallel operations and improving performance in handling ever-increasing volumes of intermediate data. Simultaneously, a dedicated address generator effectively manages data flow, enabling internal packet transfer while minimizing memory overhead and data copying resources. This increases the speed of data transfer between different layers, ensuring optimal performance for the high-throughput engine. In short, the PBUF module significantly improves data processing efficiency and performance in radar signal processing, particularly in applications requiring high throughput and fast data flow management.

[0056] like Figure 4A and Figure 4B As shown, the signal processing device may also include a CPU module, which, while implementing various control functions, also performs operations such as SEQ Queue Load and Computation Intervention. Simultaneously, the signal processing device may also include components such as a Data Register File, a sequencer, and general-purpose registers to work in conjunction with the CPU module, PBUF module, etc., to achieve the corresponding radar signal processing operations. For example, the sequencer, acting as a control unit, can determine the behavior of other modules or components by parsing instructions and configuring register configuration files, thereby controlling the relevant modules or components to achieve the corresponding radar signal processing operations.

[0057] Optionally, the CPU module in this embodiment of the application, when participating in radar signal processing, can be configured to be responsible for assembling and updating the scheduler instruction queue in real time, and / or directly accessing data and performing supplementary calculations. That is, the CPU module can not only optimize instruction execution in radar signal processing, but also enhance the flexibility and efficiency of data processing, thereby improving the performance of the entire system.

[0058] When the CPU module is configured to assemble and update the scheduler instruction queue in real time, it can assemble scheduler instructions and update the queue in real time. That is, the instruction queue stores a series of instructions in a first-in, first-out (FIFO) manner, allowing the microprocessor to fetch the next instruction with minimal latency, thereby improving performance. By prefetching instructions, the CPU module can optimize the execution order of instructions and improve overall processing efficiency. Simultaneously, when configured to directly access data and perform supplementary calculations, it can cover operations that RSPs (such as the computing resource pool in this embodiment) cannot handle or are unsuitable for handling.

[0059] In some cases, the CPU module can also directly read data from memory for computation without needing to transfer data, thereby improving data processing efficiency. This direct access and computation capability enables the CPU module to play a more critical role in radar signal processing, especially when handling complex or high-precision computational tasks.

[0060] Taking FMCW radar as an example, the digital signal processing flow of FMCW radar generally includes sequential steps such as digital front-end processing (DFE), detection, direction-of-arrival estimation (DoA), and post-processing. DFE is used to preprocess and compensate the digitized signal, typically including DC correction, window function weighting, and amplitude-phase calibration to improve data quality. Detection uses range and Doppler dimension processing (such as FFT and CFAR detection) to determine the presence of valid target signals in different range bins and Doppler bins. DoA is used to estimate the azimuth of the detected target signal to determine its spatial angular information. Post-processing may include high-level semantic processing such as target tracking, point cloud clustering, and attitude estimation.

[0061] In radar signal processing, the Direction of Attack (DOA) algorithm is a key technology for determining the incident angle of a signal source. Algorithms for DOA generally include DBF, Capon, MUSIC, RELAX, DML, and sparse learning methods. Sparse learning DOA algorithms include IAA and BLRC. Matrix inversion operations are involved in many of these algorithms, such as DML, IAA, and BLRC. However, current matrix inversion operations are mostly implemented using DSPs, which are relatively slow.

[0062] Therefore, this disclosure provides a matrix inversion circuit for inverting a Hermitian matrix. The circuit includes a Cholesky decomposition circuit array and a triangular matrix inversion circuit array, wherein: Cholesky decomposition circuit array, used to decompose Hermitian matrices Decomposed into ,in, It is a lower triangular matrix (diagonal elements are real numbers and >0, and upper triangular elements are 0). for The conjugate transpose of .

[0063] Taking a positive definite Hermitian matrix as an example, a positive definite Hermitian matrix satisfies And all eigenvalues ​​> 0. For an n-dimensional positive definite Hermitian matrix... The lower triangular matrix is ​​calculated using the following formula 1. To make it meet the conditions : Formula 1 A triangular matrix inversion circuit array used to calculate the inverse of a lower triangular matrix; Specifically, the inverse of the lower triangular matrix is ​​calculated using the following formula 2. : Formula 2 The inverse W of the lower triangular matrix is ​​calculated. ij Then, by using a matrix multiplier to calculate the product of the conjugate transpose of the inverse of the lower triangular matrix and the inverse of the lower triangular matrix, the inverse of the Hermitian matrix A (the assembled matrix) can be obtained: The inverse process is as follows: Figure 5 As shown.

[0064] For example, matrix assembly can be achieved using the computation of spectral estimation.

[0065] For a non-positive definite Hermitian matrix, starting from the non-positive definite diagonal element, the output is 0.

[0066] The above matrix inversion circuit is explained using the processing of a 4×4 Hermit matrix as an example.

[0067] The Cholesky decomposition circuit array includes nine multiply-accumulate circuit units and one solver. The circuit unit specifically includes: Circuit C is used to calculate A = A - |P| 2 Circuit markings such as Figure 6A As shown, it includes: an A-value input port for inputting data A; a P-value input port for inputting data P; and an A-value output port for outputting the calculation result A = A - |P|.2 The Q-value output port is used to output Q=P. Circuit D is used to calculate A = A - PQ*, and the circuit is labeled as follows: Figure 6B As shown, it includes: an A-value input port for inputting data A; a P-value input port for inputting data P; a Q-value input port for inputting data Q; an A-value output port for outputting the calculation result A = A - PQ, * represents the complex conjugate; a P-value output port for outputting data P, i.e., the data P input through the P-value input port; and a Q-value output port for outputting data Q, i.e., the data Q input through the Q-value input port. Circuit E, used to calculate P=AQ, circuit identification as follows: Figure 6C As shown, it includes: an A-value input port for inputting data A; a Q-value input port for inputting data Q; a P-value output port for outputting the calculation result P=AQ; and a Q-value output port for outputting data Q, which is the data Q input through the Q-value input port. Circuit F is used to calculate P=1 / A. 1 / 2 And Q=1 / A 1 / 2 Circuit markings such as Figure 6D As shown, it includes: an A-value input port for inputting data A; and a P-value output port for outputting the calculation result P=1 / A. 1 / 2 The Q-value output port is used to output the calculation result Q=1 / A. 1 / 2 .

[0068] Cholesky decomposition circuit arrays for processing 4×4 matrices, such as Figure 7 As shown, it includes three C circuits (circuit C1, circuit C2, and circuit C3 in the diagram), three D circuits (circuit D1, circuit D2, and circuit D3 in the diagram), three E circuits (circuit E1, circuit E2, and circuit E3 in the diagram), and one F circuit (circuit F1 in the diagram). In the diagram, the bold black solid lines represent the input ports (I11-I14) of the circuit array, and the bold black solid line arrows represent the output ports (O11-O14) of the circuit array.

[0069] The A-value input port of circuit C1 is the first input port I11 of the Cholesky decomposition circuit array. Circuits C1, C2, and C3 are connected in sequence. The A-value output port of circuit C1 is connected to the A-value input port of circuit C2. The A-value output port of circuit C2 is connected to the A-value input port of circuit C3. The A-value output port of circuit C3 is connected to the A-value input port of circuit F1. The P-value output port of circuit F1 is the first output port O11 of the Cholesky decomposition circuit array. The A-value input port of circuit D1 is the second input port I12 of the Cholesky decomposition circuit array. The A-value output port of circuit D1 is connected to the A-value input port of circuit D2. The P-value output port of circuit D1 is connected to the P-value input port of circuit C1. The Q-value input port of circuit D1 is connected to the Q-value output port of circuit C2. The P-value output port of circuit D2 is connected to the P-value input port of circuit C2. The Q-value input port of circuit D2 is connected to the Q-value output port of circuit C3. The A-value input port of circuit D3 is the third input port I13 of the Cholesky decomposition circuit array. The P-value output port of circuit D3 is connected to the P-value input port of circuit D1. The Q-value input port of circuit D3 is connected to the Q-value output port of circuit D2. The Q-value output port of circuit F1 is connected to the Q-value input port of circuit E3. The P-value output port of circuit E3 is connected to the P-value input port of circuit C3. The P-value output port of circuit E3 is the second output port O12 of the Cholesky decomposition circuit array. The A-value input port of circuit E3 is connected to the A-value output port of circuit D2. The Q-value output port of circuit E3 is connected to the Q-value input port of circuit E2. The P-value output port of circuit E2 is connected to the P-value input port of circuit D2. The P-value output port of circuit E2 is the third output port O13 of the Cholesky decomposition circuit array. The A-value input port of circuit E2 is connected to the A-value output port of circuit D3. The Q-value output port of circuit E2 is connected to the Q-value input port of circuit E1. The P-value output port of circuit E1 is connected to the P-value input port of circuit D3. The P-value output port of circuit E1 is the fourth output port O14 of the Cholesky decomposition circuit array. The A-value input port of circuit E1 is the third input port I14 of the Cholesky decomposition circuit array.

[0070] The timing sequence of the Cholesky decomposition circuit array is as follows: Figure 8 As shown, Figure 8 The left side of the middle section shows the input timing sequence, representing the timing relationship of the data input from the input ports. Each column corresponds to one input port, from right to left: first input port I11, second input port I12, third input port I13, and fourth input port I14. Figure 7 There are four input ports I11-I14. Each row corresponds to a time cycle (or processing cycle or time step). Figure 8 The right side of the image shows the output timing, representing the timing relationship of the data output from the output ports. Each column corresponds to one output port, from right to left: first output port O11, second output port O12, third output port O13, and fourth output port O14. Figure 7 There are four output ports O11-O14. Similarly, each row corresponds to a time period. For example, for the input ports, during period t1, input a from the first input port I11. 11 During cycle t3, input a from the second input port I12. 21During cycle t4, input a from the first input port I11. 22 ... For the output port, the output data l can be obtained from the first output port O11 during cycle t4. 11 -1 During cycle t5, output data l can be obtained from the second output port O12. 21 ,…….Depend on Figure 8 It can be seen that the Cholesky decomposition of a 4×4 Hermit matrix can be completed through 13 cycles of calculation.

[0071] The lower triangular matrix is ​​obtained using Formula 1. The process is as follows: For the first column, j=1 When i=1: When i=2: When i=3: When i=4: For the second column, j=2 When i=2: When i=3: When i=4: For the third column, j=3 When i=3: When i=4: For the fourth column, j=4 When i=4: The lower triangular matrix can be obtained through the above calculations. .

[0072] The above calculation process is implemented using a Cholesky decomposition circuit array, referring to... Figure 7 and Figure 8 The following is part of the work process: In period t1, input data a 11 When the first input port I11 is input, which is the A-value input port of circuit C1, circuit C1 performs calculations. At this time, there is no data input to the P-value input port of circuit C1, and the calculation result A=a is output from the A-value output port. 11 ; During period t2, circuit C2 receives data a from its A-value input port. 11Perform calculations and output the result A=a from its A value output port. 11 ; During period t3, circuit C3 receives data a from its A-value input port. 11 Perform calculations and output the result A=a from its A value output port. 11 Meanwhile, data a 21 Input the second input port I12, which is the A-value input port of circuit D1. Circuit D1 performs calculations and outputs the calculation result A=a from its A-value output port. 21 ; During period t4, circuit F1 receives data a from its A-value input port. 11 Perform calculations and output the calculation result P= from its P-value output port. That is Figure 8 The output l of the right-hand t4 cycle 11 -1 At the same time, circuit F1 outputs Q= from the Q-value output. Circuit D2 receives data a from its A-value input port. 11 Perform calculations and output the result A=a from its A value output port. 21 Meanwhile, data a 22 When the first input port I11 is input, circuit C1 performs calculations and outputs the calculation result A=a from its A-value output port. 22 -|a 21 | 2 ; During cycle t5, circuit E3 receives data a from its A-value input port. 21 Receive data from its Q-value input port Calculate and output Q= from its Q-value output port. The output port of its P value outputs P = a 21 / That is Figure 8 The output l of the right-hand t5 cycle 21 Circuit C2 receives data a from its A-value input port. 22 -|a 21 | 2 Perform the calculation and output the result A = a from its A value output port. 22 -|a 21 | 2 Meanwhile, data a 31 Inputting the third input port I13, which is the A-value input port of circuit D3, circuit D3 performs calculations and outputs the calculation result A=a from its A-value output port. 22 -|a 21 | 2 ; ... Similarly, after t13 cycles are completed, the triangular matrix L can be output according to the above formula 1.

[0073] The triangular array inversion circuit array consists of 9 multiply-accumulate circuit units and one delay circuit unit, specifically including: Circuit G is used to calculate Q=PB. The circuit identifier is as follows: Figure 9A As shown, it includes: a P-value input port for inputting data P; a B-value input port for inputting data B; a Q-value output port for outputting the calculation result Q=PB; and a P-value output port for outputting data P. The H circuit is used to calculate B = B - PQ. The circuit designation is as follows: Figure 9B As shown, it includes: a P-value input port for inputting data P; a B-value input port for inputting data B; a Q-value input port for inputting data Q; a B-value output port for outputting the calculation result B=B-PQ; a P-value output port for outputting data P, i.e., the data P input through the P-value input port; and a Q-value output port for outputting data Q, i.e., the data Q input through the Q-value input port. An I-circuit is used to store data and output it with a one-cycle delay. The circuit identifier is as follows: Figure 9C As shown, it includes a P-value input port for inputting data P and a Q-value output port for outputting Q=P.

[0074] Circuit arrays for inverting 4×4 triangular matrices, such as... Figure 10 As shown, it includes six H circuits (H1-H6 in the figure), three G circuits (G1, G2, and G3 in the figure), and one I circuit (I1 in the figure). In the figure, the bold black solid lines represent the input ports of the circuit array (I21-I24 in the figure), and the bold black solid line arrows represent the output ports of the circuit array (O21-O24 in the figure).

[0075] The P-value input port of circuit G1 is the first input port I21 of the triangular array inversion circuit array. Circuits G1, G2 and G3 are connected in sequence. The P-value output port of circuit G1 is connected to the P-value input port of circuit G2, the P-value output port of circuit G2 is connected to the P-value input port of circuit G3, and the P-value output port of circuit G3 is connected to the P-value input port of circuit I1. The P-value input port of circuit H1 is the second input port I22 of the triangular array inversion circuit. The P-value output port of circuit H1 is connected to the P-value input port of circuit H2. The B-value output port of circuit H1 is connected to the B-value input port of circuit G1. The Q-value input port of circuit H1 is connected to the Q-value output port of circuit G2. The P-value output port of circuit H2 is connected to the P-value input port of circuit H3. The B-value output port of circuit H2 is connected to the B-value input port of circuit G2. The Q-value input port of circuit H2 is connected to the Q-value output port of circuit G3. The B-value output port of circuit H3 is connected to the B-value input port of circuit G3. The Q-value input port of circuit H3 is connected to the Q-value output port of circuit I1. The Q-value output port of circuit G1 is the fourth output port O24 of the triangular array inversion circuit array, the Q-value output port of circuit G2 is the third output port O23 of the triangular array inversion circuit array, the Q-value output port of circuit G3 is the second output port O22 of the triangular array inversion circuit array, and the Q-value output port of circuit I1 is the first output port O21 of the triangular array inversion circuit array. The P-value input port of circuit H4 is the third input port I23 of the triangular array inversion circuit array. The P-value output port of circuit H4 is connected to the P-value input port of circuit H5. The B-value output port of circuit H4 is connected to the B-value input port of circuit H1. The Q-value input port of circuit H4 is connected to the Q-value output port of circuit H2. The B-value output port of circuit H5 is connected to the B-value input port of circuit H2. The Q-value input port of circuit H5 is connected to the Q-value output port of circuit H3. The P-value input port of circuit H6 is the fourth input port I24 of the triangular array inversion circuit array. The B-value output port of circuit H6 is connected to the B-value input port of circuit H4. The Q-value input port of circuit H6 is connected to the Q-value output port of circuit H5.

[0076] The timing of the circuit array is as follows Figure 11 As shown, Figure 11 The left side of the middle column shows the input timing sequence, representing the timing relationship of the data input from the input ports. Each column corresponds to one input port, and from right to left, they are the first input port I21, the second input port I22, the third input port I23, and the fourth input port I24. Figure 10 There are four input ports I21-I24. Each row corresponds to a time cycle (or processing cycle or time step). Figure 11 The right side of the image shows the output timing, representing the timing relationship of the data output from the output ports. Each column corresponds to one output port, from right to left: first output port O21, second output port O22, third output port O23, and fourth output port O24. Figure 10 There are four output ports O21-O24. Similarly, each row corresponds to a time period. For example, for the input ports, in period t1, input I is received from the first input port I21. 11 -1During cycle t3, input I is received from the second input port I22. 21 The t4 cycle starts from the first input port I. 22 -1 ... For the output port, the output data w can be obtained from the first output port O21 during cycle t4. 11 During cycle t6, output data w can be obtained from the second output port O22. 21 ,…….Depend on Figure 11 It can be seen that the inversion of the lower triangular matrix of a 4×4 Hermitian matrix can be completed through 13 cycles of calculation.

[0077] The inverse of the lower triangular matrix can be obtained using Formula 2. The process is as follows: For the first column, j=1 When i=1: When i=2: When i=3: When i=4: For the second column, j=2 When i=2: When i=3: When i=4: For the third column, j=3 When i=3: When i=4: For the fourth column, j=4 When i=4: The lower triangular matrix can be obtained through the above calculations. The reverse: .

[0078] The above calculation process is achieved using a triangular array inversion circuit, referring to... Figure 10 and Figure 11 The following is part of the work process: During period t1, input data l 11 -1 When the first input port I21 is input, which is the P-value input port of circuit G1, circuit G1 performs calculations. At this time, there is no data input to the B-value input port of circuit G1, so the Q-value output port has no valid calculation result output. The P-value output port of circuit G1 outputs P = l. 11 -1 ; During period t2, circuit G2 receives data l from its P-value input port. 11 -1 Similarly, since there is no input data at the B-value input port, there is no valid calculation result output at the Q-value output port, and the P-value output port of circuit G2 outputs P = l. 11 -1 ; During period t3, circuit G3 receives data l from its P-value input port. 11 -1 The output port outputs P= l. 11 -1 Meanwhile, data l 21 The second input port I22 is the P-value input port of circuit H1, and circuit H1 outputs P=1 from its P-value output port. 21 ; ... Similarly, after t13 cycles are completed, the triangular matrix L can be output according to the above formula 1.

[0079] The output of the Cholesky decomposition circuit array is the input of the triangular matrix inversion circuit array, which in turn uses... Therefore, the P-value output port of circuit F1 in the Cholesky decomposition circuit array is designed as follows: Correspondingly, the triangular array inversion circuit array can be directly obtained from the Cholesky decomposition circuit. There is no need to perform the inverse operation.

[0080] Figure 12 This diagram illustrates the connection between the Cholesky decomposition circuit array and the triangular array inversion circuit. When calculating data across multiple cycles, a delay unit can be connected between the two circuits to match the output timing of the Cholesky decomposition circuit array with the input timing of the triangular array inversion circuit array. (Z in the diagram...) -1 Z -2 and Z -3 These are used to delay one cycle, two cycles, and three cycles, respectively. Figure 12 The output of the circuits E1, E2, E3, and F1 in the Cholesky decomposition circuit array, which are used to invert the triangular array, is... Figure 7 The O14-O11 shown.

[0081] The above embodiments are illustrated using the processing of a single matrix as an example. In DoA processing of radar signals, there may be situations where it is necessary to invert multiple matrices simultaneously. Therefore, based on the circuit described above, this disclosure also provides a parallel processing scheme. Figure 13 and Figure 14 To input three matrices simultaneously [a ij],[b ij ],[c ij Timing diagram of parallel computing under the condition of ], where Figure 13 Timing diagram for Cholesky decomposition of the circuit matrix. Figure 14 The timing diagram shows the inversion circuit matrix for a triangular matrix. By pre-configuring the input timing of different matrix elements, the Hermitian matrix inversion circuit in this embodiment can process multiple matrices in parallel. Figure 13 and Figure 14 This example illustrates the parallel processing of three Hermitian matrices. The parallelism can be further increased when the pipeline of each computation unit exceeds one cycle. Assuming the pipeline depth of a computation unit is d, the maximum number of matrices that can be computed in parallel at one time is 3d. To improve computation speed... The above embodiment uses the inversion of a 4-dimensional matrix as an example for illustration. This embodiment's circuit can also invert matrices of dimensions less than 4. For example, to invert a 3-dimensional matrix, for the Cholesky decomposition circuit, only... Figure 7 For the circuit units C2, C3, D2, E2, E3, and F1 in the triangular matrix inversion circuit, only... Figure 10 The circuit units G2, G3, H2, H3, H5, and I1 in the example; for instance, if we want to invert a 2D matrix, for the Cholesky decomposition circuit, we only need to... Figure 7 For the circuit units C2, C3, D2, E2, E3, and F1 in the triangular matrix inversion circuit, only... Figure 10 The circuit units G2, G3, H2, H3, H5, and I1 are used. In other embodiments, if it is necessary to invert a matrix of more than 4 dimensions, then... Figure 7 and Figure 10 The circuit shown is expanded to include more, such as Figures 6A-6D as well as Figures 9A-9C The circuit units are sufficient, therefore the circuit array in the above embodiment can be used to invert any n-dimensional matrix.

[0082] In an exemplary embodiment, when inverting a large number of matrices that have identical submatrices, a memoization mode can be used to accelerate the matrix inversion operation. For example, given multiple n-dimensional positive definite Hermitian matrices A1, A2, ..., A... k Each matrix in this matrix shares a common submatrix, meaning that matrix A1[1:m,1:m] = A2[1:m,1:m] = ... = A k [1:m, 1:m]. This circuit can simultaneously compute the Cholesky inverse of multiple matrices. Furthermore, after inputting the first matrix A1, the circuit can memorize the common part A1[1:m,1:m] of all matrices. This means that when inputting subsequent matrices, only the A[m+1:n,:] part needs to be input, representing the varying nm rows. The circuit also only needs to output L. -1 The [m+1:n,:] part. For example... Figure 15 As shown, in the Hermitian matrix A to be inverted, A[1:3,1:3] is the memory part, and the lower triangular matrix obtained after Cholesky decomposition is L. -1 L -1 [1:3,1:3] represents the memory portion.

[0083] Taking n=4 and m=3 as an example, the memorization mode is used in the operation of the first matrix. It will receive the complete A[1:4,1:4] as input and output the complete L. -1 [1:4, 1:4]. After this calculation, the storage unit will remember the input A[1:3, 1:3] portion and the relevant intermediate calculation results. Subsequently, A2, A3, ..., A... k The matrix only requires input A[4,:], and the output will only be L. -1 [4,1:4] is sufficient.

[0084] This highly parallel, memory-mode, two-stage positive definite Hermitian matrix inversion circuit can also be configured to quickly compute the inverses of multiple matrices.

[0085] In an exemplary embodiment, in addition to using an array structure, the above inversion operation can be implemented using a non-array structure, such as employing... Figure 16 The circuit shown is implemented as follows. The Cholesky decomposition control unit is responsible for scheduling the first computation unit and the first storage unit to perform the operation process shown in Formula 1, while the triangular array inversion control unit is responsible for scheduling the second computation unit and the second storage unit to perform the operation process shown in Formula 2.

[0086] The matrix inversion circuit of this disclosure can be extended to an N*N matrix circuit and supports 2~N matrix inversion. Furthermore, it can be applied to the direction of arrival (DoA) estimation stage; for example, the matrix inversion in the maximum likelihood (DML) method or iterative adaptive (IAA) method can be implemented using the circuit of this application. It can also be applied to the tracking stage; for example, the matrix inversion in the extended Kalman filter (EKF) method can be implemented using the circuit of this application. Simultaneously, it can also be applied to radar signal processing such as super-resolution and deblurring, and specific implementations can be based on the content described in the embodiments of this application.

[0087] The embodiments disclosed herein can be applied to Figure 4A or Figure 4BThe M4INV computation engine unit shown may include the aforementioned Hermite inversion circuit.

[0088] The Hermitian inversion circuit described in this embodiment can be implemented using digital circuitry.

[0089] This application also provides an integrated circuit, which may include a radio frequency (RF) module, an analog signal processing module, and a digital signal processing module connected in sequence. The RF module is used to generate RF transmitted signals and receive RF received signals, and may include the digital circuit described in this embodiment. The analog signal processing module is used to down-convert the RF received signals to obtain intermediate frequency (IF) signals. The digital signal processing module is used to perform analog-to-digital conversion on the IF signals to obtain digital signals. The RF received signals are echo signals formed by the RF transmitted signals being emitted and / or scattered by a target, or RF signals emitted by other devices. The digital processing module may include the digital circuit provided in this embodiment. Optionally, the integrated circuit may also include a data processing module, which is used to process the digital signals to achieve target detection and / or wireless communication. For example, the integrated circuit may be a radar or a UWB chip (chip or die).

[0090] In an optional embodiment, when the integrated circuit is a millimeter-wave radar chip, the types of digital functional modules in the integrated circuit can be determined according to actual needs. For example, in a millimeter-wave radar chip, the data processing module can be used for range Vidoff transform, velocity Vidoff transform, constant false alarm rate detection, direction of arrival detection, point cloud processing, etc., to acquire information such as the target's range, horizontal angle, pitch angle, velocity, altitude, and micro-Doppler motion characteristics. It can also further generate information such as the target's shape, size, surface roughness, and dielectric properties based on the above-mentioned target-related information.

[0091] In some optional embodiments, the integrated circuit may be an AiP (Antenna-In-Package) chip structure, an AoP (Antenna on Package) chip structure, an AoC (Antenna on Chip) chip structure, or a RoP (Radiator on / through Package) structure. Optionally, the RoP structure can be formed by setting a radiator on the chip package and surrounding the radiator with solder balls to form an air waveguide structure. That is, the radio frequency (RF) signal generated by the chip can be transmitted to an external antenna through the aforementioned radiator, the air cavity waveguide structure surrounded by the solder balls, and the air waveguide built into the PCB board, so as to radiate towards the target area.

[0092] According to some other embodiments of this application, an electromagnetic wave device is also proposed. This electromagnetic wave device may include an antenna and an integrated circuit as described above. The integrated circuit is connected to the antenna and is used to transmit and receive electromagnetic wave signals. For example, the electromagnetic wave sensor may include: a carrier, an integrated circuit as described in any of the above embodiments, and an antenna, etc. The integrated circuit may be disposed on the carrier; the antenna may be disposed on the carrier (i.e., the antenna may be an antenna disposed on a PCB board in a structure such as RoP), or integrated with the integrated circuit as a single device disposed on the carrier (i.e., the antenna may be an antenna disposed in a structure such as AiP, AoP, or AoC); wherein the integrated circuit is connected to the antenna (i.e., the sensing chip or integrated circuit does not integrate an antenna, such as a conventional SoC), and is used to transmit and receive electromagnetic wave signals. The carrier may be a printed circuit board (PCB).

[0093] In some optional embodiments, the aforementioned electromagnetic wave signal can be a centimeter wave band or a millimeter wave band (such as 3.1GHz, 24GHz, 60GHz, 77GHz, 94GHz, 120GHz, 140GHz, 220GHz, 250GHz, etc.). Specifically, the 3.1GHz centimeter wave signal can include 3.1GHz~10.6GHz, for example 3.1GHz, 5GHz, 6GHz, 8GHz, 10.6GHz, etc., or it can be such as 7.163-8.812GHz, etc.; the 77GHz millimeter wave signal can include signals from 76GHz to 81GHz, for example, frequency ranges such as 76GHz~77GHz, 77GHz~79GHz, 79GHz~81GHz, etc., or fixed frequency points such as 76GHz, 77GHz, 78GHz, 79GHz, 80GHz, 81GHz, etc.

[0094] This application also provides a terminal device, which may include: a device body; and an electromagnetic wave device as described above disposed on the device body; wherein the electromagnetic wave device can be used for target detection and / or communication to provide reference information to the device body, thereby assisting or even controlling the operation of the device body and / or other electronic devices disposed in the device body.

[0095] Specifically, based on the above embodiments, in some optional embodiments of this application, the electromagnetic wave device can be disposed outside the device body or inside the device body. In other optional embodiments of this application, the electromagnetic wave sensor can be partially disposed inside the device body and partially disposed outside the device body. This application does not limit this, and the specific arrangement depends on the circumstances.

[0096] In some alternative embodiments, the aforementioned device body can be a component or product applied in fields such as smart cities, smart homes, transportation, smart homes, consumer electronics, security monitoring, industrial automation, in-cabin detection (such as smart cockpits), medical devices, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, watches, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication and office equipment (such as mobile phones, tablets, computers, air mice, keyboards, projectors, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments used to detect vital signs parameters and various devices equipped with such instruments, such as in-cabin vital sign detection in automobiles, indoor personnel monitoring, smart medical devices, and consumer electronic devices.

[0097] For example, when the aforementioned device is a vehicle, the electromagnetic wave device, as an onboard sensor, can be used to assist ADAS systems in achieving onboard applications such as adaptive cruise control, automatic emergency braking (AEB), blind spot detection warning (BSD), lane change assist warning (LCA), rear cross traffic alert (RCTA), assisted / automatic parking assist, rear vehicle warning, collision avoidance, pedestrian detection, and door collision avoidance, automatic opening and closing of the trunk door, etc. It can also be used as a digital key for the vehicle. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0098] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0099] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0100] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0101] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A circuit for inverting an Hermitian matrix, characterized in that, Used to invert Hermitian matrix A, including: Cholesky decomposition circuit, used to calculate the lower triangular matrix L to make LL H =A, where L H This is the conjugate transpose of L; A triangular matrix inverse circuit is used to calculate the inverse L of the lower triangular matrix L. -1 The L -1 The conjugate transpose of L -1 The product of these is the inverse of the Hermitian matrix A.

2. The Hermitian matrix inversion circuit according to claim 1, characterized in that, The Cholesky decomposition circuit is a circuit array composed of multiple circuit units. The Cholesky decomposition circuit includes the following circuit units: for calculating A = A - |P| 2 The C circuit unit is used to calculate A = A - PQ*, the D circuit unit is used to calculate P = AQ, and the E circuit unit is used to calculate P = 1 / A. 1 / 2 And Q=1 / A 1 / 2 The F circuit unit, wherein the C circuit unit is connected to the D circuit unit, the E circuit unit and the F circuit unit respectively, the D circuit unit is connected to the E circuit unit, and the E circuit unit is connected to the F circuit unit; The triangular array inversion circuit is a circuit array composed of multiple circuit units. The triangular array inversion circuit includes the following circuit units: a G circuit unit for calculating Q=PB, an H circuit unit for calculating B=B-PQ, and an I circuit unit for storing data and outputting the data with a one-cycle delay. The G circuit unit is connected to the H circuit unit and the I circuit unit respectively, and the H circuit unit is connected to the I circuit unit.

3. The Hermitian matrix inversion circuit according to claim 1 or 2, characterized in that, The Cholesky decomposition circuit includes: Two or more C circuit units are used to calculate A = A - |P| 2 It includes: an A-value input port for inputting data A; a P-value input port for inputting data P; and an A-value output port for outputting the calculation result A = A - |P|. 2 The Q-value output port is used to output Q=P. One or more D circuit units are used to calculate A = A - PQ*, including: an A-value input port for inputting data A; a P-value input port for inputting data P; a Q-value input port for inputting data Q; an A-value output port for outputting the calculation result A = A - PQ*, ** represents the complex conjugate; a P-value output port for outputting data P, i.e., the data P input through the P-value input port; and a Q-value output port for outputting data Q, i.e., the data Q input through the Q-value input port. Two or more E circuit units are used to calculate P=AQ, including: an A value input port for inputting data A; a Q value input port for inputting data Q; a P value output port for outputting the calculation result P=AQ; and a Q value output port for outputting data Q, which is the data Q input through the Q value input port. An F circuit unit is used to calculate P=1 / A. 1 / 2 And Q=1 / A 1 / 2 It includes: an A-value input port for inputting data A; and a P-value output port for outputting the calculation result P=1 / A. 1 / 2 The Q-value output port is used to output the calculation result Q=1 / A. 1 / 2 ; The C circuit unit, D circuit unit, E circuit unit and E circuit unit form a grid connection. When connected, the A value output port is connected to the A value input port, the P value output port is connected to the P value input port, and the Q value output port is connected to the Q value input port.

4. The Hermitian matrix inversion circuit according to claim 3, characterized in that, The Cholesky decomposition circuit comprises: 4 C circuit units, 3 D circuit units, 3 E circuit units, and 1 F circuit unit, wherein: The A-value input port of the first C circuit unit is the first input port of the Cholesky decomposition circuit. The first C circuit unit, the second C circuit unit, and the third C circuit unit are connected in sequence. The A-value output port of the first C circuit unit is connected to the A-value input port of the second C circuit unit, the A-value output port of the second C circuit unit is connected to the A-value input port of the third C circuit unit, the A-value output port of the third C circuit unit is connected to the A-value input port of the F circuit unit, and the P-value output port of the F circuit unit is the first output port of the Cholesky decomposition circuit. The A-value input port of the first D circuit unit is the second input port of the Cholesky decomposition circuit. The A-value output port of the first D circuit unit is connected to the A-value input port of the second D circuit unit. The P-value output port of the first D circuit unit is connected to the P-value input port of the first C circuit unit. The Q-value input port of the first D circuit unit is connected to the Q-value output port of the second C circuit unit. The P-value output port of the second D circuit unit is connected to the P-value input port of the second C circuit unit. The Q-value input port of the second D circuit unit is connected to the Q-value output port of the third C circuit unit. The A-value input port of the third D circuit unit is the third input port of the Cholesky decomposition circuit. The P-value output port of the third D circuit unit is connected to the P-value input port of the first D circuit unit. The Q-value input port of the third D circuit unit is connected to the Q-value output port of the second D circuit unit. The Q-value output port of circuit unit F is connected to the Q-value input port of circuit unit E. The P-value output port of circuit unit E is connected to the P-value input port of circuit unit C. The P-value output port of circuit unit E is the second output port of the Cholesky decomposition circuit. The A-value input port of circuit unit E is connected to the A-value output port of circuit unit D. The Q-value output port of circuit unit E is connected to the Q-value input port of circuit unit E. The P-value output port of circuit unit E is connected to the P-value input port of circuit unit D. The P-value output port of circuit unit E is the third output port of the Cholesky decomposition circuit. The A-value input port of circuit unit E is connected to the A-value output port of circuit unit D. The Q-value output port of circuit unit E is connected to the Q-value input port of circuit unit E. The P-value output port of circuit unit E is connected to the P-value input port of circuit unit D. The P-value output port of circuit unit E is the fourth output port of the Cholesky decomposition circuit. The A-value input port of circuit unit E is the third input port of the Cholesky decomposition circuit.

5. The Hermitian matrix inversion circuit according to claim 1 or 2, characterized in that, The triangular array inversion circuit includes: Two or more G circuit units are used to calculate Q=PB, including: a P-value input port for inputting data P; a B-value input port for inputting data B; a Q-value output port for outputting the calculation result Q=PB; and a P-value output port for outputting data P. Three or more H circuit units are used to calculate B=B-PQ, including: a P-value input port for inputting data P; a B-value input port for inputting data B; a Q-value input port for inputting data Q; a B-value output port for outputting the calculation result B=B-PQ; a P-value output port for outputting data P, i.e., the data P input through the P-value input port; and a Q-value output port for outputting data Q, i.e., the data Q input through the Q-value input port. An I-circuit unit is used to store data and output it with a one-cycle delay. It includes a P-value input port for inputting data P and a Q-value output port for outputting Q=P. The G circuit unit, H circuit unit, and I circuit unit form a grid connection. When connected, the P-value output port is connected to the P-value input port, the B-value output port is connected to the B-value input port, and the Q-value output port is connected to the Q-value input port.

6. The Hermitian matrix inversion circuit according to claim 5, characterized in that, The triangular array inversion circuit comprises: 3 G circuit units, 6 H circuit units, and 1 I circuit unit, wherein: The P-value input port of the first G circuit unit is the first input port of the triangular array inversion circuit. The first G circuit unit, the second G circuit unit, and the third G circuit unit are connected in sequence. The P-value output port of the first G circuit unit is connected to the P-value input port of the second G circuit unit, the P-value output port of the second G circuit unit is connected to the P-value input port of the third G circuit unit, and the P-value output port of the third G circuit unit is connected to the P-value input port of the I circuit unit. The P-value input port of the first H circuit unit is the second input port of the triangular array inversion circuit. The P-value output port of the first H circuit unit is connected to the P-value input port of the second H circuit unit. The B-value output port of the first H circuit unit is connected to the B-value input port of the first G circuit unit. The Q-value input port of the first H circuit unit is connected to the Q-value output port of the second G circuit unit. The P-value output port of the second H circuit unit is connected to the P-value input port of the third H circuit unit. The B-value output port of the second H circuit unit is connected to the B-value input port of the second G circuit unit. The Q-value input port of the second H circuit unit is connected to the Q-value output port of the third G circuit unit. The B-value output port of the third H circuit unit is connected to the B-value input port of the third G circuit unit. The Q-value input port of the third H circuit unit is connected to the Q-value output port of the I circuit unit. The Q-value output port of the first G circuit unit is the fourth output port of the triangular array inversion circuit, the Q-value output port of the second G circuit unit is the third output port of the triangular array inversion circuit, the Q-value output port of the third G circuit unit is the second output port of the triangular array inversion circuit, and the Q-value output port of the I circuit unit is the first output port of the triangular array inversion circuit. The P-value input port of the fourth H circuit unit is the third input port of the triangular array inversion circuit. The P-value output port of the fourth H circuit unit is connected to the P-value input port of the fifth H circuit unit. The B-value output port of the fourth H circuit unit is connected to the B-value input port of the first H circuit unit. The Q-value input port of the fourth H circuit unit is connected to the Q-value output port of the second H circuit unit. The B-value output port of the fifth H circuit unit is connected to the B-value input port of the second H circuit unit. The Q-value input port of the fifth H circuit unit is connected to the Q-value output port of the third H circuit unit. The P-value input port of the sixth H circuit unit is the fourth input port of the triangular array inversion circuit. The B-value output port of the sixth H circuit unit is connected to the B-value input port of the fourth H circuit unit. The Q-value input port of the sixth H circuit unit is connected to the Q-value output port of the fifth H circuit unit.

7. The Hermitian matrix inversion circuit according to claim 1, characterized in that, The Cholesky decomposition circuit is connected to the triangular array inversion circuit via a delay unit, so that the output data of the Cholesky decomposition circuit matches the input timing of the triangular array inversion circuit.

8. The Hermitian matrix inversion circuit according to claim 1, characterized in that, The Hermitian matrix inversion circuit is used to process multiple Hermitian matrices or multiple positive definite Hermitian matrices in parallel.

9. The Hermitian matrix inversion circuit according to claim 1 or 8, characterized in that, It also includes processing units and storage units, wherein: The processing unit is used to, when it is determined that two or more Hermitian matrices to be processed have the same element, cause the storage unit to store the same element and the intermediate calculation result of the same element, so as to improve the processing speed of the Hermitian matrix.

10. A circuit for inverting an Hermitian matrix, characterized in that, Used to invert Hermitian matrix A, including: Given multiple n-dimensional Hermitian matrices A1, A2, ... A k All matrices share a common submatrix. The Hermitian matrix inversion circuit processes the multiple Hermitian matrices in parallel. After inputting the first matrix A1, the Hermitian matrix inversion circuit stores the intermediate calculation results of the common submatrix. For A2, ..., A... k When processing the matrix, the stored intermediate calculation results are used for calculation.

11. The Hermitian matrix inversion circuit according to claim 10, characterized in that, For A2,…A k The matrix, wherein the output of the Hermitian matrix inversion circuit differs from the output of the A1 matrix.

12. A method for inverting an Hermitian matrix, characterized in that, The method for inverting a Hermitian matrix A includes: Obtain the lower triangular matrix L, where the product of the conjugate transpose of the triangular matrix L and the triangular matrix L is equivalent to the Hermitian matrix A; Obtain the inverse L of the lower triangular matrix L. -1 ;as well as Based on the L -1 The conjugate transpose of L -1 The inverse of the Hermitian matrix A is obtained.

13. The method according to claim 12, characterized in that, The lower triangular matrix L is obtained using the circuit described in any one of claims 1-11, and the inverse L of the lower triangular matrix L is also obtained. -1 .

14. The method according to claim 12, characterized in that, According to a pre-configured timing sequence, elements of two or more Hermitian matrices are input alternately, so that the Hermitian matrix inversion circuit processes the two or more Hermitian matrices in parallel.

15. The method according to any one of claims 12-14, characterized in that, When it is determined that two or more Hermitian matrices to be processed have the same element, the same element and the intermediate processing result of the same element are stored to improve the processing speed of the Hermitian matrix.

16. A method for radar signal processing, characterized in that, The method includes at least one step in the following when processing echo signals: deblurring, super-resolution, angle estimation, and target tracking based on the method of inverting the Hermitian matrix using a lower triangular matrix.

17. The method according to claim 16, characterized in that, The method of inverting the Hermitian matrix using the lower triangular matrix includes: using the circuit as described in any one of claims 1-11, or the method as described in any one of claims 12-15, to obtain the lower triangular matrix and the inverse of the lower triangular matrix.

18. A radar signal processing device, characterized in that, It includes an M4INV computing engine unit, which includes the circuitry as described in any one of claims 1-11.

19. An integrated circuit, characterized in that, include: The signal transmitting module is configured to emit electromagnetic waves for target detection; A signal receiving module is configured to receive echoes formed by the reflection and / or scattering of the electromagnetic waves; as well as The processing module is configured to process the echo signal to achieve target detection; Wherein, at least the processing module includes the circuit as described in any one of claims 1-11.

20. An electromagnetic wave sensor, characterized in that, include: Carrier; The integrated circuit as described in claim 19 is disposed on the carrier; An antenna is disposed on the carrier, or the antenna and the integrated circuit are integrated into a single device and disposed on the carrier. The integrated circuit is connected to the antenna and is used to transmit the electromagnetic wave signal and / or receive the echo signal.

21. A terminal device, characterized in that, include: Equipment body; as well as The electromagnetic wave sensor as described in claim 20 is disposed on the main body of the device; The electromagnetic wave sensor is used for target detection and / or communication to provide reference information for the operation of the device body.

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