Display device and display panel

By using an etching process to form grooves and arrange bent wiring in flexible displays, the problem of cracking in the wiring connections during bending of flexible displays has been solved, improving productivity and simplifying the manufacturing process.

CN121661909APending Publication Date: 2026-03-13LG DISPLAY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-31
Publication Date
2026-03-13

AI Technical Summary

Technical Problem

During the bending process of flexible displays, the connecting wires may crack due to stress concentration, and existing etching processes increase the reduction in manufacturing productivity.

Method used

By using an etching process to form grooves in the display panel and arranging curved wiring and connecting wiring in the curved areas, and using a planarization layer of organic material as an anti-etching layer, a separate mask process is avoided, simplifying the manufacturing process and protecting the curved wiring.

Benefits of technology

It improves the productivity of display devices, reduces damage to wiring due to bending, maintains the rigidity of the substrate, and simplifies the manufacturing process.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention relates to a display device and a display panel. A display device according to the present disclosure may include a display panel having a groove and a circuit board connected to the display panel, and the display panel may include: a substrate including a first substrate and a second substrate spaced apart from each other by the groove; a circuit layer disposed on the first substrate and including a transistor; a planarization layer extending from the circuit layer and disposed on the groove; a pad portion disposed on the second substrate and connected to the circuit board; a curved wiring line disposed on the planarization layer; and a connection wiring that is connected to the bent wiring.
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Description

Technical Field

[0001] The embodiments relate to display panels and display devices including the display panels, and more specifically, for example, but not limited to, display panels including substrates for which etching processes are applied for manufacturing process optimization and display devices including the display panels. Background Technology

[0002] Flexible displays can change screen size by rolling, folding, or bending flexible panels. Flexible displays can be implemented as rollable, foldable, bendable, and sliding displays. Such flexible displays are not only used in mobile devices such as smartphones and tablets, but also in televisions, automotive displays, wearable devices, and more, and their application areas are constantly expanding.

[0003] Flexible displays can achieve bezel-bending displays with minimized bezel areas by using flexible panel structures to fold non-display areas.

[0004] The descriptions provided in the Related Art section should not be considered prior art simply because they are mentioned or associated with in the Related Art section. The Related Art section includes information describing one or more aspects of the subject matter art, and the descriptions in this section do not limit this disclosure. Summary of the Invention

[0005] The inventors of this application have newly recognized that, as the bending area of ​​a flexible display is bent, stress may concentrate on the portion of the connecting wiring arranged in the bending area. Therefore, cracks may appear in the connecting wiring. In such cases, while various metallic materials can be made of the connecting wiring considering conductivity, limitations exist in the selection of materials for the connecting wiring due to the possibility of damage caused by bending.

[0006] Furthermore, the inventors of this application have further recognized that flexible displays can use etching processes to simplify the manufacturing process and that a separate etch-resistant layer can be arranged for the etching process of the substrate. However, the arrangement of the etch-resistant layer requires a separate masking process, and the manufacturing productivity of the display device may decrease due to the increased number of steps or processes introduced by the masking process.

[0007] Therefore, there is a need for a display panel and a display device including the display panel that can improve manufacturing productivity while preventing damage to the connection wiring due to bending or minimizing the possibility of damage to the connection wiring.

[0008] Embodiments of this disclosure provide a display panel including a substrate for process optimization by applying an etching process, and a display device including the display panel.

[0009] Embodiments of this disclosure provide a display panel that uses a portion of a component arranged in a display area as an etch-resistant layer for simplified manufacturing processes, and a display device including the display panel.

[0010] Embodiments of this disclosure provide a display panel and a display device including the display panel that prevent damage to the connection wiring due to bending or minimize the possibility of damage to the connection wiring by using curved wiring arranged in a curved region.

[0011] Embodiments of this disclosure provide a display device that includes a narrow bezel by applying a structurally modified substrate to the pad portion and bending the substrate.

[0012] The embodiments described herein are intended to address purposes other than those described above, and those skilled in the art will clearly understand, based on the following description, other purposes not mentioned.

[0013] A display device according to an exemplary embodiment of the present disclosure includes a display panel having a recess and a circuit board connected to the display panel, and the display panel includes: a substrate including a first substrate and a second substrate spaced apart from each other by the recess; a circuit layer disposed on the first substrate and including transistors; a planarization layer extending from the circuit layer and disposed on the recess; a pad portion disposed on the second substrate and connected to the circuit board; a bent wiring disposed on the planarization layer; and a connection wiring connected to the bent wiring.

[0014] According to this disclosure, process optimization can be achieved through etching. For example, since multiple recesses corresponding to the corresponding recesses of multiple display panels can be formed on a single mother substrate through etching, the manufacturing process can be simplified.

[0015] According to this disclosure, by using a portion of the components arranged in the display area as an etch resist layer, a separate etch resist layer arranged in response to an etching process can be removed. Therefore, since a separate mask process is not performed to arrange the etch resist layer, the productivity of the display device can be improved.

[0016] According to this disclosure, the rigidity of a substrate made of glass material can be maintained by using an etching process.

[0017] According to this disclosure, when a substrate made of glass material is etched, damage to curved wiring arranged in curved areas can be prevented by using a planarization layer made of organic material.

[0018] According to this disclosure, curved wiring can be protected by a pattern layer disposed on curved wiring.

[0019] The various useful advantages and effects of the embodiments described herein are not limited to those described above, and those skilled in the art will clearly understand, based on the following description, the effects not described above.

[0020] The effects of this disclosure are not limited to those exemplified above, and many more effects are included in this disclosure. Attached Figure Description

[0021] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0022] Figure 1 This is a perspective view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 3 It is along Figure 2 A cross-sectional view taken from line I-I' in the diagram;

[0025] Figure 4 It is shown Figure 3 A magnified view of region A in the image;

[0026] Figures 5A to 5D This is a diagram illustrating the manufacturing process of a display panel according to an exemplary embodiment of the present disclosure;

[0027] Figure 6 This is a diagram showing the relationship between the curved neutral plane;

[0028] Figure 7 This is a diagram illustrating a coating layer arranged on a display panel according to an exemplary embodiment of the present disclosure;

[0029] Figure 8 This is a diagram illustrating the curved appearance of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 9 This is a cross-sectional view illustrating another embodiment of a display panel according to an exemplary embodiment of the present disclosure;

[0031] Figure 10 It is shown Figure 9 A magnified view of region B in the image;

[0032] Figure 11 This is a diagram illustrating the curved appearance of a display device according to another embodiment of an exemplary embodiment of a display panel based on the present disclosure;

[0033] Figure 12 This is a cross-sectional view illustrating another exemplary embodiment of a display panel according to one exemplary embodiment of the present disclosure; and

[0034] Figure 13 It is shown Figure 12 A magnified view of region C in the image.

[0035] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their depictions, may be exaggerated.

[0036] [List of reference numerals]

[0037] 10, 10a: Display panel; 100: Substrate

[0038] 110: First substrate; 120: Second substrate

[0039] 200: Circuit layer; 240: Planarization layer

[0040] 300: Liquid crystal layer; 400: Pattern layer

[0041] 500: Color filter layer; 600: Black matrix

[0042] 700: Cover component; 800: Coating layer

[0043] BL: Curved wiring; G: Groove

[0044] LL: Connector wiring PAD: Pad portion Detailed Implementation

[0045] The advantages and features of this disclosure, as well as methods of implementing them, will become clearer from the exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments described below, but can be implemented in a variety of different forms. Rather, these exemplary embodiments will complete the disclosure and allow those skilled in the art to fully understand its scope. This disclosure is limited only to the scope of the appended claims.

[0046] The shapes, dimensions, areas, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe exemplary embodiments of this disclosure are exemplary, and this disclosure is not limited to the items shown. Throughout this disclosure, the same reference numerals refer to the same elements. Furthermore, in describing this disclosure, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the subject matter of this disclosure.

[0047] The terms used herein, such as “comprising,” “including,” “having,” “constituting,” “forming,” and “component of,” are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, references to the singular should be interpreted to include the plural.

[0048] When interpreting a component, it is interpreted as including the error range, even if there is no separate description.

[0049] When describing the position or connection between two components, such as “on,” “above,” “over,” “below,” “beside,” “below,” “near,” “close to,” “adjacent,” “on the side,” “right next to,” “connected or linked,” “crossing,” “intersecting,” etc., one or more other components may be inserted between them unless “immediately next” or “directly” is used.

[0050] When describing temporal context, such as “after,” “following,” “next,” or “before,” it may not be continuous in time scale unless “immediately after” or “directly” is used.

[0051] The terms "first," "second," "A," "B," "(a)," "(b)," etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number preceding the component or the component name. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the first component described below can be the second component.

[0052] The term "at least one" should be understood to include any and all combinations of one or more related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more items from the first, second, and third items, as well as all items derived from the first, second, or third item.

[0053] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting diodes (LEDs), etc. Furthermore, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices and automotive equipment, as well as assemblies of electronic devices (or instruments) or assemblies of devices (or instruments), such as mobile electronic devices like smartphones or tablets, which are complete products or end products that each include LEDs, etc., but embodiments of this disclosure are not limited thereto.

[0054] For ease of description, the dimensions and thickness of each component shown in the figures are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0055] The following implementations can be combined or associated with each other in whole or in part, and various types of interlocking and actuation are technically possible. These implementations can be implemented independently of each other or together in an interrelated relationship.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (as defined in a common dictionary) shall be interpreted as having a meaning consistent with, for example, the meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0057] Throughout the specification, the same reference numerals denote the same components.

[0058] The display device according to the embodiments of this disclosure may include the display device itself in the narrow sense, application products including displays in the narrow sense, or even complete sets of devices as end consumer devices.

[0059] The display device according to an exemplary embodiment of the present disclosure can be implemented as a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), an electroluminescent display (ELD), an organic light-emitting diode (OLED), a quantum dot display, a micro light-emitting diode (LED) display, etc.

[0060] Figure 1 This is a perspective view illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 2 This is a plan view showing a display panel according to an exemplary embodiment of the present disclosure. Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I' in the diagram. Figure 4 It is shown Figure 3 An enlarged view of region A in the image. Figures 5A to 5D This is a diagram illustrating the manufacturing process of a display panel according to an exemplary embodiment of the present disclosure. For example, Figure 5A This is a diagram showing a mother substrate MS in which circuit layer 200, liquid crystal layer 300, pad portion PAD, bent wiring BL, connecting wiring LL, etc. are arranged. Figure 5B This diagram illustrates the use of a mask to perform a bottom etching of the mother substrate MS. Figure 5C This is a diagram showing the groove G formed in the mother substrate by bottom etching. Figure 5D This is a diagram showing multiple display panels 10 separated by a cutting process.

[0061] refer to Figures 1 to 3A display device according to an exemplary embodiment of the present disclosure may include: a display panel 10 including a recess G; a circuit board 20 connected to a pad portion PAD of the display panel 10; and a light source unit 30 emitting light toward a liquid crystal layer 300 of the display panel 10. Furthermore, an input image can be visually reproduced on the display panel 10. The light source unit 30 may be a backlight unit.

[0062] The display panel 10 may include a display area DA for displaying images and a non-display area NA for not displaying images.

[0063] The non-display area NA can refer to the area outside the display area DA. Several types of signal lines can be located in the non-display area NA and can be connected to several types of drive circuits. At least a portion of the non-display area NA can be bent so that it is not visible from the front surface of the display device, or it can be covered by the housing or casing of the display device (not shown). The non-display area NA can also be referred to as the edge area or bezel area.

[0064] The display panel 10 can be a panel with a rectangular structure, having a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. In such a case, the width and length of the display panel 10 can be set to various design values ​​depending on the application of the display device. The X-axis direction can represent the width direction, row direction, or horizontal direction; the Y-axis direction can represent the length direction, column direction, or vertical direction; and the Z-axis direction can represent the up-down direction, vertical direction, or thickness direction. The X-axis, Y-axis, and Z-axis directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. Therefore, each of the X-axis, Y-axis, and Z-axis directions can be described as any of a first direction, a second direction, and a third direction. Planes extending along the X-axis and Y-axis directions can represent horizontal planes.

[0065] The non-display area NA may include a first non-display area NA1, a curved area BA, and a second non-display area NA2. The curved area BA may be located between the first non-display area NA1 and the second non-display area NA2.

[0066] The first non-display area NA1 can be an area surrounding at least a portion of the display area DA.

[0067] The curved region BA is an area adjacent to at least one of the multiple edges of the first non-display region NA1, and may be a bendable region. The display panel 10 can be easily bent through the curved region BA. For example, the display panel 10 can be easily bent through the groove G arranged in the curved region BA.

[0068] The second non-display area NA2 is a region adjacent to at least one of the multiple edges of the curved area BA, and the pad portion PAD can be disposed in the second non-display area NA2. For example, the curved area BA can be in a curved state from a flat state, and the remaining areas of the substrate 100 other than the curved area BA can be in a flat state. As the curved area BA is bent, the second non-display area NA2 can be positioned to overlap with the rear surface of the display area DA. The pad portion PAD can be a pad electrode.

[0069] refer to Figure 3 and Figure 6 The curved region BA is located between the first non-display region NA1 and the second non-display region NA2, and various structures (such as organic layers, inorganic layers, and wiring) arranged in the curved region BA can be bent. For example, as the curved region BA is bent, a portion of the various structures (such as organic layers, inorganic layers, and wiring) can also be bent.

[0070] The circuit board 20 may be a flexible printed circuit board and may be connected to the display panel 10 via pads, but is not limited thereto.

[0071] The liquid crystal layer of the display area DA can be driven by receiving signals from one or more circuit boards 20 via wiring of the display area DA and connection wiring LL of the non-display area NA. For example, the wiring of the display area DA can be wiring used to transmit signals output from the circuit board 20 to the liquid crystal layer of the display area DA together with multiple connection wiring LL.

[0072] When multiple connecting wires LL are arranged in a curved region BA, as the curved region BA is bent, a portion of the multiple connecting wires LL may also bend. Therefore, stress may concentrate on a portion of the bent connecting wires LL, and cracks may appear in the connecting wires LL due to stress.

[0073] Therefore, when multiple connecting wires LL are arranged in a bending region BA, the possibility of damage to the connecting wires LL due to cracks or the like can be considered. As an example, the shape and material of the connecting wires LL can be configured to prevent cracks that may occur in the multiple connecting wires LL during bending of the bending region BA. For example, to prevent cracks that may occur in the multiple connecting wires LL during bending of the bending region BA, the connecting wires LL can be made of a conductive material with excellent ductility. Furthermore, the multiple connecting wires LL can be formed in various shapes to accommodate cracks, etc. For example, at least a portion of the multiple connecting wires LL arranged in the bending region BA can have a shape in which conductive patterns of at least one of the following shapes are repeatedly arranged: diamond shape, rhombus shape, trapezoidal wave shape, triangular wave shape, sawtooth wave shape, sine wave shape, circular shape, and Ω shape, but are not limited thereto.

[0074] According to an exemplary embodiment of the present disclosure, a display device can stably connect multiple connection wires LL and the wiring of the display area DA by using curved wiring BL arranged on the curved area BA.

[0075] Multiple connection lines LL can extend from multiple pad portions PAD of the second non-display area NA2 toward the curved area BA. The multiple connection lines LL can be electrically connected to the wiring of the display area DA via multiple curved lines BL, but are not necessarily limited thereto. For example, considering the connection stability between the multiple connection lines LL and the wiring of the display area DA, the multiple connection lines LL can be electrically connected to the wiring of the display area DA, and the curved lines BL can be arranged to overlap with a portion of the connection lines LL. Specifically, the multiple connection lines LL can be arranged on the curved lines BL and electrically connected to the wiring of the display area DA, and can be electrically connected to the curved lines BL in at least three areas. For example, the connection lines LL can contact the curved lines BL in the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the connection lines LL can be arranged to overlap with the curved lines BL in the first non-display area NA1, the curved area BA, and the second non-display area NA2. Therefore, even if the connection lines LL are damaged due to the bending of the display panel 10, the signal applied through the connection lines LL can still be transmitted to the wiring of the display area DA via the curved lines BL.

[0076] Therefore, by using a double arrangement of curved wiring BL and connecting wiring LL on the curved area BA, the possibility of defects caused by the curvature of the display panel 10 can be reduced. Connecting wiring LL can be a link wiring. Curved wiring BL can be a curved wiring.

[0077] The light source unit 30 can be arranged below the first substrate 110 and emit light towards the upper part of the first substrate 110 (e.g., in the Z-axis direction). The light source unit 30 can be a backlight unit.

[0078] The display panel 10 can be manufactured based on a flexible plastic material (such as polyimide) or a flexible glass substrate with a thin thickness. For example, considering the etching process, the substrate 100 of the display panel 10 can be made of a transparent glass material. For example, the display panel 10 can be manufactured based on a flexible polymer film. For example, the flexible polymer film can be made of any of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), these are merely examples and not necessarily limited to this.

[0079] refer to Figures 1 to 4 A display panel 10 according to an exemplary embodiment of the present disclosure may include: a substrate 100 including a first substrate 110 and a second substrate 120 spaced apart from and adjacent to each other by a recess G; a circuit layer 200 disposed on the substrate 100; a liquid crystal layer 300 disposed on the circuit layer 200; a pad portion PAD disposed on the second substrate 120 for connection to a circuit board 20; a bent wiring BL disposed on a planarization layer 240 extending from the circuit layer 200 to the upper portion of the recess G; and a connection wiring LL connecting the pad portion PAD and the bent wiring BL. The circuit layer 200 may include a thin-film transistor 210, a gate insulating layer 220, a first interlayer dielectric layer 230, a planarization layer 240, a first electrode 250, a second interlayer dielectric layer 260, and a second electrode 270. The thin-film transistor 210 may include a gate electrode 211, an active layer 212, a source electrode 213, and a drain electrode 214. In this configuration, the planarization layer 240 can extend through the curved region BA to a portion of the second non-display region NA2 to be disposed on the upper portion of the recess G. Therefore, when the substrate 100 is etched to form the recess G, the planarization layer 240 can serve as an etch resist layer. The first substrate 110 can be a first region of the substrate 100, and the second substrate 120 can be a second region of the substrate 100. The first region and the second region of the substrate 100 can be spaced apart from each other and disposed adjacent to each other via the recess G.

[0080] Furthermore, the display panel 10 according to an exemplary embodiment of the present disclosure may also include a pattern layer 400 disposed on a curved wiring BL.

[0081] Furthermore, the display panel 10 according to an exemplary embodiment of this disclosure may also include: a color filter layer 500 and a black matrix 600 disposed on the liquid crystal layer 300; a sealant 310 surrounding the liquid crystal layer 300; and at least one pillar 320 disposed between the color filter layer 500 and the circuit layer 200. For example, the color filter layer 500 and the black matrix 600 are disposed adjacent to each other on the liquid crystal layer 300, but are not limited thereto.

[0082] Furthermore, the display panel 10 according to an exemplary embodiment of this disclosure may also include a cover member 700 disposed on the color filter layer 500 and the black matrix 600. For example, the cover member 700 may be arranged to cover the color filter layer 500 and the black matrix 600 and overlap with the color filter layer 500 and the black matrix 600. Therefore, the cover member 700 can protect the color filter layer 500 and the black matrix 600.

[0083] Furthermore, the display panel 10 according to an exemplary embodiment of this disclosure may also include a lower polarizing layer DPOL disposed below the first substrate 110 and an upper polarizing layer UPOL disposed above the cover member 700. In such a case, the lower polarizing layer DPOL and the upper polarizing layer UPOL may overlap with the color filter layer 500, but are not limited thereto. For example, the lower polarizing layer DPOL and the upper polarizing layer UPOL may be configured to correspond to the color filter layer 500.

[0084] The substrate 100 may be made of glass, metal, plastic, etc., but is not limited to these. However, the substrate 100 may be etched using a glass substrate with a predetermined strength to simplify the process.

[0085] The following is for reference. Figures 5A to 5D The manufacturing process of a display panel according to an exemplary embodiment of the present disclosure is described.

[0086] refer to Figure 5A and Figure 5BTo form multiple display panels 10, components of the display panels 10, such as circuit layer 200, liquid crystal layer 300, pad portions PAD, bent wiring BL, and connecting wiring LL, can be arranged on a mother substrate MS. The mother substrate MS can be made of glass. In this case, multiple semi-finished panels UP, separated by a cutting process, can be formed using a single mother substrate MS. The semi-finished panels UP can represent the panels before the display panels 10 are separated, and can be implemented in the form of components of the display panels 10 arranged on the mother substrate MS. Furthermore, multiple grooves G can be formed on the lower surface side of the mother substrate MS corresponding to the grooves G of the display panels 10 by an etching process. Therefore, process optimization can be achieved by forming multiple grooves G on the lower surface side of the mother substrate MS via a single etching process. In this case, since the substrate 100 made of glass is processed by etching, the reduction in the rigidity of the glass substrate can be minimized. Therefore, the rigidity of the glass substrate can be maintained.

[0087] refer to Figure 5A The circuit layer 200, liquid crystal layer 300, pad portion PAD, bent wiring BL, connecting wiring LL, etc., can be arranged on the upper surface of a mother substrate MS. Therefore, multiple semi-finished panels UP can be formed using a single mother substrate MS.

[0088] refer to Figure 5B and Figure 5C Multiple grooves G can be formed on the mother substrate MS by etching a portion of the lower surface of the mother substrate MS using a patterned mask and an etching solution. The grooves G can be formed in a conical shape, but are not necessarily limited to this. Since multiple grooves G are formed on the mother substrate MS in a single etching process, the manufacturing process of the display panel 10 can be simplified. Phosphoric acid (HNO3), hydrofluoric acid (HF), etc., can be used as the etching solution.

[0089] For example, by using a patterned mask and an etching solution to etch a portion of the lower surface of the mother substrate MS, multiple grooves G can be formed on the lower surface side of the mother substrate MS corresponding to the grooves G of the display panel 10, but this is not the only possibility.

[0090] The gate insulating layer 220 and the first interlayer dielectric layer 230 of the circuit layer 200 disposed on the mother substrate MS can be etched by an etching solution. Therefore, a portion of the lower surface of the planarization layer 240 can be exposed through the groove G. For example, a portion of the gate insulating layer 220 and a portion of the first interlayer dielectric layer 230 of the circuit layer 200 disposed on the mother substrate MS can be etched by an etching solution, and a portion of the lower surface of the planarization layer 240 can be exposed through the etched gate insulating layer 220 and the first interlayer dielectric layer 230. Since the planarization layer 240 can be made of an organic insulating material with strong corrosion resistance to the etching solution, the planarization layer 240 serves as an etching stop layer, stopping the etching process when the etching solution reaches the planarization layer 240.

[0091] The groove G can be formed through an etching process, reaching the planarization layer 240. The gate insulating layer 220 and the first interlayer dielectric layer 230 of the circuit layer 200 disposed on the mother substrate MS can be removed together with the mother substrate MS through the groove G. For example, the gate insulating layer 220 and the first interlayer dielectric layer 230 of the circuit layer 200 can be disposed in the first non-display area NA1 and the second non-display area NA2. The groove G can be arranged to correspond to the curved area BA of the display panel 10. Since the gate insulating layer 220 and the first interlayer dielectric layer 230 are not disposed on the groove G, damage such as cracks caused by stress due to bending will not occur in the gate insulating layer 220 and the first interlayer dielectric layer 230. For example, even if the gate insulating layer 220 and the first interlayer dielectric layer 230 are made of a flexible inorganic insulating material, since the gate insulating layer 220 and the first interlayer dielectric layer 230 are not disposed in the bending region BA, the gate insulating layer 220 and the first interlayer dielectric layer 230 will not be damaged by the stress caused by bending. Furthermore, since the second interlayer dielectric layer 260, made of an inorganic insulating material, is also not disposed in the bending region BA, the second interlayer dielectric layer 260 will not be damaged by the stress caused by bending.

[0092] refer to Figure 5D Multiple display panels 10 can be separated by performing a cutting process along the cutting line CL.

[0093] The groove G can be formed in the substrate 100 by an etching process, and the substrate 100 can be divided into a first substrate 110 and a second substrate 120 by the groove G. For example, the groove G can be disposed between the first substrate 110 and the second substrate 120.

[0094] The first substrate 110 may include a display area DA and a first non-display area NA1, and may be made of a transparent glass material.

[0095] refer to Figure 10The first substrate 110 may include a first upper surface 111 in contact with the circuit layer 200, a first lower surface 112 serving as the opposing surface of the first upper surface 111, and a first side surface 113 connecting the first upper surface 111 and the first lower surface 112. The first substrate 110 may include a first upper edge UE1 where the first upper surface 111 and the first side surface 113 meet, and a first lower edge DE1 where the first lower surface 112 and the first side surface 113 meet. The first side surface 113 may be an inclined surface with a predetermined slope relative to the first lower surface 112. Since the first side surface 113 is formed by an etching process, a curved surface may be formed at the first lower edge DE1 where the first lower surface 112 and the first side surface 113 meet.

[0096] The second substrate 120 can be arranged in the second non-display area NA2 and can be made of transparent glass material.

[0097] The second substrate 120 may include a second upper surface 121 in contact with the gate insulating layer 220, a second lower surface 122 serving as the opposing surface of the second upper surface 121, and a second side surface 123 connecting the second upper surface 121 and the second lower surface 122. The second substrate 120 may include a second upper edge UE2 where the second upper surface 121 and the second side surface 123 meet, and a second lower edge DE2 where the second lower surface 122 and the second side surface 123 meet. The second side surface 123 may be an inclined surface with a predetermined slope relative to the second lower surface 122. Since the second side surface 123 is formed by an etching process, a curved surface can be formed at the second lower edge DE2 where the second lower surface 122 and the second side surface 123 meet.

[0098] The circuit layer 200 can be disposed in the display area DA, and some components of the circuit layer 200 can be disposed in one or more of the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the circuit layer 200 can be disposed on the first upper surface 111 of the first substrate 110, and some components of the circuit layer 200 can extend through the first non-display area NA1 and the curved area BA to the second non-display area NA2. For example, the gate insulating layer 220 and the first interlayer dielectric layer 230 of the circuit layer 200 can be disposed in the first non-display area NA1 and the second non-display area NA2. For example, the gate insulating layer 220 and the first interlayer dielectric layer 230 of the circuit layer 200 can be removed from the curved area BA, but are not limited thereto. In addition, the planarization layer 240 of the circuit layer 200 can be disposed in a portion of the first non-display area NA1, the curved area BA, and the second non-display area NA2. In addition, the second interlayer dielectric layer 260 can be disposed in the first non-display area NA1 and the second non-display area NA2. For example, the second interlayer dielectric layer 260 can be removed from the bending region BA, but is not limited thereto.

[0099] refer to Figure 7 The circuit layer 200 may include, but is not limited to, a thin-film transistor 210, a gate insulating layer 220 covering the gate electrode 211 of the thin-film transistor 210, an active layer 212 covering the thin-film transistor 210, a first interlayer dielectric layer 230 covering the source electrode 213 and the drain electrode 214, a planarization layer 240 disposed on the first interlayer dielectric layer 230, a first electrode 250 disposed on the planarization layer 240, a second interlayer dielectric layer 260 disposed on the first electrode 250, and a second electrode 270 disposed on the second interlayer dielectric layer 260. It may include more or fewer layers.

[0100] The thin-film transistor 210 may include a gate electrode 211, an active layer 212, a source electrode 213, and a drain electrode 214.

[0101] The gate electrode 211 can be arranged on the first upper surface 111 of the first substrate 110.

[0102] The gate electrode 211 can be made of a conductive material. For example, the gate electrode 211 can be made of a metallic material. For example, the gate electrode 211 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0103] The first pad layer PAD2a of the second pad portion PAD2 can be arranged on the second upper surface 121 of the second substrate 120.

[0104] The first pad layer PAD2a can be made of a conductive material. For example, the first pad layer PAD2a can be made of a metallic material. For example, the gate electrode 211 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0105] Furthermore, the first pad layer PAD2a can be formed together with the gate electrode 211 using the same masking process used to form the gate electrode 211. For example, the first pad layer PAD2a on the second upper surface 121 of the second substrate 120 can be formed together with the gate electrode 211 on the first upper surface 111 of the first substrate 110 using the same masking process used to form the gate electrode 211, but is not limited thereto.

[0106] The gate insulating layer 220 can be disposed on the substrate 100 and etched into the display area DA, the first non-display area NA1, and the second non-display area NA2 by an etching process. For example, the gate insulating layer 220 can be disposed on the first substrate 110 to cover the gate electrode 211. The gate insulating layer 220 can also be disposed on the second substrate 120 to cover the first pad layer PAD2a of the second pad portion PAD2.

[0107] Since the gate insulating layer 220 can be made of inorganic insulating material, it can be etched by an etching process. Therefore, the gate insulating layer 220 can be separated into a gate insulating layer 220 disposed on the first substrate 110 and a gate insulating layer 220 disposed on the second substrate 120.

[0108] The gate insulating layer 220 can be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x The gate insulating layer 220 is made of inorganic insulating material. It can be a single layer or multiple layers made of inorganic insulating material, but is not limited thereto.

[0109] The active layer 212 can be disposed on the gate insulating layer 220 disposed on the first substrate 110. For example, the active layer 212 can be configured to cover the portion of the gate insulating layer 220 disposed on the first substrate 110. The active layer 212 can overlap with the first substrate 110. Furthermore, the active layer 212 can overlap with the gate electrode 211 in the Z-axis direction.

[0110] The active layer 212 can be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), oxide semiconductor, organic semiconductor, etc., but is not necessarily limited to these.

[0111] The first pad portion PAD1 can be disposed on the gate insulating layer 220 disposed on the second substrate 120. For example, the first pad portion PAD1 can overlap with the second substrate 120. In addition, the gate insulating layer 220 can be disposed between the second substrate 120 and the first pad portion PAD1.

[0112] The first pad portion PAD1 can be made of a conductive material. For example, the first pad portion PAD1 can be made of a metallic material. For example, the first pad portion PAD1 can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0113] The first pad portion PAD1 can be electrically connected to a chip (not shown) disposed on the first pad portion PAD1. For example, the first pad portion PAD1 can be electrically connected to the chip (not shown) via connection wiring LL disposed on the first pad portion PAD1. As an example, the first pad portion PAD1 is connected to the chip (not shown) via connection wiring LL, but is not necessarily limited thereto. For example, the first pad portion PAD1 can also be directly connected to the chip (not shown) without connection wiring LL. The chip may include driving circuitry. The connection wiring LL disposed on the first pad portion PAD1 can be a second connection wiring LL2.

[0114] For example, the source electrode 213 and drain electrode 214 of the thin-film transistor 210 can be disposed on the active layer 212.

[0115] Furthermore, the first pad portion PAD1 can be formed together with the source electrode 213 and the drain electrode 214 using the same mask process used to form the source electrode 213 and the drain electrode 214, but is not limited thereto.

[0116] The second pad layer PAD2b of the second pad portion PAD2 can be disposed on the gate insulating layer 220 disposed on the second substrate 120. For example, a portion of the second pad layer PAD2b can be disposed on the gate insulating layer 220. Furthermore, the second pad layer PAD2b can be electrically connected to the first pad layer PAD2a via contact holes formed in the gate insulating layer 220. Therefore, the second pad layer PAD2b of the second pad portion PAD2 can be disposed on and electrically connected to the first pad layer PAD2a. For example, the second pad layer PAD2b of the second pad portion PAD2 can be disposed on the portion of the gate insulating layer 220 and the first pad layer PAD2a exposed by contact holes formed in the gate insulating layer 220.

[0117] The second pad layer PAD2b can be made of a conductive material. For example, the second pad layer PAD2b can be made of a metallic material. For example, the second pad layer PAD2b can include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0118] Furthermore, the second pad layer PAD2b can be formed together with the source electrode 213 and the drain electrode 214 using the same mask process as the source electrode 213 and the drain electrode 214, but is not limited thereto.

[0119] Furthermore, the second pad layer PAD2b can be electrically connected to the circuit board 20. For example, the second pad layer PAD2b can be connected to the circuit board 20 via connection wiring LL disposed on the second pad layer PAD2b. The connection wiring LL disposed on the second pad layer PAD2b can be a second connection wiring LL2.

[0120] The source electrode 213 can be disposed on the active layer 212. For example, the source electrode 213 can be located in a different layer than the gate electrode 211. The source electrode 213 can be insulated from the gate electrode 211 through the gate insulating layer 220.

[0121] The source electrode 213 can be electrically connected to the source region of the active layer 212, and the source electrode 213 can include a region overlapping with the source region of the active layer 212. For example, the source electrode 213 can be in direct contact with the source region of the active layer 212.

[0122] The source electrode 213 may include a conductive material. For example, the source electrode 213 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0123] Drain electrode 214 can be disposed on active layer 212. For example, drain electrode 214 can be located in a different layer than gate electrode 211. Drain electrode 214 can be insulated from gate electrode 211 through gate insulating layer 220. Drain electrode 214 can be disposed in the same layer as source electrode 213. Drain electrode 214 can be disposed spaced apart from source electrode 213.

[0124] The drain electrode 214 can be electrically connected to the drain region of the active layer 212, and the drain electrode 214 can include a region overlapping with the drain region of the active layer 212. For example, the drain electrode 214 can be in direct contact with the drain region of the active layer 212.

[0125] The drain electrode 214 may include a conductive material. For example, the drain electrode 214 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0126] The first interlayer dielectric layer 230 disposed on the substrate 100 can be disposed on the display area DA, the first non-display area NA1, and the second non-display area NA2 by being etched first through an etching process. For example, the first interlayer dielectric layer 230 can be disposed on the first substrate 110 to cover the gate electrode 211, etc. Furthermore, the first interlayer dielectric layer 230 can be disposed on the second substrate 120 to cover the second pad layer PAD2b and the first pad layer PAD1 of the second pad portion PAD2. For example, the first interlayer dielectric layer 230 can be disposed on the source electrode 213 and the drain electrode 214.

[0127] For example, the first interlayer dielectric layer 230 can be disposed on the first substrate 110 to cover the active layer 212, the source electrode 213, and the drain electrode 214. The first interlayer dielectric layer 230 can also be disposed on the second substrate 120 to cover the second pad layer PAD2b and the first pad layer PAD1 of the second pad portion PAD2.

[0128] The first interlayer dielectric layer 230 can be disposed on the active layer 212, the source electrode 213, and the drain electrode 214. In this case, the first interlayer dielectric layer 230 can cover the active layer 212, the source electrode 213, and the drain electrode 214 on the first substrate 110. Therefore, the first interlayer dielectric layer 230 can protect the active layer 212, the source electrode 213, and the drain electrode 214.

[0129] Furthermore, the first interlayer dielectric layer 230 can be disposed on the second pad layer PAD2b and the first pad layer PAD1 of the second pad portion PAD2. In this case, the first interlayer dielectric layer 230 can cover a portion of the first pad portion PAD1 and a portion of the second pad layer PAD2b on the second substrate 120. Therefore, the first interlayer dielectric layer 230 can protect a portion of the first pad portion PAD1 and a portion of the second pad layer PAD2b.

[0130] The first interlayer dielectric layer 230 can be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x The first interlayer dielectric layer 230 can be a single layer or multiple layers made of inorganic insulating material, but is not limited thereto.

[0131] The planarization layer 240 can be disposed on the first interlayer dielectric layer 230. In this case, the planarization layer 240 of the circuit layer 200 can extend through the bending region BA to a portion of the second non-display region NA2 to be disposed on the upper portion of the recess G. Therefore, the planarization layer 240 can overlap with the second substrate 120 in the second non-display region NA2. For example, the planarization layer 240 can overlap with the first substrate 110 in the first non-display region NA1.

[0132] When the substrate 100 is etched to form the groove G, the planarization layer 240 is made of an organic insulating material and serves as an anti-etching layer, thereby protecting the curved wiring BL arranged on the planarization layer 240 from the effects of the etching solution.

[0133] The planarization layer 240 can be disposed on the recess G. For example, since the planarization layer 240 can extend through the first non-display area NA1 and the curved area BA to a portion of the second non-display area NA2, the planarization layer 240 can cover the upper portion of the recess G. Therefore, the display device according to an exemplary embodiment of the present disclosure does not require a separate etch-resistant layer covering the upper portion of the recess G, thereby improving process productivity.

[0134] The planarization layer 240 can be made of a transparent organic insulating material. For example, the planarization layer 240 can be made of one or more materials selected from, but not limited to, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene. The planarization layer 240 can be a single layer or multiple layers made of organic insulating material.

[0135] Furthermore, since the planarization layer 240 is made of an organic insulating material that has relatively superior ductility compared to inorganic insulating materials, it can easily withstand bending of the display panel 10. For example, since the planarization layer 240 can be disposed in the bending region BA and is made of an organic insulating material with good ductility, the planarization layer 240 can be easily bent without damage (such as cracking).

[0136] The first electrode 250 can be disposed on the planarization layer 240. The first electrode 250 can be a common electrode.

[0137] The first electrode 250 can be made of a transparent conductive material or an opaque conductive material. For example, the first electrode 250 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other conductive materials.

[0138] A voltage can be applied to the first electrode 250 and the second electrode 270. Therefore, the liquid crystal layer 300 can be driven to display an image. In this case, a voltage can be applied to the second electrode 270 through the drain electrode 214.

[0139] The curved wiring BL can be disposed on the planarization layer 240. In this case, the curved wiring BL can be disposed in the first non-display area NA1, the curved area BA, and the second non-display area NA2. As an example, the curved wiring BL can be disposed in a portion of the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the curved wiring BL can be disposed on the planarization layer 240 disposed in the first non-display area NA1, the curved area BA, and the second non-display area NA2.

[0140] The curved wiring BL can be formed to have a predetermined first length L1 in the Y-axis direction. The curved wiring BL can overlap with the groove G in the Z-axis direction, and the first length L1 of the curved wiring BL in the Y-axis direction can be greater than the width W1 of the groove G. The first length L1 of the curved wiring BL in the Y-axis direction can be greater than the width W2 of the pattern layer 400. The width W1 of the groove G can be a first width, and the width W2 of the pattern layer 400 can be a second width.

[0141] The bent wiring BL can be made of conductive materials. For example, the bent wiring BL can be made of metallic materials. For example, the bent wiring BL can be a single layer or multiple layers made of one of indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but is not limited thereto. For example, the bent wiring BL can be formed into a double-layer structure.

[0142] The bent wiring BL comprises at least two layers with different materials. For example, the bent wiring BL may include a first layer BL1 and a second layer BL2. The materials of the first layer BL1 and the second layer BL2 may be different from each other. Therefore, the bent wiring BL can easily cope with the stress caused by bending. For example, the bent wiring BL may be arranged on the planarization layer 240.

[0143] In the curved wiring BL, at least one of the first layer BL1 and the second layer BL2 may include, but is not limited to, the same metal layer as the first electrode 250.

[0144] Furthermore, the first layer BL1 and the second layer BL2 of the curved wiring BL can be made of a different material than the first electrode 250.

[0145] The first layer BL1 can be disposed on the planarization layer 240. The first layer BL1 can be made of transparent indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the first layer BL1 can include the same material as the first electrode 250, and can be formed together with the first electrode 250 by the same masking process used to form the first electrode 250, but is not limited thereto.

[0146] The second layer BL2 can be arranged on top of the first layer BL1. Based on the Y-axis direction, the second layer BL2 can have the same length as the first layer BL1. For example, the first layer BL1 and the second layer BL2 can be formed to have a predetermined first length L1 in the Y-axis direction.

[0147] The second layer BL2 can be made of a different material than the first layer BL1. For example, the second layer BL2 can be made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the second layer BL2 may include copper (Cu).

[0148] Furthermore, the bent wiring BL can include a material different from that of the connecting wiring LL. For example, since the connecting wiring LL can be made of indium tin oxide (ITO) or indium zinc oxide (IZO) and the second layer BL2 of the bent wiring BL can be made of copper, the bent wiring BL can include a material different from that of the connecting wiring LL.

[0149] Therefore, because the first connecting wire LL1 and the second connecting wire LL2 are connected via the bent wire BL, the display device according to an exemplary embodiment of the present disclosure can easily cope with stress caused by bending. Furthermore, since the bent wire BL comprises at least two layers of different materials, it can cope with stress caused by bending more effectively.

[0150] The second interlayer dielectric layer 260 can be disposed on the first electrode 250 and the bent wiring BL. For example, the second interlayer dielectric layer 260 can be disposed on the planarization layer 240 to cover the first electrode 250 and the bent wiring BL. In such a case, the second interlayer dielectric layer 260 can be disposed in the display area DA, the first non-display area NA1, and the second non-display area NA2. For example, the second interlayer dielectric layer 260 can be disposed in the bent area BA. The second interlayer dielectric layer 260 can be disposed in the first non-display area NA1 between the first connection wiring LL1 and the bent wiring BL based on the Z-axis direction.

[0151] In the second non-display area NA2, the second interlayer dielectric layer 260 can be arranged between the curved wiring BL and the second connection wiring LL2.

[0152] The second interlayer dielectric layer 260 can be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x The second interlayer dielectric layer 260 is made of inorganic insulating material. It can be a single layer or multiple layers made of inorganic insulating material, but is not limited thereto.

[0153] The second electrode 270 can be disposed on the second interlayer dielectric layer 260. The second electrode 270 can be electrically connected to the drain electrode 214 through contact holes formed in the planarization layer 240 and the second interlayer dielectric layer 260. The second electrode 270 can be a pixel electrode. For example, the second electrode 270 can be disposed on the second interlayer dielectric layer 260 in the display area DA.

[0154] The second electrode 270 can be made of a transparent conductive material or an opaque conductive material. For example, the second electrode 270 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other conductive materials.

[0155] Connection wiring LL can be arranged on the second interlayer dielectric layer 260. For example, multiple connection wiring LL can be arranged on the second interlayer dielectric layer 260 to transmit signals applied from the circuit board 20 to the display area DA. In such a case, multiple connection wiring LL can be connected to the first pad portion PAD1 and the second pad portion PAD2 through contact holes formed in the first interlayer dielectric layer 230, the planarization layer 240 and the second interlayer dielectric layer 260, or formed in the first interlayer dielectric layer 230 and the second interlayer dielectric layer 260. For example, connection wiring LL can be arranged on the second interlayer dielectric layer 260 in the first non-display area NA1 and the second non-display area NA2.

[0156] The connecting wiring LL can be made of a transparent conductive material or an opaque conductive material. For example, the second electrode 270 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other conductive materials.

[0157] The connecting wiring LL can be formed together with the second electrode 270 using the same masking process used to form the second electrode 270, but is not limited to this.

[0158] The connecting wiring LL may include a first connecting wiring LL1 and a second connecting wiring LL2 arranged spaced apart from each other. The first connecting wiring LL1 and the second connecting wiring LL2 may be electrically connected via a curved wiring BL. For example, the pattern layer 400 may be arranged between the first connecting wiring LL1 and the second connecting wiring LL2 based on the Y-axis direction. For example, the pattern layer 400 may be arranged on the curved wiring BL between the first connecting wiring LL1 and the second connecting wiring LL2. For example, the connecting wiring LL including the first connecting wiring LL1 and the second connecting wiring LL2 may not be provided in the curved region BA. In such a case, the curved wiring BL arranged below the pattern layer 400 may be electrically connected to the first connecting wiring LL1 through a first contact hole CH1 and to the second connecting wiring LL2 through a second contact hole CH2. Therefore, the first connecting wiring LL1 may contact one side of the curved wiring BL, and the second connecting wiring LL2 may contact the other side of the curved wiring BL. The first contact hole CH1 may be arranged in a first non-display region NA1. The first contact hole CH1 may be formed to penetrate a second interlayer dielectric layer 260 arranged between the curved wiring BL and the first connecting wiring LL1. The second contact hole CH2 can be disposed in the second non-display area NA2. The second contact hole CH2 can be formed to penetrate the second interlayer dielectric layer 260 disposed between the curved wiring BL and the second connection wiring LL2.

[0159] The first connection wiring LL1 can be arranged in the first non-display area NA1. For example, the first connection wiring LL1 can be arranged on the second interlayer dielectric layer 260 of the first non-display area NA1. In addition, the first connection wiring LL1 can be electrically connected to the bent wiring BL in the first non-display area NA1 through the first contact hole CH1.

[0160] The second connection wiring LL2 can be disposed in the second non-display area NA2. For example, the second connection wiring LL2 can be disposed on the second interlayer dielectric layer 260 of the second non-display area NA2. The second connection wiring LL2 can be electrically connected to the bent wiring BL in the second non-display area NA2 through the second contact hole CH2.

[0161] In this case, the curved wiring BL arranged below the pattern layer 400 can be electrically connected to the first connecting wiring LL1 in the first non-display area NA1 through the first contact hole CH1, and can be electrically connected to the second connecting wiring LL2 in the second non-display area NA2 through the second contact hole CH2.

[0162] The liquid crystal layer 300 may be disposed on the second interlayer dielectric layer 260, the second electrode 270, and the first connection wiring LL1, and may include an alignment film (not shown) for easily inducing liquid crystal alignment. For example, the liquid crystal layer 300 may be disposed on the second interlayer dielectric layer 260, the second electrode 270, and the first connection wiring LL1 in the display area DA and the first non-display area NA1, but is not limited thereto.

[0163] The sealant 310 may surround the liquid crystal layer 300. For example, the sealant 310 may be disposed along the periphery of the liquid crystal layer 300.

[0164] refer to Figure 3 The sealant 310 can be disposed on the second interlayer dielectric layer 260. For example, the sealant 310 can be disposed between the second interlayer dielectric layer 260 and the black matrix 600 based on the Z-axis direction. Furthermore, the sealant 310 can contact the second interlayer dielectric layer 260, but is not necessarily limited to this. For example, the sealant 310 can also contact the connection wiring LL disposed on the second interlayer dielectric layer 260. In such a case, the sealant 310 can overlap with the curved wiring BL in the Z-axis direction.

[0165] The sealant 310 can be a photocurable or thermocurable epoxy resin. The sealant 310 can form a gap between the second interlayer dielectric layer 260 and the black matrix 600 for liquid crystal injection. The sealant 310 can play a role in preventing leakage of liquid crystal injected into the gap.

[0166] refer to Figure 3 At least one pillar 320 may be disposed on the second interlayer dielectric layer 260. For example, the pillar 320 may be disposed between the second interlayer dielectric layer 260 and the color filter layer 500 based on the Z-axis direction. Thus, the pillar 320 can maintain a gap for liquid crystal injection.

[0167] For example, sealant 310 can be disposed in the first non-display area NA1 between the second interlayer dielectric layer 260 and the black matrix 600 based on the Z-axis direction. For example, pillar 320 can be disposed in the display area DA between the second interlayer dielectric layer 260 and the color filter layer 500.

[0168] The column 320 may include a first column portion 321 and a second column portion 322, but is not limited thereto.

[0169] The first pillar 321 can be disposed on the second interlayer dielectric layer 260. The first pillar 321 can be in contact with the second interlayer dielectric layer 260.

[0170] The first pillar portion 321 may be made of an organic insulating material and may be formed together with the pattern layer 400 by the same masking process used to form the pattern layer 400, but is not limited thereto.

[0171] The second column portion 322 can be arranged on the first column portion 321 and can overlap with the first column portion 321. The second column portion 322 can be disposed between the first column portion 321 and the color filter layer 500. The second column portion 322 can contact the color filter layer 500.

[0172] The second column 322 can be made of organic insulating material.

[0173] Pattern layer 400 can be disposed on the curved wiring BL. Therefore, pattern layer 400 can protect the curved wiring BL from physical and / or chemical impacts. For example, pattern layer 400 can prevent moisture, impurities, etc. from penetrating into the curved wiring BL. For example, pattern layer 400 can be disposed on the curved wiring BL in the curved region BA.

[0174] The pattern layer 400 can be arranged in the curved region BA, and the pattern layer 400 can also bend as the curved region BA bends. The pattern layer 400 can overlap with the groove G.

[0175] The pattern layer 400 can be made of an organic insulating material to withstand stress caused by bending. For example, the pattern layer 400 can be made of organic materials including polyester polymers, acrylic polymers, etc.

[0176] refer to Figures 1 to 4 The pattern layer 400 can be configured as a structure with a predetermined width W2 and height H, and can be arranged along the X-axis direction. For example, the pattern layer 400 can be formed as a strip including a trapezoidal cross section, but is not limited thereto.

[0177] The pattern layer 400 may be formed with a predetermined width W2, and the width W2 of the pattern layer 400 may be the same as the width W1 of the groove G, but is not necessarily limited to this. For example, the width W2 of the pattern layer 400 may be greater than the width W1 of the groove G. In addition, the width W2 of the pattern layer 400 may be less than the first length L1 of the curved wiring BL.

[0178] The pattern layer 400 can be formed to have a predetermined height H. The height H of the pattern layer 400 can be adjusted. Therefore, the display panel 10 according to an exemplary embodiment of the present disclosure can minimize the stress applied to the curved wiring BL by adjusting the height H of the pattern layer 400.

[0179] Figure 6 This is a diagram illustrating the relationship between the curved neutral plane and the curve.

[0180] refer to Figure 6The neutral plane can be defined as the plane where the stress state is zero during bending, and the magnitude of the tensile or compressive stress is determined proportionally to the distance from the neutral plane. The neutral plane can be based on its center in the Z-direction between the planes applying tensile stress and the planes applying compressive stress. The plane applying compressive stress can be defined as a plane located close to the center of curvature, and the plane applying tensile stress can be defined as the plane opposite to the plane applying compressive stress. For example, the plane applying tensile stress can be defined as a plane located away from the center of curvature.

[0181] Furthermore, cracks are more likely to occur in a structure placed in a region subjected to tensile stress than in a structure placed in a region subjected to compressive stress. For example, since the curved wiring BL arranged in the curved region BA of the display panel 10 can be placed in a region subjected to tensile stress, the likelihood of cracks occurring in the curved wiring BL is relatively high due to the bending of the curved region BA. Therefore, since cracks are more likely to occur in a region subjected to tensile stress than in a region subjected to compressive stress during bending, the stress applied to the curved wiring BL can be minimized by moving the neutral plane closer to the curved wiring BL.

[0182] Therefore, when the pattern layer 400 is arranged on the curved wiring BL (see...) Figure 3 According to an exemplary embodiment of the present disclosure, a display device can, with the thickness from the pattern layer 400 to the curved wiring BL determined, position a neutral plane on the curved wiring BL or move the neutral plane closer to the curved wiring BL by adjusting the height H of the pattern layer 400. Therefore, the display panel 10 can reduce the stress applied to the curved wiring BL during bending of the display panel 10 by using the pattern layer 400.

[0183] The color filter layer 500 can be disposed on the liquid crystal layer 300. In this case, the color filter layer 500 can be disposed in the display area DA. The black matrix 600 can be disposed in the first non-display area NA1. Furthermore, the color filter layer 500 and the black matrix 600 can be formed on the same layer. For example, the color filter layer 500 and the black matrix 600 can be disposed adjacent to each other.

[0184] The color filter layer 500 may include, but is not limited to, red, green, and blue color filters. For example, the color filter layer 500 may include acrylic resin and pigments. The color filter layer 500 may be classified as red, green, and blue according to the type of pigment that achieves the color.

[0185] The black matrix 600 can be arranged in the first non-display area NA1 and can be arranged on the liquid crystal layer 300 and the sealant 310.

[0186] Furthermore, the black matrix 600 can have a closed-loop shape surrounding the display area DA. Therefore, the black matrix 600 can prevent light leakage. In this case, the black matrix 600 can overlap with the color filter layer 500 in both the X-axis and Y-axis directions.

[0187] The cover member 700 can be disposed on the color filter layer 500 and the black matrix 600. For example, the cover member 700 can be arranged to cover the color filter layer 500 and the black matrix 600 and overlap with the color filter layer 500 and the black matrix 600. Therefore, the cover member 700 can protect the color filter layer 500 and the black matrix 600.

[0188] The end of the cover member 700 may protrude further than the black matrix 600 in the Y-axis direction, but is not necessarily limited to this. For example, the end of the cover member 700 may also be arranged to overlap with the end of the black matrix 600 in the Z-axis direction.

[0189] The cover component 700 may be made of transparent plastic material, glass material or tempered glass material, but is not limited to these.

[0190] The upper polarizing layer UPOL can be disposed on the cover member 700. The upper polarizing layer UPOL can overlap with the color filter layer 500 and can be disposed in the display area DA. For example, the upper polarizing layer UPOL can be disposed on a portion of the cover member 700 in the display area DA.

[0191] The lower polarizing layer DPOL can be disposed below the first substrate 110. For example, the lower polarizing layer DPOL can be attached to the underside of the first substrate 110 by an adhesive member. For example, the lower polarizing layer DPOL can overlap with the color filter layer 500 and can be disposed in the display area DA.

[0192] Figure 7 This is a diagram illustrating a coating layer arranged on a display panel according to an exemplary embodiment of the present disclosure.

[0193] refer to Figure 7 According to an exemplary embodiment of the present disclosure, the display panel 10 may further include a coating layer 800 disposed in a groove G.

[0194] The coating layer 800 may be disposed below the planarization layer 240 to overlap a portion of the curved wiring BL. The lower surface 810 of the coating layer 800 may be formed recessed toward the planarization layer 240, but is not necessarily limited thereto. For example, the lower surface 810 of the coating layer 800 may also be substantially flat.

[0195] The coating layer 800 may be made of organic materials, including, but not limited to, polyester-based polymers or acrylic-based polymers.

[0196] Taking into account the location of the neutral plane, the coating layer 800 can be formed to have a predetermined thickness T.

[0197] According to an exemplary embodiment of the present disclosure, the thickness T of the coating layer 800 can be adjusted while the thickness from the planarization layer 240 to the curved wiring BL or from the planarization layer 240 to the pattern layer 400 is determined. Therefore, the position of the neutral plane can be located on or near the curved wiring BL. Thus, the display panel 10 can reduce the stress applied to the curved wiring BL during bending by using the coating layer 800.

[0198] Figure 8 This is a diagram illustrating the curved appearance of a display device according to an exemplary embodiment of the present disclosure.

[0199] refer to Figure 8 According to an exemplary embodiment of the present disclosure, the display panel 10 of the display device can be bent. For example, as the bending region BA is bent, the display panel 10 can be bent such that the first substrate 110 and the second substrate 120 face each other. In such a case, the bending region BA can be bent to have a predetermined radius of curvature.

[0200] Since the gate insulating layer 220, the first interlayer dielectric layer 230, and the second interlayer dielectric layer 260, which are made of inorganic insulating materials, are not arranged in the bending region BA of the display panel 10 according to an exemplary embodiment of the present disclosure, damage to the gate insulating layer 220, the first interlayer dielectric layer 230, and the second interlayer dielectric layer 260 due to bending can be prevented in advance.

[0201] As the bending region BA is bent, the light source unit 30 can be arranged between the first substrate 110 and the second substrate 120. The light source unit 30 can emit light toward the first substrate 110. Therefore, the light source unit 30 can overlap with the first substrate 110 in the Z-axis direction. In addition, the light source unit 30 can overlap with the second substrate 120 in the Z-axis direction.

[0202] The light source unit 30 may include a backlight unit 31 and a housing 32 surrounding the light source module.

[0203] The backlight unit 31 can emit light toward the first substrate 110. The light source for the backlight unit 31 can be a light-emitting diode (LED), but is not necessarily limited to it.

[0204] The housing 32 may be arranged to surround the backlight unit 31 to protect the backlight unit 31. Furthermore, the housing 32 may include an opening OP that allows light to be emitted from the backlight unit 31 toward the first substrate 110. For example, the side of the housing 32 facing the first substrate 110 may include an opening OP that allows light to be emitted from the backlight unit 31 toward the first substrate 110, but is not limited thereto.

[0205] The opening OP can be arranged facing the first substrate 110. In addition, the lower polarizing layer DPOL can be arranged in the opening OP.

[0206] Figure 9 This is a cross-sectional view illustrating another embodiment of a display panel according to an exemplary embodiment of the present disclosure. Figure 10 It is shown Figure 9 A magnified view of region B in the image. Figure 11 This is a diagram illustrating the curved appearance of a display device that applies a display panel according to one exemplary embodiment of the present disclosure. Figures 9 to 11 The display panel 10a shown may be a display panel according to the second embodiment. Figure 3 , Figure 7 and Figure 8 The display panel 10 shown may be a display panel according to the first embodiment.

[0207] When reference Figure 3 and Figures 7 to 11 When comparing the display panel 10 according to the first embodiment and the display panel 10a according to the second embodiment, the display panel 10 according to the first embodiment uses two first connecting wires LL1 and second connecting wires LL2 arranged spaced apart from each other, with the pattern layer 400 interposed between them. However, since the display panel 10a according to the second embodiment uses only one connecting wire LL, the connecting wire LL can overlap with the curved wire BL in the curved region BA. For example, the connecting wire LL of the display panel 10a according to the second embodiment extends through the first non-display region NA1 and the curved region BA to the second non-display region NA2, and can be arranged on the curved wire BL in the curved region BA. Therefore, the connecting wire LL can contact the curved wire BL in the curved region BA. In such a case, the display panel 10a according to the second embodiment can be applied to a display device according to an exemplary embodiment of the present disclosure, instead of the display panel 10 according to the first embodiment.

[0208] Reference Figure 3 and Figures 7 to 11 When describing the display panel 10a according to the second embodiment, since the display panel 10 according to the first embodiment (for example, see...) Figure 7 and Figure 8(and other accompanying drawings) and the display panel 10a according to the second embodiment (for example, see...) Figures 9 to 11 Components substantially identical to those in other figures can be denoted by the same reference numerals, so their detailed descriptions are omitted. Detailed descriptions provided for elements in one or more figures may also be applied to elements in other figures using the same reference numerals.

[0209] refer to Figures 9 to 11 A display device according to an exemplary embodiment of the present disclosure may include: a display panel 10a, which includes a recess G; a circuit board 20 connected to a pad portion PAD of the display panel 10a; and a light source unit 30 that emits light toward a liquid crystal layer 300 of the display panel 10a.

[0210] A display panel 10a according to an exemplary embodiment of the present disclosure may include: a substrate 100 including a first substrate 110 and a second substrate 120 spaced apart from and adjacent to each other by a recess G; a circuit layer 200 disposed on the substrate 100; a liquid crystal layer 300 disposed on the circuit layer 200; a pad portion PAD disposed on the second substrate 120 for connection to a circuit board 20; a bent wiring BL disposed on a planarization layer 240 extending from the circuit layer 200 to the upper portion of the recess G; and a connection wiring LL connecting the pad portion PAD and the bent wiring BL. The circuit layer 200 may include a thin-film transistor 210, a gate insulating layer 220, a first interlayer dielectric layer 230, a planarization layer 240, a first electrode 250, a second interlayer dielectric layer 260, and a second electrode 270. The thin-film transistor 210 may include a gate electrode 211, an active layer 212, a source electrode 213, and a drain electrode 214. In this configuration, the planarization layer 240 can extend through the curved region BA to a portion of the second non-display region NA2 to be disposed on the upper portion of the recess G. Therefore, when the substrate 100 is etched to form the recess G, the planarization layer 240 can serve as an etch resist layer. The first substrate 110 can be a first region of the substrate 100, and the second substrate 120 can be a second region of the substrate 100. The first region and the second region of the substrate 100 can be spaced apart from each other and disposed adjacent to each other via the recess G.

[0211] Furthermore, a display panel 10a according to an exemplary embodiment of this disclosure may further include: a pattern layer 400 disposed on curved wiring BL; a color filter layer 500 and a black matrix 600 disposed on a liquid crystal layer 300; a sealant 310 surrounding the liquid crystal layer 300; at least one pillar 320 disposed between the color filter layer 500 and the circuit layer 200; a cover member 700 disposed on the color filter layer 500 and the black matrix 600; a lower polarizing layer DPOL disposed below the first substrate 110; and an upper polarizing layer UPOL disposed above the cover member 700. In such a case, the lower polarizing layer DPOL and the upper polarizing layer UPOL may overlap with the color filter layer 500, but are not limited thereto. For example, the lower polarizing layer DPOL and the upper polarizing layer UPOL may be configured to correspond to the color filter layer 500. In addition, the cover member 700 may protect the color filter layer 500 and the black matrix 600.

[0212] Furthermore, a display panel 10a according to an exemplary embodiment of the present disclosure may also include a coating layer 800 disposed in a groove G.

[0213] The connecting cable LL can be arranged in the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the connecting cable LL can be arranged to extend from the first non-display area NA1 to the second non-display area NA2. For example, the connecting cable LL can be arranged to extend from the first non-display area NA1 to the second non-display area NA2 through the curved area BA.

[0214] The connecting wire LL can be arranged to contact the curved wire BL in the curved region BA. Furthermore, the pattern layer 400 can be disposed on the connecting wire LL. Therefore, the connecting wire LL can protect the curved wire BL. For example, a display panel 10a according to an exemplary embodiment of this disclosure can protect the curved wire BL by disposing a portion of the connecting wire LL between the curved wire BL and the pattern layer 400. For example, the curved wire BL may include copper (Cu). When copper (Cu) is exposed to air, it can be oxidized. Therefore, when the curved wire BL comprising copper (Cu) is oxidized, the resistance of the curved wire BL can increase.

[0215] Therefore, the display panel 10a according to an exemplary embodiment of this disclosure can prevent oxidation of the bent wiring BL, which includes copper (Cu), by using a pattern layer 400, and the oxidation of the bent wiring BL can be prevented more effectively by further arranging a portion of the connecting wiring LL between the bent wiring BL and the pattern layer 400. Thus, an increase in the resistance of the bent wiring BL due to oxidation can be prevented.

[0216] The connecting wire LL can contact the curved wire BL in the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the connecting wire LL can contact the curved wire BL in a portion of the first non-display area NA1, a portion of the curved area BA, and a portion of the second non-display area NA2, but is not limited thereto. Therefore, the connecting wire LL of the display panel 10a according to an exemplary embodiment of the present disclosure can be stably connected to the curved wire BL. For example, even if a portion of the connecting wire LL or either the curved wire BL arranged in the curved area BA is damaged due to the bending of the display panel 10a, the signal applied through the connecting wire LL can still be transmitted to the wiring of the display area DA through the undamaged connecting wire LL or the curved wire BL. For example, when a portion of the connecting wire LL is damaged in the curved area BA of the display panel 10a, the signal applied through the pad portion PAD can be transmitted to the wiring of the display area DA after moving in the order of the connecting wire LL of the second non-display area NA2, the second contact hole CH2, the curved wire BL, the first contact hole CH1, and the connecting wire LL of the first non-display area NA1.

[0217] refer to Figure 9 and Figure 10 The connecting wiring LL can be arranged on the second interlayer dielectric layer 260. The connecting wiring LL can be electrically connected to the curved wiring BL through the first contact hole CH1, the second contact hole CH2 and the third contact hole CH3.

[0218] The first contact hole CH1 can be arranged in the first non-display area NA1, and the connecting wire LL can be electrically connected to the curved wire BL through the first contact hole CH1.

[0219] The second contact hole CH2 can be arranged in the second non-display area NA2, and the connecting wire LL can be electrically connected to the curved wire BL through the second contact hole CH2.

[0220] The third contact hole CH3 can be disposed in the curved region BA, and the connecting wire LL can be electrically connected to the curved wire BL through the third contact hole CH3. In this case, a portion of the connecting wire LL that contacts the curved wire BL through the third contact hole CH3 can be formed to have a predetermined second length L2 in the Y-axis direction. The second length L2 can be less than the first length L1 of the curved wire BL. For example, when considering the positions of the contact holes CH1 to CH3 formed in the second interlayer dielectric layer 260 and the sealant 310, the second length L2 can be less than the first length L1 of the curved wire BL.

[0221] Therefore, according to an exemplary embodiment of the present disclosure, the display panel 10a is electrically connected to the curved wiring BL through the first contact hole CH1, the second contact hole CH2 and the third contact hole CH3, thereby stably transmitting the signal applied through the connecting wiring LL to the wiring of the display area DA.

[0222] refer to Figure 11 The display panel 10a of the display device according to an exemplary embodiment of the present disclosure can be bent. Because portions of the connecting wiring LL are arranged to overlap to support the bent wiring BL in the bent region BA, the display panel 10a according to an exemplary embodiment of the present disclosure can have a robust, bend-resistant structure.

[0223] Figure 12 This is a cross-sectional view illustrating another embodiment of a display panel according to an exemplary embodiment of the present disclosure. Figure 13 It is shown Figure 12 A magnified view of region C in the image. Figure 12 and Figure 13 The display panel 10b shown may be a display panel according to the third embodiment.

[0224] When reference Figure 3 and Figures 7 to 13 When comparing the display panel 10 according to the first embodiment and the display panel 10b according to the third embodiment, the display panel 10b according to the third embodiment may further include a separate third connecting wire LL3 overlapping the curved wire BL. In this case, the third connecting wire LL3 may be arranged on the curved wire BL in the curved region BA. Furthermore, the display panel 10b according to the third embodiment may be applied to a display device according to an exemplary embodiment of the present disclosure, rather than the display panel 10 according to the first embodiment.

[0225] Reference Figure 3 , Figures 7 to 11 , Figure 12 and Figure 13 When describing the display panel 10b according to the third embodiment, since the display panel 10 according to the first embodiment (for example, see...) Figure 7 and Figure 8 (and other accompanying drawings) and the display panel 10b according to the third embodiment (for example, see...). Figure 12 and Figure 13 Components substantially identical to those in other figures (and other figures) may be denoted by the same reference numerals, so their detailed descriptions are omitted. Detailed descriptions provided for elements in one or more figures may also apply to elements in other figures using the same reference numerals.

[0226] refer to Figure 12 and Figure 13A display device according to an exemplary embodiment of the present disclosure may include: a display panel 10b, which includes a recess G; a circuit board 20 connected to a pad portion PAD of the display panel 10b; and a light source unit 30 that emits light toward a liquid crystal layer 300 of the display panel 10b.

[0227] The connection wiring LL of the display panel 10b may include: a first connection wiring LL1 located in a first non-display area NA1; a second connection wiring LL2 located in a second non-display area NA2; and a third connection wiring LL3 located in a curved area BA.

[0228] A third connection trace LL3 can be disposed between the first connection trace LL1 and the second connection trace LL2. For example, the first connection trace LL1, the second connection trace LL2, and the third connection trace LL3 can be connected to the curved trace BL. The third connection trace LL3 can be spaced apart from each of the first connection trace LL1 and the second connection trace LL2. For example, the first connection trace LL1, the second connection trace LL2, and the third connection trace LL3 can be disposed on the second interlayer dielectric layer 260 while being spaced apart from each other. In this case, the first connection trace LL1 can be electrically connected to the curved trace BL through the first contact hole CH1. Furthermore, the second connection trace LL2 can be electrically connected to the curved trace BL through the second contact hole CH2.

[0229] The third connecting wire LL3 can be arranged to overlap with the curved wire BL in the curved region BA. For example, the third connecting wire LL3 can be arranged on the curved wire BL in the curved region BA. For example, the third connecting wire LL3 can be arranged to contact the curved wire BL in the curved region BA. For example, the third connecting wire LL3 can be electrically connected to the curved wire BL through the third contact hole CH3.

[0230] Therefore, because the third connecting wires LL3 are arranged in an overlapping manner to support the bent wires BL in the bent region BA, the display panel 10b according to an exemplary embodiment of the present disclosure can have a robust, bend-resistant structure. Furthermore, because the third connecting wires LL3 are arranged on the bent wires BL, the display panel 10b according to an exemplary embodiment of the present disclosure can prevent oxidation of the bent wires BL, which include copper (Cu).

[0231] A display device according to one or more exemplary embodiments of the present disclosure can be described as follows.

[0232] A display device according to one or more exemplary embodiments of the present disclosure may include: a display panel including a recess; and a circuit board connected to the display panel, wherein the display panel may include: a substrate including a first substrate and a second substrate spaced apart from each other by the recess; a circuit layer disposed on the first substrate and including transistors; a liquid crystal layer disposed on the circuit layer; a planarization layer disposed on the first region and the recess; a pad portion disposed on the second substrate and connected to the circuit board; a bent wiring disposed on the planarization layer; and a connecting wiring connecting the bent wiring and the pad portion.

[0233] A display device according to one or more exemplary embodiments of the present disclosure may include a display panel comprising: a recess; a substrate including a first region and a second region spaced apart from each other by the recess; a circuit layer disposed on the first region and including transistors; a planarization layer disposed on the first region and the recess; a pad portion disposed on the second region; a bent wiring disposed on the planarization layer; and a connection wiring connected to the bent wiring.

[0234] According to one or more exemplary embodiments of this disclosure, the bent wiring may include a material different from the material of the connecting wiring.

[0235] According to one or more exemplary embodiments of this disclosure, the curved wiring may include a first layer and a second layer, and the materials of the first layer and the second layer may be different from each other.

[0236] According to one or more exemplary embodiments of this disclosure, the planarization layer disposed on the groove may extend to overlap with the second region.

[0237] According to one or more exemplary embodiments of the present disclosure, the display panel may further include a patterned layer disposed on the curved wiring, and the patterned layer may be made of an organic insulating material.

[0238] According to one or more exemplary embodiments of this disclosure, the width of the pattern layer may be less than the length of the curved wiring, based on the Y-axis direction.

[0239] According to one or more exemplary embodiments of this disclosure, the patterned layer may overlap with the groove in the Z-axis direction.

[0240] According to one or more exemplary embodiments of this disclosure, the display panel may further include a coating layer disposed in the groove.

[0241] According to one or more exemplary embodiments of the present disclosure, the display panel may further include a color filter layer and a black matrix disposed on the liquid crystal layer, as well as a sealant surrounding the liquid crystal layer.

[0242] According to one or more exemplary embodiments of this disclosure, the sealant may overlap with the curved wiring in the Z-axis direction.

[0243] According to one or more exemplary embodiments of this disclosure, the display panel may further include a cover member disposed on the color filter layer and the black matrix.

[0244] According to one or more exemplary embodiments of this disclosure, the display panel may further include a light source unit overlapping the first substrate.

[0245] According to one or more exemplary embodiments of this disclosure, the connection wiring may include a first connection wiring that contacts one side of the curved wiring and a second connection wiring that contacts the other side of the curved wiring.

[0246] According to one or more exemplary embodiments of this disclosure, the display panel may further include a patterned layer disposed between the first connection wiring and the second connection wiring, the first connection wiring and the second connection wiring being connected via the curved wiring.

[0247] According to one or more exemplary embodiments of the present disclosure, the display panel may further include a second interlayer dielectric layer disposed between the curved wiring and the first connection wiring and between the curved wiring and the second connection wiring, wherein the first connection wiring may contact the curved wiring through a first contact hole of the second interlayer dielectric layer, and the second connection wiring may contact the curved wiring through a second contact hole of the second interlayer dielectric layer.

[0248] According to one or more exemplary embodiments of this disclosure, at least a portion of the connection wiring may be arranged on the curved wiring.

[0249] According to one or more exemplary embodiments of the present disclosure, the display panel may further include a patterned layer disposed on the connection wiring, and the patterned layer may overlap with the groove in the Z-axis direction.

[0250] According to one or more exemplary embodiments of this disclosure, the display panel may further include a second interlayer dielectric layer disposed between the curved wiring and the connecting wiring, wherein the connecting wiring may contact the curved wiring through a first contact hole, a second contact hole and a third contact hole of the second interlayer dielectric layer.

[0251] According to one or more exemplary embodiments of this disclosure, the connection wiring may include a first connection wiring, a second connection wiring, and a third connection wiring arranged spaced apart from each other, and the third connection wiring may overlap with the curved wiring.

[0252] According to one or more exemplary embodiments of this disclosure, the third connection wiring may be spaced apart from each of the first connection wiring and the second connection wiring.

[0253] According to one or more exemplary embodiments of the present disclosure, the display panel may further include a second interlayer dielectric layer disposed between the curved wiring and the first connection wiring and between the curved wiring and the second connection wiring, wherein the first connection wiring may contact the curved wiring through a first contact hole of the second interlayer dielectric layer, and the second connection wiring may contact the curved wiring through a second contact hole of the second interlayer dielectric layer.

[0254] According to one or more exemplary embodiments of this disclosure, the third connection wiring may be arranged on the curved wiring to contact the curved wiring.

[0255] According to one or more exemplary embodiments of this disclosure, the first side surface of the first region and the second side surface of the second region may each be an inclined surface having a predetermined slope.

[0256] According to one or more exemplary embodiments of this disclosure, the display panel may further include a first electrode disposed on the planarization layer, the curved wiring may include a first layer and a second layer, and at least one of the first layer and the second layer may include the same metal layer as the metal layer of the first electrode.

[0257] According to one or more exemplary embodiments of this disclosure, the planarization layer may include organic materials.

[0258] A display panel according to one or more exemplary embodiments of the present disclosure may include: a substrate including a first substrate and a second substrate spaced apart from each other by the recess; a circuit layer disposed on the first substrate and including transistors; a planarization layer disposed on the first substrate and the recess; a pad portion disposed on the second substrate; a bent wiring disposed on the planarization layer; and a connection wiring connecting the pad portion and the bent wiring.

[0259] According to one or more exemplary embodiments of this disclosure, an insulating layer or dielectric layer directly disposed on the electrodes of the transistor may be disposed on the first substrate and the second substrate instead of on the groove, such that the insulating layer or dielectric layer may not exist in the bending region. For example, the insulating layer or dielectric layer may include the gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer.

[0260] According to one or more exemplary embodiments of this disclosure, the inorganic layer of the circuit layer may be disposed on the substrate other than the recess, such that the inorganic layer may not be present in the curved region. For example, the inorganic layer may include the gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer.

[0261] According to one or more exemplary embodiments of this disclosure, the metal layer of the circuit layer may be disposed on the first substrate but not on the recess, or disposed on both the first and second substrates but not on the recess. For example, the metal layer of the circuit layer may include some or all of the following electrodes: gate electrode, source electrode, drain electrode, first electrode, and second electrode.

[0262] According to one or more exemplary embodiments of this disclosure, the curved wiring may be separate from and distinct from the connecting wiring.

[0263] The objectives, means of achieving the objectives, and effects of this disclosure do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0264] While embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0265] Cross-reference to related applications

[0266] This application claims priority and benefit to Korean Patent Application No. 10-2024-0124156, filed on September 11, 2024, the disclosure of which is incorporated herein by reference in its entirety for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: Display panel, The display panel includes: Groove; A substrate, the substrate including a first region and a second region spaced apart from each other by the groove; A circuit layer disposed on the first region and comprising transistors; A planarization layer is disposed on the first region and the groove; The pad portion is arranged on the second region; The curved wiring is disposed on the planarization layer; and Connecting wiring, the connecting wiring being connected to the curved wiring.

2. The display device according to claim 1, wherein, The curved wiring includes a material different from that of the connecting wiring.

3. The display device according to claim 1, wherein, The curved wiring includes a first layer and a second layer, and The materials of the first layer and the second layer are different from each other.

4. The display device according to claim 1, wherein, The planarization layer disposed on the groove extends to overlap with the second region.

5. The display device according to claim 1, further comprising: A pattern layer is disposed on the curved wiring. The patterned layer is made of organic insulating material.

6. The display device according to claim 5, wherein, The width of the pattern layer is less than the length of the curved wiring.

7. The display device according to claim 5, wherein, The patterned layer overlaps with the groove.

8. The display device according to claim 1, further comprising: A coating layer is disposed in the groove.

9. The display device according to claim 1, wherein, The connecting wiring includes a first connecting wiring that contacts one side of the curved wiring and a second connecting wiring that contacts the other side of the curved wiring.

10. The display device according to claim 9, further comprising: A pattern layer is disposed between the first connection wiring and the second connection wiring, and The first connecting wire and the second connecting wire are connected via the curved wire.

11. The display device according to claim 9, further comprising: A second interlayer dielectric layer is disposed between the bent wiring and the first connection wiring, and between the bent wiring and the second connection wiring. The first connection wiring contacts the bent wiring through the first contact hole of the second interlayer dielectric layer, and The second connection wiring contacts the bent wiring through the second contact hole of the second interlayer dielectric layer.

12. The display device according to claim 1, wherein, At least a portion of the connecting wiring is arranged on the curved wiring.

13. The display device according to claim 12, further comprising: A pattern layer is disposed on the connection wiring. The pattern layer overlaps with the groove.

14. The display device according to claim 12, further comprising: A second interlayer dielectric layer is disposed between the curved wiring and the connecting wiring. The connecting wiring contacts the curved wiring through the first contact hole, the second contact hole, and the third contact hole of the second interlayer dielectric layer.

15. The display device according to claim 1, wherein, The connection wiring includes a first connection wiring, a second connection wiring, and a third connection wiring arranged at intervals from each other, and The third connecting wire overlaps with the curved wire.

16. The display device according to claim 15, wherein, The third connection wiring is spaced apart from each of the first connection wiring and the second connection wiring.

17. The display device according to claim 15, further comprising: A second interlayer dielectric layer is disposed between the bent wiring and the first connection wiring, and between the bent wiring and the second connection wiring. The first connection wiring contacts the bent wiring through the first contact hole of the second interlayer dielectric layer, and The second connection wiring contacts the curved wiring through the second contact hole of the second interlayer dielectric layer.

18. The display device according to claim 17, wherein, The third connecting wire is arranged on the curved wire to contact the curved wire.

19. The display device according to claim 1, wherein, The first side surface of the first region and the second side surface of the second region are each inclined surfaces with a predetermined slope.

20. The display device according to claim 1, further comprising: The first electrode is disposed on the planarization layer. The curved wiring includes a first layer and a second layer, and Wherein, at least one of the first layer and the second layer includes the same metal layer as the metal layer of the first electrode.

21. The display device according to claim 1, wherein, The planarization layer comprises organic materials.

22. The display device according to claim 1, further comprising a circuit board connected to the display panel. in, The pad portion is connected to the circuit board.

23. A display panel, the display panel comprising: A substrate, the substrate comprising a first substrate and a second substrate spaced apart from each other by grooves; A circuit layer disposed on the first substrate and including transistors; A planarization layer is disposed on the first substrate and the groove; The pad portion is disposed on the second substrate; The curved wiring is arranged on the planarization layer; as well as The connection wiring connects the pad portion and the curved wiring.

Citation Information

Patent Citations

  • Anisotropic conductive connection structure

    KR1020240124156A