Display device

Abstract

A display device includes: a pixel array including a plurality of pixels connected to a plurality of data lines; a timing controller generating a reference voltage; and a data driver including a first sense amplifier outputting a first measurement reference voltage corresponding to a first data line among the plurality of data lines, a second sense amplifier outputting a second measurement reference voltage corresponding to a second data line among the plurality of data lines, and a defect detection circuit, a second sense amplifier outputs a second measurement reference voltage smaller than the first measurement reference voltage corresponding to a second data line disposed adjacent to the first data line among the plurality of data lines, and a defect detection circuit is connected to the second sense amplifier. And generate a shutdown signal based on a comparison result between an input voltage received from the second sense amplifier and a reference voltage.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] With the development of the information society, the demand for display devices that display images is increasing, and various types of display devices such as liquid crystal displays, plasma displays, and organic light-emitting diode displays are being used.

[0003] The display device includes a display panel, multiple gate lines, multiple data lines, and multiple pixels defined by the intersections of the gate lines and data lines disposed in the display panel. The display device also includes various drive circuits, such as gate drive circuits and data drive circuits for driving these gate lines, data lines, etc.

[0004] When a crack occurs in the display panel due to an impact, short circuits may occur between different signal lines arranged in the display panel, or between the signal lines and electrodes. Furthermore, these short circuits may cause screen defects, and the heat generated by the short circuits may damage the display panel, drive circuitry, etc. However, there is a drawback that it may take a long time to detect whether a short circuit has occurred within the display panel. Summary of the Invention

[0005] This disclosure aims to provide a display device capable of detecting defects in a display panel in real time, as well as a driving method for the display device.

[0006] The display device in the embodiment includes: a pixel array including a plurality of pixels connected to a plurality of data lines; a timing controller for generating a reference voltage; and a data driver including a first sensing amplifier, a second sensing amplifier, and a defect detection circuit. The first sensing amplifier outputs a first measurement reference voltage corresponding to a first data line among the plurality of data lines. The second sensing amplifier outputs a second measurement reference voltage, which is less than the first measurement reference voltage, corresponding to a second data line among the plurality of data lines that is adjacent to (close to) the first data line. The defect detection circuit is connected to the second sensing amplifier and generates a power-off signal based on a comparison between an input voltage received from the second sensing amplifier and a reference voltage.

[0007] The display driving circuit in the embodiment includes: a timing controller for generating a reference voltage; a first sensing amplifier for outputting a first measurement reference voltage corresponding to a first data line among a plurality of data lines; a second sensing amplifier for outputting a second measurement reference voltage less than the first measurement reference voltage corresponding to a second data line among the plurality of data lines arranged adjacent to (near) the first data line; and a defect detection circuit connected to the second sensing amplifier for generating a shutdown signal based on a comparison result between an input voltage received from the second sensing amplifier and the reference voltage. Attached Figure Description

[0008] The above and other embodiments, advantages and features of this disclosure will become more apparent from the more detailed description of the embodiments of this disclosure with reference to the accompanying drawings.

[0009] Figure 1 This is a block diagram illustrating an embodiment of the display device.

[0010] Figure 2 This is a circuit diagram of an embodiment of a pixel.

[0011] Figure 3 This is a block diagram illustrating an embodiment of the configuration of a data drive.

[0012] Figure 4 This is a diagram illustrating an embodiment of the source amplifier configuration.

[0013] Figure 5 This is a diagram illustrating an embodiment of the operation of the display device.

[0014] Figure 6 This is a diagram illustrating an embodiment of the operation of a data drive.

[0015] Figure 7 This is a diagram illustrating an embodiment of the operation of a data drive.

[0016] Figure 8 This is a diagram used to illustrate an embodiment of the display system. Detailed Implementation

[0017] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0018] Descriptions of parts not related to this disclosure have been omitted, and throughout the specification, the same reference numerals denote the same elements.

[0019] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intermediary element between them. In contrast, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0020] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings herein.

[0021] Furthermore, unless explicitly stated to the contrary, the word “including” and variations such as “contains” should be understood as implying the inclusion of the stated element, but not excluding any other element.

[0022] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another(s) illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of the other elements will be oriented to be “up” of the other elements. Thus, depending on the specific orientation of the figure, the exemplary term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will be oriented to be “above” the other elements. Thus, the exemplary terms “below” or “under” can cover both “up” and “down” orientations.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and in this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Figure 1 This is a block diagram illustrating an embodiment of the display device.

[0025] The display device 100 may include a display driving circuit 10 and a display panel 30.

[0026] The display device 100 can perform display operations and panel defect detection operations.

[0027] The display operation can be an operation that displays an image corresponding to the image signal received from the host. The panel defect detection operation can be an operation that detects whether a defect has occurred in the display panel 30.

[0028] In some embodiments, when the display device 100 performs a panel defect detection operation, the display device 100 may apply a plurality of measurement reference voltages to the display panel 30 and generate a shutdown signal VS in response to the application of the plurality of measurement reference voltages.

[0029] In an embodiment, for example, the display device 100 may perform a panel defect detection operation during a vertical blank period when the display device 100 is not displaying an image. In an embodiment, since defects within the display panel 30 may occur over time, the display device 100 may measure whether the display panel 30 has defects, for example, at predetermined intervals, to accurately display the image. In an embodiment, panel defects may be, for example, short circuits between adjacent (nearby) data lines within the display panel 30, electroluminescent (“EL”) short circuits, etc.

[0030] The operation of the display device 100 can be controlled based on the power-off signal VS.

[0031] The display panel 30 can display images to the user based on image signals received from the host.

[0032] Display panel 30 may be one of a type of display device that receives electrically transmitted video signals and displays two-dimensional (“2D”) images (such as a thin-film transistor liquid crystal display (“TFT-LCD”), an organic light-emitting diode (“OLED”) display, a field emission display, or a plasma display panel (“PDP”)). In some embodiments, one or more display panels 30 may be present.

[0033] like Figure 1 As shown, the display panel 30 may include multiple signal lines (e.g., multiple gate lines GL (e.g., gate lines GL0, GL1, ..., and GLn), multiple data lines DL (e.g., data lines DL0, DL1, ..., and DLm), multiple sensing control lines SGL (e.g., sensing control lines SGL0, SGL1, ..., and SGLn), and multiple data sensing lines SDL (e.g., data sensing lines SDL0, SDL1, ..., and SDLm)) (n and m are natural numbers greater than 0). Additionally, the display panel 30 may include multiple pixels PX connected to the multiple signal lines and arranged in a matrix. The display panel 30 can display an image based on data signals received from the data driver 20 and gate drive signals received from the gate driver 13.

[0034] exist Figure 1 In the illustration, pixel PX is shown connected to multiple gate lines GL, multiple data lines DL, multiple sensing control lines SGL, and multiple data sensing lines SDL. However, the connection structure between pixel PX and signal lines in the display device 100 according to this disclosure is not limited to this. In embodiments, for example, various signal lines may be connected additionally corresponding to the circuit structure of pixel PX.

[0035] The display driving circuit 10 can generate a plurality of analog signals for driving the display panel 30 based on image signals received from the host. In an embodiment, for example, the plurality of analog signals may include a plurality of gate signals and a plurality of data signals DS (see [link to relevant documentation]) driving a plurality of pixels PX included within the display panel 30. Figure 2 The display driving circuit 10 can provide multiple gate signals and multiple data signals DS to multiple pixels PX. The display panel 30 can emit image light corresponding to the image signal through the signals provided by the display driving circuit 10.

[0036] In some embodiments, the display driving circuit 10 may include a timing controller 11, a data driver 20, and a gate driver 13.

[0037] The timing controller 11 can control the driving timing of the display driving circuit 10. The timing controller 11 can perform various types of image processing on the image signals received from the host (such as changing the format of image data and reducing power consumption).

[0038] The timing controller 11 can generate a data control signal D_CTRL based on the image signal received from the host. The timing controller 11 can also generate image data DATA based on the image signal. The timing controller 11 can transmit the data control signal D_CTRL and the image data DATA to the data driver 20. Additionally, the timing controller 11 can generate a gate control signal G_CTRL. The timing controller 11 can transmit the gate control signal G_CTRL to the gate driver 13.

[0039] In some embodiments, the timing controller 11 can divide the image signal into units of one frame based on the vertical synchronization signal and into units of multiple gate lines GL based on the horizontal synchronization signal to generate image data DATA. The timing controller 11 can detect edge periods in which no valid data signal is generated based on the data enable signal. In embodiments, for example, the edge period can be the period between a first valid data period in which a valid data signal is output (i.e., the period in which the image is displayed) and an adjacent (nearby) second valid data period—that is, the vertical back edge period ( Figure 5(VBP in the middle). The timing controller 11 can also detect the time periods during which multiple gate lines GL are not scanned—that is, the horizontal edge periods.

[0040] In some embodiments, the timing controller 11 may control the data driver 20 to output a measurement reference voltage to the display panel 30 to detect faults in the display panel 30. In some embodiments, the timing controller 11 may pre-store the measurement reference voltage required to perform panel defect detection operations.

[0041] The timing controller 11 may receive a power-off signal VS from the data driver 20. The power-off signal VS may be a signal indicating the presence of a fault within the display panel 30. In some embodiments, the timing controller 11 may control the operation of the display device 100 based on the power-off signal VS. In an embodiment, for example, when the power-off signal VS indicates a fault in the display panel 30, the timing controller 11 may stop the operation of the display device 100. In an embodiment, for example, the timing controller 11 may transmit a signal instructing the PMIC connected to the display device 100 to stop supplying power.

[0042] Data driver 20 can receive data control signal D_CTRL, image data DATA, and reference voltage Vref from timing controller 11. In some embodiments, data driver 20 can receive image data DATA in data units corresponding to multiple pixels PX included in a horizontal line of display panel 30. Image data DATA may include grayscale information corresponding to each pixel PX. Data driver 20 can convert the image data DATA received from timing controller 11 into a data signal DS in analog signal form based on multiple grayscale voltages (or gamma voltages) and reference voltage Vref. Data driver 20 can output multiple data signals DS to display panel 30 in horizontal line units via multiple data lines DL0-DLm (m is a natural number greater than 0) according to data control signal D_CTRL.

[0043] In some embodiments, the data driver 20 may apply a predetermined measurement reference voltage to a corresponding data line among multiple data lines DL to detect faults in the display panel 30. In some embodiments, the data driver 20 may apply the predetermined measurement reference voltage as a data signal DS to multiple pixels PX via multiple data lines DL, and detect whether the display panel 30 is defective based on signals (e.g., current) received via multiple data lines DL.

[0044] like Figure 1 As shown, the data driver 20 may include a defect detection circuit 21, a first source amplifier (also referred to as a first sensing amplifier) ​​23, and a second source amplifier (also referred to as a second sensing amplifier) ​​25.

[0045] The first source amplifier 23 may be a source amplifier connected to a data line (also referred to as the first data line) DL2k-1 (where k is a natural number greater than 0) among multiple data lines DL. The first source amplifier 23 may apply a first measurement reference voltage to multiple pixels PX. In some embodiments, the first measurement reference voltage may have a value greater than the reference voltage Vref.

[0046] The second source amplifier 25 may be a source amplifier connected to a data line (also referred to as a second data line) DL2k (where k is a natural number greater than 0) among multiple data lines DL. The second source amplifier 25 may apply a second measurement reference voltage to multiple pixels PX. In some embodiments, the second measurement reference voltage may have a value less than the reference voltage Vref.

[0047] The defect detection circuit 21 can be connected to the output terminal of the second source amplifier 25. The defect detection circuit 21 can compare a sensed voltage received in response to applying a first and a second measurement reference voltage to a plurality of pixels PX with a reference voltage Vref, and generate a comparison result. The sensed voltage can change based on the defect state of the display panel 30. The defect detection circuit 21 can detect defects in the display panel 30 based on the comparison result. In some embodiments, when there is a defect in the display panel 30, the comparison result can have a value higher than the reference voltage Vref. When there is no defect in the display panel 30, the comparison result can have a value lower than the reference voltage Vref.

[0048] In some embodiments, when the comparison result has a value greater than the sum of the reference voltage Vref and the first threshold, the defect detection circuit 21 can determine that a defect exists in the display panel 30. Here, the first threshold can be preset based on the design of the display device 100 (e.g., the spacing between multiple pixels PX, the spacing between multiple data lines DL, the spacing between source amplifiers, etc.).

[0049] In some embodiments, when the comparison result has a value less than the reference voltage Vref minus the second threshold, the defect detection circuit 21 can determine that a defect exists in the display panel 30. Here, the second threshold can be preset based on the design of the display device 100 (e.g., the spacing between multiple pixels PX, the spacing between multiple data lines DL, the spacing between source amplifiers, etc.).

[0050] Figure 1 The diagram illustrates that the data driver 20 is connected to the display panel 30 via m data lines DL and m data sensing lines SDL, but this disclosure is not limited thereto, and the display driver circuit 10 may include a number of data sensing lines SDL that is different from the number of data lines DL.

[0051] The data driver 20 may include a separate source amplifier for outputting a data signal DS corresponding to the image data DATA to the display panel 30, but this disclosure is not limited thereto, and the first source amplifier 23 and the second source amplifier 25 may be used to output the data signal DS corresponding to the image data DATA to the display panel 30.

[0052] Gate driver 13 can be connected to multiple gate lines GL of display panel 30 and drive the multiple gate lines GL of display panel 30 in sequence. Gate driver 13 can provide multiple gate signals to the multiple gate lines GL of display panel 30. The multiple gate signals can be pulse signals with enable and disable levels.

[0053] The gate driver 13 can apply multiple gate signals to multiple gate lines GL in different ways based on the gate control signal G_CTRL received from the timing controller 11. In an embodiment, for example, when an enable level gate signal is applied to a pixel PX connected to one of the multiple gate lines GL, a data signal DS applied to the data line connected to the corresponding pixel PX among the multiple data lines DL can be transmitted to the pixel PX.

[0054] Figure 2 This is a circuit diagram of an embodiment of a pixel.

[0055] Specifically, the display panel ( Figure 1 (30) can include multiple pixels. Figure 2 This is a graph showing pixels PXj and PXj+1 (where j is a natural number greater than 0) located at any adjacent (nearby) positions. Figure 2 As shown, pixel PXj may include a switching transistor SWTj, a driving transistor DTj, an organic light-emitting diode (“OLED”) 31j, a storage capacitor Cstj, and a sensing transistor SSTj. The switching transistor SWTj, the driving transistor DTj, and the sensing transistor SSTj may be one of a p-channel metal-oxide-semiconductor (“PMOS”) transistor and an n-channel metal-oxide-semiconductor (“NMOS”) transistor. Figure 2 The illustration shows a case where all three transistors are NMOS transistors, but this disclosure is not limited thereto.

[0056] Pixel PXj can be supplied with a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD can be higher than the second driving voltage ELVSS.

[0057] Pixel PXj can be connected to the corresponding gate line GLp, data line DL2k-1 (k is a natural number greater than 0), sensing control line SGLp (p is a natural number), and data sensing line SDL2k-1 (k is a natural number greater than 0). In Figure 2 In the diagram, pixel PXj is depicted as connected to a data line DL2k-1 and a gate line GLp (p being a natural number), and specifically, a switching transistor SWTj can be connected to the gate line GLp and the data line DL2k-1. The switching transistor SWTj can be controlled by a gate voltage applied through the gate line GLp. When the switching transistor SWTj is turned on, it can provide the data signal DS supplied through the data line DL2k-1 to the gate node N4j of the driving transistor DTj.

[0058] The sensing transistor SSTj can be connected to the sensing control line SGLp and the data sensing line SDL2k-1, and is controlled by the sensing voltage applied through the sensing control line SGLp. When turned on, the sensing transistor SSTj can supply an initialization voltage I_2k-1 to the source node N3j of the driving transistor DTj. Additionally, the turned-on sensing transistor SSTj can transfer the voltage supplied to the source node N3j to the data sensing line SDL2k-1.

[0059] The storage capacitor Cstj can store the difference between the data voltage applied to the gate node N4j of the driving transistor DTj by the switching transistor SWTj and the initial voltage I_2k-1 supplied to the source node N3j of the driving transistor DTj by the sensing transistor SSTj, thereby supplying a constant driving voltage (e.g., the gate-source voltage of the driving transistor DTj) to the driving transistor DTj during a predetermined period of time (e.g., one frame).

[0060] The first driving voltage ELVDD can be applied to the drain node of the driving transistor DTj, and the driving transistor DTj can supply the OLED 31j with a current proportional to the driving voltage (i.e., the difference between the voltage of the gate node N4j and the source node N3j of the driving transistor DTj).

[0061] OLED 31j may include an anode connected to the source node N3j of the driving transistor DTj, a cathode to which a second driving voltage ELVSS is applied, and an organic light-emitting layer between the cathode and the anode. The cathode may be a common electrode shared by multiple pixels PX. When a driving current is supplied from the driving transistor DTj, light can be generated from the organic light-emitting layer of OLED 31j. The intensity of the light may be proportional to the driving current.

[0062] Unless otherwise stated, the description given for pixel PXj similarly applies to pixel PXj+1. In an embodiment, for example, pixel PXj+1 may include a driving transistor DTj+1, a sensing transistor SSTj+1, a switching transistor SWTj+1, a storage capacitor Cstj+1, and an OLED 31j+1. The conducting sensing transistor SSTj+1 can supply an initialization voltage I_2k to the source node N3j+1 of the driving transistor DTj+1. Additionally, the conducting sensing transistor SSTj+1 can transfer the voltage supplied to the source node N3j+1 to the data sensing line SDL2k.

[0063] During display operation, the switching transistor SWTj supplies the data signal DS applied via data line DL2k-1 to the driving transistor DTj. At this time, the sensing transistor SSTj can be turned on. A current proportional to the difference between the voltage at the gate node N4j and the source node N3j of the driving transistor DTj (i.e., the driving voltage) can flow to the OLED 31j. OLED 31j can output light according to the driving current corresponding to the image data. Similarly, OLED 31j+1 can also output light according to the driving current corresponding to the corresponding image data.

[0064] During panel defect detection operations, the data driver 20 can apply the measurement reference voltage as a data signal DS to data lines DL2k-1 and DL2k.

[0065] Figure 3 This is a block diagram illustrating an embodiment of the configuration of a data drive. Figure 4 This is a diagram illustrating an embodiment of the source amplifier configuration.

[0066] The first source amplifier 23 can be a source amplifier connected to the data line DL2k-1. The first source amplifier 23 can include a first amplifier AMP23. The first amplifier AMP23 can include an input stage, an amplification stage, and an output stage 235. The output stage 235 can include a PMOS transistor TX2351 and an NMOS transistor TX2353. The first source amplifier 23 can receive a measured reference voltage D_ODD higher than the reference voltage Vref as a data signal DS.

[0067] The second source amplifier 25 can be a source amplifier connected to the data line DL2k. The second source amplifier 25 may include a second amplifier AMP25.

[0068] Also refer to Figure 4 The second source amplifier 25 may include an input stage 251, an amplification stage 253, and an output stage 255.

[0069] Input stage 251 can be connected to a first input terminal (+) and a second input terminal (-), and receives at least one gamma voltage through the first input terminal (+). In some embodiments, the first input terminal (+) can receive a measurement reference voltage. In some embodiments, the second input terminal (-) can be connected to the output terminal N25 via a feedback path. Similarly, in some embodiments, the second input terminal (-) of the first source amplifier 23 can be connected to the output terminal N23 via a feedback path.

[0070] Amplification stage 253 can operate as an amplifier circuit that amplifies the voltage input through input stage 251. In some embodiments, amplification stage 253 may include circuitry to reduce the resistive component present between input stage 251 and output stage 255.

[0071] Output stage 255 can operate as a buffer circuit. Output stage 255 can be connected to one of the multiple data lines DL connected to display panel 30. A resistive element for counteracting the effects of static electricity can be connected between output stage 255 and display panel 30. In some embodiments, output stage 255 may include an output buffer. The output buffer may include a PMOS transistor TX2551 and an NMOS transistor TX2553 connected in series between a first power node VDD and a second power node. The output voltage can be output from the output terminal N25 between PMOS transistor TX2551 and NMOS transistor TX2553. In some embodiments, the output voltage may be the grayscale voltage of a pixel PX input to display panel 30. In some embodiments, the output voltage may be a measurement reference voltage of a pixel PX input to display panel 30.

[0072] like Figure 3 and Figure 4 As shown, the voltage at the gate of the NMOS transistor TX2553 input to the output stage 255 can be transmitted to the defect detection circuit 21 as the input voltage VIN.

[0073] Although reference Figure 4 The configuration of the second source amplifier 25 is described, but unless otherwise stated, the description of the second source amplifier 25 can also be applied to the first source amplifier 23.

[0074] The second source amplifier 25 can receive a voltage (also known as the measurement reference voltage) D_EVEN that is lower than the reference voltage Vref as a data signal DS.

[0075] The defect detection circuit 21 may include a current mirror circuit 211 and a third amplifier AMP21.

[0076] The current mirror circuit 211 may include a first PMOS transistor TX211, a second PMOS transistor TX215, an NMOS transistor TX213, and a first resistor R217.

[0077] The source of the first PMOS transistor TX211 can be connected to the first power node (also known as the power supply node) VDD. The drain of the first PMOS transistor TX211 can be connected to node N213 (i.e., the gate of the first PMOS transistor TX211 and the drain of the NMOS transistor TX213).

[0078] The source of the second PMOS transistor TX215 can be connected to the first power supply node VDD. The drain of the second PMOS transistor TX215 can be connected to node N215. One terminal of the first resistor R217 can be connected to node N215, and its remaining terminals can be connected to ground. Node N215 can be connected to the first input terminal (+) of the third amplifier AMP21.

[0079] The gate of NMOS transistor TX213 can be connected to the gate of NMOS transistor TX2553 in the output stage 255 of the second source amplifier 25. The gate of NMOS transistor TX213 can receive the voltage applied to the gate of NMOS transistor TX2553 as the input voltage VIN. The source of NMOS transistor TX213 can be connected to ground.

[0080] The third amplifier AMP21 can receive the voltage of node N215 as a sense voltage Vsen through the first input terminal (+). The third amplifier AMP21 can receive the reference voltage Vref through the second input terminal (-). The third amplifier AMP21 can generate a shutdown signal VS based on the sense voltage Vsen and the reference voltage Vref.

[0081] In some embodiments, as the input voltage VIN increases, the voltage applied to the gate of the NMOS transistor TX213 increases, thus the voltage applied to node N213 can decrease. That is, the voltage applied to the gate of the first PMOS transistor TX211 and the gate of the second PMOS transistor TX215 can decrease. Correspondingly, the voltage applied to node N215 can increase. That is, the sensed voltage Vsen can increase. The third amplifier AMP21 can generate a shutdown signal VS based on the increased sensed voltage Vsen and the reference voltage Vref. In some embodiments, the shutdown signal VS can have a value greater than the reference voltage Vref. The shutdown signal VS with a value greater than the reference voltage Vref can have an enable level.

[0082] In some embodiments, when the input voltage VIN decreases, the voltage applied to the gate of the NMOS transistor TX213 decreases, thus the voltage applied to node N213 can increase. That is, the voltage applied to the gate of the first PMOS transistor TX211 and the gate of the second PMOS transistor TX215 can increase. Correspondingly, the voltage applied to node N215 can decrease. That is, the sensed voltage Vsen can decrease. The third amplifier AMP21 can generate a shutdown signal VS based on the decreased sensed voltage Vsen and the reference voltage Vref. In some embodiments, the shutdown signal VS can have a value less than the reference voltage Vref. A shutdown signal VS with a value less than the reference voltage Vref can have a disable level.

[0083] refer to Figure 3 and Figure 4 The description indicates that the first sensing amplifier 23 is connected to data line DL2k-1 and the second sensing amplifier 25 is connected to data line DL2k. However, this disclosure is not limited to this, and the first sensing amplifier 23 can be connected to data line DL2k and the second sensing amplifier 25 can be connected to data line DL2k-1. In this case, the defect detection circuit 21 can be connected to a sensing amplifier that outputs a measurement reference voltage lower than the reference voltage Vref.

[0084] The defect detection circuit 21 can be connected to both the first sensing amplifier 23 and the second sensing amplifier 25. In this case, when the first sensing amplifier 23 outputs a measurement reference voltage lower than the reference voltage Vref, a defect in the display panel 30 can be detected based on the power-off signal VS output from the defect detection circuit 21 connected to the first sensing amplifier 23. When the first sensing amplifier 23 outputs a measurement reference voltage higher than the reference voltage Vref, a defect in the display panel 30 can be detected based on the power-off signal VS output from the defect detection circuit 21 connected to the second sensing amplifier 25.

[0085] Figure 5 This is a diagram illustrating an embodiment of the operation of the display device. Figure 6 This is a diagram illustrating an embodiment of the operation of a data drive. Figure 7 This is a diagram illustrating an embodiment of the operation of a data drive.

[0086] First, the vertical synchronization signal VSYNC can transition to the logic level "H".

[0087] The display device 100 can perform a display operation to display an image corresponding to the image data DATA during the Active Data Period within a frame (between time point t500 and time point t501).

[0088] During the time period between time point t501 and time point t503, the display device 100 may not display an image during the vertical trailing edge time period VBP.

[0089] In some embodiments, during the vertical trailing edge (VBP) period, the data driver 20 can perform panel defect detection operations within the display panel 30. Specifically, the first source amplifier 23 and the second source amplifier 25 can output the measurement reference voltage required for the panel defect detection operation to the display panel 30. The first source amplifier 23 can output the measurement reference voltage D_ODD to the corresponding data line. The second source amplifier 25 can output the measurement reference voltage D_EVEN to the corresponding data line. Figure 5 As shown, the measurement reference voltage D_ODD output from the first source amplifier 23 can have a first value VH greater than the reference voltage Vref. The measurement reference voltage D_EVEN output from the second source amplifier 25 can have a second value VL less than the reference voltage Vref.

[0090] Also refer to Figure 6 The display panel 30 may include multiple resistors R1, R2, ..., Ru and multiple capacitors C1, C2, ..., Cu, where u is a natural number greater than 1. The multiple resistors R1, R2, ..., Ru and the multiple capacitors C1, C2, ..., Cu can be a simplified representation of the capacitors included in multiple pixels PX in the display panel 30 and the resistors in the wiring of the data lines DL. The RC delay time caused by the multiple resistors R1, R2, ..., Ru and the multiple capacitors C1, C2, ..., Cu can be within one frame time period.

[0091] The first source amplifier 23 outputs the measurement reference voltage D_ODD to the corresponding data line DL2k-1. The second source amplifier 25 outputs the measurement reference voltage D_EVEN to the corresponding data line DL2k. The input voltage VIN can be transmitted from the output terminal of the second source amplifier 25 to the defect detection circuit 21. The input voltage VIN can be generated by applying the measurement reference voltage to the corresponding data line using the first source amplifier 23 and the second source amplifier 25.

[0092] exist Figure 6In this configuration, data lines DL2k-1 and DL2k may not be short-circuited. That is, there may be no defects within the display panel 30. A first current I61 can flow through data line DL2k-1 in a first direction (①) via a measurement reference voltage D_ODD applied from the first source amplifier 23. Additionally, a second current I62 can flow along data line DL2k in a second direction (②) via a measurement reference voltage D_EVEN output from the second source amplifier 25. Accordingly, the input voltage VIN output from the output stage of the second source amplifier 25 can be close to the value of the measurement reference voltage D_EVEN.

[0093] refer to Figure 7 Data lines DL2k-1 and DL2k may be short-circuited. A first current I71 flows through data line DL2k-1 via the measurement reference voltage D_ODD applied from the first source amplifier 23. Because the measurement reference voltage D_ODD has a first value VH, and the measurement reference voltage D_EVEN has a second value VL less than the first value VH, the first current I71 can flow in a third direction (③). Additionally, a second current I72 flows along data line DL2k in a fourth direction (④) via the measurement reference voltage D_EVEN output from the second source amplifier 25. Here, the third direction (③) can be the opposite direction of the fourth direction (④). That is, the first current I71 can flow towards the output stage of the second source amplifier 25. With the first current I71, the input voltage VIN output from the output stage of the second source amplifier 25 can have a value greater than the measurement reference voltage D_EVEN.

[0094] Return to reference Figure 5 At time point t503, the vertical synchronization signal VSYNC can transition to logic level "L" and then transition to logic level "H".

[0095] During time points t503 to t505, the display device 100 can perform a display operation to display an image corresponding to the image data DATA. The defect detection circuit 21 can generate a shutdown signal VS based on the panel defect detection operation.

[0096] Specifically, the defect detection circuit 21 can generate a shutdown signal VS by comparing the input voltage VIN and the reference voltage Vref.

[0097] exist Figure 6 In the event of a fault, the defect detection circuit 21 can compare an input voltage VIN, which is close to the value of the measured reference voltage D_EVEN, with the reference voltage Vref to generate a shutdown signal VS based on the comparison result. The shutdown signal VS may have a value less than the reference voltage Vref.

[0098] exist Figure 7In the event of a fault, the defect detection circuit 21 can compare the input voltage VIN, which is greater than the measured reference voltage D_EVEN, with the reference voltage Vref to generate a shutdown signal VS based on the comparison result. The shutdown signal VS can have a value greater than the reference voltage Vref. The defect detection circuit 21 can transmit the shutdown signal VS to the timing controller 11. The timing controller 11 can stop the operation of the display device 100 upon receiving a shutdown signal VS with an enable level greater than the reference voltage Vref.

[0099] Despite Figure 5 The defect detection circuit 21 is illustrated to generate a shutdown signal VS at time points t503 to t505, but this disclosure is not limited thereto, and the defect detection circuit 21 may also generate a shutdown signal VS at time points t501 to t503.

[0100] The description of the time period between time point t501 and time point t503 can be applied to the time period between time point t505 and time point t507. Furthermore, the description of the time period between time point t503 and time point t505 can be applied to the time period between time point t507 and time point t509.

[0101] Figure 8 This is a diagram used to illustrate an embodiment of the display system.

[0102] refer to Figure 8 The display system 700 in the embodiment may include a processor 710, a memory 720, a display device 730, and a peripheral device 740 electrically connected to the system bus 750.

[0103] The processor 710 controls the input / output of data to the memory 720, the display device 730, and the peripheral device 740, and can perform image processing on image data transmitted between the corresponding devices.

[0104] Memory 720 may include volatile memory such as dynamic random access memory (“DRAM”) and / or non-volatile memory such as flash memory. Memory 720 may consist of DRAM, phase-change random access memory (“PRAM”), magnetic random access memory (“MRAM”), resistive random access memory (“ReRAM”), ferroelectric random access memory (“FRAM”), NOR flash memory, NAND flash memory, and fused flash memory (e.g., a memory combining a static random access memory (“SRAM”) buffer, NAND flash memory, and NOR interface logic). Memory 720 may store image data obtained from peripheral device 740 or video signals processed by processor 710.

[0105] The display device 730 includes a display panel 731, and can display image data transmitted via the system bus 750 on the display panel 731. The display panel 731 may be... Figure 1 The display panel 30 shown. The display panel 731 may include driving circuitry (in Figure 8 The indicator is "DC" 732. The drive circuit 732 can apply different measurement reference voltages to adjacent (nearby) first and second data lines among the multiple data lines in the display panel 731, and can detect whether the display panel 731 is defective based on the current flowing according to the application of the measurement reference voltage.

[0106] Peripheral device 740 may be a device that converts moving or still images into electrical signals (such as a camera, scanner, webcam, etc.). Image data acquired by peripheral device 740 may be stored in memory 720 or displayed in real time on display panel 731.

[0107] The display system 700 can be equipped in mobile electronic products such as smartphones, but is not limited to them, and can be equipped in various types of electronic products that display images.

[0108] In some embodiments, reference Figures 1 to 7 Each of the components described, or a combination of two or more components, can be implemented as a digital circuit, a programmable or non-programmable logic device or array, or an application-specific integrated circuit (“ASIC”), etc.

[0109] Although the invention has been described in conjunction with embodiments now considered to be practical, it will be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the claims.

Claims

1. A display device, comprising: A pixel array, comprising multiple pixels connected to multiple data lines; The timing controller is configured to generate a reference voltage; as well as Data drives, including: A first sensing amplifier is configured to output a first measurement reference voltage corresponding to a first data line among the plurality of data lines; The second sensing amplifier is configured to output a second measurement reference voltage, which is less than the first measurement reference voltage, corresponding to a second data line that is adjacent to the first data line among the plurality of data lines; and A defect detection circuit, connected to the second sensing amplifier, is configured to generate a shutdown signal based on a comparison between an input voltage received from the second sensing amplifier and the reference voltage.

2. The display device according to claim 1, wherein: The second sensing amplifier includes a first input terminal configured to receive the second measurement reference voltage, an output stage connected to the second data line, and a second input terminal connected to the output stage via a feedback path.

3. The display device according to claim 2, wherein: The output stage includes a first transistor of a first type and a second transistor of a second type connected in series with the first transistor, and the output node between the first transistor and the second transistor is connected to the second data line.

4. The display device according to claim 3, wherein: The defect detection circuit is configured to receive the voltage input to the gate of the second transistor as the input voltage.

5. The display device according to claim 4, wherein: The defect detection circuit includes a current mirror circuit and a first amplifier, and The current mirror circuit includes: a third transistor of the second type, configured to receive the input voltage as a gate voltage and having a source connected to a first power node; a fourth transistor of the first type connected in series with the third transistor; a fifth transistor of the first type, having a common gate with the fourth transistor and having a source connected to the first power node; and a first resistor connected to the drain of the fifth transistor. The first amplifier is configured to generate the shutdown signal based on the sensed voltage at the node between the fifth transistor and the first resistor and the reference voltage.

6. The display device according to claim 5, wherein: The first type is p, and the second type is n.

7. The display device according to claim 1, wherein: The timing controller is configured to control the operation of the display device based on the power-off signal.

8. The display device according to claim 7, wherein: When the power-off signal has a value greater than the reference voltage, the timing controller is configured to stop the operation of the display device.

9. The display device according to claim 7, wherein: When the power-off signal is greater than a value obtained by adding the reference voltage to a predetermined first threshold, the timing controller stops the operation of the display device.

10. The display device according to any one of claims 1 to 9, wherein: The multiple data lines include multiple first data lines and multiple second data lines, and the multiple first data lines and multiple second data lines are arranged alternately.

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