Display panel, driving method thereof and display device

Abstract

The embodiment of the invention discloses a display panel, a driving method thereof and a display device. Initialization voltage is transmitted to a first electrode or a second electrode of a driving transistor through a first function module in an initialization time period; the duration of the initialization time periods of the at least two working frames is set to be different, the first initialization voltages of the at least two working frames are set to be different, each initialization time period comprises at least one initialization sub-time period, and the number of the initialization sub-time periods of the at least two working frames is different; the number of the initialization sub-periods in each of the at least two working frames is at least one, so that the brightness change directions of the sub-pixels for displaying low gray scales and the sub-pixels for displaying high gray scales in the display panel in the same working period are the same, for example, the brightness change directions are gradually reduced. And the duration of the light-emitting time periods of the at least two working frames is set to be different, so that the brightness reduction of the sub-pixels for displaying high gray scales and the sub-pixels for displaying low gray scales is compensated, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for screen display effects.

[0003] The existing technology still suffers from poor display quality. Summary of the Invention

[0004] This invention provides a display panel and its driving method and display device to improve the display effect of the display panel and enhance the user experience.

[0005] According to one aspect of the present invention, a display panel is provided, including an electrically connected light-emitting module and a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control module, and a first functional module. The light-emitting control module, the light-emitting module, and the driving transistor are connected in series between a first power line and a second power line. The first functional module is connected to a first or second terminal of the driving transistor. The first functional module is connected to a first initialization voltage and is used to transmit the first initialization voltage to the first or second terminal of the driving transistor when it is turned on. Each working cycle of at least one working cycle of the pixel circuit includes multiple working frames, each working frame including a light emission period, and at least one working frame also including an initialization period; during at least a portion of the initialization period, a first functional module is turned on; during the light emission period, a light emission control module is turned on; the durations of the light emission periods in at least two working frames are different. The initialization periods of at least two working frames are of different durations, and / or the first initialization voltages of at least two working frames are different, and / or the initialization periods include at least one initialization sub-period, the number of initialization sub-periods of at least two working frames is different, and / or the number of initialization sub-periods in each of the at least two working frames is multiple.

[0006] According to another aspect of the present invention, a display device is provided, including a display panel according to any embodiment of the present invention.

[0007] According to another aspect of the present invention, a driving method for a display panel is provided. The display panel includes an electrically connected light-emitting module and a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control module, and a first functional module. The light-emitting control module, the light-emitting module, and the driving transistor are connected in series between a first power line and a second power line. The first functional module is connected to a first or second terminal of the driving transistor. The first functional module is connected to a first initialization voltage and is used to transmit the first initialization voltage to the first or second terminal of the driving transistor when it is turned on. Each of at least one operating cycles of the pixel circuit includes multiple operating frames, each operating frame including a light emission period, and at least one operating frame also including an initialization period; in each of the at least one operating cycle, the driving method includes: During at least a portion of the initialization period, the first functional module is activated; During the light-emitting period, the light-emitting control module is turned on; the duration of the light-emitting period is different for at least two working frames; The initialization periods of at least two working frames are of different durations, and / or the first initialization voltages of at least two working frames are different, and / or the initialization periods include at least one initialization sub-period, the number of initialization sub-periods of at least two working frames is different, and / or the number of initialization sub-periods in each of the at least two working frames is multiple.

[0008] The display panel, driving method, and display device of this invention transmit an initialization voltage to the first or second electrode of the driving transistor during at least a portion of the initialization period via a first functional module. The initialization period durations of at least two working frames are set to be different, the first initialization voltages of at least two working frames are different, the number of initialization periods in each of the at least two working frames is multiple, the initialization period includes at least one initialization sub-period, the number of initialization sub-periods of at least two working frames is different, and the number of initialization sub-periods in each of the at least two working frames is multiple. This ensures that the brightness change direction of sub-pixels displaying low grayscale and sub-pixels displaying high grayscale in the same working cycle is the same, for example, both gradually decreasing. Furthermore, the durations of the light-emitting periods of at least two working frames are set to be different. By setting the relationship between the light-emitting durations of the light-emitting periods in different working frames, the brightness change of sub-pixels displaying high grayscale and sub-pixels displaying low grayscale is compensated, for example, decreased, thereby improving the flicker phenomenon of the display panel and enhancing the display effect.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the output characteristic curve of the driving transistor; Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 7 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 8 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 9a This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 9b This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 9c This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 10 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 11 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 12 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 14 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 15 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 16 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 17 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 18 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 19aThis is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 19b This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 19c This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 20 It is a curve of the luminous brightness at the first grayscale of the first display brightness level; Figure 21 It is a curve of the luminous brightness of the first display grayscale at the second display brightness level; Figure 22 It is a curve of the luminous brightness at the second grayscale of the first display brightness level; Figure 23 It is a graph of the luminous intensity at the second grayscale level of the second display brightness level; Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention; Figure 25 This is a flowchart of a display panel driving method provided in an embodiment of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. At least one may include one or more. At least part may include some or all. The first and second directions intersect, for example, they may be perpendicular. Connections may include direct connections and / or indirect connections.

[0014] As described in the background section, existing technologies still suffer from poor display quality. The inventors have discovered that this problem arises because, during low-frequency, high-grayscale display, the brightness of the display panel gradually decreases due to transistor leakage in the pixel circuit. Furthermore, during low-frequency, low-grayscale display, the low driving current causes a gradual increase in brightness within a single frame during the light-emitting module's startup process (equivalent to gradually charging the parasitic capacitance of the LED through the driving current, where the parasitic capacitance is connected in series with the LED). Both of these phenomena cause flickering on the display panel, affecting its display quality and user experience. In the same working cycle, when the same display screen includes both high-grayscale and low-grayscale sub-pixels, the significant difference in brightness between these sub-pixels leads to poor display quality.

[0015] For the reasons stated above, embodiments of the present invention provide a display panel. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 1 The display panel includes multiple sub-pixels, and each sub-pixel may include an electrically connected light-emitting module 200 and a pixel circuit 100. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 2 The pixel circuit includes a driving transistor 110, a light-emitting control module 120, and a first functional module 130. The light-emitting control module 120, the light-emitting module 120, and the driving transistor 110 are connected in series between the first power line ELVDD and the second power line ELVSS. The first functional module 130 is connected to the first or second terminal of the driving transistor 110 and is connected to a first initialization voltage VEH. When the module is turned on, the first initialization voltage VEH is transmitted to the first or second terminal of the driving transistor 110. The display panel's operating mode includes a first mode. In the first mode, each operating cycle of at least one operating cycle of the pixel circuit includes multiple operating frames, each operating frame including a light-emitting period, and at least one operating frame. It also includes an initialization period; during at least a portion of the initialization period, the first functional module 130 is turned on; during the light emission period, the light emission control module 120 is turned on; the durations of the light emission periods of at least two working frames are different, the durations of the initialization periods of at least two working frames are different, and / or, the first initialization voltage VEH of at least two working frames is different, and / or, the number of initialization periods in at least two working frames is different, and / or, the initialization period includes at least one initialization sub-period, the number of initialization sub-periods of at least two working frames is different, and / or, the number of initialization periods in each of at least two working frames is multiple, and / or, the number of initialization sub-periods in each of at least two working frames is multiple.

[0016] Specifically, the light-emitting control module 120, the light-emitting module 200, and the driving transistor 110 are connected in series between the first power line ELVDD and the second power line ELVSS. In some embodiments, the light-emitting control module 120 is connected between the first power line ELVDD and the first terminal of the driving transistor 110, and the light-emitting module 200 is connected in series between the second terminal of the driving transistor 110 and the second power line ELVSS. In other embodiments, the light-emitting control module 120 includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is connected between the second terminal of the driving transistor 110 and the first terminal of the light-emitting module 200, and the second light-emitting control unit is connected between the first power line ELVDD and the first terminal of the driving transistor 110. The second terminal of the light-emitting module 200 is connected to the second power line ELVSS. The light-emitting module 200 may include a light-emitting diode, such as an organic light-emitting diode.

[0017] In this embodiment of the invention, the operating mode of the display panel includes a first mode, which may be a low-frequency display mode of the display panel. For example, in the low-frequency display mode, the refresh rate of the display panel is less than or equal to 60Hz. In the first mode, each operating cycle of at least one operating cycle of the pixel circuit includes multiple operating frames. Optionally, the multiple operating frames may include a write frame and at least one hold frame. Each operating frame includes a light-emitting period, and at least one operating frame also includes an initialization period. Optionally, each hold frame includes an initialization period, and within the same operating frame, the initialization period occurs before at least one light-emitting period. Each operating frame may include a non-light-emitting period, which may or may not include the initialization period; this embodiment of the invention does not specifically limit this.

[0018] The pixel circuit also includes a first functional module 130, which is connected to the first or second terminal of the driving transistor 110. During at least a portion of the initialization period, the first functional module 130 is turned on, for example, when the initialization period includes at least one initialization sub-period. During the initialization sub-period, the first functional module 130 is turned on to transmit the first initialization voltage VEH to the first or second terminal of the driving transistor 110, thereby changing the bias stress on the driving transistor 110 and causing the threshold voltage of the driving transistor 110 to be biased, for example, it can be negatively biased or positively biased. For example, the driving transistor 110 is a P-type transistor. By transmitting the first initialization voltage VEH to the first or second terminal of the driving transistor 110 during the initialization period, the threshold voltage of the driving transistor 110 is negatively biased. Figure 3 This is a schematic diagram of the output characteristic curve of the driving transistor 110. Figure 3In the figure, the abscissa represents the gate-source voltage difference Vgs of the driving transistor 110, and the ordinate represents the driving current Id generated by the driving transistor 110. Figure 3 The situation shown corresponds to the case where the driving transistor 110 is a P-type transistor. As Figure 3 shown, three output characteristic curves are shown, which are respectively denoted as the first curve L1, the second curve L2, and the third curve L3. Among them, the first curve L1 corresponds to the threshold voltage of the driving transistor 110 being Vth1, the second curve L2 corresponds to the threshold voltage of the driving transistor 110 being Vth2, and the third curve L3 corresponds to the threshold voltage of the driving transistor 110 being Vth3, and Vth3 < Vth2 < Vth1. According to Figure 3 it can be known that at the same gate-source voltage difference Vgs (for example Figure 3 Vgs0 in the figure), the magnitude relationship of the driving currents corresponding to the first curve L1, the second curve L2, and the third curve L3 is Id1 > Id2 > Id3, where Id1 is the driving current corresponding to the threshold voltage being Vth1, Id2 is the driving current corresponding to the threshold voltage being Vth2, and Id3 is the driving current corresponding to the threshold voltage being Vth3. That is, after the threshold voltage undergoes a negative shift, at the same gate-source voltage difference, the driving current generated by the driving transistor 110 decreases.

[0019] In some embodiments, by controlling the first initialization voltage VEH corresponding to at least two working frames to be different, the bias stress on the driving transistor 110 during the initialization period of at least two working frames is different, thereby causing the threshold voltage offset of the driving transistor 110 to be different. Optionally, in at least two working frames, under the initialization voltage corresponding to the later working frame, the absolute value of the bias stress on the driving transistor 110 is greater than the absolute value of the bias stress on the driving transistor 110 under the initialization voltage of the earlier working frame. For example, by gradually changing the offset stress applied to the driving transistor 110 according to the sequence of working frames (that is, by gradually changing the initial voltage corresponding to different working frames in the same direction according to the time sequence), the negative bias of the driving transistor 110 (driving transistor 110 is a P-type transistor) is gradually enhanced, or the positive bias of the driving transistor 110 (driving transistor 110 is an N-type transistor) is gradually enhanced. This results in the driving current generated by the driving transistor 110 in later working frames being less than the driving current generated by the driving transistor 110 in earlier working frames. Consequently, the brightness of both high grayscale and low grayscale display images gradually decreases, achieving the opposite direction of brightness change in low grayscale images in related technologies. And / or, the brightness change direction of sub-pixels displaying low grayscale and sub-pixels displaying high grayscale in the same working cycle is the same, for example, both gradually decrease (when the light emission period is the same in different working frames). The system sets at least two working frames with different durations for the light emission periods. By setting the relationship between the light emission durations in different working frames, it compensates for the brightness decrease of sub-pixels displaying high grayscale and sub-pixels displaying low grayscale, thereby improving the flicker phenomenon of the display panel and enhancing the display effect of the display panel.

[0020] In other embodiments, the initialization periods of at least two working frames have different durations, resulting in different times for the initialization voltage to be transmitted to the first or second terminal of the driving transistor 110 during the initialization period in the at least two working frames. The longer the initialization period, the more fully the initialization voltage is written to the first or second terminal of the driving transistor 110. When the initialization period is insufficient, the initialization voltage cannot be fully written to the first or second terminal of the driving transistor 110, and the first functional module 130 is turned off. Therefore, by controlling the duration of the initialization periods corresponding to at least two working frames to be different, the sufficiency of writing the initialization voltage to the first or second terminal of the driving transistor 110 during the initialization period of different working frames is different, resulting in different bias stresses on the driving transistor 110 and different threshold voltage offset values ​​in different working frames. Optionally, in the at least two working frames, the duration of the initialization period corresponding to the later working frame is greater than the duration of the initialization period corresponding to the earlier working frame. For example, the duration of the initialization period is gradually changed according to the order of the working frames (e.g., according to the time sequence, the duration of the initialization period corresponding to different working frames gradually changes in the same direction, such as gradually increasing), thereby gradually enhancing the sufficiency of writing the initialization voltage to the first or second electrode of the driving transistor 110. This results in the negative bias gradually increasing (driving transistor 110 is a P-type transistor) or the positive bias gradually increasing (driving transistor 110 is an N-type transistor) according to the order of the working frames. Consequently, the driving current generated by the driving transistor 110 in later working frames is less than the driving current generated by the driving transistor 110 in earlier working frames. This causes the brightness to gradually decrease in both high and low grayscale display images, achieving the opposite direction of brightness change in low grayscale images in related technologies. And / or, it causes the brightness change direction of sub-pixels displaying low grayscale and sub-pixels displaying high grayscale in the same working cycle to be the same, for example, both gradually decreasing (when the light emission period is the same in different working frames). The system sets at least two working frames with different durations for the light emission periods. By setting the relationship between the light emission durations in different working frames, it compensates for the brightness decrease of sub-pixels displaying high grayscale and sub-pixels displaying low grayscale, thereby improving the flicker phenomenon of the display panel and enhancing the display effect of the display panel.

[0021] In other embodiments, the number of initialization periods in at least two working frames is different, or the initialization period is set to include at least one initialization sub-period, and the number of initialization sub-periods in at least two working frames is different. The initialization period includes the time from the start time of the first initialization sub-period to the end time of the last initialization period. Optionally, there is a time interval between adjacent initialization sub-periods in the same initialization period. Optionally, the duration of each (or more) initialization sub-periods is equal. Wherein, the more initialization sub-periods included in the initialization period, the longer the initialization period, and the more fully the initialization voltage is written to the first or second terminal of the driving transistor 110. When the number of initialization sub-periods included in the initialization period is small, resulting in insufficient duration of the initialization period, the initialization voltage cannot be fully written to the first or second terminal of the driving transistor 110, and the first functional module 130 is turned off. Therefore, by controlling the number of initialization sub-periods included in the initialization period corresponding to at least two working frames to be different, the duration of the initialization period corresponding to at least two working frames is made different. This results in different sufficiency of writing initialization voltage to the first or second terminal of the driving transistor 110 during the initialization period of different working frames, thereby causing different bias stresses on the driving transistor 110 and different threshold voltage offset values ​​in different working frames. Optionally, in at least two working frames, the number of initialization sub-periods included in the initialization period corresponding to the later working frame is greater than the number of initialization sub-periods included in the initialization period corresponding to the earlier working frame. For example, the number of initialization sub-segments included in the initialization period gradually changes according to the order of the working frames (e.g., according to the time sequence, the number of initialization sub-segments included in the initialization period corresponding to different working frames gradually changes in the same direction, e.g., gradually increasing). Correspondingly, the duration of the initialization period gradually changes, thereby gradually enhancing the sufficiency of writing the initialization voltage to the first or second electrode of the driving transistor 110. This results in the negative bias gradually increasing (driving transistor 110 is a P-type transistor) or the positive bias gradually increasing (driving transistor 110 is an N-type transistor) according to the order of the working frames. This causes the driving current generated by the driving transistor 110 in later working frames to be less than the driving current generated by the driving transistor 110 in earlier working frames. Consequently, the brightness gradually decreases in both high and low grayscale display images, achieving the opposite direction of brightness change in low grayscale images to that in related technologies. And / or, it causes the brightness change direction of sub-pixels displaying low grayscale and sub-pixels displaying high grayscale in the same working cycle to be the same, e.g., both gradually decreasing (when the light emission period is the same in different working frames). The system sets at least two working frames with different durations for the light emission periods. By setting the relationship between the light emission durations in different working frames, it compensates for the brightness decrease of sub-pixels displaying high grayscale and sub-pixels displaying low grayscale, thereby improving the flicker phenomenon of the display panel and enhancing the display effect of the display panel.

[0022] In other embodiments, the number of initialization periods in each of at least two working frames is multiple (e.g., 2 or at least 3), and / or the number of initialization sub-periods in each of at least two working frames is multiple (e.g., 2 or at least 3). The larger number of initialization periods and / or initialization sub-periods in a working frame means that within one or each working cycle, as time increases, the initialization voltage is written more fully to the first or second electrode of the driving transistor 110, gradually increasing the sufficiency of the initialization voltage written to the first or second electrode of the driving transistor 110, gradually increasing the negative bias (if the driving transistor 110 is a P-type transistor), or gradually increasing the positive bias (if the driving transistor 110 is an N-type transistor). This results in the driving current generated by the driving transistor 110 in later working frames being less than the driving current generated by the driving transistor 110 in earlier working frames, causing the brightness to gradually decrease in both high and low grayscale display images, achieving the opposite direction of brightness change in low grayscale images in related technologies. And / or, to ensure that the brightness change direction of sub-pixels displaying low grayscale and sub-pixels displaying high grayscale in the same working cycle is the same, for example, both gradually decreasing (when the light emission period is the same in different working frames). And to set the light emission period duration to be different in at least two working frames, the brightness decrease of sub-pixels displaying high grayscale and sub-pixels displaying low grayscale is compensated by setting the relationship between the light emission period duration in different working frames, thereby improving the flicker phenomenon of the display panel and enhancing the display effect. For example, the number of initialization periods in at least two working frames is multiple and equal, or multiple and unequal. And / or, the number of initialization sub-periods in at least two working frames is multiple and equal, or multiple and unequal.

[0023] It should be noted that the above embodiments can be combined with each other, that is, the embodiments of the present invention can satisfy at least one of the following three conditions: 1) the first initialization voltage VEH corresponding to at least two working frames is different; 2) the duration of the initialization period of at least two working frames is different; 3) the number of initialization periods in at least two working frames is different, or, the initialization period includes at least one initialization sub-period, and the number of initialization sub-periods in at least two working frames is different; 4) the number of initialization periods in each of at least two working frames is multiple, and / or, the number of initialization sub-periods in each of at least two working frames is multiple. In this way, the brightness change direction is the same under low grayscale and high grayscale, that is, in each display cycle (i.e., working cycle or screen refresh cycle), the brightness gradually decreases with time.

[0024] In this embodiment of the invention, the pixel circuit further includes a light-emitting control module 120. During the light-emitting period, the light-emitting control module 120 is turned on, driving the light-emitting module 200 to emit light using the driving current generated by the driving transistor 110. The duration of the light-emitting period is different for at least two working frames. Specifically, when the driving module outputs the same driving current, the longer the duration of the light-emitting period within a working frame, the greater the brightness perceived by the human eye. By setting different durations for the light-emitting periods in at least two working frames, the brightness decrease under high grayscale sub-pixels and low grayscale sub-pixels can be compensated by setting the relationship between the light-emitting durations in different working frames. Optionally, in at least two working frames, the duration of the light-emitting period in the later working frame is longer than the duration of the light-emitting period in the earlier working frame. In some embodiments, the duration of the light-emitting period gradually increases according to the order of the working frames. Thus, by increasing the light-emitting duration of the later working frames, the brightness decrease under high grayscale sub-pixels and low grayscale sub-pixels is compensated, improving the problem of brightness decreasing over time and thus improving the flickering phenomenon of the display panel.

[0025] In this embodiment, the display panel transmits an initialization voltage to the first or second electrode of the driving transistor during the initialization period via a first functional module. The initialization period duration is set to be different for at least two working frames, the first initialization voltage is different for at least two working frames, the number of initialization periods in at least two working frames is different, the number of initialization periods in each of the at least two working frames is multiple, the initialization period includes at least one initialization sub-period, the number of initialization sub-periods in the at least two working frames is different, and the number of initialization sub-periods in each of the at least two working frames is multiple. This ensures that the brightness change direction of the display panel, including both low-grayscale sub-pixels and high-grayscale sub-pixels, gradually decreases within the working cycle. Furthermore, the duration of the light-emitting period is set to be different for at least two working frames. By setting the relationship between the light-emitting periods in different working frames, the brightness decrease under high-grayscale sub-pixels and low-grayscale sub-pixels is compensated, thereby improving the flicker phenomenon of the display panel and enhancing its display effect.

[0026] For example, in the same screen in the first mode, the gray levels corresponding to multiple pixel circuits on the display panel are different. For example, some pixel circuits correspond to high gray levels (e.g., greater than 64 gray levels), while other pixel circuits correspond to low gray levels (e.g., less than or equal to 64 gray levels).

[0027] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 6This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. (Reference) Figures 4-6 Optionally, the first terminal of the first functional module 130 is connected to the first initialization voltage VEH, and the second terminal of the first functional module 130 is connected to the first or second terminal of the driving transistor 110 (wherein, Figure 4 and Figure 6 The diagram shows the connection between the second terminal of the first functional module 130 and the first terminal of the driving transistor 110. Figure 5 (The diagram shows the second terminal of the first functional module 130 connected to the second terminal of the driving transistor 110). The control terminal of the first functional module 130 is connected to the first control signal G1. The pixel circuit also includes an initialization module 140. The first terminal of the initialization module 140 is connected to the second initialization voltage VREFN1, and the second terminal of the initialization module 140 is connected to the first terminal of the light-emitting module 200. The control terminal of the initialization module 140 is connected to the first control signal G1. Optionally, the initialization module 140 and the first functional module 130 include transistors of the same channel type, for example, both include P-type transistors. When the first functional module 130 is turned on, the light-emitting control module 120 can be turned off. When the light-emitting control module 120 is turned on, the first functional module 130 can be turned off.

[0028] In this embodiment, when the initialization module 140 is turned on, it transmits a first initialization voltage VEH to the first end of the light-emitting module 200, thereby clearing the residual charge on the first end of the light-emitting module 200 from the previous frame and improving the display effect. In this embodiment, the control terminal of the initialization module 140 and the control terminal of the first functional module 130 are connected to the same signal. On the one hand, this reduces the number of signal lines connected to the pixel circuit, simplifies the wiring of the display panel, and optimizes the layout of the display panel. On the other hand, it allows the initialization module 140 and the first functional module 130 to be turned on and off simultaneously, resulting in different transmission durations of the second initialization voltage VREFN1 to the first end of the light-emitting module 200 in at least two working frames, and / or, the initialization period of at least two working frames is divided into different numbers of initialization sub-periods to transmit the second initialization voltage VREFN1 to the first end of the light-emitting module 200. This achieves differentiated transmission of the second initialization voltage VREFN1 to the first end of the light-emitting module 200 in at least two working frames, which is more conducive to improving the flickering phenomenon of the light-emitting module 200.

[0029] Continue to refer to Figures 4-6Optionally, the light-emitting control module 120 includes a first light-emitting control unit 121, which is connected between the first terminal of the light-emitting module 200 and the second terminal of the driving transistor 110. The first light-emitting control unit 121 can control the conduction state between the second terminal of the driving transistor 110 and the first terminal of the light-emitting module 200. During the light-emitting period, the first light-emitting control unit 121 is turned on; during the non-light-emitting period outside the light-emitting period, the first light-emitting control unit 121 is turned off.

[0030] Optionally, each working frame in at least one working cycle of the pixel circuit includes a write frame and at least one hold frame following the write frame; the write frame includes a first emission period; and the hold frame includes a second initialization period and a second emission period.

[0031] In some embodiments, the write frame further includes a first initialization period, which precedes the first emission period. The initialization period included in the write frame is denoted as the first initialization period, and the emission period included in the write frame is denoted as the first emission period; the initialization period included in the hold frame is denoted as the second initialization period, and the emission period included in the hold frame is denoted as the second emission period.

[0032] Continue to refer to Figures 4-6 Optionally, the pixel circuit also includes a data writing module 150, which is connected to the gate or first electrode of the driving transistor 110. The first end of the data writing module 150 is connected to the data line Data (which can transmit data voltage), and the other end is connected to the gate or first electrode of the driving transistor 110. Figures 4-6 The diagram schematically illustrates the connection between the data writing module 150 and the first terminal of the driving transistor 110. Optionally, the pixel circuit also includes a compensation module 160, and the light-emitting control module 120 includes a second light-emitting control unit 122. The compensation module 160 is connected between the second terminal and the gate of the driving transistor 110, and the second light-emitting control unit 122 is connected between the first power line ELVDD and the first terminal of the driving transistor 110. The compensation module 160 transmits a voltage related to the data voltage and the threshold voltage of the driving transistor 110 to the gate of the driving transistor 110. The second light-emitting control unit 122 can control the conduction state between the first power line ELVDD and the first terminal of the driving transistor 110. During the light-emitting period, the second light-emitting control unit 122 is turned on; during non-light-emitting periods, the second light-emitting control unit 122 is turned off. Figures 3-5 As shown, optionally, the control terminal of the second light-emitting control unit 122 and the control terminal of the first light-emitting control unit 121 are both connected to the light-emitting control signal line EM.

[0033] Optionally, the write frame also includes a data write period, which includes at least one data write sub-period; the data write module 150 and the compensation module 160 are turned on during the data write sub-period to realize the data write period, writing a voltage related to the data voltage and the threshold voltage of the drive transistor 110 to the gate of the drive transistor 110.

[0034] Continue to refer to Figures 4-6 Optionally, the pixel circuit also includes a gate reset module 170, which is connected to the gate of the driving transistor 110; the write frame also includes a gate reset period, which includes at least one gate reset sub-period, which is performed before the corresponding data write sub-period; the gate reset module 170 is turned on during the gate reset sub-period; the gate reset module 170 is connected to the second control signal S1.

[0035] Optionally, the number of gate reset sub-periods and data write sub-periods are equal, with each gate reset sub-period corresponding to one data write sub-period. The gate reset sub-period occurs before the corresponding data write sub-period. For example, within the same write frame, the gate reset sub-period and data write sub-period can be alternated. During the gate reset sub-period, the gate reset module 170 is turned on in response to the conduction pulse in the second control signal S1; outside the gate reset sub-period, the gate reset module 170 is turned off in response to the cutoff pulse in the second control signal S1. Setting the gate reset module 170 can clear the residual charge on the gate of the driving transistor 110 from the previous frame, thereby improving the display effect.

[0036] Optionally, the gate reset module 170 is connected to the second terminal of the driving transistor 110. During the gate reset period or gate reset sub-period, the gate reset module 170 and the compensation module 160 are turned on, transmitting the gate reset voltage VREFN2 to the gate of the driving transistor 110 through the turned-on gate reset module 170 and compensation module 160, thereby resetting the gate of the driving transistor 110.

[0037] Optionally, the pixel circuit further includes a storage module 180, which is connected to the gate of the driving transistor 110. In some embodiments, a first terminal of the storage module 180 is connected to the gate of the driving transistor 110, and a second terminal of the storage module 180 is connected to a first power supply line ELVDD. The storage module 180 may include a storage capacitor Cst.

[0038] Figure 7 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 8 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 9a This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Wherein, Figures 7-9aThe driving timing shown can be used for driving. Figure 4 or Figure 5 The pixel circuit shown. (Reference) Figure 4 , Figure 5 as well as Figures 7-9a In some embodiments, the data writing module 150 and the compensation module 160 are connected to the third control signal S2; in each first initialization period, the first control signal G1 includes at least one first conduction pulse, and in each second initialization period, the first control signal G1 includes at least one first conduction pulse; in each gate reset period, the second control signal S1 includes at least one second conduction pulse; in each data writing period, the third control signal S2 includes at least one third conduction pulse; wherein the third conduction pulse of the third control signal S2 follows the corresponding second conduction pulse.

[0039] Each first conduction pulse can correspond to an initialization sub-period, and each second conduction pulse can correspond to a gate reset sub-period. Each third conduction pulse corresponds to a data writing sub-period. Optionally, in the last data writing sub-period of the write frame, the data writing module 150 writes the corresponding data voltage to the driving transistor 110. In the data writing sub-periods before the last data writing sub-period, the data voltage written by the data writing module 150 is the data voltage corresponding to the pixel circuit preceding the pixel circuit where the data writing module 150 is located. Within a working frame, the number of second conduction pulses included in the second control signal S1 is equal to the number of third conduction pulses included in the third control signal S2, and each third conduction pulse corresponds to one second conduction pulse. For example, within the same write frame, the second conduction pulse and the third conduction pulse are alternately set. The duration of the conduction level corresponding to the first conduction pulse can correspond to an initialization sub-period.

[0040] The following are Figure 4 and Figure 5 The pixel circuit shown is described in one working cycle. Taking as an example, the driving transistor 110 includes a first transistor T1, the data writing module 150 includes a second transistor T2, the compensation module 160 includes a third transistor T3, the gate reset module 170 includes a fourth transistor T4, the first light-emitting control unit 121 includes a sixth transistor T6, the second light-emitting control unit 122 includes a fifth transistor T5, the initialization module 140 includes a seventh transistor T7, the first functional module 130 includes an eighth transistor T8, and the storage module 180 includes a storage capacitor Cst, and all transistors in the pixel circuit are P-type transistors. Optionally, the third transistor T3 and the fourth transistor T4 are dual-gate transistors. Specifically, the third transistor T3 includes a first sub-transistor T3_1 and a second sub-transistor T3_2 connected in series; the fourth transistor T4 includes a third sub-transistor T4_1 and a fourth sub-transistor T4_2 connected in series.

[0041] refer to Figure 4 , Figure 5 , Figures 7-9a During the write frame XF, the operation of the pixel circuit includes a gate reset period, a data write period, a first initialization period t31, and a first light emission period t41; during the hold frame BF, the operation of the pixel circuit includes a second initialization period t32 and a second light emission period t42.

[0042] During the gate reset period, in each gate reset sub-period t1, the second control signal S1 is at the on level (i.e., the second on pulse), for example, at a low level. The fourth transistor T4 is turned on, transmitting the gate reset voltage VREFN2 to the gate of the driving transistor 110, thereby resetting the gate of the driving transistor 110.

[0043] During the data writing period, in each data writing sub-period t2, the third control signal S2 is at the on level (i.e., the third on pulse), for example, at a low level. The second transistor T2 and the third transistor T3 are turned on, transmitting a voltage related to the data voltage and the threshold voltage of the driving transistor 110 to the gate of the driving transistor 110 until the voltage difference between the gate and the first electrode of the driving transistor 110 equals the threshold voltage of the driving transistor 110.

[0044] During the first initialization period t31 (e.g., the initialization sub-stage of the first initialization period t31), the first control signal G1 is at the on level (i.e., the first on pulse), for example, at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 transmits the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200, and the eighth transistor T8 transmits the first initialization voltage VEH to the first terminal of the driving transistor 110. Figure 4 (The pixel circuit shown) or the second pole ( Figure 5 (as shown in the pixel circuit), or, the driving transistor 110 is turned on, and the eighth transistor T8 transmits the first initialization voltage VEH to the first and second terminals of the driving transistor 110. Figures 7 to 9a An example is drawn showing the case where the first initialization period t31 includes an initialization sub-phase.

[0045] During the first light-emitting period t41, the light-emitting control signal EM is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the driving transistor 110 generates a driving current, and drives the light-emitting module 200 to emit light.

[0046] During the second initialization period t32 (e.g., the initialization sub-stage of the second initialization period t32), the first control signal G1 is at the on level (i.e., the first on pulse), for example, at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 transmits the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200, and the eighth transistor T8 transmits the first initialization voltage VEH to the first terminal of the driving transistor 110. Figure 4 (The pixel circuit shown) or the second pole ( Figure 5 (as shown in the pixel circuit), or, the driving transistor 110 is turned on, and the eighth transistor T8 transmits the first initialization voltage VEH to the first and second terminals of the driving transistor 110. Figures 7 to 9a An example is drawn showing the case where the second initialization period t32 includes an initialization sub-phase.

[0047] During the second light-emitting period t42, the light-emitting control signal EM is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on, the driving transistor 110 generates a driving current, and drives the light-emitting module 200 to emit light.

[0048] in, Figures 7-9a Taking a gate reset period consisting of three gate reset sub-periods t1 and a data write period consisting of three data write sub-periods t2 as an example, the data write sub-periods t2 are performed after the corresponding gate reset sub-periods t1, that is, the gate reset sub-periods t1 and the data write sub-periods t2 are set alternately. Specifically, in the third data write sub-period t2, the data write module 150 writes the corresponding data voltage to the gate of the driving transistor 110 of the pixel circuit (e.g., the m-th row pixel circuit, where m can be an integer greater than or equal to 3); in the second data write sub-period t2, the data write module 150 writes the data voltage corresponding to the pixel circuit of the same column in the previous row (e.g., the m-1-th row) to the driving transistor 110 of the pixel circuit; in the first data write sub-period t2, the data write module 150 writes the data voltage corresponding to the pixel circuit of the same column in the previous two rows (e.g., the m-2-th row) to the driving transistor 110 of the pixel circuit.

[0049] For example, the first initialization period t31 includes at least two initialization sub-phases, or the same write frame includes at least two first initialization phases. In the write frame, each first conduction pulse may correspond to one initialization sub-phase, or each first conduction pulse may correspond to one first initialization period. In the write frame, one or each non-emitting phase may include one or more first initialization periods. In the write frame, one or each non-emitting phase may include one or more initialization sub-phases. For example, in the write frame, one or each non-emitting phase may include one first initialization period, or one or each non-emitting phase may include multiple initialization sub-phases.

[0050] Figure 9b This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 The pixel circuit shown is described in the image. Figure 9b For example, the second initialization period t32 includes at least two initialization sub-phases, or the same holding frame includes at least two second initialization phases. In the holding frame, each first conduction pulse may correspond to one initialization sub-phase, or each first conduction pulse may correspond to one second initialization period. In the holding frame, one or each non-emitting phase may include one or more second initialization periods. In the holding frame, one or each non-emitting phase may include one or more initialization sub-phases. For example, in the holding frame, one or each non-emitting phase may include one second initialization period, or one or each non-emitting phase may include multiple initialization sub-phases.

[0051] Figure 9c This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 The pixel circuit shown.

[0052] refer to Figure 6 In other embodiments, the compensation module 160 is connected to the third control signal S2, and the data writing module 150 is connected to the fourth control signal R1. The compensation module 160 and the data writing module 150 are connected to different control signals. Figure 10 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 11 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 12 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Wherein, Figures 10-12 The driving timing shown can be used for driving. Figure 6 The pixel circuit shown. (Reference) Figure 6 as well as Figures 10-12In some embodiments, in each first initialization period t31, the first control signal G1 includes at least two first conduction pulses; in each second initialization period t32, the first control signal G1 includes at least two first conduction pulses; in each gate reset period, the second control signal S1 includes at least two second conduction pulses; the third control signal S2 includes at least two third conduction pulses, wherein, in write frame XF, the third conduction pulse of the third control signal S2 follows the corresponding second conduction pulse; the fourth conduction pulse of the fourth control signal R1 overlaps with the last third conduction pulse; in write frame XF, the last first conduction pulse corresponding to the first initialization period t31 follows the fourth conduction pulse and / or the last third conduction pulse; in write frame XF, the first conduction pulse before the last first conduction pulse corresponding to the first initialization period t31 overlaps with the corresponding third conduction pulse. In write frame XF, the second and third conduction pulses are alternately set.

[0053] Each first conduction pulse corresponds to an initialization sub-period, and each second conduction pulse corresponds to a gate reset sub-period t1. The last third conduction pulse of the third control signal S2 corresponds to the data writing sub-period t2. The first to the penultimate third conduction pulses of the third control signal S2 overlap with the first to the penultimate first conduction pulses, respectively. This ensures that during the first to the penultimate initialization sub-period of the write frame XF, the compensation module 160 is turned on, and the first initialization voltage VEH is transmitted to the gate of the drive transistor 110 through the first functional module 130, the drive transistor 110, and the compensation module 160. This ensures that the same voltage is transmitted to the drive transistor 110 during the first to the penultimate initialization sub-periods before the write frame XF writes the corresponding data voltage-related voltage to the gate of the drive transistor 110, which helps to improve ghosting. The fourth conduction pulse corresponds to the data writing period. The fourth conduction pulse of the fourth control signal R1 overlaps with the last third conduction pulse, so that during the data writing period, the data writing module 150 and the compensation module 160 are turned on simultaneously, thereby transmitting a voltage related to the data voltage and the threshold voltage of the driving transistor 110 to the gate of the driving transistor 110, realizing data voltage writing and threshold voltage compensation.

[0054] Optionally, within a working frame, the interval between the last first conduction pulse and the penultimate first conduction pulse of the first control signal G1 is greater than the interval between two adjacent first conduction pulses in the first control signal G1 that precede the last first conduction pulse.

[0055] The following are Figure 6The pixel circuit shown is explained during one working cycle. Taking as an example, the driving transistor 110 includes a first transistor T1, the data writing module 150 includes a second transistor T2, the compensation module 160 includes a third transistor T3, the gate reset module 170 includes a fourth transistor T4, the first light-emitting control unit 121 includes a sixth transistor T6, the second light-emitting control unit 122 includes a fifth transistor T5, the initialization module 140 includes a seventh transistor T7, the first functional module 130 includes an eighth transistor T8, and the storage module 180 includes a storage capacitor Cst, and assuming that all transistors in the pixel circuit are P-type transistors, this explanation will be provided. (Reference) Figure 6 , Figures 10-12 During the write frame XF, the operation of the pixel circuit includes a gate reset period, a data write period, a first initialization period t31, and a first light emission period t41; during the hold frame BF, the operation of the pixel circuit includes a second initialization period t32 and a second light emission period t42.

[0056] During the gate reset period, in each gate reset sub-period t1, the second control signal S1 is at the on level (i.e., the second on pulse), for example, at a low level. The fourth transistor T4 is turned on, transmitting the gate reset voltage VREFN2 to the gate of the driving transistor 110, thereby resetting the gate of the driving transistor 110.

[0057] During initialization sub-periods other than the last initialization sub-period of the first initialization period t31 (the initialization sub-periods included in the first initialization period t31 are denoted as the first initialization sub-period t3), the first control signal G1 is at a conducting level (i.e., the first conducting pulse), for example, a low level. The seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 transmits the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200, and the eighth transistor T8 transmits the first initialization voltage VEH to the first or second terminal of the driving transistor 110. The third control signal S2 is at a conducting level (i.e., the third conducting pulse), for example, a low level. The third transistor T3 is turned on, and the first initialization voltage VEH is transmitted to the gate of the driving transistor 110 through the third transistor T3 until the voltage difference between the gate and the first terminal of the driving transistor 110 equals the threshold voltage of the driving transistor 110. That is, the voltage related to the first initialization voltage VEH and the threshold voltage of the driving transistor 110 is transmitted to the gate of the driving transistor 110. For example, the second conducting pulse and the third conducting pulse are alternately set.

[0058] During the data writing period, the third control signal S2 is at the on level (i.e., the third on pulse), for example, at a low level, and the fourth control signal R1 is at the on level (i.e., the fourth on pulse), for example, at a low level. The second transistor T2 and the third transistor T3 are turned on, transmitting a voltage related to the data voltage and the threshold voltage of the driving transistor 110 to the gate of the driving transistor 110 until the voltage difference between the gate and the first electrode of the driving transistor 110 equals the threshold voltage of the driving transistor 110.

[0059] During the last initialization sub-period of the first initialization period t31, the first control signal G1 is at the on level (i.e., the first on pulse), for example, at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 transmits the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200, and the eighth transistor T8 transmits the first initialization voltage VEH to the first or second terminal of the driving transistor 110.

[0060] During the first light-emitting period t41, the light-emitting control signal EM is at the on level, for example, low level. The fifth transistor T5 and the sixth transistor T6 are turned on, driving transistor 110 to generate driving current, driving the light-emitting module 200 to emit light.

[0061] During the second initialization period t32, the first control signal G1 is at the conduction level (i.e., the first conduction pulse), for example, at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 transmits the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200, and the eighth transistor T8 transmits the first initialization voltage VEH to the first or second terminal of the driving transistor 110.

[0062] During the second light-emitting period t42, the light-emitting control signal EM is at the on level, for example, low level. The fifth transistor T5 and the sixth transistor T6 are turned on, driving transistor 110 to generate driving current, driving the light-emitting module 200 to emit light.

[0063] in, Figures 10-12 The following example illustrates the process of the gate reset period consisting of three gate reset sub-periods t1 and the initialization period consisting of three initialization sub-periods.

[0064] Figure 13 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 14 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 15 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. Figure 16 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Wherein, Figures 14-16 The driving timing shown can be used for driving. Figure 13The pixel circuit shown. (Reference) Figures 13-16 Optionally, the first functional module 130 is connected to the first terminal of the driving transistor 110, and the first terminal of the first functional module 130 is connected to a data voltage. The pixel circuit also includes a compensation module 160, which is connected between the second terminal and the gate of the driving transistor 110, and the control terminal of the compensation module 160 is connected to a third control signal S2. The light emission control module 120 also includes a second light emission control unit 122, which is connected between the first power line ELVDD and the first terminal of the driving transistor 110. Optionally, the pixel circuit also includes a storage module 180, which is connected to the gate of the driving transistor 110.

[0065] Optionally, the write frame XF further includes a data write period, which includes at least one data write sub-period t2. During the data write period, the first terminal of the first functional module 130 is connected to the data voltage corresponding to the pixel circuit. During the second initialization period t32, the first terminal of the first functional module 130 is connected to the first initialization voltage VEH. In some embodiments, the first terminal of the first functional module 130 is connected to the data line Data. During the data write period, the data line Data transmits the data voltage; during the second initialization period t32, the data line Data transmits the first initialization voltage VEH.

[0066] Optionally, during the write frame, the first turn-on pulse of the first control signal G1 overlaps with the third turn-on pulse of the third control signal S2. Thus, during the overlapping period of the first and third turn-on pulses, the first functional module 130 and the compensation module 160 are simultaneously turned on, thereby writing a voltage related to the data voltage to the gate of the driving transistor 110.

[0067] In some embodiments, in each working frame, the first control signal G1 includes at least two first conduction pulses, and the third control signal S2 includes at least two third conduction pulses. In the write frame, the first conduction pulses overlap with the corresponding third conduction pulses. In this case, the data write period includes at least two data write sub-periods t2, and the second initialization period t32 includes at least two initialization sub-periods. In the data write sub-period t2, the first functional module 130 is turned on in response to the first conduction pulse, and the compensation module 160 is turned on in response to the third conduction pulse, thereby writing a voltage related to the data voltage and the threshold voltage of the driving transistor 110 to the gate of the driving transistor 110. In the initialization sub-period, the first functional module 130 is turned on, and the compensation module 160 is turned off, thereby initializing the first or second terminal of the driving transistor 110.

[0068] Optionally, in the last data writing sub-period t2, the data voltage is the data voltage corresponding to the pixel circuit where the data writing module 150 is located; in the data writing sub-period t2 before the last data writing sub-period t2, the data voltage is the data voltage corresponding to the pixel circuit preceding the pixel circuit where the data writing module 150 is located.

[0069] The following are Figure 13 The pixel circuit shown is explained during one working cycle. Taking as an example, the driving transistor 110 includes a first transistor T1, the compensation module 160 includes a third transistor T3, the gate reset module 170 includes a fourth transistor T4, the first light-emitting control unit 121 includes a sixth transistor T6, the second light-emitting control unit 122 includes a fifth transistor T5, the initialization module 140 includes a seventh transistor T7, the first functional module 130 includes an eighth transistor T8, and the storage module 180 includes a storage capacitor Cst, and assuming that all transistors in the pixel circuit are P-type transistors, this explanation will be provided. (Reference) Figures 13-16 During the write frame XF, the operation of the pixel circuit includes a gate reset period, a data write period, and a first light emission period t41; during the hold frame BF, the operation of the pixel circuit includes a second initialization period t32 and a second light emission period t42.

[0070] During the gate reset period, in each gate reset sub-period t1, the second control signal S1 is at the on level (i.e., the second on pulse), for example, at a low level. The fourth transistor T4 is turned on, transmitting the gate reset voltage VREFN2 to the gate of the driving transistor 110, thereby resetting the gate of the driving transistor 110.

[0071] During the data writing period, in each data writing sub-period t2, the first control signal G1 is at the on level (i.e., the first on pulse), for example, a low level, the eighth transistor T8 is turned on, and the third control signal S2 is at the on level (i.e., the third on pulse), for example, a low level, the third transistor T3 is turned on, transmitting a voltage related to the data voltage and the threshold voltage of the driving transistor 110 to the gate of the driving transistor 110 until the voltage difference between the gate and the first terminal of the driving transistor 110 equals the threshold voltage of the driving transistor 110. During the data writing sub-period t2, the seventh transistor T7 is turned on, transmitting the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200.

[0072] During the first light-emitting period t41, the light-emitting control signal EM is at the on level, for example, low level. The fifth transistor T5 and the sixth transistor T6 are turned on, driving transistor 110 to generate driving current, driving the light-emitting module 200 to emit light.

[0073] During the second initialization period t32, the first control signal G1 is at the on level (i.e., the first on pulse), for example, at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on. The seventh transistor T7 transmits the second initialization voltage VREFN1 to the first terminal of the light-emitting module 200, and the eighth transistor T8 transmits the first initialization voltage VEH to the first and / or second terminals of the driving transistor 110.

[0074] During the second light-emitting period t42, the light-emitting control signal EM is at the on level, for example, low level. The fifth transistor T5 and the sixth transistor T6 are turned on, driving transistor 110 to generate driving current, driving the light-emitting module 200 to emit light.

[0075] in, Figures 14-16 Taking a gate reset period consisting of three gate reset sub-periods t1 and a data write period consisting of three data write sub-periods t2 as an example, the data write sub-periods t2 are performed after the corresponding gate reset sub-periods t1. For example, the gate reset sub-periods t1 and the data write sub-periods t2 are set alternately. Specifically, in the third data write sub-period t2, the data write module 150 writes the corresponding data voltage (e.g., the data voltage corresponding to the m-th row of pixel circuits) to the gate of the driving transistor 110 of the pixel circuit (e.g., the m-th row of pixel circuits, where m can be an integer greater than or equal to 3); in the second data write sub-period t2, the data write module 150 writes the data voltage related to the pixel circuits in the same column of the previous row (e.g., the m-1-th row) to the driving transistor 110 of the pixel circuit; in the first data write sub-period t2, the data write module 150 writes the data voltages corresponding to the pixel circuits in the same column of the previous two rows (e.g., the m-2-th row) to the driving transistor 110 of the pixel circuit.

[0076] Optionally, in each of at least one working cycle, at least two working frames include a first working frame and a second working frame, with the first working frame preceding the second working frame. The first and second working frames satisfy at least one of the following conditions: 1) the duration of the initialization period in the first working frame is less than the duration of the initialization light period in the second working frame (see [reference]). Figure 9a or Figure 9c 2) The first initialization voltage in the first working frame is less than the first initialization voltage in the second working frame, see [reference]. Figure 8 or Figure 9c 3) The number of initialization periods in the first working frame is less than the number of initialization periods in the second working frame, and / or, the number of initialization sub-periods in the first working frame is less than the number of initialization sub-periods in the second working frame. See [reference needed] Figure 9b4) The number of initialization periods in the first working frame is multiple (e.g., 2 or at least 3), and the number of initialization periods in the second working frame is multiple (e.g., 2 or at least 3); and / or, the number of initialization sub-periods in the first working frame is multiple (e.g., 2 or at least 3), and the number of initialization sub-periods in the second working frame is multiple (e.g., 2 or at least 3); and / or, the number of initialization sub-periods in the same initialization period in the first working frame is multiple (e.g., 2 or at least 3), and the number of initialization sub-periods in the same initialization period in the second working frame is multiple (e.g., 2 or at least 3). This ensures that, at both high and low grayscale levels, if the first and second working frames have the same emission period, the brightness of the emission module in the first working frame is higher than the brightness in the second working frame. Furthermore, the duration of the light-emitting period in the first working frame is set to be shorter than the duration of the light-emitting period in the second working frame, that is, the duration of the light-emitting period in the second working frame is longer than the duration of the light-emitting period in the first working frame. In this way, the brightness decrease in the second working frame relative to the first working frame can be compensated, thereby improving the brightness flickering phenomenon.

[0077] Optionally, the first working frame is either a write frame or a hold frame, and the second working frame is a hold frame. Optionally, the write frame and the hold frame each include an initialization period and a light emission period. The write frame further includes a data write period, during which a voltage related to the data voltage and the threshold voltage of the drive transistor 110 is written to the gate of the drive transistor. Within the write frame, the data write period can occur before or after the initialization period. The hold frame does not include a data write period. For example, the compensation module 160 is not turned on during the hold frame and is always off. In the same working cycle, the hold frame follows the write frame. In the hold frame, the gate of the drive transistor holds the voltage related to the data voltage and the threshold voltage of the drive transistor 110 written to the gate of the drive transistor during the write frame. For example, in the same display cycle, the first working frame is a write frame, and the second working frame is either the first hold frame or the last hold frame; or, the first working frame and the second working frame are two adjacent hold frames; or, the first hold frame or the last hold frame.

[0078] For example, in each of at least one working cycle, at least three working frames include a write frame and at least two hold frames, or at least three hold frames; in the at least three working frames, at least one of the following conditions is satisfied: 1) the duration of the initialization period in the preceding working frame is less than the duration of the initialization optical period in the following working frame; 2) the first initialization voltage in the preceding working frame is less than the first initialization voltage in the following working frame; 3) the number of initialization periods in the preceding working frame is less than the number of initialization periods in the following working frame, and / or, the number of initialization sub-periods in the preceding working frame is less than the number of initialization sub-periods in the following working frame, and / or, the number of initialization sub-periods in the same initialization period in the preceding working frame is less than the number of initialization sub-periods in the same initialization period in the following working frame; 4) the number of initialization periods in each working frame is multiple, and / or, the number of initialization sub-periods in each working frame is multiple, and / or, the number of initialization sub-periods in the same initialization period in each working frame is multiple.

[0079] refer to Figures 4-16 Optionally, in at least one working cycle of the pixel circuit, each working cycle comprises multiple working frames including a write frame XF and w hold frames BF following the write frame XF, where w is a positive integer greater than or equal to 1; the write frame includes q first emission periods, or the write frame XF includes p first initialization periods t31 and q first emission periods t41, where the first initialization period t31 occurs before the corresponding first emission period t41, and p and q are both integers greater than or equal to 1; the hold frames BF include h second initialization periods t32 and k second emission periods t42, where the second initialization period t32 occurs before the corresponding second emission period t42, and h and k are both integers greater than or equal to 1. The value is an integer greater than or equal to 1; the first functional module 130 is turned on during at least a portion of the first initialization period t31 and at least a portion of the second initialization period t32; the light emission control module 120 is turned on during the first light emission period t41 and the second light emission period t42; the display panel also includes a control module, which is configured to ensure that the duration of at least one first light emission period t41 of the write frame XF is less than the duration of at least one second light emission period t42 of the hold frame BF; and / or, in at least two hold frames BF, the duration of at least one second light emission period t42 of the preceding hold frame BF is less than the duration of at least one second light emission period t42 of the following hold frame BF; The control module is also configured to make the first initialization voltage VEH corresponding to at least one first initialization period t31 different from the first initialization voltage VEH of at least one second initialization period t32, so that the absolute value of the bias voltage of the driving transistor in at least one first initialization period t31 is less than the absolute value of the bias voltage in at least one second initialization period t32, the bias voltage being equal to the difference between the gate voltage and the voltage of the first electrode of the driving transistor, and / or, make the duration of at least one first initialization period t31 of the write frame XF less than the duration of at least one second initialization period t32 of the hold frame BF, and / or, in at least two hold frames BF, the duration of at least one second initialization period t32 of the preceding hold frame BF is less than the duration of at least one second initialization period t32 of the following hold frame BF, and / or, in at least two hold frames BF, the first initialization voltage VEH of at least one second initialization period t32 of the preceding hold frame BF is different from the first initialization voltage VEH of at least one second initialization period t32 of the following hold frame BF;And / or, the number of first initialization periods t31 in the write frame XF is less than the number of second initialization periods t32 in each of at least one hold frame BF, and / or, the number of initialization sub-periods (e.g., within the same first initialization period) in the write frame XF is less than the number of initialization sub-periods (e.g., within the same second initialization period) in each of at least one hold frame BF, and / or, in at least two hold frame BFs, the number of second initialization periods t32 in the preceding hold frame BF is less than the number of second initialization periods t32 in the following hold frame BF. The number of initialization periods t32, and / or, in at least two hold frames BF, the number of initialization sub-periods in the preceding hold frame BF (e.g., within the same second initialization period) is less than the number of initialization sub-periods in the following hold frame BF (e.g., within the same second initialization period), and / or, the number of first initialization periods t31 in the write frame XF is multiple (e.g., 2 or at least 3), the number of second initialization periods t32 in each hold frame BF in at least one hold frame BF is multiple (e.g., 2 or at least 3), and / or, the number of first initialization periods t31 in the write frame XF is multiple (e.g., 2 or at least 3), and / or, the number of second initialization periods t32 in each hold frame BF in at least one hold frame BF is multiple (e.g., 2 or at least 3), and / or, the number of first initialization periods t31 in the write frame XF is multiple (e.g., 2 or at least 3). The number of initialization sub-time periods (i.e., the first initialization sub-time periods) is multiple (e.g., 2 or at least 3), the number of initialization sub-time periods (i.e., the second initialization sub-time periods) of each of at least one hold frame BF is multiple (e.g., 2 or at least 3), and / or, the number of first initialization sub-time periods in the same initialization time period t31 (or the same first non-light-emitting phase) of the write frame XF is multiple (e.g., 2 or at least 3), and the number of initialization sub-time periods in the same second initialization time period t32 of each of at least one hold frame BF is multiple. The number of initialization periods is multiple (e.g., 2 or at least 3), and / or, in at least two hold frames BF, the number of second initialization periods t32 in each hold frame BF is multiple (e.g., 2 or at least 3), and / or, in at least two hold frames BF, the number of initialization sub-periods in each hold frame BF is multiple (e.g., 2 or at least 3), and / or, in at least two hold frames BF, the number of initialization sub-periods in the same second initialization period t32 (or the same second non-luminescent phase) of each hold frame BF is multiple (e.g., 2 or at least 3).

[0080] Optionally, the control module includes a driver chip for the display panel. Specifically, by making the first initialization voltage VEH corresponding to at least one first initialization period t31 different from the first initialization voltage VEH of at least one second initialization period t32, the absolute value of the bias voltage of the driving transistor in at least one first initialization period t31 is less than the absolute value of the bias voltage in at least one second initialization period t32. This results in the bias stress on the driving transistor in the second initialization period t32 of the hold frame BF being greater than the bias stress on the driving transistor in the first initialization period t31 of the write frame XF. Consequently, the threshold voltage offset of the driving transistor in the hold frame BF is greater than the threshold voltage offset of the write frame XF. This also results in the driving current generated by the driving transistor in the hold frame BF being less than the driving current generated in the write frame XF. This reverses the trend of the brightness of the light-emitting module (e.g., a light-emitting module displaying low grayscale) gradually increasing in one working cycle under low brightness conditions to a trend of gradually decreasing brightness. Similarly, by setting the first initialization voltage VEH of at least one second initialization period t32 in the first hold frame BF to be different from the first initialization voltage VEH of at least one second initialization period t32 in the second hold frame BF, it is beneficial to reverse the trend of the brightness of the light-emitting module (e.g., a light-emitting module displaying low grayscale) gradually increasing in a working cycle under low brightness conditions to a trend of gradually decreasing brightness.

[0081] By ensuring that the duration of at least one first initialization period t31 in the write frame XF is shorter than the duration of at least one second initialization period t32 in the hold frame BF, the writing of the first initialization voltage VEH to the first or second terminal of the driving transistor in the hold frame BF is more sufficient than the writing of the second initialization voltage to the first or second terminal of the driving transistor in the write frame XF. This results in the bias stress on the driving transistor during the second initialization period t32 in the hold frame BF being greater than the bias stress on the driving transistor during the first initialization period t31 in the write frame XF. Similarly, this reverses the trend of gradually increasing brightness of the light-emitting module (e.g., a light-emitting module displaying low grayscale) in a working cycle to a gradually decreasing trend under low brightness conditions. Likewise, by setting the duration of at least one second initialization period t32 in the earlier hold frame BF to be shorter than the duration of at least one second initialization period t32 in the later hold frame BF, it is beneficial to reverse the trend of gradually increasing brightness of the light-emitting module (e.g., a light-emitting module displaying low grayscale) in a working cycle to a gradually decreasing trend under low brightness conditions. The above scheme ensures that the brightness change trend is the same in both low-brightness and high-brightness conditions during one working cycle of the pixel circuit, that is, the brightness gradually decreases during one working cycle (when the light emission period is the same in different working frames).

[0082] Furthermore, by controlling the module to ensure that the duration of at least one first light-emitting period t41 in the write frame XF is shorter than the duration of at least one second light-emitting period t42 in the hold frame BF, the light-emitting duration of the light-emitting module in the hold frame BF is greater than that in the write frame XF. This compensation of the light-emitting duration in the hold frame BF compensates for the brightness decrease of the light-emitting module within one working cycle, thereby improving the flicker phenomenon of the display panel. Similarly, by setting at least one first light-emitting period t41 in the earlier hold frame BF to be shorter than the duration of at least one second light-emitting period t42 in the later hold frame BF, the flicker phenomenon of the display panel can be improved.

[0083] in, Figures 7-9a , Figures 10-12 , Figures 14-16 The write frame XF and three hold frames BF in one working cycle are shown respectively. For example, each first initialization period t31 includes at least one first initialization sub-period t3, and each second initialization period t32 includes at least one second initialization sub-period t30. Figures 7-9a It is shown that a single first initialization phase includes an initialization sub-period, and a single second initialization phase includes an initialization sub-period. Figures 10-12 This illustrates that a single first initialization phase includes multiple initialization sub-segments, and a single second initialization phase also includes multiple initialization sub-segments. Wherein, Figure 7 , Figure 10 and Figure 14 The diagram schematically illustrates that the duration of the light-emitting period gradually increases within each working frame: the duration of the first light-emitting period t41 in the write frame XF, the duration of the second light-emitting period t42 in the first hold frame BF, the duration of the second light-emitting period t42 in the second hold frame BF, and the duration of the second light-emitting period t42 in the third hold frame BF, all increasing sequentially. Correspondingly, the duration of the first non-light-emitting period E1 in the write frame XF, the duration of the second non-light-emitting period E2 in the first hold frame BF, the duration of the second non-light-emitting period E3 in the second hold frame BF, and the duration of the second non-light-emitting period E4 in the third hold frame BF, all decreasing sequentially. Here, the light-emitting period corresponds to the on-pulse, and the non-light-emitting period corresponds to the off-pulse.

[0084] in, Figure 8 , Figure 11 and Figure 15 The diagram illustrates that in each working frame, the first initialization voltage gradually increases, that is, the voltage value V1 of the first initialization voltage written to frame XF, the voltage value V2 of the first initialization voltage of the first holding frame BF, the voltage value V3 of the first initialization voltage of the second holding frame BF, and the voltage value V4 of the first initialization voltage of the third holding frame BF increase sequentially.

[0085] in, Figure 9a , Figure 12 and Figure 16 The diagram illustrates that the duration of the initialization period gradually increases in each working frame, namely, the duration of the first initialization period t31 of the write frame XF, the duration of the second initialization period t32 of the first hold frame BF, the duration of the second initialization period t32 of the second hold frame BF, and the duration of the second initialization period t32 of the third hold frame BF increase sequentially.

[0086] Figure 17 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 The pixel circuit shown is for reference. Figure 17 In some embodiments, k is an integer greater than or equal to 2. In at least a portion of the hold frames, within the same hold frame BF, for example, in some or all of the light-emitting periods t42, the duration of the second light-emitting period t42 gradually increases in chronological order. Thus, by differentiating the duration of the second light-emitting period t42 within the same hold frame BF, compensation for brightness decreases within the same hold frame BF is achieved, further improving flickering. Optionally, the hold frame BF includes k second non-light-emitting periods. In at least a portion of the hold frames, within the same hold frame BF, for example, in some or all of the second non-light-emitting periods, the duration of the second non-light-emitting periods gradually decreases in chronological order. The second non-light-emitting periods are the periods within the hold frame BF excluding the second light-emitting period t42. Figure 17 An exemplary driving timing diagram of a hold frame BF is shown, illustrating a case where the hold frame BF includes two second emission periods t42, wherein the duration of the first second emission period t42 is shorter than the duration of the second second emission period t42. In the hold frame BF, the duration E21 of the first second non-emission period is longer than the duration E22 of the second non-emission period.

[0087] In other embodiments, the duration of each (or more) second light-emitting period t42 is equal within the same hold frame BF; optionally, the duration of each (or more) second non-light-emitting period is equal within the same hold frame BF. This simplifies the waveform of the control signal input to the light-emitting control module, and correspondingly, simplifies the circuit structure for generating the control signal, which is beneficial for achieving a narrow bezel.

[0088] It should be noted that the above-mentioned duration settings for the second emission period t42 are for... Figure 6 and Figure 13 The pixel circuit shown is also applicable and will not be described in detail here.

[0089] Figure 18This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 The pixel circuit shown is for reference. Figure 18 In some embodiments, h is an integer greater than or equal to 2. In at least a portion of the holding frames, within the same holding frame BF, for example, in some or all of the second initialization periods t32, the duration of the second initialization period t32 gradually increases in chronological order. Thus, by differentiating the duration of the second initialization period t32 within the same holding frame BF, the threshold voltage offset of the driving transistor within the same holding frame BF gradually increases, thereby gradually decreasing the driving current of each second light-emitting period t42 within the same holding frame BF. This ensures that the brightness of the light-emitting module changes from high to low under low brightness conditions within the holding frame BF, guaranteeing that the overall brightness of the light-emitting module decreases throughout the operating cycle. Figure 18 An exemplary driving timing of a hold frame BF is shown, and the hold frame BF includes two second initialization periods t32, wherein the duration of the first second initialization period t32 is less than the duration of the second second initialization period t32.

[0090] In other embodiments, the duration of each (or more) second initialization time periods t32 is equal within the same hold frame BF. This simplifies the waveform of the control signal received by the first functional module, and consequently, simplifies the circuit structure that generates the control signal, which is beneficial for achieving a narrow bezel.

[0091] Optionally, k=h, in the same hold frame BF, the nth second initialization period t32 is performed before the nth second emission period t42, 1≤n≤h.

[0092] It should be noted that the above-mentioned duration settings for the second initialization period t32 are for... Figure 6 and Figure 13 The same applies, and will not be elaborated further here.

[0093] Combination Figure 7 , Figure 10 and Figure 14In some embodiments, w is an integer greater than or equal to 2, and the duration of the longest second light-emitting period t42 in the i-th hold frame BF is less than the duration of the shortest second light-emitting period t42 in the (i+1)-th hold frame BF, where 1 ≤ i ≤ w-1. This allows the duration of the second light-emitting period t42 in each hold frame BF of a working cycle to gradually increase, thereby compensating for the brightness decrease in the same working cycle through gradient compensation of the light-emitting duration of the hold frame BF, thus improving the brightness flicker phenomenon. In some embodiments, the hold frame BF includes k second non-light-emitting periods, and the duration of the shortest second non-light-emitting period in the i-th hold frame BF is greater than the duration of the longest second non-light-emitting period in the (i+1)-th hold frame BF.

[0094] Combination Figure 9a , Figure 12 and Figure 16 Optionally, the duration of the longest second initialization period t32 in the i-th hold frame BF is less than the duration of the shortest second initialization period t32 in the (i+1)-th hold frame BF. This allows the duration of the second initialization period t32 to gradually increase in each hold frame BF within a working cycle. Consequently, within the same working cycle, the threshold voltage offset of the driving transistors in different hold frame BFs gradually increases according to their chronological order, leading to a gradual decrease in the driving current in different hold frame BFs and reversing the brightness increase trend under low brightness conditions.

[0095] refer to Figures 7-9a , Figures 10-12 , Figures 14-16 In some embodiments, each second initialization period t32 includes j second initialization sub-periods t30, where j is a positive integer greater than or equal to 2; adjacent second initialization sub-periods t30 in the same second initialization period t32 include a first interval period, during which the first functional module is turned on in the second initialization sub-period t30 and turned off in the first interval period.

[0096] In some embodiments, within the same second initialization period t32, the duration of each (or more) second initialization sub-periods t30 is equal; thus, it can be said that the width of the first conduction pulse in the first control signal accessed by the first functional module is the same, which simplifies the driving of the pixel circuit, simplifies the circuit structure that generates the first control signal, and is beneficial to achieving a narrow bezel.

[0097] In other embodiments, in two adjacent second initialization periods t32, the duration of the second initialization sub-period t30 in the latter second initialization period t32 is greater than the duration of the second initialization sub-period t30 in the former second initialization period t32. Specifically, the two adjacent second initialization periods t32 include the two second initialization periods t32 with the shortest interval within the same hold frame BF, and the last second initialization period t32 of the former hold frame BF and the first second initialization period t32 of the latter hold frame BF. This configuration allows the duration of the second initialization sub-period t30 to gradually increase in chronological order within the hold frame BF, more accurately reversing the increasing brightness trend of the light-emitting module at low brightness levels into a decreasing trend.

[0098] In other embodiments, in the same holding frame BF, the duration of the second initialization sub-period t30 of each (or more) second initialization period t32 is equal.

[0099] Optionally, in two adjacent second initialization periods t32, the number of second initialization sub-periods t30 included in the latter second initialization period t32 is greater than the number of second initialization sub-periods t30 included in the former second initialization period t32. This makes it easier to ensure that the conduction duration of the first functional module in the latter second initialization period t32 is greater than that in the former second initialization period t32. This, in turn, allows the threshold voltage offset of the driving transistor to gradually increase, the driving current to gradually decrease, and the brightness to gradually decrease within the frame BF, reversing the upward trend in brightness under low brightness conditions.

[0100] In some embodiments, see Figures 10-12 In two adjacent second initialization periods t32, the number of second initialization sub-periods t30 included in the latter second initialization period t32 is equal to the number of second initialization sub-periods t30 included in the former second initialization period t32.

[0101] Figures 10-12 Optionally, each first initialization period t31 includes r first initialization sub-periods t3, where r is a positive integer greater than or equal to 2; adjacent first initialization sub-periods t3 within the same first initialization period t31 include a second interval period. During the first initialization sub-period t3, the first functional module is turned on, and during the second interval period, the first functional module is turned off.

[0102] In some embodiments, within the same first initialization period t31, the duration of each (or more) first initialization sub-periods t3 is equal; thus, it can be said that the width of the first conduction pulse in the first control signal accessed by the first functional module is the same, which simplifies the driving of the pixel circuit, simplifies the circuit structure that generates the first control signal, and is beneficial to achieving a narrow bezel.

[0103] In other embodiments, in two adjacent first initialization periods t31, the duration of the first initialization sub-period t3 in the latter first initialization period t31 is greater than the duration of the first initialization sub-period t3 in the former first initialization period t31; wherein, two adjacent second initialization periods t32 include the two first initialization periods t31 with the shortest interval in the same write frame XF. Thus, it is easy to achieve that the conduction duration of the first functional module in the latter first initialization period t31 is greater than the conduction duration of the first functional module in the former first initialization period t31, thereby achieving a gradual increase in the threshold voltage offset of the driving transistor within the write frame XF, a gradual decrease in the driving current, a gradual decrease in brightness, and a reversal of the brightness increase trend under low brightness conditions.

[0104] In other embodiments, in the written frame XF, the duration of the first initialization sub-period t3 of each (or more) first initialization period t31 is equal.

[0105] In some embodiments, see Figure 9b The duration of the first initialization sub-period t3 is less than the duration of some or all of the second initialization sub-periods t30 in each hold frame BF. Optionally, the number of first initialization sub-periods t3 included in the first initialization period t31 is less than the number of second initialization sub-periods t30 included in each second initialization period t32. This allows the conduction duration of the first functional module within the first initialization period t31 in the write frame XF to be less than the conduction duration of the first functional module within the second initialization period t32 in the hold frame BF, thereby achieving a gradual increase in the threshold voltage offset of the driving transistor within the same working cycle, a gradual decrease in the driving current, and a gradual decrease in brightness, reversing the upward trend in brightness under low brightness conditions.

[0106] In some embodiments, see Figures 10-12 The number of first initialization sub-periods t3 included in the first initialization period t31 is equal to the number of second initialization sub-periods t30 included in each second initialization period t32.

[0107] Continue to refer to Figure 17 In some embodiments, q is an integer greater than or equal to 2. In the written frame XF, for example, in part or all of the first light-emitting period t41, the duration of the first light-emitting period t41 gradually increases in chronological order. Thus, by differentiating the duration of the first light-emitting period t41 within the same written frame XF, compensation for brightness decreases within the same written frame XF is achieved, further improving flickering. Optionally, the written frame XF includes q first non-light-emitting periods. In the written frame XF, for example, in at least part or all of the first non-light-emitting periods, the duration of the first non-light-emitting periods gradually decreases in chronological order. Figure 17An exemplary driving timing diagram of a write frame XF is shown, illustrating a case where the write frame XF includes two first light-emitting periods t41, wherein the duration of the first first light-emitting period t41 is shorter than the duration of the second first light-emitting period t41. In the write frame XF, the duration E11 of the first first non-light-emitting period is longer than the duration E12 of the second non-light-emitting period.

[0108] In other embodiments, the duration of each (or more) first light-emitting period t41 in the written frame XF is equal. Optionally, the duration of each (or more) first non-light-emitting period in the written frame XF is equal. This simplifies the waveform of the control signal received by the light-emitting control module, and correspondingly, simplifies the circuit structure that generates the control signal, which is beneficial for achieving a narrow bezel.

[0109] Continue to refer to Figure 18 In some embodiments, p is an integer greater than or equal to 2, written into frame XF. For example, in part or all of the first initialization period t31, the duration of the first initialization period t31 gradually increases in chronological order. Thus, by differentiating the duration of the first initialization period t31 within the same write frame XF, the threshold voltage offset of the driving transistors within the same write frame XF gradually increases, thereby gradually decreasing the driving current of each first light-emitting period t41 within the same write frame XF. This ensures that the brightness of the light-emitting module changes from high to low under low brightness conditions within the write frame XF, guaranteeing that the overall brightness of the light-emitting module decreases throughout the working cycle. Figure 18 An exemplary driving timing of a hold frame BF is shown, and the case where the write frame XF includes two first initialization periods t31 is shown, wherein the duration of the first first initialization period t31 is less than the duration of the second first initialization period t31.

[0110] In other embodiments, the duration of each (or more) first initialization time period t31 in the written frame XF is equal. This simplifies the waveform of the control signal received by the first functional module, and consequently, simplifies the circuit structure that generates the control signal, which is beneficial for achieving a narrow bezel.

[0111] Optionally, p=q, written into frame XF, the g-th first initialization period t31 is performed before the g-th first emission period t41, 1≤g≤p.

[0112] Combination Figure 7 , Figure 10 and Figure 14In some embodiments, the duration of the first light-emitting period t41 in the write frame XF is shorter than the duration of the second light-emitting period t42 in the hold frame BF. For example, the duration of the longest first light-emitting period t41 in the write frame XF is shorter than the duration of the shortest second light-emitting period t42 in the hold frame BF. This allows the light-emitting duration of the light-emitting modules in each working frame of a working cycle to gradually increase in chronological order. Gradient compensation of the light-emitting duration in each working frame can then compensate for the decrease in brightness within the same working cycle, thereby improving brightness flicker. In some embodiments, the write frame XF includes q first non-light-emitting periods, the hold frame BF includes k second non-light-emitting periods, and the duration of the shortest first non-light-emitting period in the write frame XF is longer than the duration of the longest second non-light-emitting period in the hold frame BF.

[0113] Combination Figure 9a , Figure 12 and Figure 16 Optionally, the duration of the longest initialization period t31 in the write frame XF is less than the duration of the shortest initialization period t32 in the hold frame BF. This allows the conduction duration of the first functional module to gradually increase in chronological order within each working frame of a working cycle. Consequently, the threshold voltage offset of the driving transistors in different working frames gradually increases in chronological order within the same working cycle, leading to a gradual decrease in the driving current in different working frames and reversing the brightness increase trend under low brightness conditions.

[0114] In some embodiments, the driving transistor includes a P-type transistor, and the control module is configured to ensure that the first initialization voltage during at least one first initialization period is less than the first initialization voltage during at least one second initialization period. In other embodiments, the driving transistor includes an N-type transistor, and the control module is configured to ensure that the first initialization voltage during at least one first initialization period is greater than the first initialization voltage during at least one second initialization period. This ensures that the absolute value of the bias voltage of the driving transistor during at least one first initialization period is less than the absolute value of the bias voltage during at least one second initialization period. This results in the threshold voltage offset of the driving transistor during the hold frame being greater than the threshold voltage offset during the write frame, and the driving current generated by the driving transistor during the hold frame being less than the driving current generated during the write frame. This reverses the trend of gradually increasing brightness of the light-emitting module in a working cycle under low brightness conditions to a gradually decreasing trend.

[0115] Optionally, the driving transistor includes a P-type transistor, and the control module is configured to ensure that the first initialization voltage in each first initialization period is less than the first initialization voltage in each second initialization period; or, the driving transistor includes an N-type transistor, and the control module is configured to ensure that the first initialization voltage in each first initialization period is greater than the first initialization voltage in each second initialization period. In this way, the threshold voltage offset of the driving transistor in the hold frame can be greater than the threshold voltage offset in the write frame, ensuring that the brightness of the light-emitting module in the write frame is greater than the brightness in the hold frame under low brightness conditions, thereby reversing the gradually increasing trend in one working cycle to a gradually decreasing trend.

[0116] In some embodiments, the first initialization voltages corresponding to each (or more) first initialization periods in the write frame are equal.

[0117] Figure 19a This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 The pixel circuit shown is for reference. Figure 19a In other embodiments, the driving transistor includes a P-type transistor, written into frame XF. For example, in part or all of the first initialization period t31, the first initialization voltage VEH corresponding to different first initialization periods t31 gradually increases in chronological order. Alternatively, the driving transistor includes an N-type transistor, written into frame XF. For example, in part or all of the first initialization period t31, the first initialization voltage VEH corresponding to different first initialization periods t31 gradually decreases in chronological order. In this way, the threshold voltage offset of the driving transistor in the same write frame XF can gradually increase, reversing the trend of gradually increasing brightness of the light-emitting module in a write frame XF under low brightness conditions to a gradually decreasing trend. Figure 17 The driving timing of the write frame XF is illustrated, and it is shown that the write frame XF includes two first initialization periods t31, wherein the voltage value of the first initialization voltage VEH corresponding to the first initialization period t31 is V11, and the voltage value of the first initialization voltage VEH corresponding to the second first initialization period t31 is V12. <V12。

[0118] Continue to refer to Figure 19aOptionally, the driving transistor includes a P-type transistor, and within the same holding frame BF, for example, in part or all of the second initialization time period t32, the first initialization voltage VEH corresponding to different second initialization time periods t32 gradually increases according to the time sequence; or, the driving transistor includes an N-type transistor, and within the same holding frame BF, for example, in part or all of the second initialization time period t32, the first initialization voltage VEH corresponding to different second initialization time periods t32 gradually decreases according to the time sequence. In this way, the threshold voltage offset of the driving transistor within the same holding frame BF can be gradually increased, reversing the trend of gradually increasing brightness of the light-emitting module in a holding frame BF under low brightness conditions to a gradually decreasing trend. Figure 17 An exemplary driving timing diagram of a hold frame BF is shown, illustrating the case where the hold frame BF includes two second initialization periods t32, wherein the voltage value of the first initialization voltage VEH corresponding to the first second initialization period t32 is V21, and the voltage value of the first initialization voltage VEH corresponding to the second second initialization period t32 is V22. <V22。

[0119] In other embodiments, the first initialization voltage VEH is equal in each (or more) second initialization time periods t32 within the same holding frame BF.

[0120] Optionally, w≥2, the driving transistor includes a P-type transistor, and the maximum first initialization voltage of each second initialization period t32 in the i-th hold frame BF is less than the minimum first initialization voltage of each second initialization period t32 in the (i+1)-th hold frame BF; or, the driving transistor includes an N-type transistor, and the maximum first initialization voltage of each second initialization period t32 in the i-th hold frame BF is greater than the minimum first initialization voltage of each second initialization period t32 in the (i+1)-th hold frame BF, 1≤i≤w-1. In this way, the threshold voltage offset of the driving transistor can be gradually increased in each working frame according to the chronological order, reversing the trend of gradually increasing brightness of the light-emitting module in each working frame under low brightness conditions to a gradually decreasing trend.

[0121] Figure 19b This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 The pixel circuit shown is described in the image. Figure 19b In some embodiments, p is an integer greater than or equal to 2, written into frame XF, for example, in part or all of the first initialization period t31, where the number of initialization sub-periods in the first initialization period t31 gradually increases in chronological order. For example, see... Figure 19bThe number of initialization sub-periods in the first initialization period t31 is 1, and the number of initialization sub-periods in the second initialization period t31 is 2.

[0122] See Figure 19b In some embodiments, h is an integer greater than or equal to 2. Within the same hold frame BF, for example, in part or all of the first initialization period t31, the number of initialization sub-periods in the second initialization period t32 gradually increases in chronological order. For example, see... Figure 19b The number of initialization sub-periods in the first second initialization period t32 is 3, and the number of initialization sub-periods in the second second initialization period t32 is 4.

[0123] Figure 19c This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used to drive... Figure 4 or Figure 5 In the pixel circuit shown, the duration of each (or more) first light-emitting period t41 in frame XF is equal. For example, the duration of each (or more) first non-light-emitting period in frame XF is equal. For example, the duration of each (or more) second light-emitting period t42 in the same hold frame BF is equal. For example, the duration of each (or more) second non-light-emitting period in the same hold frame BF is equal.

[0124] Optionally, the light-emitting control module includes a first light-emitting control unit. In some embodiments, the driving transistor includes a P-type transistor, and the first light-emitting control unit is connected between the second electrode of the driving transistor and the first terminal of the light-emitting module. The first electrode of the driving transistor is used to connect a first power supply voltage during the first light-emitting period and the second light-emitting period, and the first initialization voltage is greater than the first power supply voltage. The second terminal of the light-emitting module is connected to a second power supply voltage. In other embodiments, the driving transistor includes an N-type transistor, and the first light-emitting control unit is connected between the first electrode of the driving transistor and the first terminal of the light-emitting module. The second electrode of the driving transistor is used to connect the first power supply voltage during the first light-emitting period and the second light-emitting period. The second terminal of the light-emitting module is connected to a second power supply voltage, and the first initialization voltage is less than the second power supply voltage. This configuration allows the bias stress on the driving transistor during the initialization period to be stronger than the bias stress on the driving transistor during other periods, thereby causing a larger shift in the threshold voltage of the driving transistor. This causes the driving current of the driving transistor to gradually decrease in chronological order in each working frame, reversing the trend of gradually increasing brightness of the light-emitting module in each working frame under low brightness conditions to a gradually decreasing trend.

[0125] Optionally, the display panel can display at multiple brightness levels. Specifically, mobile phones, computers, and other display devices typically include brightness adjustment buttons. Users adjust the overall brightness of the display using these buttons, with each press corresponding to an input brightness level. At each brightness level, the display panel can display multiple grayscale levels, such as from the minimum to the maximum grayscale. For example, the minimum grayscale is 0, and the maximum grayscale is 255. Each brightness level corresponds to the maximum grayscale level on the display panel. Changing the brightness of the maximum grayscale level will change the brightness of the other grayscale levels. Specifically, when the brightness of the maximum grayscale level increases, the brightness of the other grayscale levels also increases; conversely, when the brightness of the maximum grayscale level decreases, the brightness of the other grayscale levels also decreases.

[0126] Optionally, the multiple display brightness levels include a first display brightness level and a second display brightness level, wherein the first display brightness level is greater than the second display brightness level. Figure 20 It is a curve of the luminous intensity at the first grayscale level of the first display brightness level. Figure 21 This is a curve showing the luminous intensity at the first grayscale level of the second display brightness level. Figure 22 It is a graph of the luminous intensity at the second grayscale level of the first display brightness level. Figure 23 It is a graph of the luminous intensity at the second grayscale of the second display brightness level. Figures 20-23 In the diagram, the horizontal axis represents time (in seconds), and the vertical axis represents brightness (in nits). The first display grayscale is greater than the second display grayscale. Figure 20 and Figure 21 In the scenario shown, the first display grayscale is equal to 255 grayscale; Figure 22 and Figure 23 In the shown scenario, the second display grayscale is 32 grayscale levels. Figure 20 and Figure 22 As shown, the maximum grayscale brightness corresponding to the first display brightness level DBV1 is 1800 nits; Figure 21 and Figure 23 In the scenario shown, the maximum grayscale brightness corresponding to the second display brightness level DBV2 is 800 nits. Among these, Figure 20 In the middle, the brightness decrease rate within the next frame at grayscale level 255 is 1.8%; Figure 21 In the middle, the brightness decrease rate within the next frame at grayscale level 255 is 0.68%. According to Figure 20 and Figure 21 It can be seen that at high grayscale, the higher the display brightness level, the greater the decrease in brightness within a frame. Figure 22In the 32-grayscale test, the brightness increase rate within the next frame is 2.2%. Figure 23 In the middle, the brightness ratio within the next frame at grayscale level 32 increases to 9%. According to... Figure 22 and Figure 23 It is known that at low grayscale levels, the lower the display brightness level, the greater the increase in brightness within a single frame. Therefore, the following relationship can be set to improve the brightness flicker of the pixel circuit during the operating cycle.

[0127] Specifically, at higher display brightness levels, the leakage current of the driving transistor is larger, resulting in a larger decrease in the brightness of the light-emitting module during the display cycle. Conversely, at lower display brightness levels, the leakage current of the driving transistor is smaller, leading to a smaller decrease in the brightness of the light-emitting module during the display cycle. Optionally, at the first display brightness level, a first difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame is set to be different from, greater than, or equal to a second difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame at the second display brightness level. Optionally, the first difference is different from the second difference, with the first difference being greater than the second difference. Thus, at the same refresh rate, the increase in the duration of the light-emitting period of the second working frame relative to the duration of the light-emitting period of the first working frame at the first display brightness level is greater than or equal to the increase in the duration of the light-emitting period of the second working frame relative to the duration of the light-emitting period of the first working frame at the second display brightness level. This results in a greater degree of compensation for brightness attenuation through the duration of the light-emitting period at the first display brightness level compared to the second display brightness level. Consequently, there is more compensation for brightness attenuation at high brightness levels and less compensation at low brightness levels, thus adapting to the brightness variation (e.g., attenuation) pattern at high and low brightness levels. This ensures adaptive compensation for brightness at both high and low brightness levels, further improving the flicker phenomenon of the display panel.

[0128] Within a single working frame, the signals received by the control terminal of the light-emitting control module include a turn-on pulse and a cut-off pulse. When a cut-off pulse is received by the control terminal of the light-emitting control module, the light-emitting control module is turned off, and the pixel circuit operates during the non-light-emitting period. When a turn-on pulse is received by the control terminal of the light-emitting control module, the light-emitting control module is turned on, and the pixel circuit operates during the light-emitting period. In a write frame, the non-light-emitting period includes a data writing period; if the write frame includes an initialization period, the non-light-emitting module also includes an initialization period. In a hold frame, the non-light-emitting period includes an initialization period. Optionally, at the first display brightness level, a third difference between the cut-off pulse width (i.e., the duration of the non-light-emitting period) of the control terminal of the light-emitting control module in the first working frame and the cut-off pulse width of the control terminal of the light-emitting control module in the second working frame is different from, greater than, or equal to, a fourth difference between the cut-off pulse width of the control terminal of the light-emitting control module in the first working frame and the cut-off pulse width of the control terminal of the light-emitting control module in the second working frame at the second display brightness level. Optionally, the third difference and the fourth difference are different, with the third difference being greater than the fourth difference. In this way, the first difference between the duration of the conduction pulse (i.e., the light-emitting period) in the second working frame and the duration of the conduction pulse (i.e., the light-emitting period) in the first working frame at the first display brightness level can be greater than or equal to the second difference between the duration of the conduction pulse (i.e., the light-emitting period) in the second working frame and the duration of the conduction pulse (i.e., the light-emitting period) in the first working frame at the second display brightness level, thereby improving the flickering phenomenon.

[0129] Because the driving current of the driving transistor is lower when the display brightness level is lower, the light-emitting module lights up more slowly. Without the addition of the first functional module, the brightness increase within a display cycle is larger. Therefore, to achieve the reversal from a gradual increase in brightness within a display cycle to a gradual decrease in brightness within a display cycle when the display brightness level is lower, it is necessary to set a greater difference in the initialization voltage between later and earlier working frames at lower display brightness levels compared to higher display brightness levels, or a greater degree of initialization.

[0130] In some embodiments, at the first display brightness level, the seventh difference between the first initialization voltage in the second working frame and the first initialization voltage in the first working frame is different from, less than, or equal to, the eighth difference between the first initialization voltage in the second working frame and the first initialization voltage in the first working frame at the second display brightness level. Optionally, the seventh difference and the eighth difference are different, with the seventh difference being less than the eighth difference. Thus, at the same refresh rate, at the second display brightness level, the increase in the first initialization voltage of the second working frame relative to the first initialization voltage of the first working frame is greater than the increase in the first initialization voltage of the second working frame relative to the first working frame at the first display brightness level. This results in a greater shift in the threshold voltage of the driving transistor at the second working frame relative to the first working frame at the second display brightness level. Consequently, the driving current generated by the driving transistor at the second working frame relative to the first working frame at the second display brightness level decreases more significantly. Consequently, at lower second display brightness levels, the brightness of the light-emitting module gradually decreases during the display cycle, reversing the upward trend in brightness of the light-emitting module at lower display brightness levels in related technologies.

[0131] In other embodiments, at the first display brightness level, a fifth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame is different from, less than, or equal to a sixth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame at the second display brightness level. Optionally, the fifth difference and the sixth difference are different, with the fifth difference being less than the sixth difference. Thus, at the same refresh rate, the increase in the initialization period of the second working frame relative to the initialization period of the first working frame at the second display brightness level is greater than the increase in the initialization period of the second working frame relative to the initialization period of the first working frame at the first display brightness level. Consequently, the initialization voltage is written more fully to the first or second electrode of the driving transistor at the second display brightness level compared to the first working frame. Correspondingly, the driving current generated by the driving transistor at the second working frame is reduced more significantly at the second display brightness level compared to the first working frame. This results in a gradual decrease in the brightness of the light-emitting module during the display cycle at lower second display brightness levels, reversing the upward trend of brightness of the light-emitting module at lower display brightness levels in related technologies.

[0132] In some embodiments, the first working frame and the second working frame are two adjacent working frames. In other embodiments, they are two working frames spaced apart. In still other embodiments, the first working frame and the second working frame are the first and last working frames in the same working cycle.

[0133] Optionally, Tya-Tx at the first display brightness level is different from, greater than, or equal to Tya-Tx at the second display brightness level; where Tx represents the duration of the x-th first light-emitting period in the write frame, and Tya represents the duration of the a-th second light-emitting period in the y-th hold frame; where 1≤x≤q, 1≤y≤w, and 1≤a≤k. Thus, at the same refresh rate, under the first display brightness level, the increase in the duration of the light-emitting period of the hold frame relative to the duration of the light-emitting period of the write frame within the same display cycle is greater than or equal to the increase in the duration of the light-emitting period of the hold frame relative to the duration of the light-emitting period of the write frame within the same display cycle under the second display brightness level, further improving the flicker phenomenon of the display panel.

[0134] In some embodiments, w≥2, and T(i+1)b-Tia at the first display brightness level is different from, greater than, or equal to T(i+1)b-Tia at the second display brightness level, where Tia represents the duration of the a-th second light-emitting period in the i-th hold frame, T(i+1)b represents the duration of the b-th second light-emitting period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤b≤k. Thus, at the same refresh rate, under the first display brightness level, within the same display cycle, the increase in the duration of the light-emitting period of the later hold frame relative to the duration of the earlier hold frame is greater than or equal to the increase in the duration of the light-emitting period of the later hold frame relative to the duration of the earlier hold frame within the same display cycle under the second display brightness level, further improving the flicker phenomenon of the display panel.

[0135] In some embodiments, a working frame includes multiple sub-cycles of equal duration. Each sub-cycle includes a non-light-emitting period and a light-emitting period. The initialization period occurs during the non-light-emitting period. During the non-light-emitting period, a cutoff pulse is applied to the control terminal of the light-emitting control module, and during the light-emitting period, a turn-on pulse is applied to the light-emitting control module. Optionally, multiple working frames within the same working cycle may have equal durations.

[0136] Optionally, the absolute value of Vz-Vuc at the first display brightness level is different from, less than, or equal to the absolute value of Vz-Vuc at the second display brightness level; where Vz represents the first initialization voltage during the z-th first initialization period in the write frame, and Vuc represents the first initialization voltage during the c-th second initialization period in the u-th hold frame; where 1≤z≤p, 1≤u≤w, and 1≤c≤h. Thus, at the same refresh rate, under the second display brightness level, within the same display cycle, the change in the first initialization voltage of the hold frame relative to the first initialization voltage of the write frame is greater than the change in the first initialization voltage of the hold frame relative to the first initialization voltage of the write frame within the same display cycle under the first display brightness level. This results in a greater shift in the threshold voltage of the driving transistor between the hold frame and the write frame under the second display brightness level compared to the first display brightness level, reversing the upward trend of the light-emitting module's brightness at lower display brightness levels in related technologies.

[0137] Optionally, w≥2, the absolute value of V(i+1)d-Vic at the first display brightness level is less than or equal to the absolute value of V(i+1)d-Vic at the second display brightness level, where Vic represents the first initialization voltage of the c-th second initialization period in the i-th hold frame, V(i+1)d represents the first initialization voltage of the d-th second initialization period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤d≤h. Thus, at the same refresh rate, under the second display brightness level, within the same display cycle, the change in the first initialization voltage of the later hold frame relative to the first initialization voltage of the earlier hold frame is greater than the change in the first initialization voltage of the later hold frame relative to the first initialization voltage of the earlier frame within the same display cycle under the first display brightness level. This results in a greater shift in the threshold voltage of the driving transistors between the later and earlier hold frames under the second display brightness level compared to the first display brightness level, reversing the upward trend of the light-emitting module's brightness at lower display brightness levels in related technologies.

[0138] Optionally, the Tuc-Tz at the first display brightness level is different from, less than, or equal to the Tuc-Tz at the second display brightness level; where Tz represents the duration of the z-th first initialization period in the write frame, and Tuc represents the duration of the c-th second initialization period in the u-th hold frame; where 1≤z≤p, 1≤u≤w, and 1≤c≤h. Thus, at the same refresh rate, under the second display brightness level, the increase in the duration of the second initialization period of the hold frame relative to the duration of the first initialization period of the write frame within the same display cycle is greater than the increase in the duration of the second initialization period of the hold frame relative to the duration of the first initialization period of the write frame within the same display cycle under the first display brightness level. This results in a more sufficient writing of the initialization voltage to the first or second electrode of the driving transistor under the hold frame relative to the write frame in the second display brightness level compared to the first display brightness level. Consequently, the threshold voltage offset of the driving transistor under the hold frame relative to the write frame is greater under the second display brightness level compared to the first display brightness level, reversing the upward trend of the light-emitting module's brightness at lower display brightness levels in related technologies.

[0139] Optionally, w≥2, T(i+1)d-Tic under the first display brightness level is different from, less than or equal to, T(i+1)d-Tic under the second display brightness level, where Tic represents the duration of the c-th second initialization period in the i-th hold frame, T(i+1)d represents the duration of the d-th second initialization period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤d≤h. Thus, at the same refresh rate, under the second display brightness level, within the same display cycle, the increase in the duration of the second initialization period of the later hold frame relative to the duration of the second initialization period of the earlier hold frame is greater than the increase in the duration of the second initialization period of the later hold frame relative to the duration of the first initialization period of the earlier hold frame within the same display cycle under the first display brightness level. Consequently, under the second display brightness level, the later hold frame writes the initialization voltage to the first or second electrode of the driving transistor more fully than under the first display brightness level. This results in a greater shift in the threshold voltage of the driving transistor under the later hold frame relative to the earlier hold frame under the second display brightness level, reversing the upward trend of the light-emitting module's brightness at lower display brightness levels in related technologies.

[0140] It should be noted that in the above embodiments of the present invention, the various relationships under the first display brightness level and the second display brightness level can all be under the premise of the same refresh rate.

[0141] Since flickering is more pronounced at lower refresh rates, some embodiments of the present invention improve flickering at different refresh rates through the following settings. Optionally, at a first refresh rate, the ninth difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame is different from, greater than, or equal to, the tenth difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame at a second refresh rate, wherein the first refresh rate is lower than the second refresh rate. Optionally, the ninth difference is different from the tenth difference, and the ninth difference is greater than the tenth difference. Thus, at the same display brightness level, the increase in the duration of the light-emitting period of the second working frame relative to the duration of the light-emitting period of the first working frame at the first refresh rate is greater than or equal to the increase in the duration of the light-emitting period of the second working frame relative to the duration of the light-emitting period of the first working frame at the second refresh rate. Consequently, the degree of compensation for brightness attenuation through the duration of the light-emitting period at the first refresh rate is greater than that at the second refresh rate. This results in more compensation for brightness attenuation at lower refresh rates and less compensation at higher refresh rates, thus adapting to the attenuation pattern of light emission brightness at both high and low refresh rates. This ensures that the light emission brightness is adaptively compensated at both high and low refresh rates, further improving the flicker phenomenon of the display panel.

[0142] At the first refresh rate, the eleventh difference between the cutoff pulse width of the control terminal of the light-emitting control module in the first working frame and the cutoff pulse width of the control terminal of the light-emitting control module in the second working frame is different from, greater than, or equal to, the twelfth difference between the cutoff pulse width of the control terminal of the light-emitting control module in the first working frame and the cutoff pulse width of the control terminal of the light-emitting control module in the second working frame at the second refresh rate. Optionally, the eleventh and twelfth differences are different, with the eleventh difference being greater than the twelfth difference. Thus, at the same display brightness level, it is possible to achieve a ninth difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame at the first refresh rate, which is greater than or equal to the tenth difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame at the second refresh rate, thereby improving the screen flicker phenomenon of the display panel at different refresh rates.

[0143] At the first refresh frequency, the fifteenth difference between the first initialization voltage in the second working frame and the first initialization voltage in the first working frame is different from, greater than, or equal to, the sixteenth difference between the first initialization voltage in the second working frame and the first initialization voltage in the first working frame at the second refresh frequency. Optionally, the fifteenth difference and the sixteenth difference are different, with the fifteenth difference being greater than the sixteenth difference. Thus, at the same display brightness level, the increase in the first initialization voltage of the second working frame relative to the first initialization voltage of the first working frame at the first refresh frequency is greater than the increase in the first initialization voltage of the second working frame relative to the first working frame at the second refresh frequency. Consequently, the threshold voltage offset of the driving transistor of the second working frame relative to the first working frame is greater at the first refresh frequency than at the second refresh frequency. Correspondingly, the driving current generated by the driving transistor of the second working frame relative to the first working frame is reduced more at the first refresh frequency than at the second refresh frequency. This makes the flicker reversal effect from low to high brightness stronger at the lower first refresh frequency and weaker at the higher second refresh frequency. As a result, the brightness changes from high to low at both the first and second refresh frequencies, which is compatible with the brightness flicker situation at the first and second refresh frequencies.

[0144] At the first refresh rate, the thirteenth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame is different from or greater than or equal to the fourteenth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame at the second refresh rate. Optionally, the thirteenth and fourteenth differences are different, with the thirteenth difference being greater than the fourteenth difference. Thus, at the same display brightness level, the increase in the initialization period of the second working frame relative to the initialization period of the first working frame at the first refresh frequency is greater than the increase in the initialization period of the second working frame relative to the initialization period of the first working frame at the second refresh frequency. Consequently, the initialization voltage written to the first or second electrode of the driving transistor is more sufficient at the first refresh frequency compared to the second refresh frequency. Correspondingly, the driving current generated by the driving transistor is reduced more at the first refresh frequency compared to the second refresh frequency. This results in a stronger reversal effect on the flicker from low to high brightness at the lower first refresh frequency and a weaker reversal effect on the flicker from low to high brightness at the higher second refresh frequency. This allows the brightness to change from high to low at both the first and second refresh frequencies, which is compatible with the brightness flicker situation at the first and second refresh frequencies.

[0145] In some embodiments, both the first refresh frequency and the second refresh frequency are less than or equal to a preset refresh frequency, which is between 30Hz and 60Hz. For example, the preset refresh frequency is equal to 30Hz, 35Hz, 40Hz, 46Hz, 50Hz, 55Hz, or 60Hz.

[0146] In some embodiments, the display panel displays at at least one display brightness level; at the same display brightness level, Tya-Tx at the first refresh rate is different from, greater than or equal to, Tya-Tx at the second refresh rate; wherein, Tx represents the duration of the x-th first light emission period in the write frame, and Tya represents the duration of the a-th second light emission period in the y-th hold frame; wherein, 1≤x≤q, 1≤y≤w, 1≤a≤k; the first refresh rate is less than the second refresh rate. Thus, at the same display brightness level, at the first refresh rate, the increase in the duration of the light-emitting period of the hold frame relative to the duration of the light-emitting period of the write frame within the same display cycle is greater than or equal to the increase in the duration of the light-emitting period of the hold frame relative to the duration of the light-emitting period of the write frame within the same display cycle at the second refresh rate. Consequently, the degree of compensation for brightness attenuation through the duration of the light-emitting period at the first refresh rate is greater than that at the second refresh rate, ensuring that the brightness is adaptively compensated at both high and low refresh rates, further improving the flicker phenomenon of the display panel.

[0147] Optionally, w≥2, T(i+1)b-Tia at the first refresh frequency is different from, greater than or equal to, T(i+1)b-Tia at the second refresh frequency, where Tia represents the duration of the a-th second light emission period in the i-th hold frame, T(i+1)b represents the duration of the b-th second light emission period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤b≤k. Thus, at the same display brightness level, under the first refresh rate, within the same display cycle, the increase in the duration of the second light-emitting period of the later hold frame relative to the duration of the second light-emitting period of the earlier hold frame is greater than or equal to the increase in the duration of the light-emitting period of the later hold frame relative to the duration of the second light-emitting period of the earlier hold frame within the same display cycle under the second refresh rate. Consequently, the degree of compensation for brightness attenuation through the duration of the light-emitting period under the first refresh rate is greater than that under the second refresh rate, ensuring that the brightness is adaptively compensated under both high and low refresh rates, further improving the flicker phenomenon of the display panel.

[0148] In some embodiments, the absolute value of Vz-Vuc at the first refresh frequency is different from, greater than or equal to, the absolute value of Vz-Vuc at the second refresh frequency; where Vz represents the first initialization voltage of the z-th first initialization period in the write frame, and Vuc represents the first initialization voltage of the c-th second initialization period in the u-th hold frame; where 1≤z≤p, 1≤u≤w, and 1≤c≤h. Thus, at the same display brightness level, the increase in the first initialization voltage of the hold frame relative to the first initialization voltage of the write frame within the same display cycle at the first refresh frequency is greater than that at the second refresh frequency. Consequently, the threshold voltage offset of the hold frame relative to the write frame driving transistor is greater at the first refresh frequency relative to the second refresh frequency. Correspondingly, the driving current generated by the hold frame relative to the write frame driving transistor is reduced more at the first refresh frequency relative to the second refresh frequency. This results in a stronger flicker reversal effect from low to high brightness at the lower first refresh frequency and a weaker effect at the higher second refresh frequency. This allows the brightness to change from high to low at both the first and second refresh frequencies, which is compatible with the brightness flicker situation at the first and second refresh frequencies.

[0149] Optionally, w≥2, the absolute value of V(i+1)d-Vic at the first refresh frequency is different from, greater than or equal to, the absolute value of V(i+1)d-Vic at the second refresh frequency, where Vic represents the first initialization voltage of the c-th second initialization period in the i-th hold frame, V(i+1)d represents the first initialization voltage of the d-th second initialization period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤d≤h. Thus, at the same display brightness level, at the first refresh rate, within the same display cycle, the increase in the first initialization voltage of the subsequent hold frame relative to the first initialization voltage of the previous hold frame is greater than that at the second refresh rate, within the same display cycle. Consequently, at the first refresh rate relative to the second refresh rate, the threshold voltage offset of the driving transistor for the subsequent hold frame relative to the previous hold frame is greater. Correspondingly, at the first refresh rate relative to the second refresh rate, the driving current generated by the driving transistor for the subsequent hold frame relative to the previous hold frame is reduced more significantly. This results in a stronger flicker reversal effect from low to high brightness at the lower first refresh rate and a weaker effect at the higher second refresh rate. This allows the brightness to change from high to low at both the first and second refresh rates, which is compatible with the brightness flicker situation at the first and second refresh rates.

[0150] In some embodiments, Tuc-Tz at the first refresh frequency is different from, greater than or equal to, Tuc-Tz at the second refresh frequency; wherein, Tz represents the duration of the z-th first initialization period in the write frame, and Tuc represents the duration of the c-th second initialization period in the u-th hold frame. Thus, at the same display brightness level, at the first refresh rate, the increase in the duration of the hold frame initialization period relative to the duration of the write frame initialization period within the same display cycle is greater than that at the second refresh rate. Consequently, at the first refresh rate, the hold frame writes the initialization voltage to the first or second electrode of the driving transistor more fully than the write frame. Correspondingly, at the first refresh rate, the driving current generated by the drive transistor is reduced more significantly than that of the write frame. This results in a stronger flicker reversal effect from low to high brightness at the lower first refresh rate and a weaker effect at the higher second refresh rate. This allows the brightness to change from high to low at both the first and second refresh rates, which is compatible with the brightness flicker situation at both refresh rates.

[0151] Optionally, w≥2, T(i+1)d-Tic at the first refresh frequency is different from, greater than or equal to, T(i+1)d-Tic at the second refresh frequency, where Tic represents the duration of the c-th second initialization period in the i-th hold frame, and T(i+1)d represents the duration of the d-th second initialization period in the (i+1)-th hold frame. Thus, at the same display brightness level, at the first refresh rate, the increase in the initialization period of the later hold frame relative to the initialization period of the earlier hold frame within the same display cycle is greater than that at the second refresh rate. Consequently, at the first refresh rate, the later hold frame writes the initialization voltage to the first or second electrode of the driving transistor more fully than at the second refresh rate. Correspondingly, at the first refresh rate, the driving current generated by the driving transistor in the later hold frame is reduced more significantly than at the second refresh rate. This results in a stronger flicker reversal effect from low to high brightness at the lower first refresh rate and a weaker effect at the higher second refresh rate. This allows the brightness to change from high to low at both the first and second refresh rates, which is compatible with the brightness flicker situation at both refresh rates.

[0152] This invention also provides a display device. Figure 24 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device 1 includes a display panel 10 according to any embodiment of the present invention and possesses the beneficial effects of the display panel according to any embodiment of the present invention, which will not be described in detail here. In this embodiment, the display device 1 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, wearable devices, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. The present invention does not make any special limitations on these products.

[0153] This invention also provides a driving method for a display panel. The display panel includes an electrically connected light-emitting module and a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control module, and a first functional module. The light-emitting control module, the light-emitting module, and the driving transistor are connected in series between a first power line and a second power line. The first functional module is connected to a first or second terminal of the driving transistor. The first functional module is connected to a first initialization voltage and is used to transmit the first initialization voltage to the first or second terminal of the driving transistor when it is turned on. The operating mode of the display panel includes a first mode. In the first mode, each operating cycle of at least one operating cycle of the pixel circuit includes multiple operating frames. Each operating frame includes a light-emitting period and at least one operating frame also includes an initialization period. Figure 25 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, see reference. Figure 25 In each of at least one work cycle, the driving method includes: S210. During at least a portion of the initialization period, control the first functional module to be turned on.

[0154] S220. During the light-emitting period, the light-emitting control module is turned on.

[0155] The duration of the emission period is different in at least two working frames.

[0156] The initialization periods of at least two working frames are of different durations, and / or the first initialization voltages of at least two working frames are different, and / or the number of initialization periods in at least two working frames is different, and / or the initialization period includes at least one initialization sub-period, and the number of initialization sub-periods of at least two working frames is different; and / or the number of initialization periods in each of at least two working frames is multiple, and / or the number of initialization sub-periods in each of at least two working frames is multiple.

[0157] The display panel driving method of this invention is used to drive the display panel of any embodiment of this invention, and has the beneficial effects of the display panel of any embodiment of this invention, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0158] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0159] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The device includes an electrically connected light-emitting module and a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control module, and a first functional module. The light-emitting control module, the light-emitting module, and the driving transistor are connected in series between a first power line and a second power line. The first functional module is connected to a first or second terminal of the driving transistor. The first functional module is connected to a first initialization voltage and is used to transmit the first initialization voltage to the first or second terminal of the driving transistor when it is turned on. Each of the at least one operating cycles of the pixel circuit includes multiple operating frames, each operating frame including a light emission period, and at least one operating frame also including an initialization period; during at least a portion of the initialization period, the first functional module is turned on. During the light-emitting period, the light-emitting control module is turned on; the duration of the light-emitting period is different in at least two of the working frames; The initialization period durations of at least two of the working frames are different, and / or the first initialization voltages of at least two of the working frames are different, and / or the initialization period includes at least one initialization sub-period, the number of initialization sub-periods of at least two of the working frames is different, and / or the number of initialization sub-periods in each of the at least two working frames is multiple.

2. The display panel according to claim 1, characterized in that, At least two working frames include a first working frame and a second working frame, wherein the first working frame precedes the second working frame, and the duration of the light emission period in the first working frame is shorter than the duration of the light emission period in the second working frame. The duration of the initialization period in the first working frame is less than the duration of the initialization light period in the second working frame, and / or, the first initialization voltage in the first working frame is less than the first initialization voltage in the second working frame, and / or, the number of initialization sub-periods in the first working frame is less than the number of initialization sub-periods in the second working frame; and / or, the number of initialization sub-periods in the first working frame and the number of initialization sub-periods in the second working frame are both multiple; Preferably, the first working frame is a write frame or a hold frame, and the second working frame is a hold frame.

3. The display panel according to claim 2, characterized in that, The display panel displays at multiple brightness levels; the multiple brightness levels include a first brightness level and a second brightness level, wherein the first brightness level is greater than the second brightness level; At the first display brightness level, a first difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame is greater than or equal to a second difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame at the second display brightness level. And / or, At the first display brightness level, a third difference between the cutoff pulse width of the control terminal of the light-emitting control module in the first working frame and the cutoff pulse width of the control terminal of the light-emitting control module in the second working frame is greater than or equal to a fourth difference between the cutoff pulse width of the control terminal of the light-emitting control module in the first working frame and the cutoff pulse width of the control terminal of the light-emitting control module in the second working frame; and / or, At the first display brightness level, the fifth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame is less than or equal to the sixth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame at the second display brightness level. And / or, At the first display brightness level, the seventh difference between the first initialization voltage in the second working frame and the first initialization voltage in the first working frame is less than or equal to the eighth difference between the first initialization voltage in the second working frame and the first initialization voltage in the first working frame at the second display brightness level. Preferably, the first difference is different from the second difference, and / or the third difference is different from the fourth difference, or the fifth difference is different from the sixth difference; And / or, the seventh difference and the eighth difference are different; Preferably, the first working frame and the second working frame are two adjacent working frames, or two working frames spaced apart, or the first working frame and the second working frame are the first and last working frames in the same working cycle.

4. The display panel according to claim 2, characterized in that, At the first refresh frequency, the ninth difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame is greater than or equal to the tenth difference between the duration of the light-emitting period in the second working frame and the duration of the light-emitting period in the first working frame at the second refresh frequency. And / or, At the first refresh frequency, the eleventh difference between the cutoff pulse width of the control terminal of the light-emitting control module in the first working frame and the cutoff pulse width of the control terminal of the light-emitting control module in the second working frame is greater than or equal to the twelfth difference between the cutoff pulse width of the control terminal of the light-emitting control module in the first working frame and the cutoff pulse width of the control terminal of the light-emitting control module in the second working frame at the second refresh frequency; and / or, At the first refresh frequency, the thirteenth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame is greater than or equal to the fourteenth difference between the duration of the initialization period in the second working frame and the duration of the initialization period in the first working frame at the second refresh frequency. And / or, At the first refresh frequency, the fifteenth difference between the first initial voltage in the second working frame and the first initial voltage in the first working frame is greater than or equal to the sixteenth difference between the first initial voltage in the second working frame and the first initial voltage in the first working frame at the second refresh frequency. The first refresh rate is less than the second refresh rate; Preferably, the ninth difference is different from the tenth difference, and / or the eleventh difference is different from the twelfth difference, or the thirteenth difference is different from the fourteenth difference; And / or, the fifteenth difference and the sixteenth difference are different.

5. The display panel according to claim 1, characterized in that, Each working frame in at least one working cycle of the pixel circuit includes a write frame and w hold frames following the write frame, where w is a positive integer greater than or equal to 1; the write frame includes q first emission periods, or the write frame includes p first initialization periods and q first emission periods, where the first initialization period occurs before the corresponding first emission period, and p and q are both integers greater than or equal to 1; the hold frames include h second initialization periods and k second emission periods, where the second initialization period occurs before the corresponding second emission period, and h and k are both integers greater than or equal to 1; the first functional module is turned on during at least a portion of the first initialization period and at least a portion of the second initialization period; the emission control module is turned on during the first emission period and the second emission period; The display panel further includes a control module, which is configured to ensure that the duration of at least one first light-emitting period of the write frame is less than the duration of at least one second light-emitting period of the hold frame; And / or, in at least two of the holding frames, the duration of at least one second light emission period in the preceding holding frame is less than the duration of at least one second light emission period in the subsequent holding frame; The control module is further configured to make the first initialization voltage corresponding to at least one first initialization period different from the first initialization voltage of at least one second initialization period, so that the absolute value of the bias voltage of the driving transistor in at least one first initialization period is less than the absolute value of the bias voltage in at least one second initialization period, the bias voltage being equal to the difference between the gate voltage and the voltage of the first electrode of the driving transistor, and / or, make the duration of at least one first initialization period of the write frame less than the duration of at least one second initialization period of the hold frame, and / or, in at least two hold frames, the duration of at least one second initialization period of the earlier hold frame is less than the duration of at least one second initialization period of the later hold frame, and / or, in at least two hold frames, the first initialization voltage of at least one second initialization period of the earlier hold frame is different from the first initialization voltage of at least one second initialization period of the later hold frame; and / or, the first initialization period of the write frame... The number of initialization sub-periods of the write frame is less than the number of second initialization periods of each of the at least one of the holding frames; and / or, in at least two of the holding frames, the number of second initialization periods of the preceding holding frame is less than the number of second initialization periods of the following holding frame; and / or, the number of first initialization periods of the write frame and the number of second initialization periods of the holding frame are both multiple; and / or, in at least two of the holding frames, the number of second initialization periods of each holding frame is multiple; and / or, the number of initialization sub-periods of the write frame is less than the number of initialization sub-periods of each of the at least one holding frame; and / or, in at least two of the holding frames, the number of initialization sub-periods of the preceding holding frame is less than the number of initialization sub-periods of the following holding frame; and / or, the number of initialization sub-periods of the write frame and the number of initialization sub-periods of each of the at least one holding frame are both multiple; and / or, in at least two of the holding frames, the number of initialization sub-periods of each holding frame is multiple.

6. The display panel according to claim 5, characterized in that, k is an integer greater than or equal to 2. Within the same holding frame, the duration of the second light emission period gradually increases in chronological order. Preferably, the holding frame includes k second non-light-emitting periods, and within the same holding frame, the duration of the second non-light-emitting periods gradually decreases in chronological order; Alternatively, within the same holding frame, the duration of each of the second light-emitting periods is equal; Preferably, within the same holding frame, the duration of each of the second non-light-emitting periods is equal.

7. The display panel according to claim 5 or 6, characterized in that, h is an integer greater than or equal to 2. In the same holding frame, the duration of the second initialization period gradually increases in chronological order; or, in the same holding frame, the duration of each second initialization period is equal. Preferably, k=h, and in the same holding frame, the nth second initialization period is performed before the nth second emission period, 1≤n≤h.

8. The display panel according to claim 5 or 6, characterized in that, w is an integer greater than or equal to 2, the duration of the second light emission period with the longest duration in the i-th holding frame is less than the duration of the second light emission period with the shortest duration in the (i+1)-th holding frame, 1≤i≤w-1; And / or, the duration of the second initialization period with the longest duration in the i-th holding frame is less than the duration of the second initialization period with the shortest duration in the (i+1)-th holding frame; Preferably, the holding frame includes k second non-light-emitting periods, and the duration of the shortest second non-light-emitting period in the i-th holding frame is greater than the duration of the longest second non-light-emitting period in the (i+1)-th holding frame.

9. The display panel according to claim 5 or 6, characterized in that, Each second initialization period includes j second initialization sub-periods, where j is a positive integer greater than or equal to 2; adjacent second initialization sub-periods within the same second initialization period include a first interval period, during which the first functional module is turned on and during the first interval period, the first functional module is turned off; Preferably, within the same second initialization period, the duration of each second initialization sub-period is equal; Preferably, in two adjacent second initialization periods, the duration of the second initialization sub-period in the latter second initialization period is greater than the duration of the second initialization sub-period in the former second initialization period; wherein, the two adjacent second initialization periods include the two second initialization periods with the shortest interval in the same holding frame, and the last second initialization period of the former holding frame and the first second initialization period of the latter holding frame in two adjacent holding frames; or, in the same holding frame, the duration of the second initialization sub-periods of each second initialization period is equal; Preferably, in two adjacent second initialization periods, the number of second initialization sub-periods included in the latter second initialization period is greater than the number of second initialization sub-periods included in the former second initialization period.

10. The display panel according to claim 9, characterized in that, Each first initialization period includes r first initialization sub-periods, where r is a positive integer greater than or equal to 2; adjacent first initialization sub-periods within the same first initialization period include a second interval period, during which the first functional module is turned on and during the second interval period, the first functional module is turned off; Preferably, within the same first initialization period, the duration of each first initialization sub-period is equal; Preferably, in two adjacent first initialization periods, the duration of the first initialization sub-period in the latter first initialization period is greater than the duration of the first initialization sub-period in the former first initialization period; wherein, the two adjacent second initialization periods include the two first initialization periods with the shortest interval in the same write frame; or, the duration of the first initialization sub-period in each first initialization period in the write frame is equal; Preferably, the duration of the first initialization sub-period is less than the duration of the second initialization sub-period in each of the holding frames; Preferably, the number of first initialization sub-time periods included in the first initialization time period is less than the number of second initialization sub-time periods included in each second initialization time period.

11. The display panel according to claim 5, characterized in that, q is an integer greater than or equal to 2. In the written frame, the duration of the first light-emitting period gradually increases in chronological order. Preferably, the write frame includes q first non-light-emitting time periods, and in the write frame, the duration of the first non-light-emitting time periods gradually decreases in chronological order; Alternatively, in the written frame, the duration of each of the first light emission periods is equal; Preferably, in the written frame, the duration of each of the first non-light-emitting periods is equal.

12. The display panel according to claim 5 or 11, characterized in that, p is an integer greater than or equal to 2. In the write frame, the duration of the first initialization period gradually increases in chronological order; or, in the write frame, the duration of each first initialization period is equal. Preferably, p=q, and in the writing frame, the g-th first initialization period is performed before the g-th first emission period, and 1≤g≤p.

13. The display panel according to claim 5 or 6, characterized in that, The duration of the longest first light-emitting period in the write frame is less than the duration of the shortest second light-emitting period in the hold frame; And / or, the duration of the longest first initialization period in the write frame is less than the duration of the shortest second initialization period in the hold frame; Preferably, the write frame includes q first non-light-emitting periods, the hold frame includes k second non-light-emitting periods, and the duration of the shortest first non-light-emitting period in the write frame is greater than the duration of the longest second non-light-emitting period in the hold frame.

14. The display panel according to claim 5 or 6, characterized in that, The driving transistor includes a P-type transistor, and the control module is used to make the first initialization voltage of at least one of the first initialization periods less than the first initialization voltage of at least one of the second initialization periods. Alternatively, the driving transistor includes an N-type transistor, and the control module is configured to make the first initialization voltage of at least one of the first initialization periods greater than the first initialization voltage of at least one of the second initialization periods; Preferably, the driving transistor includes a P-type transistor, and the control module is configured to ensure that the first initialization voltage in each of the first initialization periods is less than the first initialization voltage in each of the second initialization periods. Preferably, the driving transistor includes an N-type transistor, and the control module is configured to ensure that the first initialization voltage in each of the first initialization periods is greater than the first initialization voltage in each of the second initialization periods; Preferably, the first initialization voltage corresponding to each first initialization period in the write frame is equal; or, the driving transistor includes a P-type transistor, and the first initialization voltage corresponding to different first initialization periods in the write frame gradually increases in chronological order; or the driving transistor includes an N-type transistor, and the first initialization voltage corresponding to different first initialization periods in the write frame gradually decreases in chronological order.

15. The display panel according to claim 14, characterized in that, The driving transistor includes a P-type transistor, and within the same holding frame, the first initialization voltage corresponding to different second initialization periods in chronological order gradually increases; or, the driving transistor includes an N-type transistor, and within the same holding frame, the first initialization voltage corresponding to different second initialization periods in chronological order gradually decreases. Alternatively, within the same holding frame, the first initialization voltage is equal for each of the second initialization periods.

16. The display panel according to claim 14, characterized in that, w≥2, the driving transistor includes a P-type transistor, and the maximum first initialization voltage of each second initialization period in the i-th holding frame is less than the minimum first initialization voltage of each second initialization period in the (i+1)-th holding frame; or, the driving transistor includes an N-type transistor, and the maximum first initialization voltage of each second initialization period in the i-th holding frame is greater than the minimum first initialization voltage of each second initialization period in the (i+1)-th holding frame, 1≤i≤w-1.

17. The display panel according to claim 5 or 6, characterized in that, The light-emitting control module includes a first light-emitting control unit; The driving transistor includes a P-type transistor. The first light-emitting control unit is connected between the second terminal of the driving transistor and the first terminal of the light-emitting module. The first terminal of the driving transistor is used to access a first power supply voltage during the first light-emitting period and the second light-emitting period. The first initialization voltage is greater than the first power supply voltage. The second terminal of the light-emitting module is connected to a second power supply voltage; Alternatively, the driving transistor includes an N-type transistor, the first light-emitting control unit is connected between the first terminal of the driving transistor and the first terminal of the light-emitting module, and the second terminal of the driving transistor is used to access a first power supply voltage during the first light-emitting period and the second light-emitting period; The second terminal of the light-emitting module is connected to a second power supply voltage; The first initialization voltage is less than the second power supply voltage.

18. The display panel according to claim 5 or 6, characterized in that, The display panel displays at multiple brightness levels; the multiple brightness levels include a first brightness level and a second brightness level, wherein the first brightness level is greater than the second brightness level; Wherein, Tya-Tx at the first display brightness level is greater than or equal to Tya-Tx at the second display brightness level; where Tx represents the duration of the xth first light emission period in the write frame, and Tya represents the duration of the ath second light emission period in the yth hold frame; where 1≤x≤q, 1≤y≤w, and 1≤a≤k; Preferably, w≥2, T(i+1)b-Tia at the first display brightness level is greater than or equal to T(i+1)b-Tia at the second display brightness level, where Tia represents the duration of the a-th second light-emitting period in the i-th hold frame, T(i+1)b represents the duration of the b-th second light-emitting period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤b≤k; Preferably, the working frame includes multiple sub-cycles of the same duration, each sub-cycle including a non-light-emitting period and a light-emitting period, the initialization period is in the non-light-emitting period, the control terminal of the light-emitting control module is connected to a cutoff pulse in the non-light-emitting period, and the light-emitting control module is connected to a conduction pulse in the light-emitting period; Preferably, the durations of multiple working frames in the same working cycle are equal.

19. The display panel according to claim 5 or 6, characterized in that, The display panel displays at multiple brightness levels; the multiple brightness levels include a first brightness level and a second brightness level, wherein the first brightness level is greater than the second brightness level; Wherein, the absolute value of Vz-Vuc under the first display brightness level is less than or equal to the absolute value of Vz-Vuc under the second display brightness level; where Vz represents the first initialization voltage of the z-th first initialization period in the write frame, and Vuc represents the first initialization voltage of the c-th second initialization period in the u-th hold frame; where 1≤z≤p, 1≤u≤w, 1≤c≤h; Preferably, w≥2, the absolute value of V(i+1)d-Vic at the first display brightness level is less than or equal to the absolute value of V(i+1)d-Vic at the second display brightness level, where Vic represents the first initialization voltage of the c-th second initialization period in the i-th hold frame, V(i+1)d represents the first initialization voltage of the d-th second initialization period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤d≤h.

20. The display panel according to claim 5 or 6, characterized in that, The display panel displays at multiple brightness levels; the multiple brightness levels include a first brightness level and a second brightness level, wherein the first brightness level is greater than the second brightness level; Wherein, Tuc-Tz at the first display brightness level is less than or equal to Tuc-Tz at the second display brightness level; where Tz represents the duration of the z-th first initialization period in the write frame, and Tuc represents the duration of the c-th second initialization period in the u-th hold frame; where 1≤z≤p, 1≤u≤w, 1≤c≤h; Preferably, w≥2, T(i+1)d-Tic under the first display brightness level is less than or equal to T(i+1)d-Tic under the second display brightness level, where Tic represents the duration of the c-th second initialization period in the i-th hold frame, T(i+1)d represents the duration of the d-th second initialization period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤d≤h.

21. The display panel according to claim 5 or 6, characterized in that, The display panel displays at at least one brightness level; at the same brightness level, Tya-Tx at the first refresh rate is greater than or equal to Tya-Tx at the second refresh rate; where Tx represents the duration of the x-th first light-emitting period in the write frame, and Tya represents the duration of the a-th second light-emitting period in the y-th hold frame; where 1≤x≤q, 1≤y≤w, 1≤a≤k; the first refresh rate is less than the second refresh rate; Alternatively, the absolute value of Vz-Vuc at the first refresh frequency is greater than or equal to the absolute value of Vz-Vuc at the second refresh frequency; where Vz represents the first initialization voltage of the z-th first initialization period in the write frame, and Vuc represents the first initialization voltage of the c-th second initialization period in the u-th hold frame; where 1≤z≤p, 1≤u≤w, and 1≤c≤h. Alternatively, Tuc-Tz at the first refresh frequency is greater than or equal to Tuc-Tz at the second refresh frequency; where Tz represents the duration of the z-th first initialization period in the write frame, and Tuc represents the duration of the c-th second initialization period in the u-th hold frame; Preferably, w≥2, T(i+1)b-Tia at the first refresh frequency is greater than or equal to T(i+1)b-Tia at the second refresh frequency, where Tia represents the duration of the a-th second light-emitting period in the i-th hold frame, T(i+1)b represents the duration of the b-th second light-emitting period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤b≤k; Preferably, w≥2, the absolute value of V(i+1)d-Vic at the first refresh frequency is greater than or equal to the absolute value of V(i+1)d-Vic at the second refresh frequency, where Vic represents the first initialization voltage of the c-th second initialization period in the i-th hold frame, V(i+1)d represents the first initialization voltage of the d-th second initialization period in the (i+1)-th hold frame, 1≤i≤w-1, 1≤d≤h; Preferably, w≥2, T(i+1)d-Tic at the first refresh frequency is greater than or equal to T(i+1)d-Tic at the second refresh frequency, where Tic represents the duration of the c-th second initialization period in the i-th hold frame, and T(i+1)d represents the duration of the d-th second initialization period in the (i+1)-th hold frame. Preferably, the second refresh frequency is less than or equal to the preset refresh frequency; Preferably, the preset refresh rate is between 30Hz and 60Hz.

22. The display panel according to claim 1, characterized in that, The first terminal of the first functional module is connected to the first initialization voltage, the second terminal of the first functional module is connected to the first or second pole of the driving transistor, and the control terminal of the first functional module is connected to the first control signal. Preferably, the pixel circuit further includes an initialization module, the first terminal of the initialization module is connected to a second initialization voltage, the second terminal of the initialization module is connected to the first terminal of the light-emitting module, and the control terminal of the initialization module is connected to the first control signal; Preferably, the light-emitting control module includes a first light-emitting control unit, which is connected between a first end of the light-emitting module and a second electrode of the driving transistor; Preferably, in at least one working cycle of the pixel circuit, each working cycle comprises multiple working frames including a write frame and at least one hold frame following the write frame; the write frame includes a first emission period; and the hold frame includes a second initialization period and a second emission period.

23. The display panel according to claim 22, characterized in that, The pixel circuit further includes a data writing module, which is connected to the gate or first electrode of the driving transistor. Preferably, the data writing module is connected to the first electrode of the driving transistor, the pixel circuit further includes a compensation module, the light emission control module further includes a second light emission control unit, the compensation module is connected between the second electrode and the gate of the driving transistor, and the second light emission control unit is connected between the first power line and the first electrode of the driving transistor; Preferably, the write frame further includes a data write period, which includes at least one data write sub-period; the data write module and the compensation module are activated during the data write sub-period. Preferably, the pixel circuit further includes a gate reset module, which is connected to the gate of the driving transistor; the write frame further includes a gate reset period, which includes at least one gate reset sub-period, which is performed before the corresponding data write sub-period; the gate reset module is turned on during the gate reset sub-period; the gate reset module is connected to a second control signal; Preferably, the write frame further includes a first initialization period; Preferably, the pixel circuit further includes a storage module, which is connected to the gate of the driving transistor.

24. The display panel according to claim 23, characterized in that, The data writing module and the compensation module are connected to a third control signal; Preferably, in each of the first initialization periods, the first control signal includes at least one first conduction pulse; in each of the second initialization periods, the first control signal includes at least one first conduction pulse; in each of the gate reset periods, the second control signal includes at least one second conduction pulse; and in each of the data write periods, the third control signal includes at least one third conduction pulse; wherein the third conduction pulse of the third control signal follows the corresponding second conduction pulse.

25. The display panel according to claim 23, characterized in that, The compensation module is connected to a third control signal, and the data writing module is connected to a fourth control signal; Preferably, in each of the first initialization periods, the first control signal includes at least two first conduction pulses; in each of the second initialization periods, the first control signal includes at least two first conduction pulses; in each of the gate reset periods, the second control signal includes at least two second conduction pulses; wherein, in a write frame, the third conduction pulse of the third control signal follows the corresponding second conduction pulse; and the fourth conduction pulse of the fourth control signal overlaps with the last third conduction pulse. In the write frame, the last first conduction pulse corresponding to the first initialization period is after the fourth conduction pulse; In the write frame, the first conduction pulse before the last first conduction pulse corresponding to the first initialization period overlaps with the corresponding third conduction pulse.

26. The display panel according to claim 22, characterized in that, The first functional module is connected to the first terminal of the driving transistor, and the first terminal of the first functional module is connected to the data voltage. The pixel circuit further includes a compensation module, which is connected between the second electrode and the gate of the driving transistor, and the control terminal of the compensation module is connected to a third control signal; the light emission control module further includes a second light emission control unit, which is connected between the first power line and the first electrode of the driving transistor. Preferably, the pixel circuit further includes a storage module, which is connected to the gate of the driving transistor; Preferably, the write frame further includes a data write period, which includes at least one data write sub-period; during the data write period, the first terminal of the first functional module is connected to the data voltage corresponding to the pixel circuit; During the second initialization period, the first terminal of the first functional module is connected to the first initialization voltage; Preferably, in the write frame, the first turn-on pulse of the first control signal overlaps with the third turn-on pulse of the third control signal; Preferably, in each working frame, the first control signal includes at least two first conduction pulses, and the third control signal includes at least two third conduction pulses; in the write frame, the first conduction pulse overlaps with the corresponding third conduction pulse. Preferably, in the last data writing sub-period, the data voltage is the data voltage corresponding to the pixel circuit where the data writing module is located; in the data writing sub-periods before the last data writing sub-period, the data voltage is the data voltage corresponding to the pixel circuit preceding the pixel circuit where the data writing module is located. Preferably, the first end of the first functional module is connected to the data cable.

27. A display device, characterized in that, Includes the display panel as described in any one of claims 1-26.

28. A driving method for a display panel, characterized in that, The display panel includes an electrically connected light-emitting module and a pixel circuit. The pixel circuit includes a driving transistor, a light-emitting control module, and a first functional module. The light-emitting control module, the light-emitting module, and the driving transistor are connected in series between a first power line and a second power line. The first functional module is connected to a first or second terminal of the driving transistor. The first functional module is connected to a first initialization voltage and is used to transmit the first initialization voltage to the first or second terminal of the driving transistor when it is turned on. Each of at least one operating cycles of the pixel circuit includes multiple operating frames, each operating frame including a light emission period, and at least one operating frame further including an initialization period; in each of the at least one operating cycle, the driving method includes: During at least a portion of the initialization period, the first functional module is controlled to be turned on; During the light emission period, the light emission control module is turned on; the duration of the light emission period is different in at least two of the working frames; The initialization period durations of at least two of the working frames are different, and / or the first initialization voltages of at least two of the working frames are different, and / or the initialization period includes at least one initialization sub-period, the number of initialization sub-periods of at least two of the working frames is different, and / or the number of initialization sub-periods in each of the at least two working frames is multiple.

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