Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a plurality of pixel circuits and a plurality of light-emitting devices, and the light-emitting devices are connected with the pixel circuits. The pixel circuit comprises a driving transistor, a data write-in transistor, a threshold compensation transistor and a gate reset transistor. An active layer of the driving transistor includes silicon. The gate reset transistor is electrically connected with the second electrode of the driving transistor, and an active layer of the gate reset transistor comprises metal oxide; alternatively, the active layer of the electrode reset transistor contains a metal oxide. According to the invention, the voltage of the low-level signal required by the control transistor can be increased, so that the difference value between the high-level signal and the low-level signal required by the control transistor is reduced, and the power consumption can be reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] The display panel contains pixel circuits and light-emitting devices. The pixel circuits are connected to the light-emitting devices, and the driving transistors in the pixel circuits provide driving current to the light-emitting devices to control the display of different grayscale brightness levels. Currently, pixel circuits generally use metal-oxide transistors with low leakage current connected to the gate of the driving transistor. That is, the transistor connected to the gate of the driving transistor is a n-type transistor, while the driving transistor and other transistors are p-type transistors, thereby achieving low-frequency driving. Since the switching on and off of transistors requires certain conditions, controlling some transistors in the pixel circuit requires relatively high high-level signals and relatively low low-level signals, which increases the power consumption of the display driver chip. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the problem of increased power consumption of the display driver chip caused by the operation of the pixel driving circuit in the prior art.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a plurality of pixel circuits and a plurality of light-emitting devices, the light-emitting devices being connected to the pixel circuits; the pixel circuits include a driving transistor, a data writing transistor, a threshold compensation transistor, and a gate reset transistor; the data writing transistor is electrically connected to the first terminal of the driving transistor, the threshold compensation transistor is connected between the gate and the second terminal of the driving transistor, and the gate reset transistor is electrically connected to the second terminal of the driving transistor; The pixel circuit's operating cycle includes a data writing phase and a gate reset phase. During the gate reset phase, the gate reset transistor and threshold compensation transistor are turned on, and a first reset signal is written to the gate of the driving transistor; the voltage value of the first reset signal is negative. During the data writing phase, the data writing transistor and threshold compensation transistor are turned on, and a data voltage is written to the gate of the driving transistor. The active layer of the driving transistor contains silicon, while the active layer of the gate reset transistor contains metal oxide.

[0005] Secondly, based on the same inventive concept, embodiments of the present invention provide another display panel, the display panel including multiple pixel circuits and multiple light-emitting devices, the light-emitting devices being connected to the pixel circuits; the pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a gate reset transistor, and an electrode reset transistor; the data writing transistor is electrically connected to the first electrode of the driving transistor, the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor, the gate reset transistor is electrically connected to the gate of the driving transistor, and the electrode reset transistor is electrically connected to the first electrode of the light-emitting device; The pixel circuit's operating cycle includes an electrode reset phase, a gate reset phase, and a data writing phase. In the gate reset phase, the gate reset transistor is turned on, and a first reset signal is written to the gate of the driving transistor; the voltage value of the first reset signal is negative. In the electrode reset phase, the electrode reset transistor is turned on, and a second reset signal is written to the first electrode of the light-emitting device; the voltage value of the second reset signal is negative. In the data writing phase, the data writing transistor and the threshold compensation transistor are turned on, and a data voltage is written to the gate of the driving transistor. The active layer of the driving transistor contains silicon, while the active layers of the electrode reset transistor and the gate reset transistor contain metal oxide.

[0006] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of the present invention.

[0007] The display panel and display device provided in the embodiments of the present invention have the following beneficial effects: In some embodiments of the present invention, considering the impact of the voltage required to control the switching state of the gate reset transistor on power consumption, the active layer of the gate reset transistor is configured to contain metal oxide. In other embodiments, considering the impact of the voltage required to control the switching state of the electrode reset transistor on power consumption, the active layer of the electrode reset transistor is configured to contain metal oxide. The present invention can overcome the limitation in related technologies that controlling the on-state of certain transistors requires a lower low-level signal, and increases the voltage value of the low-level signal required to control the transistor. Without adjusting the types of other transistors in the pixel circuit, the high-level voltage value of the control signal required by the pixel circuit remains unchanged, while increasing the low-level voltage value of the required control signal reduces the difference between the high-level signal and the low-level signal required to drive the pixel circuit, thereby reducing power consumption. Furthermore, by increasing the voltage of the low-level signal required to control the transistor, the power management integrated chip does not need to receive an additional power supply when driving the pixel circuit; it can utilize the analog voltage of the display driver chip itself to generate the high-level and low-level signals required to control the transistor, thus reducing the power consumption of the power management integrated chip. At the same time, the number of components in the source management integrated chip will also be reduced, which can further reduce manufacturing costs. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a pixel circuit in related technologies; Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 A signal timing diagram provided in an embodiment of the present invention; Figure 4 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 5 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 6 Another signal timing diagram provided in an embodiment of the present invention; Figure 7 Another signal timing diagram provided in an embodiment of the present invention; Figure 8 Another signal timing diagram provided in an embodiment of the present invention; Figure 9 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 10 Another signal timing diagram provided in an embodiment of the present invention; Figure 11 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 12 Another signal timing diagram provided in an embodiment of the present invention; Figure 13 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 14 Another signal timing diagram provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] Figure 1 This is a schematic diagram of a pixel circuit in related technologies. For example... Figure 1 As shown, the pixel circuit includes transistors T1 to T8, a storage capacitor Cst, and nodes N1 to N4. Specifically, transistor T3 is the driving transistor, transistors T1 and T6 are the light-emitting control transistors, transistor T2 is the data writing transistor, transistor T4 is the threshold compensation transistor, transistors T5 and T7 are the reset transistors, and transistor T8 is the bias transistor. Transistor T1 is connected to the first power supply terminal ELVDD, and the light-emitting device is connected to the second power supply terminal ELVSS. Driving the pixel circuit also requires data voltage Vdata, a first reset signal VREF1, a second reset signal VREF2, a bias signal DVH, scan signals ScanP1, ScanP2, ScanP3, ScanN, and a light-emitting control signal EM.

[0013] exist Figure 1In the related technology, the fourth transistor T4 is an n-type transistor, and the remaining transistors are p-type transistors. In the first driving mode, the voltage required for the driving pixel circuit is 4.6V for the first power supply terminal ELVDD, -4.0V for the second power supply terminal ELVSS, 2V~6V for the data voltage Vdata, -4.0V for the first reset signal VREF1 and the second reset signal VREF2, and 6.0V for the bias signal DVH. To control the second transistor T2 to turn off, the high-level signal VGH of the scan signal ScanP1 needs to be greater than 7V. The source voltage of the seventh transistor T7 is -4.0V, and to fully turn on the seventh transistor T7, the low-level signal VGL of the scan signal ScanP2 needs to be less than -8V. Similarly, the source voltage of the fifth transistor T5 is -4.0V, and to fully turn on the fifth transistor T5, the low-level signal VGL of the scan signal ScanP3 also needs to be less than -8V. However, the voltage range that the current display driver chip can supply is only -7.5V to 7.5V. To achieve a voltage range of -8V to 8V for the display driver chip, adjustments to the chip's manufacturing process are necessary. This requires header room margin, the physical or electrical space reserved in the chip design to ensure signal integrity, heat dissipation, and manufacturing tolerances. Voltages below -8V must be generated by the PMIC (Power Management IC), which combines AVDD (the chip's analog voltage) with an additional power supply to obtain the low-level signal VGL. However, the inefficiency of the voltage converter leads to increased power loss, impacting power consumption.

[0014] exist Figure 1 In the second driving mode, the voltage required for the first power supply terminal ELVDD to operate the pixel circuit is 2.8V, the voltage of the second power supply terminal ELVSS is -5.8V, the data voltage Vdata ranges from 1V to 6V, the first reset signal VREF1 is -5.0V, the second reset signal VREF2 is -5.8V, and the bias signal DVH is 6.0V. To control the second transistor T2 to turn off, the high-level signal VGH of the scan signal ScanP1 needs to be greater than 7V. The source voltage of the seventh transistor T7 is -5.8V, and to control the seventh transistor T7 to be fully turned on, the low-level signal VGL of the scan signal ScanP2 needs to be less than -9.8V. In this case, the low-level signal VGL required to control the seventh transistor T7 to turn on is even lower, and the low-level signal VGL must also be generated by AVDD in combination with an additional power supply. The voltage converter efficiency also leads to increased power loss, affecting power consumption.

[0015] Based on the problems existing in related technologies, the embodiments of the present invention design the transistors in the pixel circuit in a coordinated manner, raising the voltage of the low-level signal required by the control transistor, thereby reducing the difference between the high-level and low-level signals required by the control transistor and thus reducing power consumption. Furthermore, by raising the voltage of the low-level signal required by the control transistor, the power management integrated chip does not need to receive an additional power supply when driving the pixel circuit; it can utilize the analog voltage of the display driver chip itself to generate the high-level and low-level signals required by the control transistor, further reducing the power consumption of the power management integrated chip. The above is the main technical idea of ​​the present invention; the following specific embodiments illustrate the invention.

[0016] This invention provides a display panel comprising multiple pixel circuits and multiple light-emitting devices, the light-emitting devices being connected to the pixel circuits. The light-emitting devices can be, for example, organic light-emitting diodes (OLEDs) or inorganic light-emitting diodes (LEDs). The pixel circuits drive the light-emitting devices to emit light, displaying different grayscale brightness levels.

[0017] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 As shown, the pixel circuit includes a driving transistor T3, a data writing transistor T2, a threshold compensation transistor T4, a gate reset transistor T5, a first light-emitting control transistor T1, a second light-emitting control transistor T6, and a storage capacitor Cst. The gate of the driving transistor T3 is connected to a first node N1, its first electrode is connected to a second node N2, and its second electrode is connected to a third node N3. The first electrode of the data writing transistor T2 receives a data voltage Vdata, and its second electrode is electrically connected to the first electrode of the driving transistor T3. The threshold compensation transistor T4 is connected between the gate and the second electrode of the driving transistor T3. The first electrode of the gate reset transistor T5 receives a first reset signal VREF1, and its second electrode is electrically connected to the second electrode of the driving transistor T3. The first light-emitting control transistor T1 is connected between the first power supply terminal ELVDD and the first electrode of the driving transistor T3, and the second light-emitting control transistor T6 is connected between the second electrode of the driving transistor T3 and the first electrode of the light-emitting device. The second electrode of the light-emitting device is connected to the second power supply terminal ELVSS. The gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are connected to the light-emitting control signal EM. The gate of the data writing transistor T2 receives the scan signal ScanP1, the gate of the gate reset transistor T5 receives the scan signal ScanN1, and the gate of the threshold compensation transistor T4 receives the scan signal ScanN2.

[0018] Among them, the active layer of the driving transistor T3 contains silicon, such as low-temperature polycrystalline silicon, and the driving transistor T3 is a p-type transistor; the active layer of the gate reset transistor T5 contains metal oxide, such as indium gallium zinc oxide, and the gate reset transistor T5 is an n-type transistor.

[0019] Figure 3 This is a signal timing diagram provided for an embodiment of the present invention. Figure 3 The provided signal timing can be used for Figure 2 The pixel circuitry within the module is used for driving. Combined with... Figure 2 and Figure 3 The pixel circuit's operating cycle includes a gate reset phase t1 and a data writing phase t2. In the gate reset phase t1, the scan signal ScanN1 provides an effective level to turn on the gate reset transistor T5, and the scan signal ScanN2 provides an effective level to turn on the threshold compensation transistor T4. The first reset signal VREF1 is written to the gate of the driving transistor T3, resetting the gate of the driving transistor T3. The voltage value of the first reset signal VREF1 is negative. In the data writing phase t2, the scan signal ScanP1 provides an effective level to turn on the data writing transistor T2, and the scan signal ScanN2 provides an effective level to turn on the threshold compensation transistor T4. The data voltage Vdata is written to the gate of the driving transistor T3.

[0020] The display panel provided in this embodiment of the invention includes a pixel circuit. In the pixel circuit, a data writing transistor T2 is connected to the first terminal of a driving transistor T3, a threshold compensation transistor T4 is connected between the gate and the second terminal of the driving transistor T3, and a gate reset transistor T5 is connected to the second terminal of the driving transistor T3. The driving transistor T3 is a p-type transistor, and the gate reset transistor T5 is an n-type transistor. In the gate reset phase t1, the gate reset transistor T5 and the threshold compensation transistor T4 are turned on to reset the gate of the driving transistor T3. In the data writing phase t2, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, writing the data voltage Vdata to the gate of the driving transistor T3 and performing self-testing and compensation on the threshold voltage of the driving transistor T3. Since the gate reset transistor T5 is not directly connected to the gate of the driving transistor T3 in the pixel circuit, the leakage current of the gate reset transistor T5 in the off state has no effect on the gate potential of the driving transistor T3. Therefore, it is not necessary to consider the leakage current of the gate reset transistor T5 when designing its type. In this embodiment of the invention, considering the impact of the voltage required to control the switching state of the gate reset transistor T5 on power consumption, the gate reset transistor T5 is configured as an n-type transistor.

[0021] In the embodiment of the present invention, the driving transistor T3 is a p-type transistor. In order to reset the gate of the driving transistor T3, it is necessary to set the voltage value of the first reset signal VREF1 received by the first pole of the gate reset transistor T5 to be negative. When the gate reset transistor T5 is a p-type transistor, the threshold voltage Vth of the p-type transistor is negative, and it can be turned on only when Vgs < Vth. Vgs represents the gate-source voltage difference of the transistor, Vgs = Vg - Vs, Vg represents the gate voltage of the transistor, and Vs represents the source voltage of the transistor. Since the voltage value of the first reset signal VREF1 is negative, that is, the source voltage of the gate reset transistor T5 is negative, the gate of the gate reset transistor T5 needs to receive a lower low-level signal to satisfy the opening adjustment of the gate reset transistor T5. However, the voltage value of the low-level signal of the scan signal received by the gate of the gate reset transistor T5 is too low, resulting in the need for the power management chip to cooperate with an additional power supply to generate a lower low-level signal, which will inevitably lead to an increase in power consumption.

[0022] In the embodiment of the present invention, the gate reset transistor T5 is set as an n-type transistor. The threshold voltage Vth of the n-type transistor is positive, and it is turned on when Vgs > Vth. The gate of the gate reset transistor T5 receives a high-level signal to control the opening of the gate reset transistor T5. Since the voltage value of the first reset signal VREF1 is negative, that is, the source voltage of the gate reset transistor T5 is negative, the voltage value of the high-level signal received by the gate of the gate reset transistor T5 does not need to be too large.

[0023] From the perspective of the influence of the voltage required to control the switching state of the gate reset transistor T5 on power consumption, the embodiment of the present invention sets the active layer of the gate reset transistor T5 to include metal oxide, breaking the requirement limit of the opening state of the gate reset transistor T5 for a lower low-level signal in the related art, and the voltage value of the high-level signal required to control the opening of the gate reset transistor T5 does not need to be too large, which is equivalent to raising the voltage value of the low-level signal required by the control transistor. Without adjusting the types of other transistors in the pixel circuit, the high-level voltage value of the control signal required by the pixel circuit remains unchanged, while raising the low-level voltage value of the required control signal, so that the difference between the high-level signal and the low-level signal required to drive the pixel circuit is reduced, thereby reducing power consumption. In addition, by raising the low-level signal voltage required by the control transistor, the power management integrated chip does not need to receive an additional power supply when driving the pixel circuit to work, and can use the analog voltage of the display driving chip itself to generate the high-level signal and the low-level signal required by the control transistor, and the power consumption of the power management integrated chip will also be reduced. At the same time, the number of components in the source management integrated chip will also be reduced, which can further reduce the manufacturing cost.

[0024] In some embodiments, such as Figure 2As shown, the active layer of the threshold compensation transistor T4 contains metal oxide, such as indium gallium zinc oxide. That is, the threshold compensation transistor T4 is an n-type transistor. This configuration results in lower leakage current in the off-state of the threshold compensation transistor T4, improving the gate potential stability of the driving transistor T3 and thus enhancing the brightness stability of the light-emitting device. Especially in low-frequency displays, the display panel includes write frames and hold frames. Data voltage is written to the gate of the driving transistor only in the write frame, while the display effect in low-frequency display mode is improved during the hold frame.

[0025] Combination Figure 2 and Figure 3 As can be seen, the threshold compensation transistor T4 is multiplexed in both the threshold compensation phase t1 and the data writing phase t2. The high-level signal of the scan signal ScanN2 controls the threshold compensation transistor T4 to turn on in both the threshold compensation phase t1 and the data writing phase t2. The high-level active pulse of the scan signal ScanN2 covers both the threshold compensation phase t1 and the data writing phase t2 of the pixel circuit operation. By setting the scan signal ScanN2 to have an active level pulse when driving the pixel circuit, the number of signal inversions of the scan signal ScanN2 is reduced, which helps to reduce power consumption.

[0026] like Figure 2 As shown, the pixel circuit includes a first light-emitting control transistor T1 and a second light-emitting control transistor T6. The first light-emitting control transistor T1 is connected between the first power supply terminal and the first electrode of the driving transistor T3, and the second light-emitting control transistor T6 is connected between the second electrode of the driving transistor T3 and the first electrode of the light-emitting device. The pixel circuit's operating cycle also includes a light-emitting phase, which occurs after the data writing phase t2. Figure 3 The timing is not specified. During the light-emitting stage: the light-emitting control signal EM provides an effective level to control the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to turn on, and the driving transistor T3 generates a driving current under the control of its gate potential, thereby controlling the light-emitting device to emit light.

[0027] In other implementations, Figure 4 This is another pixel circuit schematic diagram provided for an embodiment of the present invention. (See diagram below.) Figure 4As shown, the pixel circuit includes a driving transistor T3, a data writing transistor T2, a threshold compensation transistor T4, a gate reset transistor T5, a first light-emitting control transistor T1, a second light-emitting control transistor T6, and a storage capacitor Cst. The pixel circuit also includes an electrode reset transistor T7. The first electrode of the electrode reset transistor T7 receives a second reset signal VREF2, and the second electrode of the electrode reset transistor T7 is electrically connected to the first electrode of the light-emitting device. The second electrode of the electrode reset transistor T7, the first electrode of the light-emitting device, and the second light-emitting control transistor T6 are connected to a fourth node N4. The voltage value of the second reset signal VREF2 is negative. The active layer of the electrode reset transistor T7 contains a metal oxide, such as indium gallium zinc oxide, and the electrode reset transistor T7 is an n-type transistor. The electrode reset transistor T7 is used to reset the first electrode of the light-emitting device.

[0028] In related technologies, when the driving transistor in the pixel circuit is a p-type transistor, the electrode reset transistor T7 is also set to a p-type transistor to simplify the manufacturing process. Furthermore, the function of the electrode reset transistor T7 is to reset the electrodes of the light-emitting device, and there is no requirement for it to have low leakage current. Therefore, when the driving transistor is a p-type transistor and the pixel circuit's operating performance is relatively stable, setting the electrode reset transistor T7 to a p-type transistor is not considered, because changing the transistor type in actual products would inevitably change the pixel circuit layout, increasing the difficulty of the manufacturing process.

[0029] And this application Figure 4 In this embodiment, both the electrode reset transistor T7 and the gate reset transistor T5 are n-type transistors, and the voltage values ​​of both the second reset signal VREF2 and the first reset signal VREF1 are negative. Combined with... Figure 2The reason and effect of setting the gate reset transistor T5 as an n-type transistor in this embodiment are explained. It can be understood that the voltage value of the second reset signal VREF2 received by the first terminal of the electrode reset transistor T7 is negative. When the electrode reset transistor T7 is a p-type transistor, controlling the electrode reset transistor T7 to turn on requires a relatively lower low-level signal, which increases power consumption. In this embodiment, the electrode reset transistor T7 is set as an n-type transistor. The threshold voltage Vth of an n-type transistor is positive, and it turns on when Vgs > Vth. The gate of the electrode reset transistor T7 receives a high-level signal to control its turn-on, and since the voltage value of the second reset signal VREF2 is negative, the voltage value of the high-level signal received by the gate of the electrode reset transistor T7 does not need to be too large. From the perspective of the impact of the voltage required for the switching state of the control electrode reset transistor T7 on power consumption, setting the active layer of the control electrode reset transistor T7 to contain metal oxide eliminates the limitation of requiring a lower low-level signal for the on-state of the control electrode reset transistor T7 in related technologies. Furthermore, the voltage value of the high-level signal required for the control electrode reset transistor T7 to turn on does not need to be excessively large, effectively increasing the voltage value of the low-level signal required by the control transistor. Without adjusting the types of other transistors in the pixel circuit, the high-level voltage value of the control signal required by the pixel circuit remains unchanged, while increasing the low-level voltage value of the required control signal reduces the difference between the high-level and low-level signals required to drive the pixel circuit, thereby reducing power consumption. In addition, by increasing the voltage of the low-level signal required by the control transistor, the power management integrated chip does not need to receive an additional power supply when driving the pixel circuit. It can utilize the analog voltage of the display driver chip itself to generate the high-level and low-level signals required by the control transistor, further reducing the power consumption of the power management integrated chip. Simultaneously, the number of components in the power management integrated chip is reduced, further lowering manufacturing costs.

[0030] In some implementations, the gate of electrode reset transistor T7 and the gate of gate reset transistor T5 receive the same signal. Figure 4 The diagram illustrates that the gates of both electrode reset transistor T7 and gate reset transistor T5 receive the scan signal ScanN1. (Combined with...) Figure 3From the timing diagram, during the gate reset stage t1: the scan signal ScanN1 provides an effective level to control the gate reset transistor T5 to turn on, and the scan signal ScanN2 provides an effective level to control the threshold compensation transistor T4 to turn on. The first reset signal VREF1 is written to the gate of the driving transistor T3, resetting the gate of the driving transistor T3. Simultaneously, the scan signal ScanN1 provides an effective level to control the electrode reset transistor T7 to turn on, and the second reset signal VREF2 is written to the first electrode of the light-emitting device, resetting the first electrode of the light-emitting device. In this embodiment, both the electrode reset transistor T7 and the gate reset transistor T5 are set as n-type transistors, which can reduce power consumption. Simultaneously, by setting the gates of the electrode reset transistor T7 and the gate reset transistor T5 to receive the same signal, the two transistors have the same structure in the display panel film layer, and the two transistors can be controlled by the same control line, which helps to save the number of control lines required for the driving pixel circuit and saves wiring space in the display panel.

[0031] In some embodiments, the voltage value of the first reset signal VREF1 is V1, and the voltage value of the second reset signal VREF2 is V2; where V2 = V1. In this embodiment, the first terminal of the electrode reset transistor T7 and the first terminal of the gate reset transistor T5 can be connected to the same reset signal line, which can help reduce the number of wires in the display panel and save wiring space. Moreover, when V2 = V1, the electrode reset transistor T7 and the gate reset transistor T5 have the same size, and the conditions that both satisfy when they are turned on are the same. By setting both the electrode reset transistor T7 and the gate reset transistor T5 as n-type transistors, the voltage value of the low-level signal required by the control transistor can be increased. Without adjusting the other transistor types in the pixel circuit, the high-level voltage value of the control signal required by the pixel circuit remains unchanged, while increasing the low-level voltage value of the required control signal reduces the difference between the high-level signal and the low-level signal required to drive the pixel circuit, thereby reducing power consumption.

[0032] In one embodiment, the voltage of the first power supply terminal ELVDD required for the pixel circuit to operate is 4.6V, the voltage of the second power supply terminal ELVSS is -4.0V, the data voltage Vdata ranges from 2V to 6V, and the first reset signal VREF1 and the second reset signal VREF2 are both -4.0V. That is, V2 = V1.

[0033] In some embodiments, the voltage value of the first reset signal VREF1 is V1, and the voltage value of the second reset signal VREF2 is V2; where V2 < V1. In this embodiment, different voltages are used to reset the gate of the driving transistor T3 and the electrode of the light-emitting device. Providing a relatively high reset voltage to the gate of the driving transistor T3 can make the threshold capture of the gate of the driving transistor T3 faster. When applied to high-frequency display or low-gray-scale display, the threshold capture time of the gate of the driving transistor T3 is shorter, and the threshold capture is more accurate, which can improve the problem of display unevenness. At the same time, providing a relatively low voltage to reset the electrode of the light-emitting device can reduce the light leakage of the light-emitting device and improve the low-gray-scale display effect.

[0034] In one embodiment, the voltage of the first power supply terminal ELVDD required for the driving pixel circuit to operate is 2.8V, the voltage of the second power supply terminal ELVSS is -5.8V, the data voltage Vdata ranges from 1V to 6V, the first reset signal VREF1 is -5.0V, and the second reset signal VREF2 is -5.8V. That is, V2 < V1.

[0035] Since V2 < V1, when both the electrode reset transistor T7 and the gate reset transistor T5 are p-type transistors, both need to be turned on when the control signal is a low-level signal and Vgs < Vth. Then, compared with the gate reset transistor T5, the voltage value of the low-level signal required to turn on the control electrode reset transistor T7 is lower. That is, the voltage required to turn on the control electrode reset transistor T7 has a greater impact on power consumption. Starting from the perspective of reducing the impact of the voltage required to turn on the control electrode reset transistor T7 on power consumption, the active layer of the electrode reset transistor T7 is provided to include metal oxide, so as to be able to raise the voltage value of the signal required by the control electrode reset transistor T7. Then, there is no need to set a lower low-level signal for the control electrode reset transistor T7, which can reduce the difference between the high-level signal and the low-level signal required by the driving pixel circuit, thereby reducing power consumption. On the basis of setting the active layer of the electrode reset transistor T7 to include metal oxide, the active layer of the gate reset transistor T5 is also set to include metal oxide, so that the gate reset transistor T5 and the electrode reset transistor T7 are of the same type, and their control ends can receive the same signal. A control line can be set in the display panel to control the gate reset transistor T5 and the electrode reset transistor T7, thereby saving the wiring space in the display panel.

[0036] In some other embodiments, Figure 5 is another schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 6 is another signal timing diagram provided by an embodiment of the present invention. As Figure 5As shown, the pixel circuit also includes a bias adjustment transistor T8. The active layer of the bias adjustment transistor T8 contains silicon, and the bias adjustment transistor T8 is a p-type transistor. The bias adjustment transistor T8 is electrically connected to the first or second terminal of the driving transistor T3. Figure 5 The diagram illustrates the bias adjustment transistor T8, where the gate receives the scan signal ScanP2, the first terminal receives the bias voltage DVH, and the second terminal is connected to the first terminal of the drive transistor T3.

[0037] Combination Figure 6 The pixel circuit's operating cycle also includes a bias phase t0. During the bias phase t0, the bias adjustment transistor T8 is turned on, writing the bias voltage DVH to either the first or second terminal of the driving transistor T3. In this embodiment, the pixel circuit also includes the bias adjustment transistor T8, which can adjust the bias state of the driving transistor T3, improving the threshold shift caused by the driving transistor T3 being in a forward bias state for a long time, and thus enhancing display uniformity.

[0038] In some implementations, during the pixel circuit's duty cycle: at least one bias phase t0 is performed before the gate reset phase t1, or at least one bias phase t0 is performed after the data write phase t2. During bias phase t0, the scan signal ScanP2 provides an active level to control the bias adjustment transistor T8 to turn on and write the bias voltage DVH to the first or second terminal of the drive transistor T3. The setting of bias phase t0 does not affect the gate reset phase t1 and the data write phase t2.

[0039] In other implementations, such as Figure 6 As shown, in the pixel circuit's operating cycle: at least one bias stage t0 is executed before the gate reset stage t1, and at least one bias stage t0 is executed after the data write stage t2. By setting the number of effective pulses of the scan signal ScanP2, the pixel circuit's operation can include two or more bias stages t0. Properly configuring two or more bias stages t0 within the pixel circuit's operating cycle can increase the bias adjustment time and improve the effect of adjusting the bias state of the driving transistor T3.

[0040] In other implementations, Figure 7 Another signal timing diagram provided for an embodiment of the present invention. Figure 7 The provided signal timing can be used for Figure 5 The provided pixel circuitry is used for driving. For example... Figure 7 As shown, the working cycle of the pixel circuit includes the gate reset stage t1, the data writing stage t2, and the auxiliary bias stage t0'.

[0041] During the gate reset phase t1, the scan signal ScanN1 provides an effective level to control the gate reset transistor T5 to turn on, and the scan signal ScanN2 provides an effective level to control the threshold compensation transistor T4 to turn on. The first reset signal VREF1 is written to the gate of the driving transistor T3, and the gate of the driving transistor T3 is reset. The voltage value of the first reset signal VREF1 is negative.

[0042] During the data writing phase t2, the scan signal ScanP1 provides an effective level to control the data writing transistor T2 to turn on, and the scan signal ScanN2 provides an effective level to control the threshold compensation transistor T4 to turn on, so that the data voltage Vdata is written to the gate of the driving transistor T3.

[0043] During the auxiliary bias phase t0', the gate reset transistor T5 is turned on and the threshold compensation transistor T4 is turned off, writing the auxiliary bias voltage to the second terminal of the drive transistor T3.

[0044] Figure 5 The diagram illustrates that in the pixel circuit's operating cycle, at least one auxiliary bias stage t0' is executed after the data writing stage t2. This embodiment includes an auxiliary bias stage t0', during which the gate reset transistor T5 adjusts the bias state of the driving transistor T3 to mitigate threshold shift caused by the driving transistor T3 being in a forward bias state for an extended period. The gate reset transistor T5 can reset the gate of the driving transistor T3 in the gate reset stage t1 and also adjust its bias state in the auxiliary bias stage t0', allowing a single transistor to be multiplexed in both stages, resulting in high pixel circuit integration. By simply adjusting the timing of the gate receiving the scan signal from the gate reset transistor T5, the multiplexing of the gate reset transistor T5 in both stages can be achieved, such as... Figure 6 The scan signal ScanN1 shown in the diagram includes two valid level pulses, which cause the gate reset transistor T5 to turn on during the gate reset phase t1 and the auxiliary bias phase t0', respectively.

[0045] Optionally, the first reset signal VREF1 is multiplexed as an auxiliary bias voltage. The first terminal of the gate reset transistor T5 in the display panel is connected to the reset signal line, and the first reset signal VREF1 is multiplexed as an auxiliary bias voltage. This eliminates the need to adjust the voltage on the reset signal line during pixel circuit operation, simplifying the signal supply method.

[0046] In one embodiment, with Figure 7Taking the illustrated timing as an example, the gate of the gate reset transistor T5 receives the first control signal, and the scan signal ScanN1 is the first control signal. During the pixel circuit's operating cycle, the first control signal provides at least two valid pulses; in the gate reset phase t1, the first control signal provides one valid pulse to control the gate reset transistor T5 to turn on; in the auxiliary bias phase t0', the first control signal provides one valid pulse to control the gate reset transistor T5 to turn on. By adjusting the timing of the gate receiving the scan signal from the gate of the gate reset transistor T5, it is possible to multiplex the gate reset transistor T5 in both phases.

[0047] In other embodiments, at least one auxiliary bias stage t0' is performed before the gate reset stage t1. During the auxiliary bias stage t0', the gate reset transistor T5 is turned on, the threshold compensation transistor T4 is turned off, and the auxiliary bias voltage is written to the second terminal of the driving transistor T3. That is, before the gate reset stage t1, the period during which the high-level active pulse of the scan signal ScanN1 and the low-level pulse of the scan signal ScanN2 coincide can be set as the auxiliary bias stage t0'. Adding the auxiliary bias stage t0' before the gate reset stage t1 improves the bias adjustment effect on the driving transistor T3. Optionally, the number of active pulses of the scan signal ScanN1 can be increased so that at least one auxiliary bias stage t0' is performed before the gate reset stage t1, or the width of the active pulses of the scan signal ScanN1 can be increased so that the active pulses of the scan signal ScanN1 cover both the auxiliary bias stage t0' and the gate reset stage t1.

[0048] In other embodiments, at least one auxiliary bias stage t0' is performed before the gate reset stage t1, and at least one auxiliary bias stage t0' is performed after the data write stage t2. This allows for full utilization of the pixel circuit's operating cycle, and increasing the number of auxiliary bias stages t0' improves the bias adjustment effect on the drive transistor T3.

[0049] In other implementations, Figure 8 Another signal timing diagram provided for an embodiment of the present invention. Figure 8 The provided signal timing can be used for driving Figure 5 The pixel circuit provided in the embodiment. (For example...) Figure 8 As shown, the pixel circuit operates in stages including a gate reset phase t1, a data writing phase t2, a bias phase t0, and an auxiliary bias phase t0'. In the bias phase t0, the bias adjustment transistor T8 is turned on, writing the bias voltage DVH to either the first or second terminal of the driving transistor T3. In the auxiliary bias phase t0', the gate reset transistor T5 is turned on, the threshold compensation transistor T4 is turned off, and the auxiliary bias voltage is written to the second terminal of the driving transistor T3. Figure 8The timing analysis shows that the bias phase t0 and the auxiliary bias phase t0' do not overlap in time. This ensures the effectiveness of the two bias phases and avoids mutual interference.

[0050] Figure 8 As illustrated in the timing diagram, a bias stage t0 and an auxiliary bias stage t0' are set after the data writing stage t2, with the auxiliary bias stage t0' located between the data writing stage t2 and the bias stage t0. In other embodiments, a bias stage t0 and an auxiliary bias stage t0' are set after the data writing stage t2, with the bias stage t0 located between the data writing stage t2 and the auxiliary bias stage t0'.

[0051] Figure 9 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 10 This is another signal timing diagram provided in an embodiment of the present invention. Figure 10 The provided signal timing can be used for Figure 5 and Figure 9 The provided pixel circuitry is used for driving. For example... Figure 9 As shown, the pixel circuit includes a bias adjustment transistor T8, the active layer of which contains silicon, and the bias adjustment transistor T8 is a p-type transistor; the gate of the bias adjustment transistor T8 receives the scan signal ScanP2, the first terminal receives the bias voltage DVH, and the second terminal is connected to the second terminal of the driving transistor T3.

[0052] Figure 10 The timing diagram illustrates the operation of the pixel circuit, including a gate reset stage t1, a data write stage t2, a bias stage t0, and an auxiliary bias stage t0'. The bias stage t0 and the auxiliary bias stage t0' are set after the data write stage t2, with the bias stage t0 located between the data write stage t2 and the auxiliary bias stage t0'.

[0053] Based on the same inventive concept, embodiments of the present invention also provide another pixel circuit, which can be applied in a display panel, wherein a light-emitting device is connected to the pixel circuit. Figure 11 This is another pixel circuit schematic diagram provided for an embodiment of the present invention. (See diagram below.) Figure 11As shown, the pixel circuit includes a driving transistor T3, a data writing transistor T2, a threshold compensation transistor T4, a gate reset transistor T5, and an electrode reset transistor T7. The gate of the driving transistor T3 is connected to a first node N1, its first electrode is connected to a second node N2, and its second electrode is connected to a third node N3. The first electrode of the data writing transistor T2 receives a data voltage Vdata, and its second electrode is electrically connected to the first electrode of the driving transistor T3. The threshold compensation transistor T4 is connected between the gate and the second electrode of the driving transistor T3. The first electrode of the gate reset transistor T5 receives a first reset signal VREF1, and its second electrode is connected to the gate of the driving transistor T3. The first electrode of the electrode reset transistor T7 receives a second reset signal VREF2, and its second electrode is connected to the first electrode of the light-emitting device. The active layer of the driving transistor T3 is composed of silicon, while the active layers of the electrode reset transistor T7 and the gate reset transistor T5 are composed of metal oxide. The driving transistor T3 is a p-type transistor, and the electrode reset transistor T7 and the gate reset transistor T5 are n-type transistors.

[0054] The gate of data writing transistor T2 receives scan signal ScanP1, the gate of gate reset transistor T5 receives scan signal ScanN1, the gate of threshold compensation transistor T4 receives scan signal ScanN2, and the gate of electrode reset transistor T7 receives scan signal ScanN3. The pixel driving circuit also requires a first power supply terminal ELVDD and a second power supply terminal ELVSS to operate.

[0055] Figure 12 This is another signal timing diagram provided in an embodiment of the present invention. Figure 12 The signal timing in the code can be used to drive Figure 11 The pixel circuitry within. Combined with... Figure 11 and Figure 12 The working cycle of the pixel circuit includes the electrode reset stage t3, the gate reset stage t1, and the data writing stage t2.

[0056] In the gate reset phase t1, the scan signal ScanN1 provides an effective level to control the gate reset transistor T5 to turn on and write the first reset signal VREF1 to the gate of the driving transistor T3. The voltage value of the first reset signal VREF1 is negative. In the electrode reset phase t3, the scan signal ScanN3 provides an effective level to control the electrode reset transistor T7 to turn on and write the second reset signal VREF2 to the first electrode of the light-emitting device. The voltage value of the second reset signal VREF2 is negative. In the data writing phase t2, the scan signal ScanP1 provides an effective level to control the data writing transistor T2 to turn on and the scan signal ScanN2 provides an effective level to control the threshold compensation transistor T4 to turn on, writing the data voltage to the gate of the driving transistor T3.

[0057] In this embodiment, the driving transistor T3 is a p-type transistor, and the electrode reset transistor T7 and the gate reset transistor T5 are n-type transistors. The gate reset transistor T5 is connected to the gate of the driving transistor T3 and is used to reset the gate of the driving transistor T3. The gate reset transistor T5 is connected to the first electrode of the light-emitting device and is used to reset the first electrode of the light-emitting device. Since the gate reset transistor T5 is connected to the gate of the driving transistor T3, the leakage current of the gate reset transistor T5 in the off state affects the gate potential of the driving transistor T3. By setting the gate reset transistor T5 as an n-type transistor, the leakage current of the gate reset transistor T5 in the off state can be reduced, the stability of the gate potential of the driving transistor T3 can be improved, and thus the brightness stability of the light-emitting device can be improved. Especially in low-frequency display, the display panel includes a writing frame and a holding frame. Data voltage is only written to the gate of the driving transistor in the writing frame, which can improve the display effect of the display panel in the low-frequency display mode in the holding frame.

[0058] For the electrode reset transistor T7, its function is to reset the electrode of the light-emitting device, and there is no requirement for it to have a small leakage current in the pixel circuit. Therefore, when the driving transistor is a p-type transistor and the working performance of the pixel circuit is relatively stable, the electrode reset transistor T7 is not considered to be set as a p-type transistor because changing the type of transistor in the actual product will inevitably change the layout of the pixel circuit and increase the difficulty of the manufacturing process. The inventor of the present application considered from the perspective of the influence of the voltage required to control the switching state of the electrode reset transistor T7 on the power consumption, and set the active layer of the electrode reset transistor T7 to include metal oxide.

[0059] In the embodiment of the present invention, the voltage value of the second reset signal VREF2 received by the first pole of the electrode reset transistor T7 is negative. When the electrode reset transistor T7 is a p-type transistor, the threshold voltage Vth of the p-type transistor is negative, and it can be turned on only when Vgs < Vth is satisfied. Since the voltage value of the second reset signal VREF2 is negative, that is, the source voltage of the electrode reset transistor T7 is negative, the gate of the electrode reset transistor T7 needs to receive a lower low-level signal to meet the opening adjustment of the electrode reset transistor T7. However, the voltage value of the low-level signal of the scanning signal received by the gate of the electrode reset transistor T7 is too low, resulting in that the power management chip needs to cooperate with an additional power supply to generate a lower low-level signal, which will inevitably lead to an increase in power consumption.

[0060] In this embodiment of the invention, the electrode reset transistor T7 is configured as an n-type transistor. The threshold voltage Vth of the n-type transistor is positive, and it turns on when Vgs > Vth. The gate of the electrode reset transistor T7 receives a high-level signal to control the electrode reset transistor T7 to turn on. Since the voltage value of the second reset signal VREF2 is negative, that is, the source voltage of the electrode reset transistor T7 is negative, the voltage value of the high-level signal received by the gate of the electrode reset transistor T7 does not need to be too large.

[0061] This invention addresses the impact of the voltage required for the switching state of the control electrode reset transistor T7 on power consumption. By including a metal oxide layer in the active layer of T7, it overcomes the limitation in related technologies where the control electrode reset transistor T7 requires a lower low-level signal for its on-state. Furthermore, the voltage value of the high-level signal required for T7 to turn on is also reduced, effectively increasing the voltage value of the low-level signal required by the control transistor. Without adjusting the types of other transistors in the pixel circuit, the high-level voltage value of the control signal required by the pixel circuit remains unchanged, while increasing the low-level voltage value reduces the difference between the high-level and low-level signals required to drive the pixel circuit, thereby reducing power consumption. Additionally, by increasing the voltage of the low-level signal required by the control transistor, the power management integrated chip does not need an additional power supply when driving the pixel circuit. It can utilize the analog voltage of the display driver chip itself to generate the high-level and low-level signals required by the control transistor, further reducing the power consumption of the power management integrated chip. Simultaneously, the number of components in the power management integrated chip is reduced, further lowering manufacturing costs.

[0062] Furthermore, the active layers of both the electrode reset transistor T7 and the gate reset transistor T5 contain metal oxide. While setting the gate reset transistor T5 as an n-type transistor to reduce its leakage current in the off-state, the electrode reset transistor T7 is also set as an n-type transistor to reduce power consumption. Since the electrode reset transistor T7 and the gate reset transistor T5 are of the same type, they can be manufactured using the same process, without requiring additional manufacturing processes during display panel production.

[0063] like Figure 11 As shown, the pixel circuit includes a first light-emitting control transistor T1 and a second light-emitting control transistor T6. The first light-emitting control transistor T1 is connected between the first power supply terminal and the first electrode of the driving transistor T3, and the second light-emitting control transistor T6 is connected between the second electrode of the driving transistor T3 and the first electrode of the light-emitting device. The pixel circuit's operating cycle also includes a light-emitting phase, which occurs after the data writing phase t2. Figure 12It is not marked in the timing sequence. In the light-emitting stage: the light-emitting control signal EM provides an effective level to control the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to turn on, and the driving transistor T3 generates a driving current under the control of its gate potential, thereby controlling the light-emitting device to emit light.

[0064] In some embodiments, the active layer of the threshold compensation transistor T4 includes metal oxide. The threshold compensation transistor T4 is an n-type transistor. Such an arrangement makes the leakage current of the threshold compensation transistor T4 in the off state small, which can improve the stability of the gate potential of the driving transistor T3, and further improve the brightness stability of the light-emitting device. Especially in low-frequency display, the display panel includes a writing frame and a holding frame. Data voltage is only written to the gate of the driving transistor in the writing frame, and the display effect of the display panel in the low-frequency display mode can be improved in the holding frame.

[0065] In some embodiments, the voltage value of the first reset signal VREF1 is V1, and the voltage value of the second reset signal VREF2 is V2; where V2 = V1. In this embodiment, the first pole of the electrode reset transistor T7 and the first pole of the gate reset transistor T5 can be connected to the same reset signal line, which is beneficial to reducing the number of wirings in the display panel and saving wiring space.

[0066] In one embodiment, the voltage of the first power supply terminal ELVDD required for the driving pixel circuit to operate is 4.6V, the voltage of the second power supply terminal ELVSS is -4.0V, the data voltage Vdata ranges from 2V to 6V, and both the first reset signal VREF1 and the second reset signal VREF2 are -4.0V. That is, V2 = V1.

[0067] In some other embodiments, the voltage value of the first reset signal VREF1 is V1, and the voltage value of the second reset signal VREF2 is V2; where V2 < V1. In this embodiment, different voltages are used for the gate reset of the driving transistor T3 and the electrode reset of the light-emitting device. Providing a relatively high reset voltage to the gate of the driving transistor T3 can make the threshold capture of the gate of the driving transistor T3 faster. When applied to high-frequency display or low-gray-scale display, the threshold capture time of the gate of the driving transistor T3 is shorter, and the threshold capture is more accurate, which can improve the problem of display unevenness. At the same time, providing a relatively low voltage to reset the electrode of the light-emitting device can reduce the light leakage of the light-emitting device and improve the low-gray-scale display effect.

[0068] In one embodiment, the voltage of the first power supply terminal ELVDD required to drive the pixel circuit is 2.8V, the voltage of the second power supply terminal ELVSS is -5.8V, the data voltage Vdata ranges from 1V to 6V, the first reset signal VREF1 is -5.0V, and the second reset signal VREF2 is -5.8V. That is, V2 < V1.

[0069] When V2 < V1, when the electrode reset transistor T7 is a p-type transistor, the lower the low-level signal required to control the opening of the electrode reset transistor T7, the greater the impact of the voltage required to control the opening of the electrode reset transistor T7 on the power consumption. From the perspective of reducing the impact of the voltage required to control the opening of the electrode reset transistor T7 on the power consumption, the active layer of the electrode reset transistor T7 is provided with metal oxide, so as to be able to raise the voltage value of the signal required for the electrode reset transistor T7. Then, there is no need to set a lower low-level signal for the electrode reset transistor T7, which can reduce the difference between the high-level signal and the low-level signal required to drive the pixel circuit, thereby reducing the power consumption. On the basis that the active layer of the gate reset transistor T5 is provided with metal oxide, the active layer of the electrode reset transistor T7 is also provided with metal oxide, so that the gate reset transistor T5 and the electrode reset transistor T7 are of the same type, and their manufacturing processes are the same. When manufacturing the display panel, no new process needs to be added.

[0070] In some embodiments, the gate of the gate reset transistor T5 receives the first control signal, the gate of the threshold compensation transistor T4 receives the second control signal, and the gate of the electrode reset transistor T7 receives the third control signal. The scan signal ScanN1 is the first control signal, the scan signal ScanN2 is the second control signal, and the scan signal ScanN3 is the third control signal.

[0071] Combined Figure 12 with this, in the gate reset stage t1, the first control signal provides an effective pulse to control the opening of the gate reset transistor T5; in the data writing stage t2, the second control signal provides an effective pulse to control the opening of the threshold compensation transistor T4; in the electrode reset stage, the third control signal provides an effective pulse to control the opening of the electrode reset transistor T7. Using Figure 12When driven sequentially, the electrode reset phase t3 and the gate reset phase t1 in the pixel circuit's operating cycle do not overlap. Although the electrode reset transistor T7 and the gate reset transistor T5 are the same type of transistor, their gates receive different control signals. That is, a separate scan signal is used to control the electrode reset phase t3, separating the time period for resetting the gate of the driving transistor T3 from the time period for resetting the electrodes of the light-emitting device. In applications, the display panel can be configured to have a low-frequency operating mode. In this mode, the electrode reset transistor T7 can be used alone to reset the device electrodes within the pixel circuit's operating cycle to meet low-frequency driving requirements.

[0072] In other implementations, Figure 13 This is another pixel circuit schematic diagram provided for an embodiment of the present invention. Figure 14 This is another signal timing diagram provided in an embodiment of the present invention. Figure 14 The signal timing in the code can be used to drive Figure 13 The pixel circuitry in [the system]. For example... Figure 13 As shown, the pixel circuit also includes a bias adjustment transistor T8. The active layer of the bias adjustment transistor T8 contains silicon, and the bias adjustment transistor T8 is a p-type transistor. The bias adjustment transistor T8 is electrically connected to the first or second terminal of the driving transistor T3. Figure 14 The diagram illustrates the bias adjustment transistor T8 with its gate receiving the scan signal ScanP2, its first terminal receiving the bias voltage DVH, and its second terminal connected to the first terminal of the drive transistor T3.

[0073] Combination Figure 13 and Figure 14 The pixel circuit's operating cycle also includes a bias phase t0. During the bias phase, the bias adjustment transistor T8 is turned on, and the bias voltage DVH is written to either the first or second terminal of the driving transistor T3. In this embodiment, the pixel circuit also includes the bias adjustment transistor T8, which can adjust the bias state of the driving transistor T3, improving the threshold shift caused by the driving transistor T3 being in a forward bias state for a long time, and thus enhancing display uniformity.

[0074] During the pixel circuit's operating cycle: at least one bias stage t0 is executed before the gate reset stage t1, and / or at least one bias stage t0 is executed after the data write stage t2. The setting of the bias stage t0 does not affect the gate reset stage t1 or the data write stage t2. The gate of the bias adjustment transistor T8 receives the scan signal ScanP2. By setting the number of effective pulses of the scan signal ScanP2, one, two, or more bias stages t0 can be included in the operation of the pixel circuit. Properly configuring one, two, or more bias stages t0 within the pixel circuit's operating cycle can increase the bias adjustment time and improve the effect of adjusting the bias state of the driving transistor T3.

[0075] like Figure 14 As shown, the pixel circuit's operating cycle includes two bias stages t0. One bias stage t0 is located before the gate reset stage t1, and the other bias stage t0 is located after the data write stage t2. The scan signal ScanN2 includes two valid pulses, and the scan signal ScanP2 also includes two valid pulses.

[0076] In the bias phase t0 prior to the gate reset phase t1, the scan signal ScanP2 provides a valid pulse to control the bias adjustment transistor T8 to turn on, writing the bias voltage DVH to the first terminal of the driving transistor T3. Simultaneously, the scan signal ScanN2 provides a valid level to control the threshold compensation transistor T4 to turn on. Before the gate reset phase t1, the gate of the driving transistor T3 maintains the signal written in the previous frame, and the driving transistor T3 is turned on, conducting its first and second terminals. This allows the bias voltage DVH to be written to the second terminal of the driving transistor T3 via its first terminal, and then to the gate of the driving transistor T3 via the threshold compensation transistor T4. In this phase, the bias state of the gate of the driving transistor T3 is adjusted by writing the signal to its gate. During this bias phase, the first valid pulse of the scan signal ScanP2 and the first valid pulse of the scan signal ScanN2 at least partially overlap. By adjusting the signal timing of the scan signal ScanN2, the threshold compensation transistor T4 is multiplexed between the bias phase t0 and the data writing phase t2.

[0077] In the bias stage t0 following the data writing stage t2, the scan signal ScanP2 provides an effective pulse to control the bias adjustment transistor T8 to turn on and write the bias voltage DVH to the first terminal of the drive transistor T3 to adjust the bias state of the gate of the drive transistor T3.

[0078] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 15 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 15As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The display panel includes a pixel circuit provided in any embodiment of the present invention. The structure of the pixel circuit has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel circuits and multiple light-emitting devices, and the light-emitting devices are connected to the pixel circuits. The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, and a gate reset transistor. The data writing transistor is electrically connected to the first terminal of the driving transistor, the threshold compensation transistor is connected between the gate and the second terminal of the driving transistor, and the gate reset transistor is electrically connected to the second terminal of the driving transistor. The pixel circuit's operating cycle includes a data writing phase and a gate reset phase. During the gate reset phase, the gate reset transistor and the threshold compensation transistor are turned on, and a first reset signal is written to the gate of the driving transistor, the voltage value of which is negative. During the data writing phase, the data writing transistor and the threshold compensation transistor are turned on, and a data voltage is written to the gate of the driving transistor. The active layer of the driving transistor comprises silicon, and the active layer of the gate reset transistor comprises metal oxide.

2. The display panel according to claim 1, characterized in that, The active layer of the threshold compensation transistor comprises a metal oxide.

3. The display panel according to claim 1, characterized in that, The pixel circuit further includes an electrode reset transistor, the first electrode of which receives a second reset signal, and the second electrode of which is electrically connected to the first electrode of the light-emitting device. The voltage value of the second reset signal is negative, and the active layer of the electrode reset transistor contains metal oxide.

4. The display panel according to claim 3, characterized in that, The gate of the electrode reset transistor and the gate of the gate reset transistor receive the same signal; During the gate reset phase, the electrode reset transistor is turned on, and the second reset signal is written to the first electrode of the light-emitting device.

5. The display panel according to claim 3, characterized in that, The voltage value of the first reset signal is V1, and the voltage value of the second reset signal is V2; wherein, V2≤V1.

6. The display panel according to claim 1, characterized in that, The pixel circuit further includes a bias adjustment transistor, the active layer of which comprises silicon; the bias adjustment transistor is electrically connected to the first or second terminal of the driving transistor. The operating cycle of the pixel circuit also includes a bias phase; during the bias phase, the bias adjustment transistor is turned on and a bias voltage is written to the first or second terminal of the driving transistor.

7. The display panel according to claim 6, characterized in that, During the operating cycle of the pixel circuit: at least one bias phase is performed before the gate reset phase, and / or at least one bias phase is performed after the data write phase.

8. The display panel according to claim 1 or 6, characterized in that, The working cycle of the pixel circuit also includes an auxiliary bias stage; during the auxiliary bias stage, the gate reset transistor is turned on, and the auxiliary bias voltage is written to the second terminal of the driving transistor. During the operating cycle of the pixel circuit: at least one of the auxiliary bias stages is performed before the gate reset stage, and / or at least one of the auxiliary bias stages is performed after the data write stage.

9. The display panel according to claim 8, characterized in that, The first reset signal is multiplexed as the auxiliary bias voltage.

10. The display panel according to claim 8, characterized in that, The gate of the gate reset transistor receives a first control signal, which provides at least two valid pulses during the operating cycle of the pixel circuit. During the gate reset phase, the first control signal provides a valid pulse to control the gate reset transistor to turn on; During the auxiliary bias phase, the first control signal provides a valid pulse to control the gate reset transistor to turn on.

11. The display panel according to claim 8, characterized in that, The operating cycle of the pixel circuit includes the bias phase, and the bias phase and the auxiliary bias phase do not overlap in time.

12. The display panel according to claim 1, characterized in that, The pixel circuit includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is connected between a first power supply terminal and a first electrode of the driving transistor, and the second light-emitting control transistor is connected between a second electrode of the driving transistor and a first electrode of the light-emitting device. The working cycle of the pixel circuit also includes a light-emitting phase, in which the first light-emitting control transistor and the second light-emitting control transistor are turned on, and the driving transistor generates a driving current under the control of its gate potential.

13. A display panel, characterized in that, The display panel includes multiple pixel circuits and multiple light-emitting devices, with the light-emitting devices connected to the pixel circuits. The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a gate reset transistor, and an electrode reset transistor. The data writing transistor is electrically connected to the first electrode of the driving transistor, the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor, the gate reset transistor is electrically connected to the gate of the driving transistor, and the electrode reset transistor is electrically connected to the first electrode of the light-emitting device. The working cycle of the pixel circuit includes an electrode reset phase, a gate reset phase, and a data writing phase. During the gate reset phase, the gate reset transistor is turned on and a first reset signal is written to the gate of the driving transistor, wherein the voltage value of the first reset signal is negative; During the electrode reset phase, the electrode reset transistor is turned on, and a second reset signal is written to the first electrode of the light-emitting device, wherein the voltage value of the second reset signal is negative; during the data writing phase, the data writing transistor and the threshold compensation transistor are turned on, and a data voltage is written to the gate of the driving transistor; wherein, The active layer of the driving transistor comprises silicon, and the active layers of the electrode reset transistor and the gate reset transistor comprise metal oxide.

14. The display panel according to claim 13, characterized in that, The active layer of the threshold compensation transistor comprises a metal oxide.

15. The display panel according to claim 13, characterized in that, The voltage value of the first reset signal is V1, and the voltage value of the second reset signal is V2; wherein, V2≤V1.

16. The display panel according to claim 13, characterized in that, The pixel circuit further includes a bias adjustment transistor, the active layer of which comprises silicon; the bias adjustment transistor is electrically connected to the first or second terminal of the driving transistor. The operating cycle of the pixel circuit also includes a bias phase; during the bias phase, the bias adjustment transistor is turned on and a bias voltage is written to the first or second terminal of the driving transistor.

17. The display panel according to claim 16, characterized in that, During the operating cycle of the pixel circuit: at least one bias phase is performed before the gate reset phase, and / or at least one bias phase is performed after the data write phase.

18. The display panel according to claim 13, characterized in that, The gate of the gate reset transistor receives a first control signal, the gate of the threshold compensation transistor receives a second control signal, and the gate of the electrode reset transistor receives a third control signal. During the gate reset phase, the first control signal provides a valid pulse to control the gate reset transistor to turn on; during the data write phase, the second control signal provides a valid pulse to control the threshold compensation transistor to turn on; during the electrode reset phase, the third control signal provides a valid pulse to control the electrode reset transistor to turn on.

19. The display panel according to claim 13, characterized in that, The pixel circuit includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is connected between a first power supply terminal and a first electrode of the driving transistor, and the second light-emitting control transistor is connected between a second electrode of the driving transistor and a first electrode of the light-emitting device. The working cycle of the pixel circuit also includes a light-emitting phase, in which the first light-emitting control transistor and the second light-emitting control transistor are turned on, and the driving transistor generates a driving current under the control of its gate potential.

20. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1 to 19.

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