Pixel circuit and display device including same

Abstract

The present disclosure relates to a pixel circuit and a display device including the same, in which the pixel circuit includes: a first transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a light emitting element connected to the third node; and a pulse width modulation (PWM) driver connected to the first transistor and configured to adjust a light emission time of the light emitting element according to a data voltage of the pixel data. A first power supply line to which a pixel driving voltage is applied is connected to the first node. An anode of the light emitting element is connected to the third node, and a cathode of the light emitting element is connected to a second power supply line to which a lower ground voltage is applied in a display mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0124432, filed on September 12, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Technology

[0004] Various flat panel displays, such as liquid crystal displays (LCDs) and electroluminescent displays, are known. Electroluminescent displays can display input images without backlighting by using light-emitting elements, each individually disposed in a pixel, to emit light themselves. Based on the material of the light-emitting layer, the light-emitting elements of electroluminescent displays can be classified into organic light-emitting elements and inorganic light-emitting elements.

[0005] Recently, display devices using light-emitting diodes (LEDs) as inorganic light-emitting elements (e.g., micro LEDs as pixel light-emitting elements) have attracted considerable attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect organic materials from moisture, and they offer superior reliability and longer lifespan compared to organic light-emitting diodes (OLEDs). Furthermore, micro LEDs exhibit high conduction speed, excellent luminous efficiency, and shock resistance.

[0006] In pixel circuits used to drive micro-light-emitting diodes (LEDs), color deviations can occur due to shifts in the wavelength of light depending on the amount or density of current flowing through the micro-LED. To address this issue, a pulse-width modulation (PWM) driving method has been proposed that maintains a constant current density in the micro-LED and adjusts the emission time of the micro-LED to represent the grayscale of the pixel data. PWM pixel circuits may also include a constant current source, a data line connected to the constant current source, capacitors, etc. Such PWM pixel circuits involve a large number of transistors and require high-speed driving during digital driving, making it difficult to achieve high resolution. Summary of the Invention

[0007] The purpose of this disclosure is to address the aforementioned needs and / or problems.

[0008] This disclosure provides a pixel circuit that can be driven by PWM without adding data lines and has a simple circuit configuration, as well as a display device including the pixel circuit.

[0009] The problems addressed in this disclosure are not limited to those described above, and other issues not mentioned will become apparent to those skilled in the art from the following description.

[0010] A pixel circuit according to an embodiment of the present disclosure includes: a first transistor including a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; a light-emitting element connected to the third node; and a pulse width modulation (PWM) driver connected to the first transistor and configured to adjust the emission time of the light-emitting element according to the data voltage of pixel data. A first power supply line to which a pixel driving voltage is applied is connected to the first node. The anode of the light-emitting element is connected to the third node, and the cathode of the light-emitting element is connected to a second power supply line to which a voltage lower than the pixel driving voltage is applied in display mode.

[0011] The PWM driver can be connected to a data line to which a data voltage is applied, a first gate line to which a first gate signal is applied, a second gate line to which a second gate signal is applied, a first node, a second node, and a second power supply line.

[0012] The first gate signal may include a pulse that oscillates between a gate high voltage and a gate low voltage during each frame period in display mode. The second gate signal may be generated as a ramp waveform signal that rises from a minimum voltage to a maximum voltage during each frame period in display mode. The gate high voltage may be higher than the pixel drive voltage, and the gate low voltage may be lower than the ground voltage. The maximum voltage of the ramp waveform signal may be lower than the gate high voltage and higher than the pixel drive voltage, and the minimum voltage of the ramp waveform signal may be lower than the ground voltage and higher than the gate low voltage.

[0013] The light-emitting period of the light-emitting element can be lengthened as the data voltage increases.

[0014] The PWM driver may include: a capacitor disposed between a fourth node and a second gate line; a second transistor including a first electrode connected to the second node, a gate connected to the first gate line, and a second electrode connected to a second power line; a third transistor including a first electrode connected to a data line, a gate connected to the first gate line, and a second electrode connected to the fourth node; and a fourth transistor including a first electrode connected to the second node, a gate connected to the fourth node, and a second electrode connected to the first node.

[0015] When the fourth transistor is turned on, the light-emitting element can begin to emit light. The earlier the fourth transistor is turned on, the longer the light-emitting period of the element can last.

[0016] The PWM driver can be connected to a data line to which a data voltage is applied, a first gate line to which a first gate signal is applied, a second gate line to which a second gate signal is applied, a third gate line to which a third gate signal is applied, a first node, a second node, and a second power supply line.

[0017] The pixel circuit further includes: a first switching element configured to supply a first gate signal to the third gate line in a display mode and a third gate signal to the third gate line in a sensing mode; and a sensing circuit connected to the pixel circuit and operating in a sensing mode.

[0018] The sensing circuit may include: an analog-to-digital converter; and a second switching element configured to supply a ground voltage to the cathode of the light-emitting element in display mode and to connect the cathode of the light-emitting element to the input terminal of the analog-to-digital converter in sensing mode.

[0019] The first gate signal can be a high gate voltage during the initialization and sensing periods in sensing mode, and a low gate voltage during the sampling period in sensing mode. In sensing mode, the voltage of the second gate signal can remain at a reference voltage during the initialization, sampling, and sensing periods. In sensing mode, the voltage of the third gate signal can be a low gate voltage during the initialization and sensing periods, and a high gate voltage during the sampling period. The high gate voltage can be higher than the pixel drive voltage, and the low gate voltage and reference voltage can be lower than the ground voltage. The maximum voltage of the ramp waveform signal can be lower than the high gate voltage and higher than the pixel drive voltage, and the minimum voltage of the ramp waveform signal can be lower than the ground voltage and higher than the low gate voltage.

[0020] The PWM driver may include: a capacitor disposed between a fourth node and a second gate line; a second transistor including a first electrode connected to the second node, a gate connected to the first gate line, and a second electrode connected to a second power line; a third transistor including a first electrode connected to a data line, a gate to which a third gate signal is applied in sensing mode, and a second electrode connected to the fourth node; and a fourth transistor including a first electrode connected to the second node, a gate connected to the fourth node, and a second electrode connected to the first node.

[0021] A display device according to an embodiment of the present disclosure includes: a display panel, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of sub-pixels are arranged therein; a data driver connected to the data lines; and a gate driver connected to the gate lines. Each sub-pixel includes pixel circuitry.

[0022] According to the embodiments of this disclosure, light-emitting elements can be driven with high efficiency and high brightness, thereby improving service life and achieving low-power driving. Furthermore, PWM driving of the light-emitting elements can be performed without adding data lines, which simplifies the configuration of pixel circuits.

[0023] Embodiments of this disclosure can improve the image quality and lifespan of a display device by sensing the threshold voltage of a transistor that affects the light-emitting period of the light-emitting element and compensating for threshold voltage deviations between transistors of sub-pixels or threshold voltage offsets caused by stress accumulation in the transistors.

[0024] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the description of the claims other effects not mentioned. Attached Figure Description

[0025] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0027] Figure 2 This is a block diagram illustrating a display device according to another embodiment of the present disclosure;

[0028] Figure 3 This is a diagram showing the display mode and sensing mode;

[0029] Figure 4 It is shown Figure 1 and Figure 2 A diagram showing an example of a gate driver;

[0030] Figure 5 This is a circuit diagram showing the ramp signal output section according to an embodiment of the present disclosure;

[0031] Figure 6 It is shown Figure 5 The waveform diagrams of the input and output signals of the ramp signal output section shown are examples.

[0032] Figure 7 This is a waveform diagram illustrating an example of pulse sequence shifting of the second gate signal;

[0033] Figure 8 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure;

[0034] Figure 9 This is a diagram illustrating an example of how the emission period of a light-emitting element is changed according to the grayscale of pixel data;

[0035] Figure 10 It is shown in detail Figure 8 The circuit diagram of an example pixel circuit shown;

[0036] Figure 11 It is shown Figure 10 The waveform diagram shows an example of the input and output signals of the pixel circuit in display mode;

[0037] Figure 12 It shows the basis Figure 10 The waveform diagram of the light emission period of the light-emitting element in the pixel circuit shown is a grayscale representation of the pixel data.

[0038] Figure 13 It shows when Figure 10 A waveform diagram illustrating an example of how the light-emitting period of the light-emitting element changes when the threshold voltage of the fourth transistor in the pixel circuit shown changes.

[0039] Figure 14 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure; and

[0040] Figure 15 This shows the application applied in sensing mode. Figure 14 The waveform diagram of the gate signal of the pixel circuit shown is shown. Detailed Implementation

[0041] The advantages and features of this disclosure and its implementation methods will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope.

[0042] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0043] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0044] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0045] When describing the position or interconnection between two components, such as "on top of", "above", "below", "next to", "connected to or combined with", "cross", "intersect", etc., one or more other components may be inserted between the two components, unless "close to" or "directly" is used.

[0046] When describing time-prior relationships, such as "after," "next," "immediately after," "before," etc., the time basis may not be continuous unless "immediately" or "directly" is used.

[0047] The terms “first”, “second”, etc., can be used to distinguish elements from each other, but the function or structure of a component is not limited by the ordinal number preceding the component or the component name.

[0048] The following embodiments may be combined or integrated with each other in part or in whole, and may be linked and operated in various technical ways. The embodiments may be implemented independently of each other or in connection with each other.

[0049] The pixel circuit of a display device may include multiple transistors. A transistor is a three-electrode element comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. The current direction in an n-channel transistor is from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0050] The gate signal can oscillate between the gate on-state voltage and the gate off-state voltage. The transistor turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage. In the case of an n-channel transistor, the gate on-state voltage can be the gate high voltage VGH, and the gate off-state voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-state voltage can be the gate low voltage VGL, and the gate off-state voltage can be the gate high voltage VGH.

[0051] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Reference Figure 1 A display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100, and a power supply 150 for generating power required to drive the pixels 101 and the display panel driving circuit.

[0053] The substrate of the display panel 100 may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. The display panel 100 may be, but is not limited to, a rectangular panel having a length in the X-axis direction (or a first direction), a width in the Y-axis direction (or a second direction), and a thickness in the Z-axis direction (or a third direction). For example, at least a portion of the display panel 100 may have a curved outer perimeter.

[0054] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device, in which an image is displayed on a screen and the actual object is visible outside the display panel. The display panel 100 can be made into a flexible display panel. Furthermore, the display panel 100 can be made from a stretchable panel that can be stretched.

[0055] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels 101. The power lines are commonly connected to the pixels and supply a constant voltage required to drive the pixels 101. The power lines may be implemented as elongated wiring along a first direction or a second direction, or as a mesh-like wiring where wiring in the first direction and wiring in the second direction are electrically connected.

[0056] Each pixel 101 can be divided into red, green, and blue sub-pixels for color display. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving the light-emitting element. In the following text, "pixel" can be understood as "sub-pixel".

[0057] The pixel array comprises multiple pixel rows L1 to Ln, where n is a natural number greater than or equal to 2. Each of the pixel rows L1 to Ln may include multiple sub-pixels arranged along the X-axis in the pixel array of the display panel 100. Pixels arranged in a pixel row may share a gate line 103. Sub-pixels arranged along the Y-axis may share the same data line 102. A horizontal time period is approximated by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0058] Power supply 150 uses a DC-DC converter to generate a constant voltage (or direct current (DC) voltage) required to drive the pixel array and display panel driving circuitry of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can regulate the level of the input voltage Vin from host system 200 to output a constant voltage, such as a gamma reference voltage, gate low voltage, gate high voltage, pixel drive voltage, pixel ground voltage (hereinafter referred to as "ground voltage"), etc. The gamma reference voltage is supplied to data driver 110. The dynamic range of the data voltage output from data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the maximum and minimum voltage of the data voltage.

[0059] Gate high and gate low voltages are supplied to level shifter 140 and gate driver 120. For example, a constant voltage, such as the pixel drive voltage and ground voltage, is supplied to pixel 101 via a power line commonly connected to pixel 101. The pixel drive voltage can be supplied to the display panel 100 from the main power supply of host system 200. In this case, power supply 150 does not need to output the pixel drive voltage.

[0060] The display panel driving circuit, under the control of the timing controller 130, writes pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a data driver 110, a gate driver 120, and a level shifter 140. The display panel driving circuit may also include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single driver IC (integrated circuit). The timing controller 130, power supply 150, level shifter 140, data driver 110, and touch sensor driver can be further integrated into the driver IC.

[0061] Data driver 110 receives pixel data DATA' of the input image supplied as a digital signal from timing controller 130 and outputs a data voltage for the pixel data. Data driver 110 outputs the data voltage by converting the pixel data DATA' of the input image into a gamma-compensated voltage using a digital-to-analog converter (hereinafter referred to as "DAC") arranged in the data output channel. The gamma reference voltage is divided into gamma-compensated voltages for individual grayscale values ​​by a voltage divider circuit in data driver 110 and supplied to the DAC. The DAC generates a data voltage as a gamma-compensated voltage corresponding to the grayscale value of the pixel data DATA'. The data voltage output from the DAC is output to data line 102 through an output buffer in each data output channel of data driver 110.

[0062] The gate driver 120 may be formed in the display panel 100 together with the TFT array of the pixel array and wiring. The gate driver 120 may be disposed in the non-display area NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed in the display area AA.

[0063] Gate driver 120 can be located in the left non-display area NA or right non-display area NA outside the display area AA in the display panel 100 to supply gate signal to gate line 103 using a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. Gate driver 120 can also be located in the left non-display area NA and right non-display area NA in the display panel 100 to apply gate signal to gate line 103 using a dual-feed method. In the dual-feed method, the gate signal is applied to both ends of gate line 103 simultaneously. At least a portion of the circuitry of gate driver 120 can be located within the display area AA. Gate driver 120 may include one or more shift registers and / or one or more edge-triggered flip-flops to output pulses of the gate signal under the control of timing controller 130.

[0064] The gate signal can include a square wave gate signal and a ramp waveform with a voltage that gradually changes at a constant slope. In this case, the display device may also include a ramp waveform signal generation circuit. The ramp waveform signal generation circuit may be mounted on a circuit board, such as a printed circuit board (PCB), electrically connected to the display panel 100, or may be disposed on the display panel 100. The gate driver 120 may include the ramp waveform signal generation circuit to output a ramp waveform gate signal.

[0065] The timing controller 130 receives pixel data of the input image and timing signals synchronized with the pixel data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The vertical and horizontal time intervals can be determined by counting the data enable signal DE, therefore the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has an interval of one horizontal time interval (1H).

[0066] The timing controller 130 can control the operating timing of the data driver 110 and the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The gate timing control signal output from the timing controller 130 can be input to the gate driver 120 via a level shifter 140. The level shifter 140 can receive the gate timing control signal and generate a start pulse and a clock signal to supply to the gate driver 120. The input signal to the level shifter 140 is a digital signal voltage level signal. The start pulse and clock signal output from the level shifter 140 can oscillate between a gate high voltage and a gate low voltage. The data timing control signal generated from the timing controller 130 is transmitted to the data driver 110.

[0067] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100, and can transmit it to the timing controller 130 along with the timing control signal.

[0068] Figure 2 This is a block diagram illustrating a display device according to another embodiment of the present disclosure. In this embodiment, descriptions that are redundant with those in the foregoing embodiments are omitted.

[0069] Reference Figure 2 The display area AA of the display panel 100 includes multiple data lines 302, multiple gate lines 303 intersecting the data lines 302, multiple sensing lines 304, and pixels 301. The display panel 100 may also include power lines that are commonly connected to the pixels 301. The sensing lines 304 may be electrically connected to the transistors and / or light-emitting elements of the sub-pixels.

[0070] The display device may further include a sensing circuit 400. The sensing circuit uses a data driver 310, a gate driver 320, and a sensing line 304 to supply digital data (hereinafter referred to as "sensing data") corresponding to the sensing voltage obtained from the sub-pixel to a timing controller 330. The sensing circuit can be driven into a sensing mode to output the sensing data.

[0071] Data driver 310 can be connected to data line 302 and sensing line 304. Data driver 310 receives pixel data DATA' of the input image supplied from timing controller 330 and outputs a data voltage. Data driver 310 includes a data channel electrically connected to data line 302 and outputting a data voltage, and a sensing channel electrically connected to sensing line 304 and receiving a sensing voltage. The data output channel uses a DAC to convert the pixel data DATA' of the input image into a gamma-compensated voltage and outputs the pixel data data voltage. The sensing channel includes an analog-to-digital converter (hereinafter referred to as "ADC"). The sensing channel uses the ADC to convert the sensing voltage received through sensing line 304 into digital data and outputs sensing data Dsen. Sensing line 304 can be connected to the cathode of a light-emitting element LD, such as... Figure 14 As shown. The sensing data Dsen is sent to the timing controller 330.

[0072] Each sub-pixel includes a transistor for driving the light-emitting element. The transistor should have uniform electrical characteristics across all sub-pixels; however, variations in process technology and device characteristics can lead to differences in electrical characteristics between pixels. Furthermore, transistors may degrade over time. This degradation can result in decreased image quality and reduced lifespan. An external compensation circuit can compensate for these variations in the electrical characteristics of each sub-pixel in real time by sensing the transistor's electrical characteristics and using the sensing results to modulate the pixel data of the input image.

[0073] The display panel driving circuit writes pixel data of the input image to pixel 301 by scanning pixels in display mode under the control of timing controller 330. In display mode, the input image is reproduced on display area AA. In sensing mode, the sensing circuit can be driven to sequentially sense the electrical characteristics of sub-pixels in display area AA, such as the threshold voltage of transistors.

[0074] like Figure 3 As shown, the display panel driving circuit can enter a sensing mode in at least one of the following: the power-on sequence when power is applied to the display device, the vertical blanking period during the display time (hereinafter referred to as the "blanking period"), and the power-off sequence when the power-off switch of the display device is turned on.

[0075] When driving the pixels 301 of the display panel 100, the electrical characteristics of the sub-pixels can be sensed in real time. For example, during the blanking period between the (N)th frame time period (N is a natural number) and the (N+1)th frame time period when there is no input image pixel data, the display panel driving circuit can enter a real-time sensing mode under the control of the timing controller 330 to sense the sub-pixels of the selected pixel row. Figure 3In the diagram, the shaded areas between frame periods represent blanking periods. A frame period can include a display period (AT) and a vertical blanking period, such as... Figure 3 As shown. The data of the (N)th frame can be written to the pixel 301 of the display panel 100 during the display period AT of the (N)th frame time, and the data of the (N+1)th frame can be written to the pixel 301 of the display panel 100 during the display period AT of the (N+1)th frame time.

[0076] Because the blanking period is short, it is impossible to sense the electrical characteristics of each sub-pixel in all pixel rows of the display panel 100. In this case, in real-time sensing mode, the sub-pixels of the selected pixel row can be sensed during the blanking period of the (N)th frame period under the control of the timing controller 330, and the sub-pixels of the selected pixel row can be sensed during the blanking period of the (N+1)th frame period under the control of the timing controller 330.

[0077] The timing controller 330 can receive sensing data Dsen from the sensing channel of the data driver 310 and can obtain a compensation value based on the sensing data Dsen to compensate for the threshold voltage shift of the transistors in each sub-pixel. The compensation value can be pre-stored in a lookup table memory accessed by the timing controller 330. Threshold voltage data can be stored for each sub-pixel, and this threshold voltage data is stored in the lookup table memory. When sensing data Dsen is input, the lookup table memory can output the compensation value of the threshold voltage Vth stored at the address indicated by the sensing data Dsen. The timing controller 330 can update the threshold voltage data stored in the lookup table memory with the sensing data Dsen received from the ADC.

[0078] The timing controller 330 can modulate the pixel data DATA of the input image by adding or multiplying a compensation value obtained based on the sensing data Dsen with the pixel data DATA. The modulated pixel data DATA' has a grayscale value modulated by the threshold voltage shift of the transistor DR. During the display period AT in the display mode, the modulated pixel data DATA' is transferred from the timing controller 330 to the data driver 310, where it is converted into a data voltage and written to the sub-pixel.

[0079] During the display period AT of each frame in display mode, the data driver 310 converts the modulated pixel data DATA' received from the timing controller 330 into a data voltage Vdata and outputs the converted data voltage Vdata. In sensing mode, the data driver 310 can output a sensing data voltage. The sensing data voltage can be applied to the sub-pixel through the data line 302, similar to the data voltage of the pixel data. In sensing mode, after the sensing data generated by the timing controller 330 is converted into a gamma-compensated voltage, the data driver 310 can output the sensing data voltage, but is not limited to this. The sensing data voltage can be set to a voltage lower than the threshold voltage of the light-emitting element, so as to be able to sense the threshold voltage of the transistor driving the light-emitting element, while preventing the light-emitting element from emitting light.

[0080] Gate driver 320 can output a gate signal synchronized with the data voltage corresponding to pixel data to gate line 303 during the display period AT of each frame period, and in sensing mode, gate driver 320 can output a gate signal synchronized with the sensed data voltage to gate line 303. The gate signal may include a ramp signal. Gate driver 320 may include ramp signal generation circuitry to output the ramp signal.

[0081] When multiple gate signals are applied to each pixel, gate drivers 120 and 320 may include multiple gate drivers.

[0082] Figure 4 It is shown Figure 1 and Figure 2 A diagram illustrating an example of a gate driver. Figure 4 In the given (ni), i is a positive integer less than n. SCAN1(x) is the first gate signal applied to the sub-pixel of the (x)th pixel row (where x is a positive integer less than or equal to n). SCAN2(x) is the second gate signal applied to the sub-pixel of the (x)th pixel row.

[0083] Reference Figure 4 The gate driver 120 may include a first gate driver 121 configured to output pulses of a first gate signal SCAN1(1) to SCAN1(n), a second gate driver 122 configured to output a second gate signal SCAN2(1) to SCAN2(n), and a ramp waveform signal generator 123.

[0084] The shift register of the first gate driver 121 may include multiple cascaded signal transmitters ST1. The first gate driver 121 outputs pulses of the first gate signal SCAN1(1) to SCAN1(n) sequentially by receiving the first start signal VST1 and the first clock S1CLK.

[0085] The shift register of the second gate driver 122 includes multiple cascaded signal transmitters ST2. The second gate driver 122 outputs pulses of the second gate signal SCAN2(1) to SCAN2(n) sequentially by receiving the second start signal VST2 and the second clock S2CLK.

[0086] The signal transmitter ST2 of the second gate driver 122 sequentially outputs pulses of the second gate signal SCAN2(1) to SCAN2(n), and the ramp waveform signal generator 123 can receive the pulses of the second gate signal SCAN2(1) to SCAN2(n) input from the second gate driver 122, and convert the pulses of the second gate signal SCAN2(1) to SCAN2(n) into ramp waveform signals.

[0087] The ramp waveform signal generator 123 may include a plurality of ramp signal output sections 30, each connected to a signal transmitter ST2 of the second gate driver 122. Each of the ramp signal output sections 30 converts a pulse input from the corresponding signal transmitter ST2 into a ramp waveform signal.

[0088] Gate driver 120 may further include a third gate driver 124 configured to output pulses of third gate signals SCAN3(1) to SCAN3(n). The shift register of the third gate driver 124 includes a plurality of cascaded signal transmitters ST3. The third gate driver 124 outputs pulses of the third gate signals SCAN3(1) to SCAN3(n) sequentially by receiving a third start signal VST3 and a third clock S3CLK.

[0089] Gate driver 120 may further include a fourth gate driver 125 configured to output pulses of the fourth gate signals RP(1) to RP(n). The shift register or edge-triggered flip-flop of the fourth gate driver 125 includes a plurality of cascaded signal transmitters ST4. The fourth gate driver 125 outputs pulses of the fourth gate signals RP(1) to RP(n) sequentially by receiving a fourth start signal VST4 and a fourth clock E4CLK.

[0090] Figure 5 This is a circuit diagram showing a ramp signal output section according to an embodiment of the present disclosure. Figure 6 It is shown Figure 5 The waveform diagram shows an example of the input and output signals of the ramp signal output section. Figure 6 In this text, "VGL" indicates gate low voltage, and "VGH" indicates gate high voltage. "1 frame" indicates a 1-frame time period.

[0091] Reference Figure 5 and Figure 6The ramp signal output unit 30 includes a current generator 52, a ramp waveform signal controller 54, and a charger 56. The current generator 52 generates current by receiving input signals SCAN(n-1) to SCAN(n) and RP(n). The ramp waveform signal controller 54 controls the waveform of the current generated by the current generator 52 to have a ramp waveform by initializing the charger 56 and adjusting the amount of charge accumulated in the charger 56. The charger 56 charges the charge from the current generator 52.

[0092] The ramp signal output unit 30 receives a first input signal SCAN(n-1), a second input signal SCAN(n), and a third input signal RP(n), and outputs a second gate signal SCAN2(n) with a ramp waveform. The first input signal SCAN(n-1) and the second input signal SCAN(n) can be the (n-1)th pulse and the (n)th pulse sequentially output from the second gate driver 122. The third input signal RP(n) can be a pulse output from the fourth gate driver 125.

[0093] The pulses of the first input signal SCAN(n-1) and the second input signal SCAN(n) can be generated using a low gate voltage (VGL) and can have a pulse width of approximately one horizontal period (1H), such as Figure 6 As shown. A pulse for the third input signal RP(n) can be generated using a gate high voltage (VGH), and the pulse for the third input signal RP(n) can have a pulse width of approximately three horizontal time intervals so as to overlap with the pulses for the first input signal SCAN(n-1) and the second input signal SCAN(n), as shown. Figure 6 As shown.

[0094] The ramp signal output unit 30 can receive the ramp data voltage SCD. The ramp data voltage SCD can be output from the data driver 110 under the control of the timing controller 130, or it can be output from the power supply 150. The ramp data voltage SCD can be generated with the same data value during a frame period. Therefore, the ramp data voltage SCD can be input to all the ramp signal output units 30 formed on the display panel 100 through a single wiring formed on the display panel 100.

[0095] The timing controller 130 or the host system 200 can change the slope of the second gate signal SCAN2(n) by changing the voltage level of the ramp data voltage SCD.

[0096] The current generator 52 may include first transistors M01 through M06 and a first capacitor C1. The ramp waveform signal controller 54 includes a seventh transistor M07. The charger 56 may include a second capacitor C2. Transistors M01 through M07 may be implemented as p-channel transistors, but are not limited thereto.

[0097] A first transistor M01 is connected between a first node 61 and a third node 63 to which a drive voltage VDD is applied, and generates current based on the gate-source voltage. A first capacitor C1 charges the gate-source voltage of the first transistor M01. The first transistor M01 includes a first electrode connected to the first node 61, a gate connected to the second node 62, and a second electrode connected to the third node 63. The first capacitor C1 is connected between the VDD node to which the drive voltage VDD is applied and the second node 62.

[0098] The second transistor M02 is connected between the ramp data line SL, to which the ramp data voltage SCD is applied, and the first node 61, and is turned on in response to a low gate voltage VGL of the second input signal SCAN(n). When the second transistor M02 is turned on, the ramp data line SL can be applied to the first node 61. The second transistor M02 includes a first electrode to which the ramp data voltage SCD is applied, a gate to which the second input signal SCAN(n) is applied, and a second electrode connected to the first node 61.

[0099] The third transistor M03 is connected between the VDD node and the first node 61, and is turned on in response to a low gate voltage VGL of the third input signal RP(n). When the third transistor M03 is turned on, the VDD node is electrically connected to the first node 61. The third transistor M03 includes a first electrode connected to the VDD node, a gate to which the third input signal RP(n) is applied, and a second electrode connected to the first node 61.

[0100] A fourth transistor M04 is connected between the second node 62 and the third node 63, and is turned on in response to a low gate voltage VGL of the second input signal SCAN(n). When the fourth transistor M04 is turned on, the second node 62 is electrically connected to the third node 63. The fourth transistor M04 includes a first electrode connected to the second node 62, a gate to which the second input signal SCAN(n) is applied, and a second electrode connected to the third node 63.

[0101] A fifth transistor M05 is connected between the second node 62 and the initialization voltage node to which the initialization voltage Vini is applied, and is turned on in response to a low gate voltage VGL of the first input signal SCAN(n-1). When the fifth transistor M05 is turned on, the second node 62 is electrically connected to the initialization voltage node. The fifth transistor M05 includes a first electrode connected to the second node 62, a gate to which the first input signal SCAN(n-1) is applied, and a second electrode connected to the initialization voltage node.

[0102] A sixth transistor M06 is connected between the third node 63 and the fourth node 64, and is turned on in response to a low gate voltage VGL of the third input signal RP(n). When the sixth transistor M06 is turned on, the third node 63 is electrically connected to the fourth node 64. The sixth transistor M06 includes a first electrode connected to the third node 63, a gate to which the third input signal RP(n) is applied, and a second electrode connected to the fourth node 64.

[0103] A seventh transistor M07 is connected between the fourth node 64 and a reference voltage node (or ground voltage node) to which a reference voltage Vlow is applied, and is turned on in response to a low gate voltage VGL of the first input signal SCAN(n-1). The voltage of the fourth node 64 is the voltage of the second gate signal SCAN2(n). The fourth node 64 is connected to the pixel circuit of pixel 101 via a gate line. When the seventh transistor M07 is turned on, the reference voltage node is electrically connected to the fourth node 64, and the reference voltage Vlow is applied to the fourth node 64. The seventh transistor M07 includes a first electrode connected to the fourth node 64, a gate to which the first input signal SCAN(n-1) is applied, and a second electrode connected to the reference voltage node (or ground voltage node).

[0104] The second capacitor C2 can be connected between the fourth node 64 and the reference voltage node (or the ground voltage node).

[0105] The driving period of the ramp signal output unit 30 can be divided into a first period Til, a second period Ti2, and a third period Tramp. A holding period Th can be set between the second period Ti2 and the third period Tramp (during the holding period Th, the second transistor M02 to the seventh transistor M07 are in the off state).

[0106] After a pulse of the first input signal SCAN(n-1) is generated during the first time period Til, a pulse of the second input signal SCAN(n) is generated during the second time period Ti2. During two or three horizontal time periods including the first time period Til and the second time period Ti2, a pulse of the third input signal RP(n) is generated using a high gate voltage VGH. The pulse of the third input signal RP(n) overlaps with the pulses of the first input signal SCAN(n-1) and the second input signal SCAN(n).

[0107] During the first time period Til, the voltage of the first input signal SCAN(n-1) is the gate low voltage VGL, and the voltages of the second input signal SCAN(n) and the third input signal RP(n) are the gate high voltage VGH. Therefore, during the first time period Til, the fifth transistor M05 and the seventh transistor M07 are turned on, while the second transistor M02, the third transistor M03, the fourth transistor M04, and the sixth transistor M06 are turned off.

[0108] During the first time period Til, the second node 62 is initialized to the initialization voltage Vini, and the fourth node 64 is initialized to the reference voltage Vlow. Therefore, during the first time period Til, the voltage of the second node 62 decreases to the initialization voltage Vini, and the voltage of the second gate signal SCAN2(n) decreases to the reference voltage Vlow.

[0109] During the second time period Ti2, the voltages of the first input signal SCAN(n-1) and the third input signal RP(n) are both high gate voltages VGH, while the voltage of the second input signal SCAN(n) is a low gate voltage VGL. Therefore, during the second time period Ti2, the second transistor M02 and the fourth transistor M04 are turned on, while the third transistor M03, the fifth transistor M05, the sixth transistor M06, and the seventh transistor M07 are turned off.

[0110] During the hold period Th, the voltages of the input signals SCAN(n-1), SCAN(n), and RP(n) are the gate high voltage VGH. Therefore, during the hold period Th, the second transistor M02 to the seventh transistor M07 are turned off, and the voltages of the first node 61 to the fourth node 64 remain at the voltages at the end of the second period Ti2.

[0111] During the second time period Ti2, the ramp data voltage SCD is applied to the second node 62 through the channels of the first node 61, the first transistor M01, the third node 63, and the fourth transistor M04. During Ti2, the voltage at the second node 62 becomes the ramp data voltage (i.e., SCD - Vth) compensated by the threshold voltage Vth of the first transistor M01. Therefore, at the end of Ti2, the voltage of the first capacitor C1 becomes VDD - (SCD - Vth).

[0112] During the first time period Ti1, the second time period Ti2, and the hold period Th, the first transistor M01 is turned on, and current can flow through it; however, the current is blocked by the sixth transistor M06, which is in the off state, so that no charge accumulates in the second capacitor C2. During the second time period Ti2 and the hold period Th, since the sixth transistor M06 is in the off state, the fourth node 64 is floating, and the voltage of the second gate signal SCAN2(n) remains at the reference voltage Vlow.

[0113] During the third Tramp period, the voltages of the first input signal SCAN(n-1) and the second input signal SCAN(n) are both gate high voltages VGH, and the voltage of the third input signal RP(n) is a gate low voltage VGL. Therefore, during the third Tramp period, the third transistor M03 and the sixth transistor M06 are turned on, while the second transistor M02, the fourth transistor M04, the fifth transistor M05, and the seventh transistor M07 are turned off.

[0114] During the third time period Tramp, the second capacitor C2 is charged by a constant current from the first transistor M01, and the voltage of the fourth node 64 increases. Therefore, during the third time period Tramp, the voltage of the second gate signal SCAN2(n) applied to the pixel circuit can increase linearly with time.

[0115] When the input signal pulses are sequentially input to the ramp waveform signal generator 123 in horizontal time intervals of 1H, the pulses of the second gate signal SCAN2(n) to SCAN2(n+2) can be sequentially shifted by one horizontal time interval, such as... Figure 7 As shown. In Figure 7 In this context, "Vsync" represents the vertical synchronization signal, and "VB" represents the blanking period.

[0116] Figure 8 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure.

[0117] Reference Figure 8The pixel circuit 300 includes a light-emitting element LD, a first transistor M11 configured to drive the light-emitting element LD, and a PWM driver 80 configured to drive the first transistor M11.

[0118] The light-emitting element (LD) can be implemented as an inorganic light-emitting element, such as a micro LED, or an organic light-emitting diode (OLED), and both inorganic and organic light-emitting elements include an anode and a cathode. The anode of the LD can be connected to a third node 93, and the cathode can be connected to a power line to which a ground voltage EVSS is applied. The LD can be driven and emit light by current from the first transistor M11.

[0119] An OLED comprises an anode, a cathode, and an organic compound layer interposed between the cathode and the anode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the light-emitting element (LD), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML), thereby forming excitons. Visible light is then emitted from the emissive layer (EML). OLEDs can be implemented as tandem OLEDs with multiple emissive layers stacked on top of each other. Tandem OLED structures can improve pixel brightness and lifespan.

[0120] Inorganic light-emitting elements can be implemented as microLED chips with electrodes arranged on the upper and lower surfaces of a chip integrating the light-emitting elements in a vertical structure, or as lateral structures or flip chip structures.

[0121] The first transistor M11 and the light-emitting element LD can be connected in series between the pixel driving voltage EVDD and the ground voltage EVSS. Figure 8 In this configuration, the light-emitting element (LD) is connected between the first transistor M11 and the ground voltage EVSS, but is not limited to this. The light-emitting element (LD) can also be connected between the pixel driving voltage EVDD and the first transistor M11.

[0122] The first transistor M11 controls the current flowing through the drain-source channel based on the gate-source voltage. The gate-source voltage of the first transistor M11 varies according to the data voltage Vdata of the pixel data applied to the gate of the first transistor M11. The first transistor M11 includes a first electrode connected to a first node 91, a gate connected to a second node 92, and a second electrode connected to a third node 93. A first power supply line to which the pixel driving voltage EVDD is applied is connected to the first node 91. The pixel driving voltage EVDD is applied to the first node 91. The first node 91 and the second node 92 are connected to the PWM driver 80. The third node 93 is connected to the anode of the light-emitting element LD. The second electrode of the first transistor M11 and the cathode of the light-emitting element LD are connected to a second power supply line to which the ground voltage EVSS is applied.

[0123] The PWM driver 80 is connected to the data line where the pixel data data is applied (data voltage Vdata), the first gate line GL1 where the first gate signal SCAN1(n) is applied, the second gate line GL2 where the second gate signal SCAN2(n) is applied, the first node 91, the second node 92, and the second power supply line where the ground voltage EVSS is applied. In sensing mode, Figure 14 In the case of the pixel circuit shown, the PWM driver 80 can be connected to the third gate line.

[0124] The PWM driver 80 adjusts the emission period of the light-emitting element LD in response to the grayscale value of the pixel data by receiving the data voltage Vdata of the pixel data, the first gate signal SCAN1(n), and the second gate signal SCAN2(n). When the grayscale value of the pixel data increases, the data voltage Vdata can increase. In this case, as... Figure 9 As shown, when the grayscale of the pixel data is high, the PWM driver 80 can increase the brightness of the sub-pixel by extending the light-emitting duration of the light-emitting element (LD) in proportion to the grayscale value of the pixel data. Figure 9 In this context, "ON" indicates the period during which the light-emitting element (LD) emits light, and "OFF" indicates the period during which the light-emitting element (LD) does not emit light.

[0125] Figure 10 It is shown in detail Figure 8 The circuit diagram shows an example of a pixel circuit. Figure 10 In the text, the combination with is omitted. Figure 8 The above embodiments are redundant descriptions. Figure 11 It is shown Figure 10 The waveform diagram shows an example of the input and output signals of the pixel circuit in display mode.

[0126] Reference Figure 10 and Figure 11The pixel circuit 300 includes a light-emitting element (LD), a first transistor M11 configured to drive the light-emitting element LD, and a PWM driver 80 configured to drive the first transistor M11. The PWM driver 80 includes a second transistor M12, a third transistor M13, a fourth transistor M14, and a capacitor C11. In this pixel circuit, transistors M11 to M14 can be implemented as n-channel transistors, but are not limited thereto.

[0127] The pixel circuit 300 drives the light-emitting element LD by receiving the pixel driving voltage EVDD, the ground voltage EVSS, the data voltage Vdata, the first gate signal SCAN1(n), and the second gate signal SCAN2(n). In display mode, the light-emitting element LD can emit light corresponding to the grayscale value of the pixel data during the light-emitting period.

[0128] The data voltage Vdata for pixel data can vary depending on the grayscale value of the pixel data. For example, within a dynamic range of 0V to 8.5V, when the grayscale value of the pixel data is at its maximum (or white grayscale), the data voltage Vdata can be the maximum voltage of 8.5V, while when the grayscale value of the pixel data is at its minimum (or black grayscale), the data voltage can be the minimum voltage of 0V. The pixel drive voltage EVDD can be a constant voltage higher than the maximum voltage of the data voltage Vdata, for example, 10V. The ground voltage EVSS can be a constant voltage equal to or lower than the minimum voltage of the data voltage Vdata, for example, 0V.

[0129] The first gate signal SCAN1(n) comprises a pulse that oscillates between a gate high voltage VGH and a gate low voltage VGL during each frame period in display mode. The gate high voltage VGH of the first gate signal SCAN1(n) can be a constant voltage higher than the pixel drive voltage EVDD, for example, 30V. The gate low voltage VGL of the first gate signal SCAN1(n) can be a constant voltage lower than the ground voltage EVSS, for example, -25V.

[0130] In each frame period of display mode, the second gate signal SCAN2(n) is generated as a ramp waveform signal that rises from a minimum voltage to a maximum voltage. During one frame period in display mode, the voltage of the second gate signal SCAN2(n) gradually increases from a reference voltage Vlow (i.e., the minimum voltage) to a maximum voltage Vhigh. The reference voltage Vlow can be set to, for example, the ground voltage EVSS or the gate low voltage VGL, but is not limited to these. The maximum voltage Vhigh can be adjusted by the ramp data voltage SCD. The maximum voltage Vhigh of the second gate signal SCAN2(n) can be lower than the gate high voltage VGH and higher than the pixel drive voltage EVDD, for example, 20V. The reference voltage Vlow of the second gate signal SCAN2(n) can be lower than the ground voltage EVSS and higher than the gate low voltage VGL, for example, -20V.

[0131] The first transistor M11 includes a first electrode connected to a first node 91, a gate connected to a second node 92, and a second electrode connected to a third node 93. A first power supply line to which a pixel driving voltage EVDD is applied can be connected to the first node 91. The light-emitting element LD includes an anode connected to the third node 93 and a cathode connected to a second power supply line to which a ground voltage EVSS is applied. A capacitor C11 is disposed between a fourth node 94 and a second gate line GL2. A second gate signal SCAN2(n) is applied to the second gate line GL2.

[0132] The second transistor M12 is turned on in response to a high gate voltage VGH of the first gate signal SCAN1(n). When the second transistor M12 is turned on, the second node 92 can be electrically connected to a second power supply line to which a ground voltage EVSS is applied. The second transistor M12 includes a first electrode connected to the second node 92, a gate connected to the first gate line GL1 to which the first gate signal SCAN1(n) is applied, and a second electrode connected to the second power supply line.

[0133] The third transistor M13 is connected between the fourth node 94 and the data line DL, and is turned on in response to the high gate voltage VGH of the first gate signal SCAN1(n). When the third transistor M13 is turned on, the fourth node 94 is electrically connected to the data line DL to which the data voltage Vdata is applied. The third transistor M13 includes a first electrode connected to the data line DL, a gate connected to the first gate line GL1, and a second electrode connected to the fourth node 94.

[0134] A fourth transistor M14 is connected between the first node 91 and the second node 92, and turns on when the voltage at the fourth node 94 is higher than its threshold voltage. When the fourth transistor M14 turns on, the gate voltage of the first transistor M11 increases and the first transistor M11 turns on, allowing current to flow through the first transistor M11 to the light-emitting element LD, which then emits light. When the fourth transistor M14 turns on, the light-emitting element LD begins to emit light. The earlier the fourth transistor M14 turns on, the longer the light-emitting period (ON) of the light-emitting element LD is. The fourth transistor M14 includes a first electrode connected to the second node 92, a gate connected to the fourth node 94, and a second electrode connected to the first node 91.

[0135] When the third transistor M13 is turned on, the data voltage Vdata is applied to the fourth node 94, and the voltage Va of the fourth node 94 becomes equal to the data voltage Vdata. During a frame period, the voltage Va of the fourth node 94 gradually increases from the data voltage Vdata by the voltage of the second gate signal SCAN2(n) applied through capacitor coupling. Figure 12 As shown, the higher the grayscale value of the pixel data, the higher the data voltage Vdata, and the earlier the fourth transistor M14 turns on. On the other hand, the lower the grayscale value of the pixel data, the lower the data voltage Vdata, and the later the fourth transistor M14 turns on. Therefore, the light-emitting period (ON) of the light-emitting element LD becomes longer under high grayscale, while the light-emitting period (ON) of the light-emitting element LD becomes shorter under low grayscale.

[0136] The transistors (e.g., the fourth transistor M14) that affect the emission period of the light-emitting element (LD) may experience threshold voltage shifts due to variations between sub-pixels or due to accumulated stress during the driving time. In this case, the emission period of the LD may vary even for pixel data with the same grayscale value. The turn-on voltage of the fourth transistor M14 is Vgs-Vth, where Vgs is the gate-source voltage of the transistor and Vth is the threshold voltage of the transistor.

[0137] like Figure 13 As shown, when the threshold voltage of the fourth transistor M14 is small, it turns on earlier, thus extending the emission period of the light-emitting element LD. Conversely, even with the same voltage Va at the fourth node 94, when the threshold voltage of the fourth transistor M14 increases, it turns on later, and the emission period of the light-emitting element LD becomes shorter. Therefore, even with the same grayscale value, the emission periods of sub-pixels may differ, and a longer driving time may result in a shorter emission period for the sub-pixels.

[0138] exist Figure 10In the pixel circuit shown, when the fourth transistor M14 is turned on, the first transistor M11 operates as a diode. Because the current flowing through the channel of the first transistor M11 in the on-state operates at the boundary between the linear and saturation regions, the impact of threshold voltage variations is small, and the need for threshold voltage variation compensation is low. Therefore, in Figure 10 In the pixel circuit shown, sensing the threshold voltage of the fourth transistor M14 and compensating for changes or deviations in the sensed threshold voltage of the fourth transistor M14 in real time is effective in improving image quality and extending the lifespan of the display device. To achieve this, as... Figure 14 As shown, the sensing circuit can be connected to the pixel circuit.

[0139] Figure 14 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 15 This shows the application applied in sensing mode. Figure 14 The diagram shows the waveform of the gate signal of the pixel circuit. In this embodiment, the same reference numerals are assigned to... Figure 10 The components of the pixel circuit shown are essentially the same, and redundant descriptions are omitted.

[0140] Reference Figure 14 and Figure 15 The sensing circuit 400 is connected to the pixel circuit 300.

[0141] In sensing mode, the pixel circuit 300 receives the pixel driving voltage EVDD, the ground voltage EVSS, the data voltage Vdata, the first gate signal SCAN1(n), the second gate signal SCAN2(n), and the third gate signal SCAN3(n). In sensing mode, Figure 2 The gate driver 320 shown is controlled by the timing controller 330 as follows: Figure 15 The waveforms shown are the output gate signals SCAN1(n), SCAN2(n), and SCAN3(n).

[0142] The second transistor M12 to the fourth transistor M14 of the pixel circuit 300 are turned on in response to the high gate voltage VGH of the corresponding gate signals SCAN1(n), SCAN2(n), and SCAN3(n), and are turned off at the low gate voltage VGL. When the fourth transistor M14 is turned on, the first transistor M11 can be turned on.

[0143] The sensing circuit 400 includes an ADC and a second switching element SW2 that operates in sensing mode. The sensing circuit 400 can be embedded in a driver IC along with the circuitry of the data driver 310.

[0144] In sensing mode, the driving periods of pixel circuit 300 and sensing circuit 400 can be divided into an initialization period Ti, a sampling period Tsam, and a sensing period Tsen. The voltage of the first gate signal SCAN1(n) is a high gate voltage VGH during the initialization period Ti and the sensing period Tsen, and a low gate voltage VGL during the sampling period Tsam. In sensing mode, the voltage of the second gate signal SCAN2(n) remains at the reference voltage Vlow. The voltage of the third gate signal SCAN3(n) is a low gate voltage VGL during the initialization period Ti and the sensing period Tsen, and a high gate voltage VGH during the sampling period Tsam. In sensing mode, timing controller 330 can use the first gate signal SCAN1(n) and the third gate signal SCAN3(n) to control the initialization period Ti, the sampling period Tsam, and the sensing period Tsen.

[0145] During the initialization period Ti, pixel circuit 300 is initialized. During the initialization period Ti, second transistor M12 is controlled to be in the on state, and fourth transistor M14 is controlled to be in the off state. During the sampling period Tsam, fourth transistor M14 is controlled to be in the on state, and second transistor M12 is controlled to be in the off state, so that the threshold voltage Vth of fourth transistor M14 is sampled. During the sampling period Tsam, the voltage Vb of second node 92 rises to Vdata-Vth, where Vdata is the sensed data voltage, and Vth is the threshold voltage of fourth transistor M14.

[0146] During the sensing period Tsen, the fourth transistor M14 is controlled to be in the off state, and the second transistor M12 is controlled to be in the on state, so that the voltage Vb of the second node 92 is converted into digital data and the threshold voltage Vth of the fourth transistor M14 is sensed. The ADC of the sensing circuit 400 converts the voltage Vb of the second node 92, which is input through the second switching element SW2 turned on in the sensing mode, into digital data and outputs the sensing data Dsen (see Figure 2 The sensing data Dsen indicates the threshold voltage Vth of the fourth transistor M14. The timing controller 330 can add a compensation value corresponding to the sensing data Dsen to the pixel data, modulate the pixel data, and send the modulated pixel data DATA′ to the data driver 310 to control the data driver 310 so that in display mode, the data driver 310 outputs a data voltage Vdata with the threshold voltage Vth of the fourth transistor M14 increased.

[0147] The first switching element SW1 can be connected to the pixel circuit 300. The first switching element SW1 can be implemented as a multiplexer controlled by the logic circuitry of the timing controller 330 or the data driver 310, but is not limited thereto. In display mode, the first switching element SW1 supplies the first gate signal SCAN1(n) to the gate of the third transistor M13, and in sensing mode, it supplies the third gate signal SCAN3(n) to the gate of the third transistor M13.

[0148] The second switching element SW2 can be implemented as a multiplexer controlled by the logic circuitry of the timing controller 330 or the data driver 310, but is not limited thereto. In display mode, the second switching element SW2 connects the second electrode of the second transistor M12 and the cathode of the light-emitting element LD to the second power supply line to which a ground voltage EVSS is applied. In sensing mode, the second switching element SW2 connects the second electrode of the second transistor M12 and the cathode of the light-emitting element LD to the input terminal of the ADC.

[0149] The second transistor M12 can be shared between display mode and sensing mode by sensing the voltage Vb of the second node 92 via the cathode of the light-emitting element LD. To sense the voltage Vb of the second node 92 via the anode of the light-emitting element LD, an additional transistor is required. Furthermore, the advantage of sensing the voltage Vb of the second node 92 via the cathode of the light-emitting element LD is that, since a reverse bias voltage is applied to the light-emitting element LD in sensing mode, the voltage Vb of the second node 92 is sensed while reliably turning off the light-emitting element LD. Therefore, noise is not added to the sensed value, and accidental emission of the light-emitting element LD in sensing mode can be prevented.

[0150] In sensing mode, in response to the high gate voltage VGH of the first gate signal SCAN1(n), the second transistor M12 is turned on during the initialization period Ti and the sensing period Tsen, and is turned off during the sampling period Tsam. The second transistor M12 includes a first electrode connected to the second node 92, a gate connected to the first gate line GL1, and a second electrode connected to the second power supply line.

[0151] In sensing mode, the third transistor M13 is turned on at the beginning of the sampling period Tsam in response to the high gate voltage VGH of the third gate signal SCAN3(n), remains on during the sampling period Tsam, and is turned off during the initialization period Ti and the sensing period Tsen. The third transistor M13 includes a first electrode connected to the data line DL, a gate connected to the third gate line GL3 to which the third gate signal SCAN3(n) is applied in sensing mode, and a second electrode connected to the fourth node 94.

[0152] When the voltage at the fourth node 94 rises to the sensed data voltage Vdata, the fourth transistor M14 is turned on in sensing mode. During the sampling period Tsam, the sensed data voltage Vdata is applied to the fourth node 94 through the third transistor M13, and the voltage Va at the fourth node 94 rises to the sensed data voltage Vdata. The fourth transistor M14 includes a first electrode connected to the second node 92, a gate connected to the fourth node 94, and a second electrode connected to the first node 91.

[0153] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc. Furthermore, the display device according to one or more embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0154] The purpose achieved by this disclosure, the apparatus for achieving the above purpose, and the effects of this disclosure do not specifically describe the basic features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0155] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are provided for illustrative purposes only, and these embodiments are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A pixel circuit, comprising: A first transistor, the first transistor including a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; A light-emitting element, which is connected to the third node; as well as A pulse width modulation (PWM) driver is connected to the first transistor and configured to adjust the emission time of the light-emitting element based on the data voltage of the pixel data. The first power line to which the pixel driving voltage is applied is connected to the first node, and The anode of the light-emitting element is connected to the third node, and the cathode of the light-emitting element is connected to a second power line that is subjected to a ground voltage lower than the pixel driving voltage in display mode.

2. The pixel circuit according to claim 1, wherein, The PWM driver is connected to the data line to which the data voltage is applied, the first gate line to which the first gate signal is applied, the second gate line to which the second gate signal is applied, the first node, the second node, and the second power line.

3. The pixel circuit according to claim 2, wherein, The first gate signal includes a pulse that oscillates between a gate high voltage and a gate low voltage during each frame period in the display mode. The second gate signal is generated as a ramp waveform signal, which increases from a minimum voltage to a maximum voltage during each frame period in the display mode. Wherein, the gate high voltage is higher than the pixel driving voltage, and the gate low voltage is lower than the ground voltage, and Wherein, the maximum voltage of the ramp waveform signal is lower than the gate high voltage and higher than the pixel driving voltage, and the minimum voltage of the ramp waveform signal is lower than the ground voltage and higher than the gate low voltage.

4. The pixel circuit according to claim 1, wherein, The light-emitting period of the light-emitting element becomes longer as the data voltage increases.

5. The pixel circuit according to claim 2, wherein, The PWM driver includes: A capacitor, wherein the capacitor is disposed between the fourth node and the second gate line; The second transistor includes a first electrode connected to the second node, a gate connected to the first gate line, and a second electrode connected to the second power line. A third transistor, the third transistor including a first electrode connected to the data line, a gate connected to the first gate line, and a second electrode connected to the fourth node; and A fourth transistor, the fourth transistor including a first electrode connected to the second node, a gate connected to the fourth node, and a second electrode connected to the first node.

6. The pixel circuit according to claim 5, wherein, When the fourth transistor is turned on, the light-emitting element begins to emit light, and The earlier the fourth transistor is turned on, the longer the light-emitting period of the light-emitting element.

7. The pixel circuit according to claim 1, wherein, The PWM driver is connected to the data line to which the data voltage is applied, the first gate line to which the first gate signal is applied, the second gate line to which the second gate signal is applied, the third gate line to which the third gate signal is applied, the first node, the second node, and the second power supply line.

8. The pixel circuit according to claim 7, further comprising: A first switching element is configured to supply the first gate signal to the third gate line in the display mode and to supply the third gate signal to the third gate line in the sensing mode. as well as A sensing circuit, which is connected to the pixel circuit and operates in the sensing mode.

9. The pixel circuit according to claim 8, wherein, The sensing circuit includes: Analog-to-digital converters; and A second switching element is configured to supply the ground voltage to the cathode of the light-emitting element in the display mode and to connect the cathode of the light-emitting element to the input terminal of the analog-to-digital converter in the sensing mode.

10. The pixel circuit according to claim 9, wherein, The first gate signal is a high gate voltage during the initialization and sensing periods of the sensing mode, and a low gate voltage during the sampling period of the sensing mode. In the sensing mode, the voltage of the second gate signal remains at a reference voltage during the initialization period, the sampling period, and the sensing period. In the sensing mode, the voltage of the third gate signal is a low gate voltage during the initialization period and the sensing period, and a high gate voltage during the sampling period. Wherein, the gate high voltage is higher than the pixel driving voltage, and the gate low voltage and the reference voltage are lower than the ground voltage, and The maximum voltage of the ramp waveform signal is lower than the gate high voltage and higher than the pixel driving voltage, and the minimum voltage of the ramp waveform signal is lower than the ground voltage and higher than the gate low voltage.

11. The pixel circuit according to claim 10, wherein, The PWM driver includes: A capacitor, wherein the capacitor is disposed between the fourth node and the second gate line; The second transistor includes a first electrode connected to the second node, a gate connected to the first gate line, and a second electrode connected to the second power line. A third transistor, the third transistor including a first electrode connected to the data line, a gate to which the third gate signal is applied in the sensing mode, and a second electrode connected to the fourth node; and A fourth transistor, the fourth transistor including a first electrode connected to the second node, a gate connected to the fourth node, and a second electrode connected to the first node.

12. A display device, comprising: The display panel has multiple data lines, multiple gate lines, multiple power lines and multiple sub-pixels arranged therein; A data driver, which is connected to the data line; as well as A gate driver, the gate driver being connected to the gate line. Each of the sub-pixels includes: A first transistor, the first transistor including a first electrode connected to a first node, a gate connected to a second node, and a second electrode connected to a third node; A light-emitting element, the light-emitting element being connected to the third node; and A pulse width modulation (PWM) driver is connected to the first transistor and configured to adjust the emission time of the light-emitting element based on the data voltage of the pixel data. The first power line to which the pixel driving voltage is applied is connected to the first node, and The anode of the light-emitting element is connected to the third node, and the cathode of the light-emitting element is connected to a second power line that is subjected to a ground voltage lower than the pixel driving voltage in display mode.

13. The display device according to claim 12, wherein, The PWM driver is connected to the data line to which the data voltage is applied, the first gate line to which the first gate signal is applied, the second gate line to which the second gate signal is applied, the first node, the second node, and the second power supply line. The first gate signal includes pulses that oscillate between a gate high voltage and a gate low voltage during each frame period in the display mode. The second gate signal is generated as a ramp waveform signal, which increases from a minimum voltage to a maximum voltage during each frame period in the display mode. Wherein, the gate high voltage is higher than the pixel driving voltage, and the gate low voltage is lower than the ground voltage, and Wherein, the maximum voltage of the ramp waveform signal is lower than the gate high voltage and higher than the pixel driving voltage, and the minimum voltage of the ramp waveform signal is lower than the ground voltage and higher than the gate low voltage.

14. The display device according to claim 12, wherein, The light-emitting period of the light-emitting element becomes longer as the data voltage increases.

15. The display device according to claim 13, wherein, The PWM driver includes: A capacitor, wherein the capacitor is disposed between the fourth node and the second gate line; The second transistor includes a first electrode connected to the second node, a gate connected to the first gate line, and a second electrode connected to the second power line. A third transistor, the third transistor including a first electrode connected to the data line, a gate connected to the first gate line, and a second electrode connected to the fourth node; and A fourth transistor, the fourth transistor including a first electrode connected to the second node, a gate connected to the fourth node, and a second electrode connected to the first node.

16. The display device according to claim 15, wherein, When the fourth transistor is turned on, the light-emitting element begins to emit light. The earlier the fourth transistor is turned on, the longer the light-emitting period of the light-emitting element.

17. The display device according to claim 12, wherein, The display panel also includes a sensing line connected to the cathode of the light-emitting element, and The PWM driver is connected to the data line to which the data voltage is applied, the first gate line to which the first gate signal is applied, the second gate line to which the second gate signal is applied, the third gate line to which the third gate signal is applied, the first node, the second node, and the second power supply line.

18. The display device according to claim 17, further comprising: A first switching element is configured to supply the first gate signal to the third gate line in the display mode and to supply the third gate signal to the third gate line in the sensing mode. as well as A sensing circuit, which is connected to the pixel circuit and operates in the sensing mode.

19. The display device according to claim 18, wherein, The sensing circuit includes: Analog-to-digital converters; and A second switching element is configured to supply the ground voltage to the cathode of the light-emitting element in the display mode and to connect the cathode of the light-emitting element to the input terminal of the analog-to-digital converter in the sensing mode.

20. The display device according to claim 19, wherein, The first gate signal is a high gate voltage during the initialization and sensing periods of the sensing mode, and a low gate voltage during the sampling period of the sensing mode. In the sensing mode, the voltage of the second gate signal remains at a reference voltage during the initialization period, the sampling period, and the sensing period. In the sensing mode, the voltage of the third gate signal is a low gate voltage during the initialization period and the sensing period, and a high gate voltage during the sampling period. Wherein, the gate high voltage is higher than the pixel driving voltage, and the gate low voltage and the reference voltage are lower than the ground voltage. The maximum voltage of the ramp waveform signal is lower than the gate high voltage and higher than the pixel driving voltage, and the minimum voltage of the ramp waveform signal is lower than the ground voltage and higher than the gate low voltage. The PWM driver includes: A capacitor, wherein the capacitor is disposed between the fourth node and the second gate line; The second transistor includes a first electrode connected to the second node, a gate connected to the first gate line, and a second electrode connected to the second power line. A third transistor, the third transistor including a first electrode connected to the data line, a gate to which the first gate signal is applied in the display mode and the third gate signal is applied in the sensing mode, and a second electrode connected to the fourth node; and A fourth transistor, the fourth transistor including a first electrode connected to the second node, a gate connected to the fourth node, and a second electrode connected to the first node.

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