Current detection circuit for switching power supply converter

Abstract

The invention discloses a current detection circuit for a switching power supply converter. The current detection circuit comprises a sampling module, a current detection module and a logic module, the sampling module is used for generating a first sampling signal and a second sampling signal according to the conduction voltage drop of the high-side power tube and the low-side power tube; the current detection module is used for generating a current detection output signal proportional to an inductive current according to the first sampling signal and the second sampling signal; the logic module is used for generating a first control signal and a second control signal according to a switching time sequence of a power tube, the first control signal is provided for the sampling module to adjust a generation process of the first sampling signal, and the second control signal is provided for the second sampling signal; the second control signal is provided to the sampling module to adjust a generation process of the second sampled signal.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a current detection circuit for a switching power supply converter. Background Technology

[0002] In switching power converter chips, it is often necessary to detect inductor current. The detected signal can be used for modulation of the current-mode loop system, or to limit the power transistor current and inductor current, thereby protecting these high-current devices from damage under abnormal conditions.

[0003] Common inductor current sensing methods mainly include series sampling resistor, DCR sensing, SENSE FET, and on-state voltage drop sensing. Figure 1 The current sensing methods currently on the market are as follows. DCR sensing and series sampling resistor methods both require additional discrete components, making them unsuitable for compact PCB layouts. While SENSE FETs can provide a precisely proportional mirrored current, high-frequency switching necessitates a high-speed clamping amplifier for accurate current copying, consuming additional area and power. On-state voltage drop sensing obtains inductor current information by detecting the voltage drop across the switching transistor. This method does not require additional discrete components and avoids the need for high-speed operational amplifiers on-chip, significantly saving area and power. However, when using average current mode control or requiring complete inductor current waveforms for loop modulation, the traditional approach is to sample the on-state voltage drops of the high-side and low-side power transistors separately and introduce the on-state voltage drop signals of either the high-side or low-side path into the loop modulation, which is equivalent to constructing two control paths. Another approach is to restore the on-state voltage drops of the high-side and low-side power transistors to the complete inductor current waveform and then directly introduce it into the loop modulation. However, this approach requires the use of additional high-speed operational amplifiers and still requires sampling the on-state voltage drops of the high-side and low-side power transistors separately. Both of these approaches consume more on-chip area and power.

[0004] Therefore, there is an urgent need for a current detection circuit for switching power converters to overcome the existing problems. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a current detection circuit for a switching power converter. This invention can detect the on-state voltage drop of the high-side power transistor and the low-side power transistor respectively and convert them into complete inductor current signals, eliminating the need for operational amplifiers and detecting complete inductor current signals with a smaller area and lower power consumption.

[0006] To achieve the above objectives, the present invention provides a current detection circuit for a switching power supply converter, comprising: a sampling module, a current detection module, and a logic module; The sampling module is used to generate a first sampling signal and a second sampling signal based on the on-state voltage drop of the high-side power transistor and the low-side power transistor. The current detection module is used to generate a current detection output signal that is proportional to the inductor current based on the first sampling signal and the second sampling signal. The logic module is configured to generate a first control signal and a second control signal according to the switching timing of the power transistor, wherein the first control signal is provided to the sampling module to adjust the generation process of the first sampling signal, and the second control signal is provided to the sampling module to adjust the generation process of the second sampling signal.

[0007] Optionally, the sampling module includes: a first inverter, a first NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor; The input terminal of the first inverter receives the gate drive signal, and the output terminal of the first inverter is connected to one end of the second resistor and the upper plate of the first capacitor through the first resistor, and this end is used as the output terminal of the first sampling signal. The other end of the second resistor and the lower plate of the first capacitor are grounded; One end of the third resistor is connected to the switching node voltage, and the other end of the third resistor is connected to one end of the fourth resistor, the source of the first NMOS transistor, and the upper plate of the second capacitor, and this end is used as the output end of the second sampling signal; The other end of the fourth resistor and the lower plate of the second capacitor are grounded; The gate of the first NMOS transistor receives the second control signal, and the drain of the first NMOS transistor is grounded.

[0008] Optionally, generating the first sampling signal and the second sampling signal based on the on-state voltage drop of the high-side power transistor and the low-side power transistor includes: During the high-side power transistor conduction phase, the voltage value of the first sampled signal is the voltage value after the input voltage is divided by the first resistor and the second resistor; During the high-side power transistor conduction phase, the voltage value of the second sampling signal is the voltage value obtained by dividing the input voltage by the voltage difference between the inductor current and the power transistor conduction impedance, and then by the voltage divider formed by the third resistor and the fourth resistor. During the turn-on phase of the low-side power transistor, the voltage value of the first sampled signal is zero; During the low-side power transistor conduction phase, the voltage value of the second sampled signal is the voltage value obtained by multiplying the negative inductor current by the power transistor conduction impedance and then dividing it by the third resistor and the fourth resistor.

[0009] Optionally, the current detection module includes: a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor.

[0010] Optionally, the gate of the third PMOS transistor receives the first sampling signal, and the source of the third PMOS transistor is connected to the emitter of the first transistor through the fifth resistor; The base of the first transistor is connected to the source of the second NMOS transistor and one end of the sixth resistor, and the collector of the first transistor is connected to the gate of the second NMOS transistor and the drain of the second PMOS transistor. The other end of the sixth resistor is connected to the base of the fourth transistor and the emitter of the second transistor. The base of the second transistor is connected to one end of the eighth resistor and the drain of the fourth NMOS transistor. The collector of the second transistor outputs the current detection output signal and is connected to one end of the seventh resistor. The gate of the fourth NMOS transistor receives a third bias voltage, the other end of the eighth resistor is connected to the base and collector of the third transistor, the emitter of the third transistor is connected to the source of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the fifth PMOS transistor and the collector of the fourth transistor. The source of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the emitter of the fourth transistor is connected to the source of the sixth PMOS transistor, and the gate of the sixth PMOS transistor receives the second sampling signal. The source of the first PMOS transistor, the source of the fourth PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the input voltage, while the source of the third PMOS transistor, the source of the sixth PMOS transistor, the other end of the seventh resistor, and the source of the fourth NMOS transistor are grounded.

[0011] Optionally, the first PMOS transistor, the second PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the fourth NMOS transistor constitute two common-source cascode current sources and output equal bias currents. The third NMOS transistor, the third transistor, and the eighth resistor constitute a compensation circuit, which is used to compensate for the current error caused by the channel length modulation effect of the two common source and common gate current sources. The collector of the second transistor outputs the current detection output signal, which includes a DC component proportional to the bias current and an AC component proportional to the difference between the first sampling signal and the second sampling signal.

[0012] Optionally, the logic module includes: a logic unit, a dead-time control unit, a first buffer, and a second buffer; The logic unit is connected to the dead time control unit, which outputs the first control signal through the first buffer and the second control signal through the second buffer.

[0013] Optionally, during the dead time period when both the high-side power transistor and the low-side power transistor are turned off, the dead time control unit outputs the second control signal through the second buffer to turn on the first NMOS transistor and adjust the voltage value of the second sampled signal to near zero potential.

[0014] Compared with the prior art, the present invention has the following advantages and technical effects: This invention enables the sampling and processing of the complete inductor current signal of a switching power supply system. The output signal Vcs can output a waveform in phase with the inductor current, and its value is proportional to the magnitude of the inductor current. This output signal can be used for current-mode control and overcurrent protection. This signal can also be provided to other modules that require inductor current signals. The large-signal DC current passing through the sixth resistor can be controlled by adjusting the fifth resistor, and the amplification factor of the Vinp-Vinn difference of the output signal Vcs can be controlled by adjusting the value of the seventh resistor. Attached Figure Description

[0015] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural diagram of a common inductor current detection scheme in existing technology; Figure 2 This is a circuit structure diagram of the sampling module according to an embodiment of the present invention; Figure 3 This is a circuit structure diagram of the current detection module according to an embodiment of the present invention; Figure 4 This is a block diagram of the logic module circuit of an embodiment of the present invention; Figure 5 This is a schematic diagram of the sampling module operation according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the operation of the current detection module according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a current detection circuit for a switching power supply converter according to the present invention. Detailed Implementation

[0016] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0017] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0018] This embodiment proposes a current detection circuit for a switching power supply converter, such as... Figure 7 As shown, it specifically includes: a sampling module, a current detection module, and a logic module; The sampling module is used to generate a first sampling signal and a second sampling signal based on the on-state voltage drop of the high-side power transistor and the low-side power transistor. The current detection module is used to generate a current detection output signal that is proportional to the inductor current based on the first sampling signal and the second sampling signal. The logic module is configured to generate a first control signal and a second control signal according to the switching timing of the power transistor, wherein the first control signal is provided to the sampling module to adjust the generation process of the first sampling signal, and the second control signal is provided to the sampling module to adjust the generation process of the second sampling signal.

[0019] Specifically, the sampling module is used to sample the on-state voltage drop of the high-side power transistor and the low-side power transistor; The current detection module is used to process the sampled voltage signal and output a complete inductor current waveform; The logic module is used to reduce the sampling error of the sampling module and adjust the input signal of the current detection module.

[0020] Furthermore, such as Figure 2 As shown, the sampling module includes: a first inverter INV1, a first NMOS transistor NM1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2. The input terminal of the first inverter receives the gate drive signal, and the output terminal of the first inverter is connected to one end of the second resistor and the upper plate of the first capacitor through the first resistor, and this end is used as the output terminal of the first sampling signal. The other end of the second resistor and the lower plate of the first capacitor are grounded; One end of the third resistor is connected to the switching node voltage, and the other end of the third resistor is connected to one end of the fourth resistor, the source of the first NMOS transistor, and the upper plate of the second capacitor, and this end is used as the output end of the second sampling signal; The other end of the fourth resistor and the lower plate of the second capacitor are grounded; The gate of the first NMOS transistor receives the second control signal, and the drain of the first NMOS transistor is grounded.

[0021] Specifically, one end of the first resistor R1 is connected to the output terminal of the first inverter INV1, and the other end of the first resistor R1 is connected to one end of the second resistor R2 and the upper plate of the first capacitor C1. This end serves as the first output terminal Vinp of the sampling module. The other end of the second resistor R2 and the lower plate of the first capacitor C1 are connected to ground. One end of the third resistor is connected to Vsw, and the other end of the third resistor is connected to one end of the fourth resistor, the source of the first NMOS transistor MN1, and the upper plate of the second capacitor C2. This end also serves as the second output terminal Vinn of the sampling module. The other end of the fourth resistor R4 and the lower plate of the second capacitor C2 are connected to ground. The gate of the first NMOS transistor MN1 is connected to the logic signal Vctr, the drain of the first NMOS transistor MN1 is connected to ground, and the input terminal of the first inverter INV1 is connected to Vg.

[0022] Furthermore, generating the first sampling signal and the second sampling signal based on the on-state voltage drop of the high-side power transistor and the low-side power transistor includes: During the high-side power transistor conduction phase, the voltage value of the first sampled signal is the voltage value after the input voltage is divided by the first resistor and the second resistor; During the high-side power transistor conduction phase, the voltage value of the second sampling signal is the voltage value obtained by dividing the input voltage by the voltage difference between the inductor current and the power transistor conduction impedance, and then by the voltage divider formed by the third resistor and the fourth resistor. During the turn-on phase of the low-side power transistor, the voltage value of the first sampled signal is zero; During the low-side power transistor conduction phase, the voltage value of the second sampled signal is the voltage value obtained by multiplying the negative inductor current by the power transistor conduction impedance and then dividing it by the third resistor and the fourth resistor.

[0023] Specifically, such as Figure 2As shown, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are used to adjust the common-mode input voltage when the high-side power transistor is turned on. The output voltages of the first inverter when the high-side and low-side power transistors are turned on are VIN and 0, respectively. A voltage conversion range that is too large is not conducive to the subsequent circuit operating at the normal DC operating point. The first capacitor C1 and the second capacitor C2 are mainly used to filter high-frequency noise. Assuming the high-side power transistor is turned on at stage P1 and the low-side power transistor is turned on at stage P2, the voltages Vinp and Vinn are respectively: If we subtract Vinp and Vinn from each of the two phases P1 and P2 respectively, we get: Furthermore, such as Figure 3 As shown, the current detection module is used to process the sampled voltage signal and output a complete inductor current waveform, including: second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, fifth PMOS transistor MP5, sixth PMOS transistor MP6, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, first transistor Q1, second transistor Q2, third transistor Q3, and fourth transistor Q4.

[0024] Furthermore, the gate of the third PMOS transistor receives the first sampling signal, and the source of the third PMOS transistor is connected to the emitter of the first transistor through the fifth resistor; The base of the first transistor is connected to the source of the second NMOS transistor and one end of the sixth resistor, and the collector of the first transistor is connected to the gate of the second NMOS transistor and the drain of the second PMOS transistor. The other end of the sixth resistor is connected to the base of the fourth transistor and the emitter of the second transistor. The base of the second transistor is connected to one end of the eighth resistor and the drain of the fourth NMOS transistor. The collector of the second transistor outputs the current detection output signal and is connected to one end of the seventh resistor. The gate of the fourth NMOS transistor receives a third bias voltage, the other end of the eighth resistor is connected to the base and collector of the third transistor, the emitter of the third transistor is connected to the source of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the fifth PMOS transistor and the collector of the fourth transistor. The source of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the emitter of the fourth transistor is connected to the source of the sixth PMOS transistor, and the gate of the sixth PMOS transistor receives the second sampling signal. The source of the first PMOS transistor, the source of the fourth PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the input voltage, while the source of the third PMOS transistor, the source of the sixth PMOS transistor, the other end of the seventh resistor, and the source of the fourth NMOS transistor are grounded.

[0025] Specifically, the gate of the third PMOS transistor MP3 is connected to Vinp; the source of the third PMOS transistor MP3 is connected to one end of the fifth resistor R5; the other end of the fifth resistor R5 is connected to the emitter of the first transistor Q1; the base of the first transistor Q1 is connected to the source of the second NMOS transistor MN2 and one end of the sixth resistor R6; the collector of the first transistor Q1 is connected to the gate of the second NMOS transistor MN2 and the drain of the second PMOS transistor MP2; the gate of the second PMOS transistor MP2 and the gate of the fifth PMOS transistor MP5 are connected to Vb2; the source of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1; the gate of the first PMOS transistor MP1 and the gate of the fourth PMOS transistor MP4 are connected to Vb2; the other end of the sixth resistor R6 is connected to the base of the fourth transistor Q4 and the emitter of the second transistor Q2; the base of the second transistor Q2 is connected to one end of the eighth resistor R8 and the drain of the fourth NMOS transistor MN4; the collector of the second transistor Q2... The gate of the fourth NMOS transistor MN4 is connected to Vb3, and the other end of the eighth resistor R8 is connected to the base and collector of the third transistor Q3. The emitter of the third transistor Q3 is connected to the source of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is connected to the drain of the fifth PMOS transistor MP5 and the collector of the fourth transistor Q4. The source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4. The emitter of the fourth transistor Q4 is connected to the source of the sixth PMOS transistor MP6. The gate of the sixth PMOS transistor MP6 is connected to Vinn. The sources of the first PMOS transistor MP1, the fourth PMOS transistor MP4, the second NMOS transistor MN2, and the third NMOS transistor MN3 are all connected to VIN. The sources of the third PMOS transistor MP3, the sixth PMOS transistor MP6, the other end of the seventh resistor R7, and the source of the fourth NMOS transistor MN4 are all connected to ground.

[0026] More specifically, assume that the first PMOS transistor MP1, the second PMOS transistor MP2, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the fourth NMOS transistor MN4 output the same bias current I. biasThe base voltages of Q1 and Q4 in the current detection module are as follows: If the third PMOS transistor MP3 and the sixth PMOS transistor MP6 have the same width-to-length ratio, the first transistor Q1 and the fourth transistor Q4 have the same type and area, and the current flowing through them is the same, then V gsp3 =V gsp6 V beQ1 =V beQ4 At this time, the current through the sixth resistor R6 is: Since the base currents of the second transistor Q2 and the fourth transistor Q4 are small, their effect on the current through the sixth resistor R6 can be ignored. At this time, V... cs The output voltage is: Substituting formula (5) into formula (9) yields: At this point, V can be seen. cs It can output a complete inductor current waveform, and its actual output waveform is as follows: Figure 6 As shown, the rise and fall of the waveform produce spikes because the power transistor does not satisfy formula (5) during the transient process of turning on and off.

[0027] In this embodiment, in order to achieve equal current I output from the two common-source cascode current sources formed by the first PMOS transistor MP1, the second PMOS transistor MP2, and the fourth PMOS transistor MP4... bias A third NMOS transistor MN3, a third transistor Q3, and an eighth resistor R8 were added as compensation; at this time, the drain voltages of the second PMOS transistor MP2 and the fourth PMOS transistor MP4 are respectively: Considering V beQ4 Almost equal to V beQ2 Therefore, formula (11) is approximately equal to formula (12), which compensates for the error caused by channel length modulation of the two current sources and improves the accuracy of this embodiment.

[0028] Considering that synchronous control switching power converters typically employ dead-time control technology, this prevents the high-side power transistors and low-side power transistors from conducting simultaneously, resulting in a nanosecond-level dead time. This dead time causes the voltage at the Vsw node to be approximately -700mV, which is much smaller than -I. L R ONBesides rendering formula (5) inapplicable, it also affects the filtering effect of the first capacitor C1 and the second capacitor C2. The Vctr signal adjusts the magnitude of Vinn to close to 0V during the dead time, such as Figure 5 As shown, this further improves the system's response speed and accuracy; Vg is the gate drive signal that controls the power transistor switch. This signal is input to the first inverter, which enables the output of the first inverter to switch between 0 and VIN, thus realizing formula (5) in a simple structure.

[0029] Furthermore, the first PMOS transistor, the second PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the fourth NMOS transistor constitute two common-source common-gate current sources and output equal bias currents; The third NMOS transistor, the third transistor, and the eighth resistor constitute a compensation circuit, which is used to compensate for the current error caused by the channel length modulation effect of the two common source and common gate current sources. The collector of the second transistor outputs the current detection output signal, which includes a DC component proportional to the bias current and an AC component proportional to the difference between the first sampling signal and the second sampling signal.

[0030] Furthermore, such as Figure 4 As shown, the logic module includes: LOGIC logic unit, DTC dead time control unit, first buffer Buffer1, and second buffer Buffer2; The logic unit is connected to the dead time control unit, which outputs the first control signal through the first buffer and the second control signal through the second buffer.

[0031] Furthermore, during the dead time period when both the high-side power transistor and the low-side power transistor are turned off, the dead time control unit outputs the second control signal through the second buffer to turn on the first NMOS transistor and adjust the voltage value of the second sampling signal to near zero potential.

[0032] Specifically, the operating principle is as follows: when both the high-side and low-side power transistors of the switching power converter are NMOS or PMOS transistors with the same width-to-length ratio and the same gate-source drive voltage, they have the same on-resistance R. ON Since the voltage drop across the conduction impedance due to the inductor current is reflected at Vsw, information about the inductor current can be obtained by measuring the voltage difference between VIN and Vsw when the high-side power transistor is on, and by measuring the voltage difference between ground and Vsw when the low-side power transistor is on.

[0033] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A current detection circuit for a switching power supply converter, characterized in that, include: Sampling module, current detection module, and logic module; The sampling module is used to generate a first sampling signal and a second sampling signal based on the on-state voltage drop of the high-side power transistor and the low-side power transistor. The current detection module is used to generate a current detection output signal that is proportional to the inductor current based on the first sampling signal and the second sampling signal. The logic module is configured to generate a first control signal and a second control signal according to the switching timing of the power transistor, wherein the first control signal is provided to the sampling module to adjust the generation process of the first sampling signal, and the second control signal is provided to the sampling module to adjust the generation process of the second sampling signal.

2. The current detection circuit for a switching power supply converter according to claim 1, characterized in that, The sampling module includes: a first inverter, a first NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor; The input terminal of the first inverter receives the gate drive signal, and the output terminal of the first inverter is connected to one end of the second resistor and the upper plate of the first capacitor through the first resistor, and this end is used as the output terminal of the first sampling signal. The other end of the second resistor and the lower plate of the first capacitor are grounded; One end of the third resistor is connected to the switching node voltage, and the other end of the third resistor is connected to one end of the fourth resistor, the source of the first NMOS transistor, and the upper plate of the second capacitor, and this end is used as the output end of the second sampling signal; The other end of the fourth resistor and the lower plate of the second capacitor are grounded; The gate of the first NMOS transistor receives the second control signal, and the drain of the first NMOS transistor is grounded.

3. A current detection circuit for a switching power supply converter according to claim 2, characterized in that, The generation of the first and second sampling signals based on the on-state voltage drops of the high-side and low-side power transistors includes: During the high-side power transistor conduction phase, the voltage value of the first sampled signal is the voltage value after the input voltage is divided by the first resistor and the second resistor; During the high-side power transistor conduction phase, the voltage value of the second sampling signal is the voltage value obtained by dividing the input voltage by the voltage difference between the inductor current and the power transistor conduction impedance, and then by the voltage divider formed by the third resistor and the fourth resistor. During the turn-on phase of the low-side power transistor, the voltage value of the first sampled signal is zero; During the low-side power transistor conduction phase, the voltage value of the second sampled signal is the voltage value obtained by multiplying the negative inductor current by the power transistor conduction impedance and then dividing it by the third resistor and the fourth resistor.

4. A current detection circuit for a switching power supply converter according to claim 1, characterized in that, The current detection module includes: a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor.

5. A current detection circuit for a switching power supply converter according to claim 4, characterized in that, The gate of the third PMOS transistor receives the first sampling signal, and the source of the third PMOS transistor is connected to the emitter of the first transistor through the fifth resistor; The base of the first transistor is connected to the source of the second NMOS transistor and one end of the sixth resistor, and the collector of the first transistor is connected to the gate of the second NMOS transistor and the drain of the second PMOS transistor. The other end of the sixth resistor is connected to the base of the fourth transistor and the emitter of the second transistor. The base of the second transistor is connected to one end of the eighth resistor and the drain of the fourth NMOS transistor. The collector of the second transistor outputs the current detection output signal and is connected to one end of the seventh resistor. The gate of the fourth NMOS transistor receives a third bias voltage, the other end of the eighth resistor is connected to the base and collector of the third transistor, the emitter of the third transistor is connected to the source of the third NMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the fifth PMOS transistor and the collector of the fourth transistor. The source of the fifth PMOS transistor is connected to the drain of the fourth PMOS transistor, the emitter of the fourth transistor is connected to the source of the sixth PMOS transistor, and the gate of the sixth PMOS transistor receives the second sampling signal. The source of the first PMOS transistor, the source of the fourth PMOS transistor, the drain of the second NMOS transistor, and the drain of the third NMOS transistor are connected to the input voltage, while the source of the third PMOS transistor, the source of the sixth PMOS transistor, the other end of the seventh resistor, and the source of the fourth NMOS transistor are grounded.

6. A current detection circuit for a switching power supply converter according to claim 5, characterized in that, The first PMOS transistor, the second PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the fourth NMOS transistor constitute two common-source common-gate current sources and output equal bias currents; The third NMOS transistor, the third transistor, and the eighth resistor constitute a compensation circuit, which is used to compensate for the current error caused by the channel length modulation effect of the two common source and common gate current sources. The collector of the second transistor outputs the current detection output signal, which includes a DC component proportional to the bias current and an AC component proportional to the difference between the first sampling signal and the second sampling signal.

7. A current detection circuit for a switching power supply converter according to claim 2, characterized in that, The logic module includes: a logic unit, a dead-time control unit, a first buffer, and a second buffer; The logic unit is connected to the dead time control unit, which outputs the first control signal through the first buffer and the second control signal through the second buffer.

8. A current detection circuit for a switching power supply converter according to claim 7, characterized in that, During the dead time period when both the high-side power transistor and the low-side power transistor are turned off, the dead time control unit outputs the second control signal through the second buffer to turn on the first NMOS transistor and adjust the voltage value of the second sampled signal to near zero potential.

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