Hardware-driven interlocking delay control method and circuit and network-forming type energy storage converter

Abstract

The invention discloses a hardware-driven interlocking delay control method and circuit and a net-forming type energy storage converter, and relates to the technical field of power electronics, the hardware-driven interlocking delay control circuit comprises four interlocking delay control units which respectively act on a first outer tube IGBT, a first inner tube IGBT, a second inner tube IGBT and a second outer tube IGBT; interlocking between the corresponding inner and outer tube IGBTs is controlled through respectively generated locking signals between the first and third interlocking delay control units, between the first and fourth interlocking delay control units, and between the second and fourth interlocking delay control units. Corresponding turn-off delay of the inner tube and turn-on delay of the outer tube are controlled between the first interlocking delay control unit and the second interlocking delay control unit and between the third interlocking delay control unit and the fourth interlocking delay control unit through respectively generated turn-off control signals and turn-on control signals. By means of a hardware logic circuit, interlocking of complementary signals and control over delay on-off of an inner tube and an outer tube are achieved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a hardware-driven interlock delay control method, circuit, and grid-type energy storage converter. Background Technology

[0002] In medium- and high-voltage power electronic equipment such as energy storage converters, the three-level circuit based on neutral-point clamping topology has become one of the mainstream circuit topologies due to its advantages such as reducing voltage stress on switching devices, reducing output harmonics, and increasing system power density. The core execution components of this circuit are four IGBTs (Insulated Gate Bipolar Transistors), functionally divided into two external IGBTs and two internal IGBTs. The turn-on and turn-off logic of the four IGBTs directly determines the output characteristics and operational safety of the three-level circuit.

[0003] The three-level circuit based on neutral-point clamping topology requires the orderly switching of four IGBTs to achieve a DC bus voltage divider output during operation. Its core control requirements focus on two points: (1) Prevent DC bus short circuit. If two or more IGBTs are conducting at the same time, it may cause DC bus short circuit, generate a huge short circuit current, burn out IGBTs and bus capacitors, and cause equipment failure or even safety accident.

[0004] (2) IGBT safe operation timing control: IGBTs have inherent characteristics such as turn-on delay, turn-off delay and reverse recovery time. If the switching timing of the inner and outer IGBTs is not matched, voltage spikes or current overshoots are likely to occur during the commutation process.

[0005] Therefore, in a three-level circuit based on neutral point clamping containing four IGBTs, in order to prevent DC bus shoot-through and to consider the safe operation of the IGBTs themselves, it is necessary to ensure that certain IGBTs cannot be turned on simultaneously when designing the IGBT drive circuit, and at the same time ensure that the internal and external transistors execute delayed turn-on and turn-off control logic.

[0006] Currently, there are two main approaches to driving and controlling IGBTs in three-level circuits: (1) Pure software control scheme: When generating PWM signals through a microcontroller or digital signal processor, interlock logic and delay parameters are directly written into the software program. Although the delay time can be adjusted by modifying the program parameters, the software operation depends on CPU scheduling. If there are problems such as interrupt delay or instruction errors caused by electromagnetic interference, the interlock logic will fail directly, causing the risk of bus shoot-through. In addition, the accuracy of software delay is affected by CPU clock frequency and task priority, which makes it difficult to meet the timing control requirements in high-frequency switching scenarios.

[0007] (2) Hardware and software combined control scheme: On the basis of software delay control, a hardware interlock circuit is added. Although the reliability is improved to a certain extent, it still does not get rid of the dependence on software. Moreover, the hardware circuit is only responsible for the interlock function, and the delay control still needs to be implemented by software. When the software delay fails, the problem of IGBT switching timing mismatch will still occur. In addition, this scheme requires the simultaneous design of software program and hardware circuit, which increases the system complexity and R&D cost, and also increases the difficulty of debugging and the cost of later maintenance. Summary of the Invention

[0008] To address the aforementioned issues, this invention proposes a hardware-driven interlocking delay control method, circuit, and grid-type energy storage converter. By using a locking signal to achieve interlocking of multiple IGBTs and adjusting the timing with turn-off / turn-on control signals, flexible and adjustable turn-on and turn-off delay control is achieved, thereby improving the stability and reliability of the grid-type energy storage system.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a hardware-driven interlock delay control method, comprising: Based on the high and low level transitions of the received drive signal, a lock signal is generated, and the lock signal is controlled to maintain the current level state within a set delay period. This generates a drive signal for controlling the interlocking between the first external IGBT and the second internal IGBT, between the first external IGBT and the second external IGBT, and between the first internal IGBT and the second external IGBT. Based on the high and low level transitions of the generated drive signal, control signals are generated to control the internal tube turn-off delay and external tube turn-on delay between the first external IGBT and the first internal IGBT, and between the second internal IGBT and the second external IGBT, and the current state is maintained within the set delay time period.

[0010] As an alternative implementation, the process of generating the locking signal includes: generating a locking signal that is consistent with the level state of the received driving signal during a delay period, based on the level state of the received driving signal. The process of generating a control signal for the internal tube turn-off delay includes: generating a turn-off control signal that is consistent with the level state of the generated drive signal during the delay period, based on the level state of the generated drive signal; The process of generating a control signal for the external tube turn-on delay includes: generating a turn-on control signal that is opposite to the level state of the generated drive signal during the delay period, based on the level state of the generated drive signal.

[0011] As an alternative implementation, when the received drive signal changes from high level to low level, a lock signal that remains low level during the delay period is generated, thereby obtaining a low-level drive signal for locking the IGBT off state of the inner and outer tubes.

[0012] As an alternative implementation, when the generated drive signal changes from high level to low level, the first external IGBT or the second external IGBT is turned off, and at the same time, the turn-off control signal is kept at a low level for a set time, thereby controlling the delayed turn-off of the first internal IGBT or the second internal IGBT.

[0013] As an alternative implementation, when the generated drive signal changes from low level to high level, the first inner IGBT or the second inner IGBT is turned on, and at the same time, the turn-on control signal is kept at a low level for a set time, thereby controlling the delayed turn-on of the first outer IGBT or the second outer IGBT.

[0014] In a second aspect, the present invention provides a hardware-driven interlock delay control circuit, comprising: a first interlock delay control unit, a second interlock delay control unit, a third interlock delay control unit, and a fourth interlock delay control unit, which respectively act on a first outer IGBT, a first inner IGBT, a second inner IGBT, and a second outer IGBT; The first interlock delay control unit and the fourth interlock delay control unit are used to generate a locking signal and a shutdown control signal, and the second interlock delay control unit and the third interlock delay control unit are used to generate a locking signal and an activation control signal. The first interlock delay control unit and the third interlock delay control unit, the first interlock delay control unit and the fourth interlock delay control unit, and the second interlock delay control unit and the fourth interlock delay control unit control each control the interlock between the corresponding inner and outer IGBTs through their respective generated locking signals. The first interlock delay control unit and the second interlock delay control unit, as well as the third interlock delay control unit and the fourth interlock delay control unit, control the turn-off delay of the corresponding inner tube IGBT and the turn-on delay of the outer tube IGBT through their respective generated turn-off control signals and turn-on control signals.

[0015] As an alternative implementation, the first interlocked delay control unit includes a first delay circuit, and a first logic circuit, a third NOT gate circuit, and a second delay circuit connected in series. The input of the first delay circuit is the drive signal A, and the output is the lock signal A; The inputs of the first logic circuit are drive signal A, lock signal C of the third interlock delay control unit, lock signal D of the fourth interlock delay control unit, and turn-on control signal B of the second interlock delay control unit. The third NOT gate circuit outputs drive signal A1, and the second delay circuit outputs turn-off control signal A.

[0016] As an alternative implementation, when the drive signal C received by the third interlock delay control unit changes from high level to low level, the lock signal C remains at a low level for a set time. As a result, the first logic circuit outputs a high level, and the third NOT gate circuit outputs a low-level drive signal A1, which controls and locks the off state of the first external IGBT. After a set delay, the level of the lock signal C goes high, and the lock state ends. When the drive signal D received by the fourth interlock delay control unit changes from high level to low level, the lock signal D remains low for a set time. As a result, the first logic circuit outputs a high level, and the third NOT gate outputs a low-level drive signal A1, which locks the first external IGBT to the off state. After a set delay, the lock signal D goes high, and the lock state ends. When the drive signal B1 output by the second interlock delay control unit changes from low to high, the first internal IGBT is turned on. At the same time, the turn-on control signal B is kept at a low level for a set time, so that the first logic circuit outputs a high level and the third NOT gate outputs a low-level drive signal A1, which controls the first external IGBT not to be turned on. After a set delay, the drive signal A1 becomes high.

[0017] As an alternative implementation, the second interlocked delay control unit includes a third delay circuit, and a second logic circuit, a fifth logic circuit, a first NOT gate circuit, and a fourth delay circuit connected in series. The input to the third delay circuit is the drive signal B, and the output is the lock signal B. The inputs of the second logic circuit are the drive signal B and the lock signal D of the fourth interlock delay control unit. The inputs of the fifth logic circuit are the output of the second logic circuit and the turn-off control signal A of the first interlock delay control unit. The output of the fifth logic circuit is the drive signal B1, and the output of the fourth delay circuit is the turn-on control signal B.

[0018] As an alternative implementation, when the drive signal D received by the fourth interlock delay control unit changes from high level to low level, the lock signal D remains at a low level for a set time. As a result, the second logic circuit outputs a high level. When the other inputs of the fifth logic circuit are set to high level, the fifth logic circuit outputs a low-level drive signal B1, which locks the first inner transistor IGBT in the off state. After a set delay, the lock signal D goes high, and the locking state ends. When the drive signal A1 output by the first interlock delay control unit changes from high level to low level, the first external IGBT is turned off; at the same time, the turn-off control signal A is kept at a low level for a set time, thereby the fifth logic circuit outputs a high-level drive signal B1 to control the first internal IGBT not to be turned off; after a set delay, the drive signal B1 becomes low level.

[0019] As an alternative implementation, the third interlocked delay control unit includes a fifth delay circuit, and a third logic circuit, a sixth logic circuit, a second NOT gate circuit, and a sixth delay circuit connected in series. The input of the fifth delay circuit is the drive signal C, and the output is the lock signal C; The inputs of the third logic circuit are the drive signal C and the lock signal A of the first interlock delay control unit. The inputs of the sixth logic circuit are the output of the third logic circuit and the turn-off control signal D of the fourth interlock delay control unit. The output of the sixth logic circuit is the drive signal C1, and the output of the sixth delay circuit is the turn-on control signal C.

[0020] As an alternative implementation, when the drive signal A received by the first interlock delay control unit changes from high level to low level, the lock signal A remains at a low level for a set time. As a result, the third logic circuit outputs a high level. When the other inputs of the sixth logic circuit are set to high level, the sixth logic circuit outputs a low-level drive signal C1, which locks the off state of the second inner transistor IGBT. After a set delay, the level of the lock signal A goes high, and the locking state ends. When the drive signal D1 output by the fourth interlock delay control unit changes from high level to low level, the second external IGBT is turned off; at the same time, the turn-off control signal D is kept at a low level for a set time, thereby the sixth logic circuit outputs a high-level drive signal C1 to control the second internal IGBT not to be turned off; after a set delay, the drive signal C1 becomes low level.

[0021] As an alternative implementation, the fourth interlocked delay control unit includes a seventh delay circuit, and a fourth logic circuit, a fourth NOT gate circuit, and an eighth delay circuit connected in series. The input to the seventh delay circuit is the drive signal D, and the output is the lock signal D. The inputs of the fourth logic circuit are the drive signal D, the lock signal A of the first interlock delay control unit, the lock signal B of the second interlock delay control unit, and the turn-on control signal C of the third interlock delay control unit. The fourth NOT gate circuit outputs the drive signal D1, and the eighth delay circuit outputs the turn-off control signal D.

[0022] As an alternative implementation, when the drive signal A received by the first interlock delay control unit changes from high level to low level, the lock signal A remains at a low level for a set time. As a result, the fourth logic circuit outputs a high level, and the fourth NOT gate outputs a low-level drive signal D1, which locks the second external transistor IGBT to the off state. After a set delay, the lock signal A goes high, and the locking state ends. When the drive signal B received by the second interlock delay control unit changes from high level to low level, the lock signal B remains low for a set time. As a result, the fourth logic circuit outputs a high level, and the fourth NOT gate outputs a low-level drive signal D1, which locks the second external IGBT to the off state. After a set delay, the lock signal B goes high, and the lock state ends. When the drive signal C1 output by the third interlock delay control unit changes from low to high, the second inner IGBT is turned on. At the same time, the turn-on control signal C is kept low for a set time, so the fourth logic circuit outputs a high level, and the fourth NOT gate outputs a low-level drive signal D1, which controls the second outer IGBT not to be turned on. After a set delay, the drive signal D1 becomes high.

[0023] As an alternative implementation method, the control principle of the logic circuit is: when all input channels are at a high level, the output is at a low level; when any input channel is at a low level, the output is at a high level.

[0024] Thirdly, the present invention provides a grid-type energy storage converter, including multiple switching transistors, including a first outer IGBT, a first inner IGBT, a second inner IGBT, and a second outer IGBT, wherein the multiple switching transistors are controlled to be turned on or off by a hardware-driven interlocked delay control circuit as described in the second aspect.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention innovatively proposes a hardware-driven interlock delay control method for grid-type energy storage converters, designs a hardware-driven interlock delay control circuit, and develops a grid-type energy storage converter. Each interlock delay control unit corresponds to each group of IGBTs. Multiple groups of IGBTs are interlocked through a locking signal, and the timing is adjusted by the turn-off / turn-on control signal. No software assistance is required, which solves the problem of bus shoot-through risk caused by the failure of interlock logic in traditional control strategies. It realizes flexible and adjustable turn-on and turn-off delay control, and improves the stability and reliability of grid-type energy storage systems.

[0026] This invention innovatively proposes a hardware-driven interlocking delay control method. Four interlocking delay control units apply interlocking, delayed turn-on, and delayed turn-off control logic to four drive signals respectively. Relying on hardware logic circuits, interlocking control is achieved between the first external IGBT and the second internal IGBT, between the first internal IGBT and the second external IGBT, and between the first external IGBT and the second external IGBT. This ensures that the turn-off of the internal IGBT is delayed compared to the turn-off of the external IGBT, and the turn-on of the external IGBT is delayed compared to the turn-on of the internal IGBT. Comprehensive interlocking is achieved for the complex complementary relationship of the four IGBTs in a three-level circuit, ensuring that no IGBT conduction combination leading to bus shoot-through occurs at any time. No software assistance is required, fundamentally improving system reliability.

[0027] This invention innovatively proposes a hardware-driven interlocking delay control circuit and develops a novel grid-type energy storage converter. Through a configurable hardware delay circuit, it achieves flexible and adjustable turn-on and turn-off delay control, adapting to the switching characteristics of IGBTs of different specifications. At the same time, while realizing interlocking and delay control functions, it simplifies the circuit structure, reduces R&D and production costs and debugging difficulty, and can be directly integrated into the PWM signal processing stage before the IGBT drive circuit, improving system integration.

[0028] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a control circuit diagram for hardware-driven interlock delay provided in Embodiment 1 of the present invention; Figure 2 The flowchart is a control method for hardware driver interlock delay provided in Embodiment 1 of the present invention. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0032] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. Furthermore, it should be understood that the terms “comprising” and “including”, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0035] Example 1 This embodiment provides a hardware-driven interlock delay control circuit that uses hardware logic circuits to achieve interlocking of complementary signals and control of delayed on / off switching of internal and external transistors.

[0036] like Figure 1 As shown, it specifically includes: a first interlock delay control unit, a second interlock delay control unit, a third interlock delay control unit, and a fourth interlock delay control unit; the four units are respectively the control logic for interlocking, delaying turn-on, and delaying turn-off of the four drive signals, and provide the four output signals to the four IGBT drive circuits.

[0037] The first interlock delay control unit is connected to the drive circuit of the first external IGBT; the second interlock delay control unit is connected to the drive circuit of the first internal IGBT; the third interlock delay control unit is connected to the drive circuit of the second internal IGBT; and the fourth interlock delay control unit is connected to the drive circuit of the second external IGBT.

[0038] The first interlock delay control unit and the fourth interlock delay control unit are used by the two external IGBT drive circuits of the three-level circuit. They both have a delay circuit for generating a lock signal and a delay circuit for generating a turn-off control signal, and they also have logic circuits for receiving lock signals and turn-on control signals from other interlock delay control units.

[0039] The second and third interlock delay control units are used by the two internal IGBT drive circuits of the three-level circuit. They are equipped with delay circuits for generating lock signals and delay circuits for generating turn-on control signals, and also have logic circuits for receiving lock signals and turn-off control signals from other interlock delay control units.

[0040] In this embodiment, the first interlocked delay control unit includes a first delay circuit, a first logic circuit, a third NOT gate circuit, and a second delay circuit.

[0041] The second interlocked delay control unit includes a third delay circuit, a second logic circuit, a fifth logic circuit, a first NOT gate circuit, and a fourth delay circuit.

[0042] The third interlocked delay control unit includes a fifth delay circuit, a third logic circuit, a sixth logic circuit, a second NOT gate circuit, and a sixth delay circuit.

[0043] The fourth interlocked delay control unit includes a seventh delay circuit, a fourth logic circuit, a fourth NOT gate circuit, and an eighth delay circuit.

[0044] Specifically: In the first interlocked delay control unit, the drive signal A is connected to one of the input terminals of the first logic circuit and also to the input terminal of the first delay circuit; the output signal of the first delay circuit serves as the lock signal A, which is connected to one of the input terminals of the third logic circuit and one of the input terminals of the fourth logic circuit. The output of the first logic circuit is connected to the third NOT gate circuit. The output signal of the third NOT gate circuit serves as the output signal of the first interlocked delay control unit, i.e., the drive signal A1. The drive signal A1 also serves as a control signal, connected to the input of the second delay circuit. The output signal of the second delay circuit serves as the turn-off control signal A, connected to one of the inputs of the fifth logic circuit.

[0045] In the second interlock delay control unit, the drive signal B is connected to one of the input terminals of the second logic circuit and also to the input terminal of the third delay circuit; the output signal of the third delay circuit serves as the lock signal B and is connected to one of the input terminals of the fourth logic circuit. The output of the second logic circuit is connected to the fifth logic circuit. The output signal of the fifth logic circuit serves as the output signal of the second interlocked delay control unit, namely the drive signal B1. The drive signal B1 also serves as a control signal, connected to the input of the first NOT gate circuit. The output of the first NOT gate circuit is connected to the input of the fourth delay circuit. The output signal of the fourth delay circuit serves as the turn-on control signal B, connected to one of the inputs of the first logic circuit.

[0046] In the third interlock delay control unit, the drive signal C is connected to one of the input terminals of the third logic circuit and also to the input terminal of the fifth delay circuit; the output signal of the fifth delay circuit is used as the lock signal C and is connected to one of the input terminals of the first logic circuit. The output of the third logic circuit is connected to the sixth logic circuit. The output signal of the sixth logic circuit serves as the output signal of the third interlocked delay control unit, i.e., the drive signal C1. The drive signal C1 also serves as a control signal, connected to the input of the second NOT gate circuit. The output of the second NOT gate circuit is connected to the input of the sixth delay circuit. The output signal of the sixth delay circuit serves as the turn-on control signal C, connected to one of the inputs of the fourth logic circuit.

[0047] In the fourth interlock delay control unit, the drive signal D is connected to one of the input terminals of the fourth logic circuit and also to the input terminal of the seventh delay circuit; the output signal of the seventh delay circuit serves as the lock signal D, which is connected to one of the input terminals of the second logic circuit and one of the input terminals of the first logic circuit. The output of the fourth logic circuit is connected to the fourth NOT gate circuit. The output signal of the fourth NOT gate circuit serves as the output signal of the fourth interlocked delay control unit, i.e., the drive signal D1. The drive signal D1 also serves as a control signal, connected to the input of the eighth delay circuit. The output signal of the eighth delay circuit serves as the turn-off control signal D, connected to one of the inputs of the sixth logic circuit.

[0048] In this embodiment, the logic control principle of the first logic circuit, the second logic circuit, the third logic circuit, the fourth logic circuit, the fifth logic circuit, and the sixth logic circuit is as follows: when all input channels are at a high level, the output is at a low level; otherwise, as long as any input channel is at a low level, its output is at a high level.

[0049] In this embodiment, the first interlocking delay control unit and the third interlocking delay control unit form an interlocking relationship, and the interlocking control process includes: (1) When the drive signal A changes from high level to low level, the lock signal A is kept at a low level for a set time by the first delay circuit. At the same time, the low-level lock signal A is input to the third logic circuit, thereby forcibly controlling the third logic circuit to keep at a high level output. At this time, the high-level output of the third logic circuit also serves as the input of the sixth logic circuit. When the other inputs of the sixth logic circuit are set to high level, the output of the sixth logic circuit will remain at a low level, that is, the drive signal C1 is at a low level, locking the drive circuit C connected to the third interlock delay control unit to not issue a high-level turn-on signal, and locking the turn-off state of the second inner tube IGBT. After a set time delay, the lock signal A goes high, the lock state ends, and the output of the third logic circuit is determined by other input signals.

[0050] The above process ensures that after the drive signal A changes from high to low, there is a set delay before the drive signal C is allowed to change from low to high, thus achieving locking.

[0051] (2) When the drive signal C changes from high level to low level, the lock signal C is kept at a low level for a set time by the fifth delay circuit. At the same time, the low-level lock signal C is input to the first logic circuit, thereby forcibly controlling the first logic circuit to keep at a high level output. After the high-level output of the first logic circuit is input to the third NOT gate circuit, the third NOT gate circuit maintains a low-level output, that is, the drive signal A1 is low, locking the drive circuit A connected to the first interlock delay control unit to not issue a high-level turn-on signal, locking the first external IGBT to the off state. After a set time delay, the lock signal C level goes high, the lock state ends, and the output of the first logic circuit is determined by other input signals.

[0052] The above process ensures that after the drive signal C changes from high to low, there is a set delay before the drive signal A is allowed to change from low to high, thus achieving locking.

[0053] The delay time, also known as the interlock time or dead time, can be adjusted by the parameters of the delay circuit.

[0054] Therefore, the above interlocking control process realizes the interlocking of drive signal A and drive signal C, that is, it realizes the interlocking control of the first outer tube IGBT and the second inner tube IGBT.

[0055] In this embodiment, the interlocking control logic of the fourth interlocking delay control unit and the second interlocking delay control unit is the same as that of the first interlocking delay control unit and the third interlocking delay control unit.

[0056] Specifically: (1) When the drive signal B changes from high level to low level, the lock signal B is kept at a low level for a set time by the third delay circuit. At the same time, the low-level lock signal B is input to the fourth logic circuit, thereby forcibly controlling the fourth logic circuit to keep at a high level output. After the high-level output of the fourth logic circuit is input to the fourth NOT gate circuit, the fourth NOT gate circuit maintains a low-level output, that is, the drive signal D1 is low, locking the drive circuit D connected to the fourth interlock delay control unit to not issue a high-level turn-on signal, locking the second external transistor IGBT to the off state. After a set time delay, the lock signal B level goes high, the lock state ends, and the output of the fourth logic circuit is determined by other input signals.

[0057] (2) When the drive signal D changes from high level to low level, the lock signal D is kept at a low level for a set time through the seventh delay circuit. At the same time, the low-level lock signal D is input to the second logic circuit, thereby forcibly controlling the second logic circuit to keep at a high level output. At this time, the high-level output of the second logic circuit is also used as the input of the fifth logic circuit. When the other inputs of the fifth logic circuit are set to high level, the output of the fifth logic circuit will remain at a low level, that is, the drive signal B1 is at a low level, locking the drive circuit B connected to the second interlock delay control unit to not issue a high-level turn-on signal, and locking the turn-off state of the first inner tube IGBT. After a set time delay, the lock signal D level goes high, the lock state ends, and the output of the second logic circuit is determined by other input signals.

[0058] The delay time, also known as the interlock time or dead time, can be adjusted by the parameters of the delay circuit.

[0059] Thus, the above control logic realizes the interlock control of the first inner IGBT and the second outer IGBT.

[0060] In this embodiment, the interlocking control logic of the first interlocking delay control unit and the fourth interlocking delay control unit is the same as that of the first interlocking delay control unit and the third interlocking delay control unit.

[0061] Specifically: (1) When the drive signal A changes from high level to low level, the lock signal A is kept at a low level for a set time by the first delay circuit. At the same time, the low-level lock signal A is input to the fourth logic circuit, thereby forcibly controlling the fourth logic circuit to keep at a high level output. After the high-level output of the fourth logic circuit is input to the fourth NOT gate circuit, the fourth NOT gate circuit maintains a low-level output, that is, the drive signal D1 is low, locking the drive circuit D connected to the fourth interlock delay control unit to not issue a high-level turn-on signal, locking the second external transistor IGBT to the off state. After a set time delay, the lock signal A goes high, the lock state ends, and the output of the fourth logic circuit is determined by other input signals.

[0062] This process ensures that after the drive signal A changes from high to low, there is a set delay before the drive signal D is allowed to change from low to high, thus achieving locking.

[0063] (2) When the drive signal D changes from high level to low level, the lock signal D is kept at a low level for a set time by the seventh delay circuit. At the same time, the low-level lock signal D is input to the first logic circuit, thereby forcibly controlling the first logic circuit to keep at a high level output. After the high-level output of the first logic circuit is input to the third NOT gate circuit, the third NOT gate circuit maintains a low-level output, that is, the drive signal A1 is low, locking the drive circuit A connected to the first interlock delay control unit to not issue a high-level turn-on signal, locking the first external IGBT to the off state. After a set time delay, the lock signal D level goes high, the lock state ends, and the output of the first logic circuit is determined by other input signals.

[0064] This process ensures that after the drive signal D changes from high to low, there is a set delay before the drive signal A is allowed to change from low to high, thus achieving locking.

[0065] The delay time, also known as the interlock time or dead time, can be adjusted by the parameters of the delay circuit.

[0066] Thus, the above control logic achieves the interlocking of drive signal A and drive signal D, that is, it achieves the interlocking control of the first external IGBT and the second external IGBT.

[0067] In this embodiment, the first interlocking delay control unit and the second interlocking delay control unit form a delay relationship where the outer tube is turned off first and the inner tube is turned on first. The delay control process includes: (1) When the drive signal A1 changes from high level to low level, the drive circuit A connected to the first interlock delay control unit does not send a high level turn-on signal, that is, the first external tube IGBT is turned off. The low-level drive signal A1 outputs a turn-off control signal A after passing through the second delay circuit. The second delay circuit controls the turn-off control signal A to remain at a low level for a set time. The low-level turn-off control signal A serves as the input of the fifth logic circuit, forcibly controlling the fifth logic circuit to output a high level, that is, the drive signal B1 is at a high level. The drive circuit B sends a high-level turn-on signal, that is, the first inner transistor IGBT is not turned off. After a set delay time, the drive signal B1 goes low again, thus enabling the first external IGBT to turn off before the first internal IGBT, meaning the first external IGBT turns off first.

[0068] (2) When the drive signal B1 changes from low level to high level, the drive circuit B sends a high level turn-on signal, that is, turns on the first inner tube IGBT; The high-level drive signal B1 is output as a low level after passing through the first NOT gate circuit, and then outputs the turn-on control signal B through the fourth delay circuit. The fourth delay circuit controls the turn-on control signal B to remain at a low level for a set time. The low-level turn-on control signal B serves as the input of the first logic circuit, forcibly controlling the first logic circuit to output a high level. Then, through the third NOT gate circuit, a low-level drive signal A1 is output. Thus, the drive circuit A does not issue a high-level turn-on signal, that is, the first external IGBT is not turned on. After a set delay time, the drive signal A1 goes high again, thus enabling the first inner IGBT to turn on before the first outer IGBT, meaning the first inner IGBT turns on first.

[0069] The delay time is adjusted by the parameters of the delay circuit.

[0070] Therefore, the above control logic realizes the turn-on and turn-off delay control of the first outer IGBT and the first inner IGBT.

[0071] In this embodiment, the delay control logic relationship between the fourth interlock delay control unit and the third interlock delay control unit is the same as that between the first interlock delay control unit and the second interlock delay control unit.

[0072] Specifically: (1) When the drive signal C1 changes from low level to high level, the drive circuit C sends a high level turn-on signal, that is, the second inner tube IGBT is turned on; The high-level drive signal C1 is output as a low level after passing through the second NOT gate circuit, and then outputs the turn-on control signal C through the sixth delay circuit. The sixth delay circuit controls the turn-on control signal C to remain at a low level for a set time. The low-level turn-on control signal C serves as the input of the fourth logic circuit, forcibly controlling the fourth logic circuit to output a high level. Then, through the fourth NOT gate circuit, a low-level drive signal D1 is output. Thus, the drive circuit D does not issue a high-level turn-on signal, that is, the second external IGBT is not turned on. After a set delay time, the drive signal D1 goes high again, thus enabling the second inner IGBT to turn on before the second outer IGBT, meaning the second inner IGBT turns on first.

[0073] (2) When the drive signal D1 changes from high level to low level, the drive circuit D does not send a high level turn-on signal, that is, the second external transistor IGBT is turned off. The low-level drive signal D1 outputs a turn-off control signal D after passing through the eighth delay circuit. The eighth delay circuit controls the turn-off control signal D to remain at a low level for a set time. The low-level turn-off control signal D serves as the input of the sixth logic circuit, forcing the sixth logic circuit to output a high level, i.e., the drive signal C1 is at a high level. The drive circuit C sends a high-level turn-on signal, i.e., the second inner transistor IGBT is not turned off. After a set delay time, the drive signal C1 goes low again, thus enabling the second external IGBT to turn off before the second internal IGBT, meaning the second external IGBT turns off first.

[0074] The delay time is adjusted by the parameters of the delay circuit.

[0075] Thus, the above control logic realizes the turn-on and turn-off delay control of the second inner IGBT and the second outer IGBT.

[0076] Based on the above control circuit, a hardware-driven interlock delay control method is proposed, such as... Figure 2 As shown, it specifically includes: Based on the high and low level transitions of the received drive signal, a lock signal is generated, and the lock signal is controlled to maintain the current level state within a set delay period. This generates a drive signal for controlling the interlocking between the first external IGBT and the second internal IGBT, between the first external IGBT and the second external IGBT, and between the first internal IGBT and the second external IGBT. Based on the high and low level transitions of the generated drive signal, control signals are generated to control the internal tube turn-off delay and external tube turn-on delay between the first external IGBT and the first internal IGBT, and between the second internal IGBT and the second external IGBT, and the current state is maintained within the set delay time period.

[0077] The process of generating the lock signal includes: generating a lock signal that is consistent with the level of the received drive signal during the delay period, based on the level state of the received drive signal. The process of generating a control signal for the internal tube turn-off delay includes: generating a turn-off control signal that is consistent with the level state of the generated drive signal during the delay period, based on the level state of the generated drive signal; The process of generating a control signal for the external tube turn-on delay includes: generating a turn-on control signal that is opposite to the level state of the generated drive signal during the delay period, based on the level state of the generated drive signal.

[0078] When the received drive signal changes from high level to low level, a lock signal that remains low level during the delay period is generated, thereby obtaining a low-level drive signal used to lock the IGBT turn-off state of the inner and outer tubes.

[0079] When the generated drive signal changes from high level to low level, it controls the first external IGBT or the second external IGBT to turn off. At the same time, it controls the turn-off control signal to remain at a low level for a set time, thereby controlling the delayed turn-off of the first internal IGBT or the second internal IGBT.

[0080] When the generated drive signal changes from low level to high level, it controls the first inner IGBT or the second inner IGBT to turn on, and at the same time controls the turn-on control signal to remain at a low level for a set time, thereby controlling the delayed turn-on of the first outer IGBT or the second outer IGBT.

[0081] In summary, the circuit and its control logic described in this embodiment implement interlock control between the first external IGBT and the second internal IGBT, interlock control between the first internal IGBT and the second external IGBT, and interlock control between the first external IGBT and the second external IGBT, with the interlock time adjusted by the parameters of the corresponding delay circuit; and implement turn-on and turn-off delay control between the first external IGBT and the first internal IGBT, and turn-on and turn-off delay control between the second internal IGBT and the second external IGBT, i.e., the turn-off of the internal IGBT is delayed compared to the turn-off of the external IGBT, and the turn-on of the external IGBT is delayed compared to the turn-on of the internal IGBT, with the delay time adjusted by the parameters of the delay circuit.

[0082] In further embodiments, a grid-type energy storage converter is also provided, including multiple switching transistors, including a first outer IGBT, a first inner IGBT, a second inner IGBT, and a second outer IGBT. The multiple switching transistors are controlled to turn on or off by a hardware-driven interlocking delay control circuit proposed in the above embodiments.

[0083] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A hardware-driven interlock delay control method, characterized in that, include: Based on the high and low level transitions of the received drive signal, a lock signal is generated, and the lock signal is controlled to maintain the current level state within a set delay period. This generates a drive signal for controlling the interlocking between the first external IGBT and the second internal IGBT, between the first external IGBT and the second external IGBT, and between the first internal IGBT and the second external IGBT. Based on the high and low level transitions of the generated drive signal, control signals are generated to control the internal tube turn-off delay and external tube turn-on delay between the first external IGBT and the first internal IGBT, and between the second internal IGBT and the second external IGBT, and the current state is maintained within the set delay time period.

2. The hardware-driven interlock delay control method as described in claim 1, characterized in that, The process of generating a lock signal includes: generating a lock signal that is consistent with the level of the received drive signal during the delay period, based on the level of the received drive signal. The process of generating a control signal for the internal tube turn-off delay includes: generating a turn-off control signal that is consistent with the level state of the generated drive signal during the delay period, based on the level state of the generated drive signal; The process of generating a control signal for the external tube turn-on delay includes: generating a turn-on control signal that is opposite to the level state of the generated drive signal during the delay period, based on the level state of the generated drive signal.

3. The hardware-driven interlock delay control method as described in claim 2, characterized in that, When the received drive signal changes from high level to low level, a lock signal that remains low level during the delay period is generated, thereby obtaining a low-level drive signal used to lock the IGBT turn-off state of the inner and outer tubes.

4. The hardware-driven interlock delay control method as described in claim 2, characterized in that, When the generated drive signal changes from high level to low level, it controls the first external IGBT or the second external IGBT to turn off, and at the same time controls the turn-off control signal to remain at a low level for a set time, thereby controlling the delayed turn-off of the first internal IGBT or the second internal IGBT. When the generated drive signal changes from low level to high level, it controls the first inner IGBT or the second inner IGBT to turn on, and at the same time controls the turn-on control signal to remain at a low level for a set time, thereby controlling the delayed turn-on of the first outer IGBT or the second outer IGBT.

5. A hardware-driven interlock delay control circuit, characterized in that, include: The first interlock delay control unit, the second interlock delay control unit, the third interlock delay control unit, and the fourth interlock delay control unit act on the first outer tube IGBT, the first inner tube IGBT, the second inner tube IGBT, and the second outer tube IGBT, respectively. The first interlock delay control unit and the fourth interlock delay control unit are used to generate a locking signal and a shutdown control signal, and the second interlock delay control unit and the third interlock delay control unit are used to generate a locking signal and an activation control signal. The first interlock delay control unit and the third interlock delay control unit, the first interlock delay control unit and the fourth interlock delay control unit, and the second interlock delay control unit and the fourth interlock delay control unit control each control the interlock between the corresponding inner and outer IGBTs through their respective generated locking signals. The first interlock delay control unit and the second interlock delay control unit, as well as the third interlock delay control unit and the fourth interlock delay control unit, control the turn-off delay of the corresponding inner tube IGBT and the turn-on delay of the outer tube IGBT through their respective generated turn-off control signals and turn-on control signals.

6. The hardware-driven interlock delay control circuit as described in claim 5, characterized in that, The first interlocked delay control unit includes a first delay circuit, and a first logic circuit, a third NOT gate circuit, and a second delay circuit connected in series. The input of the first delay circuit is the drive signal A, and the output is the lock signal A; The inputs of the first logic circuit are drive signal A, lock signal C of the third interlock delay control unit, lock signal D of the fourth interlock delay control unit, and turn-on control signal B of the second interlock delay control unit. The third NOT gate circuit outputs drive signal A1, and the second delay circuit outputs turn-off control signal A.

7. The hardware-driven interlock delay control circuit as described in claim 6, characterized in that, When the drive signal C received by the third interlock delay control unit changes from high level to low level, the lock signal C remains low for a set time. As a result, the first logic circuit outputs a high level, and the third NOT gate outputs a low-level drive signal A1, which controls the lock to turn off the first external IGBT. After a set delay, the lock signal C goes high, and the lock state ends. When the drive signal D received by the fourth interlock delay control unit changes from high level to low level, the lock signal D remains low for a set time. As a result, the first logic circuit outputs a high level, and the third NOT gate outputs a low-level drive signal A1, which locks the first external IGBT to the off state. After a set delay, the lock signal D goes high, and the lock state ends. When the drive signal B1 output by the second interlock delay control unit changes from low to high, the first internal IGBT is turned on. At the same time, the turn-on control signal B is kept at a low level for a set time, so that the first logic circuit outputs a high level and the third NOT gate outputs a low-level drive signal A1, which controls the first external IGBT not to be turned on. After a set delay, the drive signal A1 becomes high.

8. The hardware-driven interlock delay control circuit as described in claim 5, characterized in that, The second interlocked delay control unit includes a third delay circuit, and a second logic circuit, a fifth logic circuit, a first NOT gate circuit, and a fourth delay circuit connected in series. The input to the third delay circuit is the drive signal B, and the output is the lock signal B. The inputs of the second logic circuit are the drive signal B and the lock signal D of the fourth interlock delay control unit. The inputs of the fifth logic circuit are the output of the second logic circuit and the turn-off control signal A of the first interlock delay control unit. The output of the fifth logic circuit is the drive signal B1, and the output of the fourth delay circuit is the turn-on control signal B.

9. The hardware-driven interlock delay control circuit as described in claim 8, characterized in that, When the drive signal D received by the fourth interlock delay control unit changes from high level to low level, the lock signal D remains low for a set time. As a result, the second logic circuit outputs a high level. When the other inputs of the fifth logic circuit are set to high level, the fifth logic circuit outputs a low-level drive signal B1, which locks the first internal IGBT in the off state. After a set delay, the lock signal D goes high, and the locking state ends. When the drive signal A1 output by the first interlock delay control unit changes from high level to low level, the first external IGBT is turned off; at the same time, the turn-off control signal A is kept at a low level for a set time, thereby the fifth logic circuit outputs a high-level drive signal B1 to control the first internal IGBT not to be turned off; after a set delay, the drive signal B1 becomes low level.

10. The hardware-driven interlock delay control circuit as described in claim 5, characterized in that, The third interlocked delay control unit includes a fifth delay circuit, and a third logic circuit, a sixth logic circuit, a second NOT gate circuit, and a sixth delay circuit connected in series. The input of the fifth delay circuit is the drive signal C, and the output is the lock signal C; The inputs of the third logic circuit are the drive signal C and the lock signal A of the first interlock delay control unit. The inputs of the sixth logic circuit are the output of the third logic circuit and the turn-off control signal D of the fourth interlock delay control unit. The output of the sixth logic circuit is the drive signal C1, and the output of the sixth delay circuit is the turn-on control signal C.

11. The hardware-driven interlock delay control circuit as described in claim 10, characterized in that, When the drive signal A received by the first interlock delay control unit changes from high level to low level, the lock signal A remains low for a set time. As a result, the third logic circuit outputs a high level. When the other inputs of the sixth logic circuit are set to high level, the sixth logic circuit outputs a low-level drive signal C1, which locks the second inner tube IGBT in the off state. After a set delay, the lock signal A goes high, and the lock state ends. When the drive signal D1 output by the fourth interlock delay control unit changes from high level to low level, the second external IGBT is turned off; at the same time, the turn-off control signal D is kept at a low level for a set time, thereby the sixth logic circuit outputs a high-level drive signal C1 to control the second internal IGBT not to be turned off; after a set delay, the drive signal C1 becomes low level.

12. The hardware-driven interlock delay control circuit as described in claim 5, characterized in that, The fourth interlocked delay control unit includes a seventh delay circuit, and a fourth logic circuit, a fourth NOT gate circuit, and an eighth delay circuit connected in series. The input to the seventh delay circuit is the drive signal D, and the output is the lock signal D. The inputs of the fourth logic circuit are the drive signal D, the lock signal A of the first interlock delay control unit, the lock signal B of the second interlock delay control unit, and the turn-on control signal C of the third interlock delay control unit. The fourth NOT gate circuit outputs the drive signal D1, and the eighth delay circuit outputs the turn-off control signal D.

13. The hardware-driven interlock delay control circuit as described in claim 12, characterized in that, When the drive signal A received by the first interlock delay control unit changes from high level to low level, the lock signal A remains low for a set time. As a result, the fourth logic circuit outputs a high level, and the fourth NOT gate outputs a low-level drive signal D1, which locks the second external IGBT to the off state. After a set delay, the lock signal A goes high, and the locking state ends. When the drive signal B received by the second interlock delay control unit changes from high level to low level, the lock signal B remains low for a set time. As a result, the fourth logic circuit outputs a high level, and the fourth NOT gate outputs a low-level drive signal D1, which locks the second external IGBT to the off state. After a set delay, the lock signal B goes high, and the lock state ends. When the drive signal C1 output by the third interlock delay control unit changes from low to high, the second inner IGBT is turned on. At the same time, the turn-on control signal C is kept low for a set time, so the fourth logic circuit outputs a high level, and the fourth NOT gate outputs a low-level drive signal D1, which controls the second outer IGBT not to be turned on. After a set delay, the drive signal D1 becomes high.

14. A hardware-driven interlock delay control circuit as described in any one of claims 5-13, characterized in that, The control principle of the logic circuit is as follows: when all input channels are at a high level, the output is at a low level; when any input channel is at a low level, the output is at a high level.

15. A grid-type energy storage converter, characterized in that, It includes multiple switching transistors, including a first external IGBT, a first internal IGBT, a second internal IGBT, and a second external IGBT. The multiple switching transistors are controlled to turn on or off by a hardware-driven interlock delay control circuit as described in any one of claims 5-14.

Images