Coupling inductor interleaving control high-step-down direct-current converter and control method thereof

Abstract

The invention discloses a coupling inductor interleaved control high-voltage-reduction direct-current converter and a control method thereof. The converter comprises a direct-current input power supply, two power switch tubes, two diodes, a coupling inductor, a flying capacitor, an output capacitor and a load resistor, wherein the coupling inductor is composed of two tightly-coupled inductors with the same winding direction; zero-voltage turn-on and zero-current turn-off of a power device can be realized without additionally designing an auxiliary circuit, the soft switching capability is realized, the switching loss is reduced, and the efficiency is improved; meanwhile, current sharing can be automatically achieved without additionally designing a current sharing control strategy, the power device bears small voltage stress, element parameter type selection is facilitated, and miniaturization and light weight of the converter are facilitated. The control method comprises the steps of detecting input and output voltage, calculating a duty ratio, judging a working interval, generating a PWM signal, driving a power switch tube and monitoring and adjusting in real time, and high step-down ratio, low output voltage ripple and output current ripple are realized by adopting an interleaving control technology and a magnetic coupling technology.

Description

Technical Field

[0001] This invention relates to a coupled inductor interleaved control high step-down DC-DC converter and its control method, belonging to the field of DC-DC conversion technology. Background Technology

[0002] DC-DC buck converters are widely used in photovoltaic power generation, wind power generation, AC / DC charging piles, hydrogen production, uninterruptible power supplies, grid-connected inverters, microprocessors, and other fields. By achieving voltage conversion, they meet the voltage level requirements of different application scenarios. Therefore, these fields place high demands on the converter's structure, size, weight, efficiency, reliability, and economy.

[0003] Traditional single-phase Buck converters are characterized by simple structure, convenient control, and wide input / output voltage range, and they occupy a large share of the application market. However, traditional single-phase Buck converters also have disadvantages such as large size, heavy weight, wide ripple, high current stress on switching devices, low efficiency and difficulty in improving efficiency, which do not conform to the current development trend of miniaturization, lightweight, low loss and fast response speed of DC converters.

[0004] To address this issue, scholars both domestically and internationally have conducted extensive scientific research. For example, replacing the freewheeling diode in a conventional Buck converter with a MOSFET (Metal-Oxide-Semiconductor Transistor) with low on-resistance creates a synchronous Buck converter. This reduces the conduction losses and improves efficiency to some extent, but it still cannot overcome the drawbacks of large output voltage and current ripple. In practical applications, synchronous Buck converters also need to consider the dead time of the two power switches to avoid shoot-through and subsequent device damage.

[0005] Studies have shown that increasing the switching frequency of a converter can effectively reduce the size of magnetic components such as inductors and capacitors. However, increasing the switching frequency also brings other risks. On the one hand, as the switching frequency increases, the number of switching operations of the power devices (i.e., power switches) in the converter increases, leading to increased switching losses and ultimately reduced converter efficiency. On the other hand, as the switching frequency increases, the heat generated by the power devices in the converter increases, reducing their safe service life and potentially affecting the reliability of the converter in severe cases.

[0006] To address the aforementioned technical problems, this invention combines interleaved control technology and magnetic coupling technology to propose a high buck ratio DC-DC converter, achieving the target requirements of high buck ratio, high power density, and fast voltage regulation. Summary of the Invention

[0007] To address the aforementioned issues, this invention proposes a coupled inductor interleaved control high buck DC-DC converter and its control method, which can achieve target requirements such as high buck ratio, high power density, and fast voltage regulation.

[0008] The technical solution adopted by this invention to solve its technical problem is as follows: In a first aspect, the present invention provides a coupled inductor interleaved control high step-down DC-DC converter, comprising a DC input power supply, a first power switch, a second power switch, a first diode, a second diode, a coupled inductor, a flying capacitor, an output capacitor, and a load resistor; The coupled inductor consists of a first inductor and a second inductor, which are tightly coupled and have the same winding direction. The drain of the first power switch is connected to the positive terminal of the DC input power supply, and the source is connected to the drain of the second power switch, and is also connected to one end of the flying capacitor. The drain of the second power switch is connected to the source of the first power switch, the source is connected to the cathode of the second diode, and one end of the second inductor is also connected to the coupling inductor. The anode of the first diode is connected to the negative terminal of the DC input power supply, and the cathode is connected to one end of the first inductor of the coupling inductor, and at the same time connected to the other end of the flying capacitor; The anode of the second diode is connected to the negative terminal of the DC input power supply, the cathode is connected to the source of the second power switch, and one end of the second inductor is also connected to the coupling inductor. The other end of the first inductor and the other end of the second inductor are both connected to the positive terminal of the output capacitor and one end of the load resistor; The negative terminal of the output capacitor and the other end of the load resistor are connected to the negative terminal of the DC input power supply.

[0009] Secondly, the present invention provides a control method for a high-step DC-DC converter with interleaved coupled inductor control as described above, comprising the following steps: Step S1: Detect the input voltage and output voltage of the DC-DC converter; Step S2: Calculate the required duty cycle α based on the target voltage drop ratio; Step S3: Determine the working range of the duty cycle α, wherein the working range of the duty cycle α includes: 0.5≤α<1 and 0<α<0.5; Step S4: Generate a first PWM signal and a second PWM signal, with a phase difference of 180° and a duty cycle of α. Step S5: Drive the first power switch with the first PWM signal and drive the second power switch with the second PWM signal. Step S6: Monitor the converter's operating status in real time and dynamically adjust the duty cycle α to maintain stable output.

[0010] The beneficial effects of the technical solutions of the embodiments of the present invention are as follows: This invention employs magnetic coupling technology, introduces a coupling inductor into the converter, and rationally sets the duty cycle of the PWM drive signal. This ensures that the DC-DC buck converter can output voltage over a wide buck ratio range, effectively avoiding the situation where the converter achieves buck output through an extreme duty cycle.

[0011] This invention, by employing an interleaved control method, can reduce the output voltage ripple and output current ripple of a DC-DC buck converter, thereby improving the safety performance and service life of magnetic components such as inductors and capacitors in the converter.

[0012] This invention eliminates the need for additional auxiliary circuit design for the DC-DC buck converter, enabling zero-voltage turn-on and zero-current turn-off of power devices. The converter itself already possesses soft-switching capability, which can reduce switching losses and improve efficiency.

[0013] This invention can automatically achieve current sharing without requiring additional current sharing control strategies to be designed for the DC-DC buck converter.

[0014] The power devices in the DC-DC buck converter of this invention can withstand smaller voltage stress, which facilitates the selection of parameters for power devices and magnetic components such as inductors and capacitors. This is beneficial for miniaturization and weight reduction of the converter, thereby reducing its size and cost. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a high buck DC-DC converter with coupled inductor interleaving control, according to an exemplary embodiment. Figure 2 This is an equivalent circuit diagram of a coupled inductor according to an exemplary embodiment; Figure 3 This is a PWM drive signal diagram illustrating a duty cycle α when 0.5 ≤ α < 1, according to an exemplary embodiment. Figure 4 This is a diagram of a PWM drive signal with a duty cycle α of 0 < α < 0.5, according to an exemplary embodiment. Figure 5 This is a flowchart illustrating a control method for a high buck DC-DC converter with coupled inductor interleaving control according to an exemplary embodiment; Figure 6 This is an equivalent loop diagram of converter mode 11 with a duty cycle α of 0.5 ≤ α < 1, according to an exemplary embodiment. Figure 7 This is an equivalent loop diagram of converter mode 12 with a duty cycle α of 0.5 ≤ α < 1, according to an exemplary embodiment. Figure 8This is an equivalent loop diagram of converter mode 13 with a duty cycle α of 0.5 ≤ α < 1, according to an exemplary embodiment. Figure 9 This is an equivalent loop diagram of converter mode 14 with a duty cycle α of 0.5 ≤ α < 1, according to an exemplary embodiment. Figure 10 This is an exemplary embodiment illustrating the power switch drive signal and related waveforms when the duty cycle α is 0.5 ≤ α < 1. Figure 11 This is a waveform diagram illustrating the soft-switching characteristics of a power switch transistor when the duty cycle α is 0.5 ≤ α < 1, according to an exemplary embodiment. Figure 12 This is an equivalent loop diagram of converter mode 21 with a duty cycle α of 0 < α < 0.5, according to an exemplary embodiment. Figure 13 This is an equivalent loop diagram of converter mode 22 with a duty cycle α of 0 < α < 0.5, according to an exemplary embodiment. Figure 14 This is an equivalent loop diagram of converter mode 23 with a duty cycle α of 0 < α < 0.5, according to an exemplary embodiment. Figure 15 This is an equivalent loop diagram of converter mode 24 with a duty cycle α of 0 < α < 0.5, according to an exemplary embodiment. Figure 16 This is an exemplary embodiment illustrating a power switch drive signal and related waveforms when the duty cycle α is 0 < α < 0.5. Figure 17 This is a waveform diagram illustrating the soft-switching characteristics of a power switch when the duty cycle α is 0 < α < 0.5, according to an exemplary embodiment. Figure 18 This is a waveform diagram of the dynamic response output voltage of a converter with a duty cycle α=0.6, according to an exemplary embodiment. Figure 19 This is a steady-state output voltage ripple waveform diagram of a converter with a duty cycle α=0.6, according to an exemplary embodiment. Figure 20 This is a waveform diagram illustrating the soft-switching characteristics of a power switch transistor with a duty cycle α = 0.6, according to an exemplary embodiment. Figure 21 This is a waveform diagram of the dynamic response output voltage of a converter with a duty cycle α=0.4, according to an exemplary embodiment. Figure 22This is a waveform diagram of the steady-state output voltage ripple of a converter with a duty cycle α = 0.4, according to an exemplary embodiment. Figure 23 This is a waveform diagram illustrating the soft-switching characteristics of a power switch transistor with a duty cycle α = 0.4, according to an exemplary embodiment. Detailed Implementation

[0016] To more clearly illustrate the technical features of the present invention, the present invention will be described in detail below through specific embodiments and in conjunction with the accompanying drawings.

[0017] Example 1: Coupled Inductor Interleaved Control High-Step-Down DC-DC Converter like Figure 1 As shown, the present invention provides a coupled inductor interleaved control high-step-down DC-DC converter, including a DC input power supply V. i First power switch S1, second power switch S2, first diode D1, second diode D2, coupling inductor, flying capacitor C1, output capacitor C o and load resistance R; The coupled inductor is composed of a first inductor L1 and a second inductor L2, which are tightly coupled and have the same winding direction. The drain of the first power switch S1 is connected to the DC input power supply V. i The positive terminal and the source terminal are connected to the drain terminal of the second power switch S2, and are also connected to one end of the flying capacitor C1. The drain of the second power switch S2 is connected to the source of the first power switch S1, and the source is connected to the cathode of the second diode D2, and is also connected to one end of the second inductor L2 of the coupling inductor. The anode of the first diode D1 is connected to the DC input power supply V. i The negative terminal and cathode are connected to one end of the first inductor L1 of the coupling inductor, and at the same time to the other end of the flying capacitor C1; The anode of the second diode D2 is connected to the DC input power supply V. i The negative terminal of the transistor is connected to the source of the second power switch S2, and is also connected to one end of the second inductor L2 of the coupling inductor. The other end of the first inductor L1 and the other end of the second inductor L2 are both connected to the output capacitor C. o The positive terminal and one end of the load resistor R; The output capacitor C o The negative terminal and the other end of the load resistor R are connected to the DC input power supply V. i The negative electrode.

[0018] As one possible implementation of this embodiment, the coupling coefficient k of the coupled inductor satisfies: 0.8≤k≤0.95.

[0019] As one possible implementation of this embodiment, the first power switch S1 and the second power switch S2 are MOSFETs or IGBTs.

[0020] Figure 1 middle: V i Input voltage of the DC-DC buck converter; S 1: The first power switch in the DC-DC buck converter is modulated by the PWM (Pulse Width Modulation) drive signal; S 2: The second power switch in the DC-DC buck converter is modulated by the PWM (Pulse Width Modulation) drive signal; D 1: The first diode in a DC-DC buck converter; D 2: The second diode in the DC-DC buck converter; L 1 and L 2: Coupled inductor in DC-DC buck converter (used as a component); C 1: Flying capacitor in a DC-DC buck converter; C o Output capacitor in a DC-DC buck converter; R Load resistor in a DC-DC buck converter; V o Output voltage of DC-DC buck converter.

[0021] To ensure that the DC-DC buck converter can achieve a higher buck ratio, Figure 1 Inductance in L 1 and L Two closely coupled inductors, with the same winding direction, form a coupled inductor. According to circuit theory, this coupled inductor can be decoupled into three uncoupled inductors, thus obtaining... Figure 2 The equivalent circuit shown. Figure 2 middle: and The equivalent leakage inductance of a coupled inductor; M Mutual inductance of coupled inductors.

[0022] Figure 1 and Figure 2 Inductance in , , , , The following equation applies numerically between them: (1), In the formula: , The self-inductance of the coupled inductor; , This is the equivalent leakage inductance of the coupled inductor; The mutual inductance of the coupled inductors.

[0023] To facilitate circuit analysis, the following is now... Figure 2 The following reasonable assumptions are made about the circuit components: (1) All power devices, magnetic components, and diodes in the circuit are ideal devices. The on-state resistance on the parasitic capacitance of the power devices and the diodes are ignored. D 1 and D Forward conduction voltage drop on 2; (2) Ignore flying capacitors C 1. Output capacitor C o The equivalent series resistance on the inductor and the parasitic resistance on the coupled inductor; (3) In selecting the parameters of the coupled inductors, the self-inductance of the coupled inductors should be the same, that is... L 1 =L 2 =L ; (4) S 1 and S 2. Alternating conduction operation, with a phase difference of 180°, and S 1 and S Both are driven by PWM drive signals.

[0024] Figure 3 Duty cycle α In 0.5≤ α A set of PWM drive signals when <1. Figure 3 middle: The PWM1 signal is used to drive the power switching transistor. S 1; The PWM2 signal is used to drive the power switching transistor. S 2.

[0025] Figure 4 Duty cycle α In 0< α A set of PWM drive signals when <0.5. Figure 4 middle: The PWM1 signal is used to drive the power switching transistor. S 1; The PWM2 signal is used to drive the power switching transistor. S 2.

[0026] As one possible implementation of this embodiment, the buck ratio AMP of the coupled inductor interleaved control high buck DC converter satisfies: When 0.5 ≤ α < 1, ; When 0 < α < 0.5, ; in, k The coupling coefficient is... ; , The self-inductance of the coupled inductor; The mutual inductance of the coupled inductors.

[0027] Example 2: Control Method like Figure 5 As shown in the figure, an embodiment of the present invention provides a control method for a high-step DC-DC converter with coupled inductors interleaved as described above, comprising the following steps: Step S1: Detect the input voltage V of the DC-DC converter. i and output voltage V o ; Step S2: Calculate the required duty cycle α based on the target voltage drop ratio; Step S3: Determine the working range of the duty cycle α, wherein the working range of the duty cycle α includes: 0.5≤α<1 and 0<α<0.5; Step S4: Generate a first PWM signal and a second PWM signal, with a phase difference of 180° and a duty cycle of α. Step S5: Drive the first power switch S1 with the first PWM signal and drive the second power switch S2 with the second PWM signal. Step S6: Monitor the converter's operating status in real time and dynamically adjust the duty cycle α to maintain stable output.

[0028] As one possible implementation of this embodiment, step S1 includes: Step S11: A high-precision resistor divider network is used to measure the input voltage V. i and output voltage V o Perform sampling; Step S12: The sampled signal is isolated and amplified using an isolation operational amplifier; Step S13: Use an anti-aliasing filter to filter the amplified signal; Step S14: Convert the analog signal into a digital signal using an analog-to-digital converter; Step S15: A digital signal processor is used to perform digital filtering and calibration on the converted digital signal.

[0029] As one possible implementation of this embodiment, step S2 includes: Step S201: Read the preset target output voltage V target ; Step S202, obtain the current input voltage V i The measured value; Step S203, calculate the target pressure drop ratio AMP target = V target / V i ; Step S204: Calculate the initial duty cycle α0 based on the correspondence between the step-down ratio and the duty cycle; Step S205: Limit the initial duty cycle to ensure it is within the effective range.

[0030] As one possible implementation of this embodiment, the relationship between the step-down ratio and the duty cycle in step S204 is as follows: When 0.5 ≤ α < 1, ; When 0 < α < 0.5, ; in, k The coupling coefficient is... ; , The self-inductance of the coupled inductor; The mutual inductance of the coupled inductors.

[0031] As one possible implementation of this embodiment, step S3 includes: Step S301: Read the calculated duty cycle α; Step S302: Compare the duty cycle α with the threshold 0.5; Step S303: If α ≥ 0.5, then the working interval is determined to be 0.5≤α<1; Step S304: If α < 0.5, then the working interval is determined to be 0 < α < 0.5.

[0032] As one possible implementation of this embodiment, step S4 includes: Step S401: Determine the timing parameters of the PWM signal based on the duty cycle α and the working interval, wherein the timing parameters include the on-time and off-time; Step S402: Configure the timer period T and the compare register; Step S403: Set dead time to prevent pass-through. Step S404: Enable PWM output.

[0033] As one possible implementation of this embodiment, step S5 includes: Step S501: Perform level conversion on the PWM signal; Step S502: Amplify the driving capability through the gate driving circuit; Step S503: Monitor drive current and voltage; Step S504: Implement overcurrent and overvoltage protection.

[0034] As one possible implementation of this embodiment, step S6 includes: Step S601: Monitor the input current and output current; Step S602: Detect the temperature of the power device; Step S603: Analyze current ripple and voltage ripple; Step S604: Evaluate the converter efficiency.

[0035] As one possible implementation of this embodiment, in step S4, when the duty cycle α is 0.5 ≤ α < 1, the converter has the following four operating modes within one switching cycle: Mode 11: The first power switch S1 and the second power switch S2 are turned on simultaneously; Mode 12: The first power switch S1 is turned on, and the second power switch S2 is turned off; Mode 13: The first power switch S1 and the second power switch S2 are turned on simultaneously; Mode 14: The first power switch S1 is turned off, and the second power switch S2 is turned on; When the duty cycle α is 0 < α < 0.5, the converter has the following four operating modes in one switching cycle: Mode 21: The first power switch S1 is turned on, and the second power switch S2 is turned off; Mode 22: The first power switch S1 and the second power switch S2 are turned off simultaneously; Mode 23: The first power switch S1 is turned off, and the second power switch S2 is turned on; Mode 24: The first power switch S1 and the second power switch S2 are turned off simultaneously.

[0036] Consider the duty cycle of the PWM drive signal α In 0< α <0.5 and 0.5≤ α <1 Two situations will lead to Figure 2 The converter shown exhibits different operating modes and buck ratios, which will be discussed in the following classification.

[0037] Example 3: Duty cycle α when 0.5 ≤ α < 1 (1) Working principle analysis: Figure 3 This is a set of PWM drive signals with a duty cycle α of 0.5 ≤ α < 1. Figure 3 In the diagram: PWM1 signal is used to drive power switch S1; PWM2 signal is used to drive power switch S2.

[0038] Within one switching cycle T, the equivalent circuit of the converter has four operating modes. In each operating mode, the on / off states of the power switches S1 and S2 and the diodes D1 and D2 inside the circuit are shown in Table 1.

[0039] Table 1 On / off status of power switches and diodes under different modes (0.5≤α<1)

[0040] Based on the on / off states of power switches S1 and S2 and diodes D1 and D2 during one switching cycle as described in Table 1, the operating loops of the converter equivalent circuit under different operating modes can be drawn, such as... Figures 6-9 As shown.

[0041] according to Figures 6-9 The equivalent circuits of the converter shown are in four different operating modes, and Figure 10 The drive signal waveforms of medium-power switching transistors S1 and S2, combined with the small ripple approximation principle, can be used to provide a detailed discussion of the operation of the high buck ratio DC-DC converter proposed in this invention in each mode within a switching cycle T.

[0042] Mode 1[ t 0 , t 1]: exist t At time 0, power switching transistor S 1. When conduction begins, it is affected by the previous switching cycle. S 2 is in the ON state. Inductor Due to discharge, current flows through the inductor current i L1 Linear decrease, while inductance because S 1. Conduction occurs, and current flows through the inductor. current i L2 It exhibits a linear increasing trend due to the two current loops. (Capacitor) C 1. Due to charging, the voltage at both ends v C1 Linear increase. In this mode, the equivalent circuit is as follows: Figure 6 As shown, the loop equation of the equivalent loop is: (2).

[0043] Mode 2[t 1 , t 2]: exist t At time 1, the power switching transistor S 1. Conduction, S 2. Turn off. Flow through the inductor current i L1 The inductance continues to rise linearly. Due to discharge, current flows through the inductor current i L2 Linear decrease, capacitance C 1. Due to charging, the voltage at both ends v C1 Linear increase. In this mode, the equivalent circuit is as follows: Figure 7 As shown, the loop equation of the equivalent loop is: (3).

[0044] Mode 3[ t 2 , t 3]: exist t At time 2, the power switching transistor S 1. Conduction, S 2. Conducting. Inductor Discharge begins, flowing through the inductor current i L1 Linear decrease, inductance Charging, current flows through the inductor current i L2 Linear increase, capacitance C 1 is in a continuous charging state, and the voltage at both ends is... v C1 Linear increase. In this mode, the equivalent circuit is as follows: Figure 8 As shown, the loop equation of the equivalent loop is: (4).

[0045] Mode 4[ t 3 , t 4]: exist t At time 3, the power switching transistor S 1. Turn off, S 2. Conduction. Flow through the inductor. current i L1 Linear decrease, flowing through the inductor current i L2 Then it maintains a linear upward trend, capacitance C1 is in a discharging state, and the voltage at both ends is... v C1 Linear descent. In this mode, the equivalent circuit is as follows: Figure 9 As shown, the loop equation of the equivalent loop is: (5).

[0046] from t Starting at time 4, the power switching transistor S 1 and S The drive signal 2 simultaneously enters the next switching cycle. The operation of the DC-DC buck converter in the next switching cycle is exactly the same as in the previous cycle, which will not be described in detail here.

[0047] (2) Steady-state analysis: ① Pressure drop ratio: according to Figure 10 middle i L1 and i L2 The waveforms can be obtained as follows: (6), (7), In formula (6): (8); use I 1 and I 2 represents the current flowing through the inductor. and The average current, according to the definition of average current, occurs within one switching cycle T. I 1 and I 2 can be calculated using equations (9) and (10) respectively.

[0048] (9), (10); Considering that the output power of the converter equals the input power, that is: (11); Combining equations (1), (6) to (11), duty cycle α In 0.5≤ α When <1, the converter's buck ratio AMP for: (12).

[0049] ② Power switching transistor S 1 and S Soft-switching characteristics of 2: power switching transistors S 1 and S 2. During the conduction and turn-off processes, the flow through S 1 and S 2 current i S1 and i S2 waveform and S 1 and S 2. Voltage across the terminals v S1 and v S2 The waveform is as follows Figure 11 As shown. From Figure 11 It can be seen from this that: when S When 1 is turned on, S 1. Voltage across the terminals v S1 Reduced to 0, achieving zero-voltage start-up; when S When 1 is turned off, the flow through S 1 current i S1 Reduced to 0, achieving zero-current shutdown. Similarly, when S When 2 is on, S 2. Voltage across the terminals v S2 Reduced to 0, achieving zero-voltage start-up; when S 2. When shut off, the flow through S 2 current i S2 The current is reduced to 0, achieving zero-current shutdown. In summary, in the DC-DC buck converter proposed in this invention, the power switching transistor... S 1 and S 2. During their respective turn-on and turn-off processes, no additional auxiliary circuitry is required to achieve soft switching, effectively avoiding [the following issues]. S 1 and S 2. Switching losses during turn-on and turn-off improve converter efficiency.

[0050] Example 4: Duty cycle α when 0 < α < 0.5 (1) Working principle analysis: Within one switching cycle T Figure 2 The equivalent circuit of the converter shown also has four operating modes. In each operating mode, the internal power switch transistors... S 1 and S 2 and diodes D 1 and D The on / off states of 2 are shown in Table 2.

[0051] Figure 4 This is a set of PWM drive signals with a duty cycle α of 0 < α < 0.5. Figure 4 In the diagram: PWM1 signal is used to drive power switch S1; PWM2 signal is used to drive power switch S2.

[0052] Within one switching cycle T, the equivalent circuit of the converter also has four operating modes. In each operating mode, the on / off states of the power switches S1 and S2 and the diodes D1 and D2 inside the circuit are shown in Table 2.

[0053] Table 2 On / off status of power switches and diodes under different modes (0<α<0.5)

[0054] Based on the on / off states of power switches S1 and S2 and diodes D1 and D2 during one switching cycle as described in Table 2, the operating loops of the converter equivalent circuit under different operating modes can be drawn, such as... Figures 12-15 As shown.

[0055] according to Figures 12-15 The equivalent circuits of the converter shown are in four different operating modes, and Figure 16 The driving signal waveforms of medium-power switching transistors S1 and S2, combined with the small ripple approximation principle, provide a detailed discussion of the operation of the high buck ratio DC-DC buck converter proposed in this invention in various modes within one switching cycle T.

[0056] Mode 1[ t 0 , t 1]: exist t At time 0, power switching transistor S 1. When conduction begins, it is affected by the previous switching cycle. S 2 is in the off state. Inductor Due to charging, current flows through the inductor current i L1 Linear rise, inductance Due to discharge, current flows through the inductor current i L2 It exhibits a linear decreasing trend. Capacitance C 1. Due to charging, the voltage at both ends v C1 Linear increase. In this mode, the equivalent circuit is as follows: Figure 12 As shown, the loop equation of the equivalent loop is: (13).

[0057] Mode 2[ t 1 , t 2]: exist tAt time 1, the power switching transistor S 1. Turn off, S 2. Turn off. Inductor M Discharge, flowing through the inductor M current i M Linear decrease, inductance current i L1 exist i M The inductance remains unchanged under the influence of [the following]. Because of diodes D 2. Turn off, current i L2 The capacitance remains unchanged. C 1. Voltage across terminals v C1 It remains unchanged. In this mode, the equivalent circuit is as follows: Figure 13 As shown, the loop equation of the equivalent loop is: (14).

[0058] Mode 3[ t 2 , t 3]: exist t At time 2, the power switching transistor S 1. Turn off, S 2. Conducting. Inductor Discharge, flowing through the inductor current i L1 Linear decrease, inductance Charging, current flows through the inductor current i L2 Linear increase, capacitance C 1 is in a discharging state, and the voltage at both ends is... v C1 Linear descent. In this mode, the equivalent circuit is as follows: Figure 14 As shown, the loop equation of the equivalent loop is: (15).

[0059] Mode 4[ t 3 , t 4]: exist t At time 3, the power switching transistor S 1. Turn off, S 2. Turn off. Inductor M Discharge, flowing through the inductor M current i M Linear decrease, inductance Because of diodesD 1. Turn off, current i L1 Keeping constant, inductance current i L2 exist i M The capacitance remains unchanged under the influence of [the following]. C 1. Voltage across terminals v C1 It remains unchanged. In this mode, the equivalent circuit is as follows: Figure 15 As shown, the loop equation of the equivalent loop is: (16).

[0060] from t Starting at time 4, the power switching transistor S 1 and S The drive signal 2 simultaneously enters the next switching cycle. The operation of the DC-DC buck converter in the next switching cycle is exactly the same as in the previous cycle, which will not be described in detail here.

[0061] (2) Steady-state analysis: ① Pressure drop ratio: According to the duty cycle mentioned above α In 0.5≤ α The calculation method for the voltage drop ratio when it is less than 1 can be used to obtain the duty cycle similarly. α In 0< α When <0.5, the converter's buck ratio AMP for: (17).

[0062] ② Power switching transistor S 1 and S Soft-switching characteristics of 2: power switching transistors S 1 and S 2. During the conduction and turn-off processes, the flow through S 1 and S 2 current i S1 and i S2 waveform and S 1 and S 2. Voltage across the terminals v S1 and v S2 The waveform is as follows Figure 17 As shown. From Figure 17 It can be seen from this that: when S When 1 is turned on, S 1. Voltage across the terminals vS1 Reduced to 0, achieving zero-voltage start-up; when S When 1 is turned off, the flow through S 1 current i S1 Reduced to 0, achieving zero-current shutdown. Similarly, when S When 2 is on, S 2. Voltage across the terminals v S2 Reduced to 0, achieving zero-voltage start-up; when S 2. When shut off, the flow through S 2 current i S2 The current is reduced to 0, achieving zero-current shutdown. In summary, in the DC-DC buck converter proposed in this invention, the power switching transistor... S 1 and S 2. During their respective turn-on and turn-off processes, no additional auxiliary circuitry is required to achieve soft switching, effectively avoiding [the following issues]. S 1 and S 2. Switching losses during turn-on and turn-off improve converter efficiency.

[0063] Example 5: Verification of Soft Switching Characteristics During the turn-on and turn-off processes of power switches S1 and S2, the current i flowing through S1 and S2 is... S1 and i S2 The waveform and the voltage v across S1 and S2 S1 and v S2 The waveform is as follows Figure 11 and Figure 17 As shown. From Figure 11 and Figure 17 As can be seen from this: when S1 is turned on, the voltage v across S1 is... S1 The voltage drops to 0, achieving zero-voltage start-up; when S1 is turned off, the current i flowing through S1... S1 The voltage drops to 0, achieving zero-current turn-off. Similarly, when S2 is on, the voltage v across S2... S2 The voltage drops to 0, achieving zero-voltage startup; when S2 is turned off, the current i flowing through S2... S2 The current is reduced to 0, achieving zero-current shutdown. In summary, in the DC-DC buck converter proposed in this invention, power switches S1 and S2 can achieve soft switching without additional auxiliary circuitry during their respective turn-on and turn-off processes, effectively avoiding switching losses of S1 and S2 during turn-on and turn-off, and improving the converter efficiency.

[0064] Example 6: Simulation Verification To verify the feasibility and effectiveness of the high buck ratio DC-DC buck converter proposed in this invention, necessary experimental verifications were conducted on the converter in a simulation environment. The relevant parameter settings are as follows: [The following appears to be a list of parameters:] capacitors in the DC-DC buck converter. C 1 is 2.2μF, coupled inductor L 1 and L Both are 4.5mH, and the self-coupling coefficient is... k The output capacitor is 0.9. C o The load resistance is 4.7μF. R The Ω is 10Ω. The input voltage of the converter is 100V, and the duty cycle of the PWM drive signal is... α It is set to two cases: 0.6 and 0.4.

[0065] 1. When the duty cycle α When the value is set to 0.6, the relevant experimental waveforms are as follows: Figures 18-20 As shown.

[0066] In terms of dynamic response, Figure 18 This is the output voltage waveform of the DC-DC buck converter. Figure 18 As can be seen above, after a short-time dynamic adjustment control of 2ms, the DC-DC buck converter can quickly reach a steady-state output voltage, achieving the target requirement of rapid voltage reduction. During the dynamic adjustment control process, the output voltage waveform of the DC-DC buck converter is oscillating without any fluctuations, exhibiting good dynamic response performance.

[0067] In terms of steady-state output, Figure 19 This describes the output voltage ripple after the DC-DC buck converter has stabilized. Figure 19 As can be seen above, the output voltage range of the DC buck converter is 31.98~32.02V, and the voltage ripple is stably controlled within 0.02V, following the buck ratio law expressed by equation (12), while achieving accurate bucking and maintaining good steady-state response performance.

[0068] Regarding the implementation of soft switching, Figure 20 The image shows the power devices in a DC-DC buck converter. S 1 and S 2. Voltage across the terminals during their respective conduction and turn-off periods v S1 and v S2 With the current flowing through i S1 and i S2 The waveform diagram. From Figure 20 As can be seen, when S When 1 is turned on, S 1. Voltage across the terminals v S1Reduced to 0, achieving zero-voltage start-up; when S When 1 is turned off, the flow through S 1 current i S1 Reduced to 0, achieving zero-current shutdown. Similarly, when S When 2 is on, S 2. Voltage across the terminals v S2 Reduced to 0, achieving zero-voltage start-up; when S 2. When shut off, the flow through S 2 current i S2 The current is reduced to zero, achieving zero-current shutdown. In summary, the DC-DC buck converter proposed in this invention can achieve soft switching without the need for additional auxiliary circuit design, effectively avoiding switching losses of power devices during turn-on and turn-off, and improving the converter efficiency.

[0069] II. When the duty cycle α When the value is set to 0.4, the relevant experimental waveforms are as follows: Figures 21-23 As shown.

[0070] In terms of dynamic response, Figure 21 This is the output voltage waveform of the DC-DC buck converter. Figure 21 As can be seen above, after a short-time dynamic adjustment control of 2ms, the DC-DC buck converter can quickly reach a steady-state output voltage, achieving the target requirement of rapid voltage reduction. During the dynamic adjustment control process, the output voltage waveform of the DC-DC buck converter is oscillating without any fluctuations, exhibiting good dynamic response performance.

[0071] In terms of steady-state output, Figure 22 This describes the output voltage ripple after the DC-DC buck converter has stabilized. Figure 22 As can be seen above, the output voltage range of the DC buck converter is 17.99~18.01V, and the voltage ripple is stably controlled within 0.01V, following the buck ratio law expressed by equation (17), while achieving accurate bucking and maintaining good steady-state response performance.

[0072] Regarding the implementation of soft switching, Figure 23 The image shows the power devices in a DC-DC buck converter. S 1 and S 2. Voltage across the terminals during their respective conduction and turn-off periods v S1 and v S2 With the current flowing through i S1 and i S2 The waveform diagram. From Figure 23 As can be seen, when S When 1 is turned on,S 1. Voltage across the terminals v S1 Reduced to 0, achieving zero-voltage start-up; when S When 1 is turned off, the flow through S 1 current i S1 Reduced to 0, achieving zero-current shutdown. Similarly, when S When 2 is on, S 2. Voltage across the terminals v S2 Reduced to 0, achieving zero-voltage start-up; when S 2. When shut off, the flow through S 2 current i S2 The current is reduced to zero, achieving zero-current shutdown. In summary, the DC-DC buck converter proposed in this invention can achieve soft switching without the need for additional auxiliary circuit design, effectively avoiding switching losses of power devices during turn-on and turn-off, and improving the converter efficiency.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A high-step DC-DC converter with coupled inductor interleaved control, characterized in that, Including DC input power supply (V i ), First power switch (S1), Second power switch (S2), First diode (D1), Second diode (D2), Coupling inductor, Flying capacitor (C1), Output capacitor (C o and load resistance (R); The coupled inductor consists of a first inductor (L1) and a second inductor (L2), which are closely coupled and have the same winding direction; The drain of the first power switch (S1) is connected to the DC input power supply (V). i The positive terminal of the first power switch (S1) is connected to the source of the second power switch (S2) and one end of the flying capacitor (C1). The drain of the second power switch (S2) is connected to the source of the first power switch (S1), and the source of the second power switch (S2) is connected to the cathode of the second diode (D2) and one end of the second inductor (L2). The anode of the first diode (D1) is connected to the DC input power supply (V). i The cathode of the first diode (D1) is connected to one end of the first inductor (L1) and the other end of the flying capacitor (C1); The anode of the second diode (D2) is connected to the DC input power supply (V). i The negative terminal of the second diode (D2) is connected to the source of the second power switch (S2) and one end of the second inductor (L2). The other end of the first inductor (L1) and the other end of the second inductor (L2) are connected to the output capacitor (C). o The positive terminal of the resistor and one end of the load resistor (R); The output capacitor (C) o The negative terminal of the load resistor (R) is connected to the other end of the DC input power supply (V). i The negative electrode of ).

2. The coupled inductor interleaved control high-step-down DC-DC converter according to claim 1, characterized in that, The buck ratio AMP of the coupled inductor interleaved control high buck DC converter satisfies: When 0.5 ≤ α < 1, ; When 0 < α < 0.5, ; in, k The coupling coefficient is... ; , The self-inductance of the coupled inductor; The mutual inductance of the coupled inductors.

3. A control method for a high-step DC-DC converter with coupled inductor interleaving control as described in claim 1 or 2, characterized in that, Includes the following steps: Step S1, detect the input voltage (V) of the DC-DC converter. i ) and output voltage (V o ); Step S2: Calculate the required duty cycle α based on the target voltage drop ratio; Step S3: Determine the working range of the duty cycle α, wherein the working range of the duty cycle α includes: 0.5≤α<1 and 0<α<0.5; Step S4: Generate a first PWM signal and a second PWM signal, with a phase difference of 180° and a duty cycle of α. Step S5: Drive the first power switch transistor (S1) with the first PWM signal and drive the second power switch transistor (S2) with the second PWM signal. Step S6: Monitor the converter's operating status in real time and dynamically adjust the duty cycle α to maintain stable output.

4. The control method for a high-step DC-DC converter with coupled inductors interleaved control according to claim 3, characterized in that, Step S1 includes: Step S11: A high-precision resistor divider network is used to measure the input voltage (V). i ) and output voltage (V o Sampling is performed; Step S12: The sampled signal is isolated and amplified using an isolation operational amplifier; Step S13: Use an anti-aliasing filter to filter the amplified signal; Step S14: Convert the analog signal into a digital signal using an analog-to-digital converter; Step S15: A digital signal processor is used to perform digital filtering and calibration on the converted digital signal.

5. The control method for a high-step DC-DC converter with coupled inductor interleaving control according to claim 3, characterized in that, Step S2 includes: Step S201: Read the preset target output voltage V target ; Step S202, obtain the current input voltage V i The measured value; Step S203, calculate the target pressure drop ratio AMP target = V target / V i ; Step S204: Calculate the initial duty cycle α0 based on the correspondence between the step-down ratio and the duty cycle; Step S205: Limit the initial duty cycle to ensure it is within the effective range.

6. The control method for a high-step DC-DC converter with coupled inductors interleaved control according to claim 3, characterized in that, Step S3 includes: Step S301: Read the calculated duty cycle α; Step S302: Compare the duty cycle α with the threshold 0.5; Step S303: If α ≥ 0.5, then the working interval is determined to be 0.5≤α<1; Step S304: If α < 0.5, then the working interval is determined to be 0 < α < 0.

5.

7. The control method for a high-step DC-DC converter with coupled inductors interleaved control according to claim 3, characterized in that, Step S4 includes: Step S401: Determine the timing parameters of the PWM signal based on the duty cycle α and the working interval, wherein the timing parameters include the on-time and off-time; Step S402: Configure the timer period T and the compare register; Step S403: Set dead time to prevent pass-through. Step S404: Enable PWM output.

8. The control method for a high-step DC-DC converter with coupled inductors interleaved control according to claim 3, characterized in that, Step S5 includes: Step S501: Perform level conversion on the PWM signal; Step S502: Amplify the driving capability through the gate driving circuit; Step S503: Monitor drive current and voltage; Step S504: Implement overcurrent and overvoltage protection.

9. The control method for a high-step DC-DC converter with coupled inductors interleaved control according to claim 3, characterized in that, Step S6 includes: Step S601: Monitor the input current and output current; Step S602: Detect the temperature of the power device; Step S603: Analyze current ripple and voltage ripple; Step S604: Evaluate the converter efficiency.

10. The control method for a high-step DC-DC converter with coupled inductor interleaving control according to any one of claims 3-9, characterized in that, In step S4, when the duty cycle α is 0.5 ≤ α < 1, the converter has the following four operating modes within one switching cycle: Mode 11: The first power switch (S1) and the second power switch (S2) are turned on simultaneously; Mode 12: The first power switch (S1) is turned on, and the second power switch (S2) is turned off; Mode 13: The first power switch (S1) and the second power switch (S2) are turned on simultaneously; Mode 14: The first power switch (S1) is turned off, and the second power switch (S2) is turned on; When the duty cycle α is 0 < α < 0.5, the converter has the following four operating modes in one switching cycle: Mode 21: The first power switch (S1) is turned on, and the second power switch (S2) is turned off; Mode 22: The first power switch (S1) and the second power switch (S2) are turned off simultaneously; Mode 23: The first power switch (S1) is turned off, and the second power switch (S2) is turned on; Mode 24: The first power switch (S1) and the second power switch (S2) are turned off simultaneously.

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