Self-adaptive phase locking method, device, equipment and storage medium

Abstract

The invention discloses a self-adaptive phase locking method, device and equipment and a storage medium, and relates to the technical field of power systems. The method comprises the following steps: acquiring common coupling point voltage of a current power grid; outputting a phase-locked loop parameter by using a neural network according to the common coupling point voltage; and outputting the phase reference of the common coupling point through a phase-locked loop by using the phase-locked loop parameter. According to the technical scheme, the problem that the phase locking precision is reduced due to voltage distortion of the common coupling point is effectively solved, and the stability of a power system under broadband disturbance is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and in particular to an adaptive phase-locked loop method, apparatus, device, and storage medium. Background Technology

[0002] Traditional power systems are primarily based on synchronous generators, characterized by simple impedance characteristics and stable operation. In recent years, however, with the rapid development of new energy technologies such as wind and photovoltaic power generation, a large number of power electronic converters have been connected to the grid, forming new power systems with "high voltage and high efficiency" characteristics, and their impedance characteristics have changed accordingly. Compared to physical models based on theoretical derivations, impedance measured in real time can reflect the actual characteristics of the system at every moment, which is of great significance for system status monitoring and the formulation of early warning measures.

[0003] In traditional impedance measurement methods, the frequency sweep method injects sinusoidal disturbance signals at each frequency point and calculates the impedance based on the voltage and current response. However, injecting non-power frequency harmonics into the power grid can cause voltage distortion at the point of common coupling. Since the phase-locked loop (PLL) relies on the voltage at the point of common coupling to generate a synchronous phase reference, voltage distortion directly affects the accuracy of the PLL, thereby reducing system stability. Summary of the Invention

[0004] This invention provides an adaptive phase-locked loop method, apparatus, device, and storage medium to solve the problem of decreased phase-locked loop accuracy caused by voltage distortion at the common coupling point.

[0005] In a first aspect, the present invention provides an adaptive phase-locked loop method, comprising:

[0006] Obtain the voltage at the common coupling point of the current power grid;

[0007] The phase-locked loop parameters are output using a neural network based on the voltage at the common coupling point.

[0008] Using the phase-locked loop parameters, the phase reference of the common coupling point is output through the phase-locked loop.

[0009] In a second aspect, the present invention provides an adaptive phase-locked loop device, comprising:

[0010] The voltage acquisition module is used to acquire the voltage at the common coupling point of the current power grid;

[0011] A phase-locked loop parameter determination module is used to output phase-locked loop parameters based on the common coupling point voltage using a neural network;

[0012] The phase-locked loop (PLL) module is used to output the phase reference of the common coupling point through the PLL using the PLL parameters.

[0013] Thirdly, the present invention provides an electronic device comprising:

[0014] At least one processor;

[0015] and memory that is communicatively connected to at least one processor;

[0016] The memory stores a computer program that can be executed by at least one processor, which enables the at least one processor to perform the adaptive phase-locked method of the first aspect described above.

[0017] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a processor to execute the adaptive phase-locked method of the first aspect described above.

[0018] The adaptive phase-locked loop (PLL) scheme provided by this invention acquires the common coupling point (CCP) voltage of the current power grid, uses a neural network to output PLL parameters based on the CCP voltage, and uses these PLL parameters to output a phase reference for the CCP. By adopting the above technical solution, and through real-time acquisition of the CCP voltage and dynamic adjustment of the PLL parameters using a neural network, the problem of decreased PLL accuracy caused by CCP voltage distortion is effectively solved, significantly improving the stability of the power system under broadband disturbances.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of an adaptive phase-locked loop method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 This is a flowchart of an adaptive phase-locked loop method provided according to Embodiment 2 of the present invention;

[0023] Figure 3 This is a schematic diagram of an adaptive phase-locked loop device according to Embodiment 3 of the present invention;

[0024] Figure 4 This is a schematic diagram of the structure of an electronic device provided according to Embodiment 4 of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0027] Example 1

[0028] Figure 1 The flowchart of an adaptive phase-locked loop method is provided in Embodiment 1 of the present invention. This embodiment is applicable to the case of phase-locking using a phase-locked loop. The method can be executed by an adaptive phase-locked loop device, which can be implemented in hardware and / or software. The adaptive phase-locked loop device can be configured in an electronic device, which can be composed of two or more physical entities or a single physical entity.

[0029] like Figure 1 As shown, the adaptive phase-locked loop method provided in Embodiment 1 of the present invention specifically includes the following steps:

[0030] S101. Obtain the voltage of the common coupling point of the current power grid.

[0031] S102. Using a neural network, output phase-locked loop parameters based on the voltage at the common coupling point.

[0032] In this embodiment, the current grid's point of common coupling (PCC) voltage data can be acquired in real time. After PCC voltage distortion occurs, the neural network can calculate and output appropriate phase-locked loop (PLL) parameters based on the distorted PCC voltage. The neural network includes an input layer, hidden layers, and an output layer.

[0033] S103. Using the phase-locked loop parameters, output the phase reference of the common coupling point through the phase-locked loop.

[0034] In this embodiment, the phase-locked loop can output a phase reference for the common coupling point based on the phase-locked loop parameters.

[0035] The technical solution of this invention effectively solves the problem of decreased phase-locked loop accuracy caused by voltage distortion at the common coupling point by real-time acquisition of the voltage at the common coupling point and dynamically adjusting the phase-locked loop parameters using a neural network, thus significantly improving the stability of the power system under broadband disturbances.

[0036] Optionally, the step of using a neural network to output phase-locked loop parameters based on the common coupling point voltage includes: processing the q-axis voltage of the common coupling point using a neural network to output the change in phase-locked loop parameters.

[0037] Specifically, after voltage distortion occurs at the point of common coupling, the q-axis voltage at the point of common coupling will change. This q-axis voltage can be input into the neural network to obtain the change in the phase-locked loop parameters output by the neural network.

[0038] Optionally, before outputting the phase-locked loop (PLL) parameters based on the common coupling point voltage using a neural network, the method further includes: offline tuning of the initial PLL parameters using a first neural network to obtain the basic values ​​of the PLL parameters; wherein, outputting the PLL parameters based on the common coupling point voltage using a neural network includes: outputting the change in the PLL parameters based on the common coupling point voltage using a second neural network; wherein, outputting the phase reference of the common coupling point using the PLL parameters through the PLL includes: outputting the phase reference of the common coupling point through the PLL using the basic values ​​of the PLL parameters and the change in the PLL parameters.

[0039] Specifically, phase-locked loop (PLL) parameters under different operating conditions can be pre-collected to form a dataset, which is then preprocessed to generate training, validation, and test sets. Next, the (first) neural network is initialized, trained using the training set, and its hyperparameters are adjusted using the validation set. The generalization ability of the neural network is then evaluated using the test set. Finally, the trained neural network is used for offline tuning of the initial PLL parameters, which are those under normal operating conditions. By calculating the base values ​​and changes in the PLL parameters, updated PLL parameters for voltage distortion can be obtained. These updated parameters can then be used to establish a phase reference for the common coupling point of the PLL output. The first neural network differs from the second neural network.

[0040] Optionally, the adaptive phase-locked loop method described above can be applied to impedance measurements for islanding detection, weak characteristic fault detection, and / or oscillation prediction in power systems.

[0041] Example 2

[0042] Figure 2 The flowchart shows an adaptive phase-locked loop method provided in Embodiment 2 of the present invention. The technical solution of the present invention is further optimized based on the above optional technical solutions, and a specific method of using a phase-locked loop for phase locking is given.

[0043] Optionally, the step of using a neural network to process the q-axis voltage of the common coupling point to output the change in phase-locked loop parameters includes: when the q-axis voltage of the common coupling point is greater than a preset threshold, inputting the actual value of the q-axis voltage, the expected value of the q-axis voltage, and the error value of the common coupling point into the neural network to output the change in phase-locked loop parameters, wherein the error value is the deviation between the actual value of the q-axis voltage and the expected value of the q-axis voltage, and the change in phase-locked loop parameters includes the change in the proportional coefficient and the change in the integral coefficient of the phase-locked loop.

[0044] Optionally, the neural network includes a backpropagation (BP) neural network.

[0045] Optionally, the step of using the base value of the phase-locked loop parameters and the change in the phase-locked loop parameters to output the phase reference of the common coupling point through the phase-locked loop includes: determining the sum of the base value of the phase-locked loop parameters and the change in the phase-locked loop parameters as the phase-locked loop update parameters, and using the phase-locked loop to output the phase reference of the common coupling point based on the phase-locked loop update parameters and the voltage of the common coupling point.

[0046] like Figure 2 As shown, the adaptive phase-locked loop method provided in Embodiment 2 of the present invention specifically includes the following steps:

[0047] S201. Obtain the common coupling point voltage of the current power grid in impedance measurements for islanding detection, weak characteristic fault detection, and / or oscillation prediction in power systems.

[0048] S202. The initial phase-locked loop parameters are tuned offline using the first neural network to obtain the basic values ​​of the phase-locked loop parameters.

[0049] S203. When the q-axis voltage of the common coupling point is greater than a preset threshold, the actual value of the q-axis voltage, the expected value of the q-axis voltage, and the error value of the common coupling point are input into the BP neural network to output the change in phase-locked loop parameters. The error value is the deviation between the actual value of the q-axis voltage and the expected value of the q-axis voltage. The change in phase-locked loop parameters includes the change in the proportional coefficient and the change in the integral coefficient of the phase-locked loop.

[0050] Specifically, the main circuit of the inverter system includes the inverter bridge, filters, and the power grid. The control section is primarily based on current inner-loop control, and the phase-locked loop (PLL) module integrates an SRF-PLL (Synchronous Reference Frame Phase-Locked Loop) module, a BP (Back Propagation) neural network module, and a parameter optimization module. The BP neural network, inspired by biological nervous systems, is an artificial intelligence algorithm that simulates information transmission between neurons. It possesses powerful nonlinear fitting capabilities, mapping a given input to an output through nonlinear fitting, and then backpropagating based on the output to adjust the weights of each layer, gradually bringing the network's output value closer to the desired value. The BP neural network structure includes an input layer, hidden layers, and an output layer. Neurons in each layer are connected to neurons in the previous layer through a weight ω, forming a weight matrix. The neurons in the hidden layers play a dominant computational role.

[0051] SRF-PLL modules often use PI controllers. For different system operating conditions, the phase-locked loop (PLL) should have different PI parameters to support stable system operation. This method combines a backpropagation (BP) neural network with the SRF-PLL module. Utilizing the adaptive learning capability of the BP neural network, when system operating conditions change, the PLL parameters are adaptively adjusted through updates to the weight matrix to ensure stable system operation.

[0052] For example, the input to the BP neural network consists of three elements: the actual q-axis voltage at the common coupling point, the expected q-axis voltage, and the error value. The number of neurons in the hidden layer is set to n, and the output element is 2. The weight matrix from the input layer to the hidden layer can be set to Wi, the weight matrix from the hidden layer to the output layer to Wj, the activation function of the hidden layer to f1, and the activation function of the output layer to f2.

[0053] The input to a BP neural network is represented as:

[0054]

[0055] Where k represents the sampling time, This is the actual value of the q-axis voltage. Let e(k) be the expected value of the q-axis voltage, and e(k) be the error value. Since the controller sampling exhibits some fluctuation in practical applications, a threshold value can be set for the actual q-axis voltage. If |uq|> Then, the changes in the phase-locked loop parameters (i.e., the changes in the proportional coefficient ΔKp and the integral coefficient ΔKi) are output using a BP neural network. When 0 < | < If the actual value of the q-axis voltage is large, then the outputs ΔKp and ΔKi remain unchanged. Optionally, considering that when the actual value of the q-axis voltage is large, ΔKp and ΔKi should also be large to facilitate system stability, a positive correlation function F(uq) with the actual value of the q-axis voltage can be introduced as the coefficients of ΔKp and ΔKi to increase or decrease ΔKp and ΔKi, thereby further improving the calculation speed.

[0056] The output of the input layer is:

[0057]

[0058] Where i represents the i-th element of the input layer vector.

[0059] The input to the hidden layer activation function is:

[0060]

[0061] in, It is the input signal received by the j-th neuron in the hidden layer. These are the weights from the i-th neuron in the input layer to the j-th neuron in the hidden layer. The output of the hidden layer is:

[0062]

[0063] The input to the output layer activation function is:

[0064]

[0065] In the above formula, It is the input signal received by the p-th neuron in the output layer. These are the weights from the j-th neuron in the input layer to the p-th neuron in the hidden layer. The output of the output layer is:

[0066]

[0067] The output value of the BP neural network is:

[0068]

[0069] Based on this, a backpropagation path is set up to automatically update the weight matrix, making the BP neural network output close to the expected value, thus completing autonomous loop closure. The performance index function is defined as the mean squared error function:

[0070]

[0071] Based on the gradient descent principle, we find the weight matrix that minimizes E(k), i.e., whose gradient is 0. The gradient of E(k) with respect to the weights is as follows:

[0072]

[0073] because The calculation is difficult, so to simplify the operation, a symbolic function is used instead:

[0074]

[0075] Through mathematical derivation, the gradient of the mean squared error function can be obtained for each expression as follows:

[0076]

[0077] Let the learning rate be... The coefficient of inertia is The iterative weights are as follows:

[0078]

[0079] The same principle applies to updating the weight matrix from the input layer to the hidden layer.

[0080] S204. The sum of the base value of the phase-locked loop (PLL) parameters and the change in the PLL parameters is determined as the PLL update parameters. The PLL is then used to output the phase reference of the common coupling point based on the PLL update parameters and the voltage of the common coupling point.

[0081] Specifically, the sum of the base values ​​of the phase-locked loop (PLL) parameters and the changes in the PLL parameters is the updated PLL control parameters.

[0082] The adaptive phase-locked loop (PLL) method provided in this invention fully utilizes the powerful nonlinear fitting capability of BP neural networks, combining BP neural networks with traditional SRF-PLLs to construct a PLL structure with adaptively adjustable parameters. This method maintains fixed PLL parameters during steady-state operation of the converter, without introducing any additional disturbances. When system operating conditions change (voltage distortion at the point of common coupling), it optimizes controller parameters online in real time. This method achieves seamless switching between steady-state operation and dynamic adjustment, ensuring accurate PLL performance in steady state while significantly improving response speed and robustness during transient processes. It effectively solves the common problem of traditional PLLs, which struggle to balance steady-state accuracy and dynamic performance due to fixed parameters. This method has a clear structure, is easy to implement, and has significant engineering application value in impedance measurement and stability control of new power systems.

[0083] Example 3

[0084] Figure 3 This is a schematic diagram of an adaptive phase-locked loop device provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes: a voltage acquisition module 301, a phase-locked loop parameter determination module 302, and a phase-locked loop module 303, wherein:

[0085] The voltage acquisition module is used to acquire the voltage at the common coupling point of the current power grid;

[0086] A phase-locked loop parameter determination module is used to output phase-locked loop parameters based on the common coupling point voltage using a neural network;

[0087] The phase-locked loop (PLL) module is used to output the phase reference of the common coupling point through the PLL using the PLL parameters.

[0088] The adaptive phase-locked loop device provided in this invention effectively solves the problem of decreased phase-locked loop accuracy caused by voltage distortion at the common coupling point by real-time acquisition of the voltage at the common coupling point and dynamically adjusting the phase-locked loop parameters using a neural network, thus significantly improving the stability of the power system under broadband disturbances.

[0089] Optionally, the phase-locked loop parameter determination module is specifically used to process the q-axis voltage of the common coupling point using a neural network to output the change in phase-locked loop parameters.

[0090] Furthermore, the step of using a neural network to process the q-axis voltage of the common coupling point to output the change in phase-locked loop parameters includes: when the q-axis voltage of the common coupling point is greater than a preset threshold, inputting the actual value of the q-axis voltage, the expected value of the q-axis voltage, and the error value of the common coupling point into the neural network to output the change in phase-locked loop parameters, wherein the error value is the deviation between the actual value of the q-axis voltage and the expected value of the q-axis voltage, and the change in phase-locked loop parameters includes the change in the proportional coefficient and the change in the integral coefficient of the phase-locked loop.

[0091] Furthermore, the neural network includes a backpropagation (BP) neural network.

[0092] Optionally, the device may also include:

[0093] The offline tuning module is used to perform offline tuning of the initial phase-locked loop parameters using a first neural network before the phase-locked loop parameters are output based on the common coupling point voltage using a neural network, so as to obtain the basic values ​​of the phase-locked loop parameters.

[0094] Specifically, the phase-locked loop parameter determination module is used to output the change in phase-locked loop parameters based on the voltage at the common coupling point using a second neural network.

[0095] Specifically, the phase-locked loop (PLL) module is used to output the phase reference of the common coupling point through the PLL by utilizing the basic values ​​of the PLL parameters and the changes in the PLL parameters.

[0096] Furthermore, the step of using the base value of the phase-locked loop (PLL) parameters and the change in the PLL parameters to output the phase reference of the common coupling point through the PLL includes: determining the sum of the base value of the PLL parameters and the change in the PLL parameters as the PLL update parameters, and using the PLL to output the phase reference of the common coupling point based on the PLL update parameters and the voltage of the common coupling point.

[0097] Furthermore, the method is applied to impedance measurements for islanding detection, weak characteristic fault detection, and / or oscillation prediction in power systems.

[0098] The adaptive phase-locked device provided in the embodiments of the present invention can execute the adaptive phase-locked method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0099] Example 4

[0100] Figure 4A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0101] like Figure 4 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded from storage unit 48 into the RAM 43. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0102] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0103] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as adaptive phase-locked loop methods.

[0104] In some embodiments, the adaptive phase-locked method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the adaptive phase-locked method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to perform the adaptive phase-locked method by any other suitable means (e.g., by means of firmware).

[0105] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoC) systems, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0107] The computer equipment provided above can be used to execute the adaptive phase-locked loop method provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0108] Example 5

[0109] In the context of this invention, the computer-readable storage medium may be a tangible medium, and the computer-executable instructions, when executed by a computer processor, are used to perform an adaptive phase-locked method, the method comprising:

[0110] Obtain the voltage at the common coupling point of the current power grid;

[0111] The phase-locked loop parameters are output using a neural network based on the voltage at the common coupling point.

[0112] Using the phase-locked loop parameters, the phase reference of the common coupling point is output through the phase-locked loop.

[0113] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by, or in conjunction with, an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0114] The computer equipment provided above can be used to execute the adaptive phase-locked loop method provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0115] It is worth noting that in the above embodiments of the adaptive phase-locked loop device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0116] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An adaptive phase-locked loop method, characterized in that, include: Obtain the voltage at the common coupling point of the current power grid; The phase-locked loop parameters are output using a neural network based on the voltage at the common coupling point. Using the phase-locked loop parameters, the phase reference of the common coupling point is output through the phase-locked loop.

2. The method according to claim 1, characterized in that, The step of using a neural network to output phase-locked loop parameters based on the voltage at the common coupling point includes: The q-axis voltage at the common coupling point is processed using a neural network to output the change in phase-locked loop parameters.

3. The method according to claim 2, characterized in that, The process of using a neural network to process the q-axis voltage at the common coupling point to output the change in phase-locked loop parameters includes: When the q-axis voltage at the common coupling point is greater than a preset threshold, the actual value of the q-axis voltage, the expected value of the q-axis voltage, and the error value are input into the neural network to output the change in phase-locked loop parameters. The error value is the deviation between the actual value of the q-axis voltage and the expected value of the q-axis voltage. The change in phase-locked loop parameters includes the change in the proportional coefficient and the change in the integral coefficient of the phase-locked loop.

4. The method according to claim 3, characterized in that, The neural network includes a backpropagation (BP) neural network.

5. The method according to claim 1, characterized in that, Before using a neural network to output phase-locked loop parameters based on the common coupling point voltage, the method further includes: The initial phase-locked loop (PLL) parameters are tuned offline using the first neural network to obtain the basic values ​​of the PLL parameters; The step of using a neural network to output phase-locked loop parameters based on the voltage at the common coupling point includes: The second neural network is used to output the changes in phase-locked loop parameters based on the voltage at the common coupling point; The step of using the phase-locked loop parameters to output the phase reference of the common coupling point through the phase-locked loop includes: Using the base values ​​of the phase-locked loop (PLL) parameters and the changes in the PLL parameters, the phase reference of the common coupling point is output through the PLL.

6. The method according to claim 5, characterized in that, The step of using the base values ​​of the phase-locked loop (PLL) parameters and the changes in the PLL parameters to output the phase reference of the common coupling point through the PLL includes: The sum of the base value of the phase-locked loop (PLL) parameters and the change in the PLL parameters is determined as the PLL update parameters. The PLL then outputs the phase reference of the common coupling point based on the PLL update parameters and the voltage of the common coupling point.

7. The method according to claim 1, characterized in that, It is applied to impedance measurements for islanding detection, weak characteristic fault detection, and / or oscillation prediction in power systems.

8. An adaptive phase-locked loop device, characterized in that, include: The voltage acquisition module is used to acquire the voltage at the common coupling point of the current power grid; A phase-locked loop parameter determination module is used to output phase-locked loop parameters based on the common coupling point voltage using a neural network; The phase-locked loop (PLL) module is used to output the phase reference of the common coupling point through the PLL using the PLL parameters.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the adaptive phase-locked method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the adaptive phase-locked method according to any one of claims 1-7.

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