Core unit, high-performance frequency hopping carrier generator and frequency hopping transmitter

Abstract

The invention discloses a core unit, a high-performance frequency hopping carrier generator and a frequency hopping transmitter, and the core unit comprises a phase interpolator which is used for initializing a clock period signal with an adjustable phase, and the frequency of the clock period signal is the same as the frequency of a reference clock; the counter is used for outputting an integral multiple frequency hopping result of the reference clock; the delay adjusting module is used for adjusting the time sequence relation between the output of the phase interpolator and the output of the counter; the either-or selector is used for selecting the output of the counter; and the window selection module is used for selecting the required phase interpolator output according to the output of the counter.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit design technology, specifically relating to a core unit, a high-performance frequency-hopping carrier generator, and a frequency-hopping transmitter. Background Technology

[0002] Frequency hopping (FH) communication is a wireless communication method that transmits signals by rapidly switching carrier frequencies between multiple predetermined frequency points. This method allows signals to propagate in a time-division manner across different frequency channels, thereby avoiding energy concentration on a single frequency point and improving anti-interference capabilities and confidentiality to a certain extent. As the requirements for speed, stability, and reliability in wireless communication systems continue to increase, FH has been widely applied in various fields such as military communications, satellite communications, drone control, and industrial wireless networks.

[0003] In frequency hopping systems, the frequency hopping transmitter is a crucial component. It is responsible for digitally modulating, mixing, and amplifying the baseband signal to form a radio frequency signal that varies with the frequency sequence, and then transmitting it. The performance indicators of the frequency hopping transmitter directly determine the system's frequency hopping speed, signal quality, and overall reliability. Its main indicators include: (1) Frequency hopping rate refers to the number of frequency switching operations that can be completed per second, and is used to measure the frequency hopping speed of the transmitter. The higher the frequency hopping rate, the stronger the communication continuity and anti-interference capability of the system in complex interference environments.

[0004] (2) Frequency hopping bandwidth refers to the frequency range that the transmitter can cover, reflecting the frequency flexibility of the frequency hopping signal. The wider the frequency hopping bandwidth, the greater the communication flexibility and anti-interference capability.

[0005] (3) Frequency Hopping Sequence Support refers to the transmitter’s ability to support different frequency hopping sequences, covering multiple aspects such as sequence capacity, type and flexibility. The higher the support, the lower the probability of the system being predicted or interfered with.

[0006] (4) Frequency accuracy and stability refers to the ability of the carrier to maintain its frequency and phase after frequency hopping, and is used to evaluate signal synchronization. The higher the accuracy and stability, the better the synchronization of the frequency hopping signal and the better the communication reliability.

[0007] (5) Radio Frequency Output Quality refers to the power, spurious suppression, and spectral purity of the output signal, and is used to measure signal quality. The higher the output quality, the clearer the signal and the higher the spectral efficiency, while reducing interference to other channels.

[0008] However, as the modern communication environment becomes increasingly complex, existing transmitters have gradually revealed some shortcomings, including: (1) Insufficient frequency hopping rate: Performance: Frequency switching speeds are typically only at the microsecond or even millisecond level, making it difficult to support high-speed frequency hopping.

[0009] Cause: The local oscillator (LO) or frequency synthesizer of the existing transmitter has a long response time. The circuit design is based on the traditional phase-locked loop (PLL), and its frequency adjustment process involves locking and stabilization, which leads to switching delay.

[0010] (2) Poor frequency accuracy and phase stability: Problem: During frequency hopping, the carrier exhibits phase jitter and frequency shift, making it difficult to synchronize the frequency hopping signal.

[0011] Reason: The mixer is highly dependent on the local oscillator signal. When the local oscillator phase noise is large or the frequency stability is insufficient, the output RF signal will be distorted, which will directly affect the synchronization performance.

[0012] (3) Frequency hopping bandwidth is limited Performance: The frequency hopping range that can be covered is relatively narrow, which limits anti-interference and communication flexibility.

[0013] Reason: Existing frequency synthesis circuits and power amplifiers are often optimized within specific frequency bands, making it difficult to maintain good output power and spectral characteristics over a wide range, thus limiting bandwidth expansion.

[0014] (4) Limited sequence capacity and insufficient flexibility Performance: The number of supported frequency hopping sequences is limited, and most are limited to pseudo-random sequences, making it difficult to meet the needs of special applications.

[0015] Reason: Traditional frequency hopping controllers have fixed hardware implementations and lack flexible programming interfaces, making them unable to support complex or custom frequency hopping modes, which reduces the system's security and adaptability.

[0016] (5) Insufficient coordination between modulation and frequency hopping Manifestations: When high-speed digital modulation signals are combined with frequency-hopping signals, spectral leakage and signal distortion are likely to occur.

[0017] Cause: In the existing architecture, there is a lack of high-precision coordinated control between the digital modulator and the frequency synthesizer, which leads to discontinuity in the signal phase at the moment of frequency hopping switching, thereby affecting the integrity of the modulated signal.

[0018] (6) Limited RF output quality Characteristics: Fluctuations in output power, numerous stray components, and insufficient spectral purity.

[0019] Causes: Nonlinear distortion and local oscillator noise coupling introduced into the mixer and power amplifier structure lead to a decrease in signal purity; at the same time, untimely adjustment of circuit bias during rapid frequency switching can also introduce additional spurious signals.

[0020] In summary, existing frequency hopping transmitters mainly rely on the traditional combination of PLL-type frequency synthesizer + mixer + power amplifier in terms of structure. However, these devices have inherent limitations in terms of switching speed, phase stability, bandwidth coverage and coordinated control, which in turn restricts the performance improvement of frequency hopping systems. Summary of the Invention

[0021] Purpose of the invention: To address the shortcomings of existing frequency hopping transmitters, this invention provides a core unit, a high-performance frequency hopping carrier generator, and a frequency hopping transmitter.

[0022] Technical solution: In a first aspect, the present invention proposes a core unit, applied in a frequency hopping carrier generator, comprising: A phase interpolator is used for an initial phase-adjustable clock cycle signal, the frequency of which is the same as the reference clock frequency. A counter used to output the result of frequency hopping at integer multiples of the reference clock; The delay adjustment module is used to adjust the timing relationship between the output of the phase interpolator and the output of the counter; A 2-to-1 selector is used to select the output of the counter; The window selection module is used to select the desired phase interpolator output based on the counter output.

[0023] Furthermore, the input of the phase interpolator is connected to a four-phase clock and a 7-bit control code word fine_code<6:0>, wherein the clock with an initial phase of 0 in the four-phase clock is called the reference clock; the output of the phase interpolator is connected to the input of the delay adjustment module; the four-phase clock consists of four clock signals with initial phases of 0°, 90°, 180°, and 270° respectively. The delay adjustment module adds a delay to the output of the phase interpolator based on the externally given 6-bit input control word delay_trim<5:0>, and the output of the delay adjustment module is connected to the in input of the window selection module. The inputs of the counter include the first phase of the four-phase clock, the 7-bit control code word coarse_code<6:0>, and the counting control signal count_set; the outputs of the counter include the Fearly signal and the Flat signal, and the outputs of the counter are connected to the inputs of a 2-to-1 multiplexer. The output of the two-to-one selector is connected to the sel input of the window selection module; The output of the window selection module is the final output of the core unit.

[0024] Furthermore, the phase interpolator selects two adjacent phases for weighted interpolation of the input four-phase clock. By adjusting the weights of the two phases, it outputs a signal of any phase. The specific phase signal is selected for output based on the 7-bit control code word fine_code<6:0>. The final output of the phase interpolator is a clock cycle signal with different initial phases.

[0025] Furthermore, the 7-bit control codeword fine_code<6:0> divides one reference clock cycle into 128 parts. The 7-bit control codeword fine_code<6:0> = 000_0000 corresponds to a clock cycle signal with an initial phase of 0. Similarly, the initial phase corresponding to each codeword in the 7-bit control codeword fine_code<6:0> is: .

[0026] Furthermore, the delay adjustment module is composed of multiple buffers connected in series. Each buffer output is tapped and connected to the output port of the delay adjustment module. Each branch is controlled by a switch. A unique path is determined based on the 6-bit input control word delay_trim<5:0> to determine the delay.

[0027] Furthermore, the counter comprises a subtraction step ripple counter, a counter detection module, and a preset signal generation module; The subtraction step ripple counter is composed of seven asynchronously connected D flip-flops with set / reset functions connected in series, and its function is a subtraction counter; The counter detection module is used to output a pulse signal with a pulse width of one reference clock cycle based on the output of the subtraction step ripple counter, the counting control signal count_set, the first phase of the four-phase clock, and the 7-bit control codeword coarse_code<6:0>, and to control the Reload signal based on the counting control signal count_set and its own output pulse signal. When the count value of the subtraction step ripple counter decreases to 0, a pulse signal is output Fearly at the rising edge of the next reference clock with a pulse width of one reference clock cycle, and a pulse signal is output Flat at the falling edge of the next reference clock with a pulse width of one reference clock cycle. The Flat signal lags the Fearly signal by half a reference clock cycle. The Reload signal is high by default when the system is powered on / reset, and it toggles when it encounters the rising edge of the counting control signal count_set or the Flat signal. The preset signal generation module performs logical operations based on the 7-bit control codeword coarse_code<6:0> and the Reload signal to generate signals S<6:0> and R<6:0>, which serve as the set / reset signals for the D flip-flop inside the subtraction step ripple counter. The logical relationship is as follows: ; .

[0028] Furthermore, the two-to-one selector selects the output based on the mux_sel signal. If the mux_sel signal is 0, it outputs the Fearly signal; if the mux_sel signal is 1, it outputs the Flat signal. The mux_sel signal is determined by the 7-bit control code word fine_code<6:0>. If the 7-bit control code word fine_code<6:0> is less than X, the mux_sel signal is 0. If the 7-bit control code word fine_code<6:0> is greater than or equal to X, the mux_sel signal is 1. X is a user-defined 7-bit constant.

[0029] Furthermore, the window selection module includes a D flip-flop, with the in input serving as the clock signal CLK of the D flip-flop, the inverted signal of the sel input serving as the input signal of the D flip-flop, and then performing a OR operation between the output signal of the D flip-flop and the inverted signal of the in input.

[0030] Secondly, the present invention proposes a high-performance frequency-hopping carrier generator, which is composed of multiple cascaded core units; the core unit is the core unit described in any one of claims 1 to 8; The four-phase clock input and static trim codeword are shared by each core unit at each level; each core unit corresponds to a FIFO, the FIFO input is connected to a register, the control read signal is connected to the output of the corresponding core unit, and the FIFO output is connected to the dynamic codeword input of the corresponding core unit; the count_next output of each core unit is connected to the count control signal count_set input of the next core unit; the output of each core unit is connected to an OR gate input; the OR gate output is the final output, and count_next is the trigger signal of the next core unit.

[0031] Thirdly, the present invention proposes a frequency hopping transmitter, comprising: a digital baseband processor, a frequency hopping carrier generator, a mixer, and a power amplifier; The digital baseband processor is used to digitally modulate and shape the input signal, and output a digitally modulated signal; The frequency hopping carrier generator is a high-performance frequency hopping carrier generator as described in claim 9, used to generate radio frequency carriers; The mixer is used to mix the digital modulation signal output by the digital baseband processor and the radio frequency carrier output by the frequency hopping carrier generator to form a modulated radio frequency signal. The power amplifier is used to amplify the modulated radio frequency signal to the transmit power level.

[0032] Beneficial effects: Compared with the prior art, the present invention has the following advantages: (1) To address the slow response and large frequency hopping delay of traditional phase-locked loop (PLL) frequency synthesizers, where the frequency hopping speed cannot exceed f0 / 10 due to the need to maintain PLL stability, this invention employs a combination of a multi-mode counter (MMC) and a phase interpolator (PI) to generate the frequency hopping carrier. These components are responsible for the integer and fractional parts of the frequency hopping, respectively, significantly improving the frequency hopping rate and supporting frequency modulation operations at the highest clock frequency. If the clock frequency is f0, the frequency hopping speed can operate at f0. This increased frequency hopping speed greatly enhances the system's communication continuity and anti-interference capabilities in complex interference environments.

[0033] (2) In view of the problem that the phase noise of traditional frequency synthesizers is large, which makes it difficult to synchronize the frequency hopping signal, the present invention uses PI to realize the fractional part of the frequency hopping function. The phase noise and frequency modulation accuracy are both determined by PI, which significantly reduces the phase noise of the output, improves the frequency hopping accuracy, and improves the reliability of the transmitter system.

[0034] (3) To address the problem of limited bandwidth in traditional frequency synthesizers restricting the frequency hopping range, this invention uses MMC to implement the integer part of the frequency hopping function. The upper and lower limits of the frequency hopping range are determined by the number of bits in the counter, thus widening the frequency hopping range. It can cover a wider frequency range, improve anti-interference capabilities and communication flexibility.

[0035] (4) In view of the problem that traditional frequency synthesizers and frequency hopping controllers only support a limited number of pseudo-random sequences and lack customization capabilities, the PI and MMC used in this invention are both controlled by codewords, which makes the frequency hopping sequence customizable and programmable, thereby enhancing the capacity and flexibility of the frequency hopping sequence and improving the system security and adaptability.

[0036] (5) The high-performance frequency hopping carrier generator proposed in this invention focuses on the frequency synthesizer part. Through high-speed frequency switching, high-precision low-noise frequency hopping, wide frequency coverage and flexible sequence generation, it solves the shortcomings of traditional frequency hopping transmitters in terms of frequency hopping rate, frequency accuracy, frequency hopping bandwidth and sequence capacity, thereby improving the overall performance of the frequency hopping system. Attached Figure Description

[0037] Figure 1 The structure of the core module of the high-performance frequency hopping carrier generator; Figure 2 This describes the structure of the Counter submodule within the core module of the carrier generator; Figure 3 This is a time series diagram; where, Figure 3 (a) in the figure represents the timing relationship between the input signals of the carrier generator window selection module; Figure 3 (b) shows the timing relationship between the rising edge of the in signal and the sel signal under different fine_codes in the carrier generator window selection module; Figure 3 (c) in the figure shows the timing relationship between the rising edge of the Fearly signal and the Flat signal after the optimization scheme and the in signal under different fine_codes; Figure 4 The overall structure of a high-performance frequency-hopping carrier generator; Figure 5 This is the structure of one embodiment of a frequency hopping transmitter. Detailed Implementation

[0038] The technical solution of the present invention will now be further described in conjunction with the accompanying drawings and embodiments.

[0039] Example 1: The present invention provides a high-performance frequency-hopping carrier generator, which is composed of multiple cascaded core units; the core unit is the most important unit in the frequency-hopping carrier generator.

[0040] Figure 1 The diagram shows the core unit's structure, which mainly consists of two functional modules: a phase interpolator (PI) and a counter. The counter outputs the result of frequency hopping to an integer multiple of the reference clock, with a hopping range of f to f / 128, where f is the reference clock frequency. The PI provides an initial phase-adjustable clock signal with the same frequency as the reference clock and a phase accuracy of T / 128, where T is the reference clock period. The delay_trim module adjusts the timing relationship between the PI output and the counter output. A 2-to-1 selector (MUX) selects either the Counter output signal "Fearly" or "Flate" as its output. The window selection module (Sel) uses the processed Counter output to select the desired PI output. "Fearly" refers to a leading pulse signal, and "Flate" refers to a lagging pulse signal. Both "Fearly" and "Flate" are pulse signals with a pulse width of one reference clock period, with "Flate" lagging behind "Fearly" by one-quarter of a period.

[0041] In this embodiment of the invention, the input of the phase interpolator PI is connected to a four-phase clock (referring to four clock signals with initial phases of 0°, 90°, 180°, and 270°, i.e., phase difference of ¼). The clock consists of a clock cycle and a 7-bit control codeword fine_code<6:0>. The clock clk_ip with an initial phase of 0 is called the reference clock. The output of the phase interpolator PI is connected to the input of the delay adjustment module delay_trim. The delay adjustment module delay_trim adds a delay to the output of the phase interpolator PI based on the 6-bit input control word delay_trim<5:0>, and its output is connected to the in input of the window selection module Sel. The counter input is connected to the first phase clk_ip of the four-phase clock, the 7-bit control codeword coarse_code<6:0>, and the counting control signal count_set. The output signals Fearly and Flat are connected to a 2-to-1 selector (MUX). The output signal Fearly is also separately output as the count_next signal. The input of the 2-to-1 selector MUX is connected to the custom signal mux_sel, and the output of the 2-to-1 selector MUX is connected to the sel input of the window selection module Sel. The output of the window selection module Sel is the final output of the core unit.

[0042] The working principles of each module are as follows: The phase interpolator (PI) employs a high-speed IMPI (Integrating-Mode Phase Interpolator) structure. It takes a four-phase clock as input, selects two adjacent phases for weighted interpolation, and outputs a signal of arbitrary phase by adjusting the weights of the two phases. The specific phase output is selected based on the codeword configured by `fine_code<6:0>`. The final output is a clock cycle signal with different initial phases, but the frequency is the same as the reference clock frequency. `fine_code<6:0>` divides one reference clock cycle into 128 parts. `fine_code<6:0> = 000_0000` corresponds to a clock signal with an initial phase of 0°, and so on. The initial phase corresponding to each codeword is as follows:

[0043] The delay adjustment module delay_trim consists of multiple buffers connected in series. Each buffer output is tapped and connected to the delay adjustment module delay_trim output port. Each branch is controlled by a switch. The unique path is determined by the control code delay_trim<5:0> to determine the module delay.

[0044] The counter uses a programmable multi-mode counter (MMC) structure, such as... Figure 2 As shown, it consists of three modules: a subtraction step ripple counter, a counter detection module (End of Counter, EoC), and a preset signal generation module (SR Generator).

[0045] The Ripple Counter consists of seven asynchronously connected D flip-flops (DFFs) with set / reset functions, and functions as a down counter. When the Reload signal is 1, it sets the value; when the Reload signal is 0, it decrements the count by one on each rising edge of the reference clock, starting from the set value.

[0046] The EoC module has two functions: first, it outputs a pulse signal with a pulse width of one reference clock cycle based on the state of the Ripple Counter; second, it controls the Reload signal based on the input signal count_set and its own pulse output. Both functions are implemented using DFF as the core. When the Ripple Counter count value decreases to 0, a pulse signal is output Fearly at the rising edge of the next reference clock, with a pulse width of one reference clock cycle. At the falling edge of the next reference clock, a pulse signal is output Flat, also with a pulse width of one reference clock cycle. That is, the Flat signal lags the Fearly signal by half a reference clock cycle. The Reload signal is high by default when the system powers on / resets, and toggles when it encounters the rising edge of the count_set or Flat signal.

[0047] The SR Generator performs logical operations based on Cnum<6:0> and the Reload signal to generate signals S<6:0> and R<6:0>, which serve as the set / reset signals for the D flip-flops within the Ripple Counter. The logical relationship is as follows:

[0048]

[0049] A 2-to-1 multiplexer selects the output based on the `mux_sel` signal. If `mux_sel` is 0, the output is `Fearly`; if `mux_sel` is 1, the output is `Flate`. The `mux_sel` signal is determined by the control codeword `fine_code<6:0>`. If `fine_code<6:0>` is less than X, then `mux_sel` is 0; if `fine_code<6:0>` is greater than or equal to X, then `mux_sel` is 1. X is a user-defined 7-bit constant, written via a FIFO. The `mux_sel` generation logic can be implemented using a 7-bit comparator. In this invention, a 1-bit comparator is used to build 2-bit and 3-bit comparators, and then the two 2-bit comparators and one 3-bit comparator are cascaded to obtain a 7-bit comparator. Because only two states need to be judged: less than or greater than or equal to, the logic is simplified.

[0050] The window selection module Sel uses the input signal sel from the Counter to select the input signal in from the PI. Specifically, it selects one high-level pulse from a specific clock cycle signal by using a high-level signal within a reference clock cycle. This clock cycle signal has the same frequency as the reference clock frequency, and its initial phase is adjustable according to the control codeword with an accuracy of 1 / 128, where T is the reference clock cycle. The window selection module Sel uses the DFF as its core. The input signal in serves as the clock signal CLK of the DFF, and the inverted signal of the input signal sel serves as the input signal D of the DFF. The desired function is achieved by performing a NOR operation between the output signal of the DFF and the inverted signal of the input signal in.

[0051] When implementing the Sel function of the window selection module, note that the input signal in is a clock signal with a period of T (T is the reference clock period), and its initial phase is adjustable from 0° to 360° with an accuracy of 1 / 128. The Fearly signal is a high-level pulse signal with a pulse width of T. Their timing relationship is as follows: Figure 3 As shown in (a) above. The sel signal is used to select the in signal. Even if the high-level range of the sel signal frames the high-level range of the in signal, when implementing with DFF logic, it is only necessary to ensure that the rising edge of the in signal is within the high-level range of the sel signal. Therefore, only the timing relationship between the rising edge of the in signal and the high-level range of the sel signal needs to be considered. Note that the initial phase of the in signal is adjustable from 0° to 360°, and it must be ensured that the rising edge at any initial phase is within the high-level range of the sel signal. If the sel signal is generated only by the Fearly signal, when the initial phase of the in signal is close to the extreme values ​​of 0° or 360°, i.e., when the value of fine_code<6:0> is close to 0 or 127, the rising edge of the in signal will be very close to the edge of the high-level range of the sel signal, or even coincide with it, as shown below. Figure 3 As shown in (b) above. Considering the setup and hold times of the DFF itself, in these extreme cases, the DFF cannot be flipped, and the Sel selection function of the window selection module cannot be implemented.

[0052] Therefore, in extreme cases, the high level of sel needs to be broadened, but the high level range cannot simultaneously cover two adjacent rising edges. The approach taken in this invention is to output a Flat signal of the same pulse width on the next falling edge after the Fearly rising edge. After appropriate delay_trim, the following can be obtained: Figure 3As shown in (c) therein, the timing relationship between the in signal and Fearly and Flate for different fine_code values. At this time, it can be selected that when fine_code < X, the sel signal is Fearly; when fine_code ≥ X, the sel signal is Flate. The value of X should be such that when fine_code = X, the corresponding rising edge is within the overlapping area of Fearly and Flate, and specific values can be customized within this range.

[0053] The working process of a core unit is as follows: In the reset state, the Reload signal is always 1, and the Ripple Counter always reads the configuration codeword coarse_code<6:0>, that is, the count value of the Ripple Counter is always coarse_code<6:0>.

[0054] When the count_set signal is received as 1, the Reload signal is set to 0 and invalidated, and the Ripple Counter starts to perform subtraction counting.

[0055] When the Ripple Counter subtracts to 0, Fearly jumps to 1 at the next rising edge of the reference clock, and then jumps back to 0 at the next rising edge. Flate is delayed by half a cycle and makes the same jump with the falling edge as the reference.

[0056] PI output is selected by comprehensively considering Flate and Fearly.

[0057] The rising edge of Flate resets the Reload signal to 1, and Fearly is output as count_next.

[0058] Embodiment 2: Taking the cascading of 4 core units as an example, as Figure 4 shown. The four-phase clock inputs and static trim codewords of each level of core unit are shared; each level of core corresponds to a FIFO. The FIFO input is connected to a register, the control read signal is connected to the core_output output of the corresponding core module, and the FIFO output is connected to the dynamic codeword input of the corresponding core; the count_next output of each level of core is connected to the count_set input of the next level of core; the core_output outputs of each level of core are all connected to the input of an OR gate; the output of the OR gate is the final output. count_next is the name of an internal signal and is used as the trigger signal for the next level of core unit.

[0059] Referring to the core module workflow mentioned in Example 1, note that after power-on / reset, the Reload signal inside each core unit is 1, the Ripple Counter is in the preset state and does not perform counting, and each core unit has no output. Therefore, it is necessary to... <0> Add a startup function, that is, core reset <0> The internal Reload signal is set to 1, and the Reload signal is set to 0 after de-reset.

[0060] The workflow of a frequency-hopping carrier generator is as follows: After power-on / reset, all modules of the circuit are in the reset state, the Reload signal of each stage is set to 1, and the output is set to 0; After resetting, core <0> When the Reload signal is set to 0, counting begins. Based on the initial reset codeword, core_output (denoted as cout0) and count_next (denoted as count_next0) are output. cout0 is used as a control signal to make the FIFO <0> Read configuration to core <0> The first set of dynamic codewords, while count_next0 controls the core. <1> Start working; This process continues until all core modules have completed their output based on the initial reset codeword.

[0061] The count_next of the last-level core is passed back to the core. <0> The count_set makes core <0> Based on the output of the first set of configuration codewords, the frequency hopping carrier generator officially begins to work.

[0062] As can be seen, if there are N cascaded cores, the first N pulse signals of the final output are the outputs of each core according to the reset codeword. From the (N+1)th pulse onwards, the outputs of each core according to the configuration codeword are generated. The core_output of each core causes the corresponding FIFO to read the next set of configuration codewords and starts the next core to work, thus the entire frequency-hopping carrier generator operates cyclically. This cyclic structure also implements a frequency reduction function, reducing the operating frequency of the codewords that originally needed to switch at the reference clock frequency to one-Nth, greatly alleviating timing pressure.

[0063] The final output signal is actually a combination of multiple pulse signals with a pulse width of T / 2 (T is the reference clock period), and the interval between adjacent pulses is determined by the core. and core<i+1> The module's corresponding dynamic codeword determines its adjustable range from T to 128T, with a precision of T / 128. This frequency-hopping carrier generator supports a reference clock input of 3.2GHz to 9GHz, thus enabling frequency hopping of signals within the range of 25MHz to 9GHz. Because the output of each core module can be configured independently, frequency hopping can be performed in each output cycle, meaning the maximum frequency hopping rate is 9GHz.

[0064] The high performance of the high-performance frequency-hopping carrier generator proposed in this embodiment is reflected in the following aspects: High frequency hopping rate: This invention can support frequency hopping up to 9GHz, which enhances the system's communication continuity and anti-interference capability in complex interference environments.

[0065] High frequency hopping resolution: The frequency hopping resolution of this invention is expressed in terms of period, and the period resolution can reach [missing information]. .

[0066] Wide frequency hopping range: The frequency hopping range of this invention is... This improves anti-interference capabilities and communication flexibility.

[0067] Flexible frequency hopping sequence: The frequency hopping sequence in this invention can be customized and programmed, which is highly flexible and can be dynamically adjusted, thus improving the system's security and adaptability.

[0068] Example 3: This embodiment proposes a frequency-hopping transmitter, such as... Figure 5 As shown, it mainly includes the following modules: A digital baseband processor is used to digitally modulate (such as FSK, QPSK, etc.) and shape the input signal; it outputs a digitally modulated signal for processing by the next stage frequency synthesizer.

[0069] The high-performance frequency hopping carrier generator (HP-FHCG) uses 16 cascaded cores to reduce PI switching pressure; it provides high-frequency adjustable carrier output, frequency switching can reach the picosecond level, with low phase noise and customizable frequency hopping sequence.

[0070] A mixer is used to mix a digital modulated signal with an RF carrier generated by HP-FHCG to form a modulated RF signal. Through optimized circuit design, low spurious emissions and low phase noise RF output can be achieved.

[0071] A power amplifier (PA) is used to amplify the mixed radio frequency signal to the transmit power level while maintaining the purity of the signal spectrum.

[0072] The frequency-hopping transmitter proposed in this embodiment has the following functions and advantages: High-speed frequency hopping: Frequency switching can be completed in picoseconds according to the frequency hopping sequence, significantly improving the transmitter's frequency hopping rate.

[0073] High frequency accuracy and stability: low phase noise, stable carrier frequency, ensuring synchronization of frequency hopping signals and communication reliability.

[0074] Compatible with multiple modulation methods: Supports high-speed digital modulation signals, avoiding spectrum leakage and modulation distortion.

[0075] Sequence flexibility: Supports custom programming sequences, enhancing anti-interference capabilities and security.

[0076] Wideband output: The output frequency covers a wideband frequency hopping range, which improves the bandwidth limitation problem.

[0077] The frequency hopping transmitter (FHTransmitter) provided in this embodiment uses a high-performance frequency hopping carrier generator (HP-FHCG) in its frequency synthesis section to quickly and accurately generate hopping high-frequency carrier signals, thereby significantly improving the transmitter's frequency hopping rate, frequency accuracy, and RF output quality.

[0078] Example 4: This embodiment uses HP-FHCG as the core frequency synthesis module of the transmitter, replacing the traditional PLL+VCO structure, thereby improving the frequency switching speed and accuracy. The frequency hopping controller and frequency synthesizer are integrated into one module, providing a control codeword input interface. The custom frequency hopping sequence makes the frequency hopping function highly flexible and dynamically adjustable. Benefiting from the low phase noise and high frequency accuracy of PI, the transmitter's RF signal output is stable, the spectrum is clear, and the overall performance of the frequency hopping system is improved.

Claims

1. A core unit used in a frequency hopping carrier generator, characterized in that: include: A phase interpolator is used for an initial phase-adjustable clock cycle signal, the frequency of which is the same as the reference clock frequency. A counter used to output the result of frequency hopping at integer multiples of the reference clock; The delay adjustment module is used to adjust the timing relationship between the output of the phase interpolator and the output of the counter; A 2-to-1 selector is used to select the output of the counter; The window selection module is used to select the desired phase interpolator output based on the counter output.

2. A core unit according to claim 1, characterized in that: The input of the phase interpolator is connected to a four-phase clock and a 7-bit control code word fine_code<6:0>, wherein the clock with an initial phase of 0 in the four-phase clock is called the reference clock; the output of the phase interpolator is connected to the input of the delay adjustment module; the four-phase clock consists of four clock signals with initial phases of 0°, 90°, 180°, and 270° respectively. The delay adjustment module adds a delay to the output of the phase interpolator based on the externally given 6-bit input control word delay_trim<5:0>, and the output of the delay adjustment module is connected to the in input of the window selection module. The inputs of the counter include the first phase of the four-phase clock, the 7-bit control code word coarse_code<6:0>, and the counting control signal count_set; the outputs of the counter include the Fearly signal and the Flat signal, and the outputs of the counter are connected to the inputs of a 2-to-1 multiplexer. The output of the two-to-one selector is connected to the sel input of the window selection module; The output of the window selection module is the final output of the core unit.

3. A core unit according to claim 2, characterized in that: The phase interpolator selects two adjacent phases from the input four-phase clock and performs weighted interpolation. By adjusting the weights of the two phases, it outputs a signal of any phase. The specific phase signal is selected for output based on the 7-bit control code word fine_code<6:0>. The final output of the phase interpolator is a clock cycle signal with different initial phases.

4. A core unit according to claim 3, characterized in that: The 7-bit control codeword fine_code<6:0> divides one reference clock cycle into 128 parts. The 7-bit control codeword fine_code<6:0> = 000_0000 corresponds to a clock cycle signal with an initial phase of 0. Similarly, the initial phase corresponding to each codeword in the 7-bit control codeword fine_code<6:0> is: 。 5. A core unit according to claim 2, characterized in that: The delay adjustment module consists of multiple buffers connected in series. Each buffer output is tapped and connected to the output port of the delay adjustment module. Each branch is controlled by a switch. A unique path is determined based on the 6-bit input control word delay_trim<5:0> to determine the delay.

6. A core unit according to claim 2, characterized in that: The counter comprises a subtraction step ripple counter, a counter detection module, and a preset signal generation module; The subtraction step ripple counter is composed of seven asynchronously connected D flip-flops with set / reset functions connected in series, and its function is a subtraction counter; The counter detection module is used to output a pulse signal with a pulse width of one reference clock cycle based on the output of the subtraction step ripple counter, the counting control signal count_set, the first phase of the four-phase clock, and the 7-bit control codeword coarse_code<6:0>, and to control the Reload signal based on the counting control signal count_set and its own output pulse signal. When the count value of the subtraction step ripple counter decreases to 0, a pulse signal is output Fearly at the rising edge of the next reference clock with a pulse width of one reference clock cycle, and a pulse signal is output Flat at the falling edge of the next reference clock with a pulse width of one reference clock cycle. The Flat signal lags the Fearly signal by half a reference clock cycle. The Reload signal is high by default when the system is powered on / reset, and it toggles when it encounters the rising edge of the counting control signal count_set or the Flat signal. The preset signal generation module performs logical operations based on the 7-bit control codeword coarse_code<6:0> and the Reload signal to generate signals S<6:0> and R<6:0>, which serve as the set / reset signals for the D flip-flop inside the subtraction step ripple counter. The logical relationship is as follows: ； 。 7. A core unit according to claim 2, characterized in that: The two-to-one selector selects the output based on the mux_sel signal. If the mux_sel signal is 0, it outputs the Fearly signal; if the mux_sel signal is 1, it outputs the Flat signal. The mux_sel signal is determined by the 7-bit control code word fine_code<6:0>. If the 7-bit control code word fine_code<6:0> is less than X, the mux_sel signal is 0. If the 7-bit control code word fine_code<6:0> is greater than or equal to X, the mux_sel signal is 1. X is a user-defined 7-bit constant.

8. A core unit according to claim 1, characterized in that: The window selection module includes a D flip-flop, with the in input serving as the clock signal CLK of the D flip-flop, and the inverted signal of the sel input serving as the input signal of the D flip-flop. The output signal of the D flip-flop is then ORed with the inverted signal of the in input.

9. A high-performance frequency-hopping carrier generator, characterized in that: It is composed of multiple cascaded core units; the core unit is a core unit as described in any one of claims 1 to 8; The four-phase clock input and static trim codeword are shared by each core unit at each level; each core unit corresponds to a FIFO, the FIFO input is connected to a register, the control read signal is connected to the output of the corresponding core unit, and the FIFO output is connected to the dynamic codeword input of the corresponding core unit; the count_next output of each core unit is connected to the count control signal count_set input of the next core unit; the output of each core unit is connected to an OR gate input; the OR gate output is the final output, and count_next is the trigger signal of the next core unit.

10. A frequency-hopping transmitter, characterized in that: include: Digital baseband processor, frequency hopping carrier generator, mixer, and power amplifier; The digital baseband processor is used to digitally modulate and shape the input signal, and output a digitally modulated signal; The frequency hopping carrier generator is a high-performance frequency hopping carrier generator as described in claim 9, used to generate radio frequency carriers; The mixer is used to mix the digital modulation signal output by the digital baseband processor and the radio frequency carrier output by the frequency hopping carrier generator to form a modulated radio frequency signal. The power amplifier is used to amplify the modulated radio frequency signal to the transmit power level.

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