Multi-channel single-line return-to-zero code parallel control method and system and computer readable storage medium

Abstract

The invention discloses a multi-channel single-line return-to-zero code parallel control method and system and a computer readable storage medium, the method is realized based on a multi-path serial interface with N parallel data lines, N is an integer greater than 1, and the method comprises the following steps: for each path in N paths of independent binary logic data streams, N is an integer greater than 1, and N is an integer greater than 1; converting each individual bit in the data stream into a bit group which corresponds to the individual bit and consists of a plurality of bits, thereby forming N paths of coded data streams; the method comprises the following steps of: iteratively and synchronously extracting a bit from each path in N paths of coded data streams, and combining the extracted N bits into a bit unit to generate a single sending data stream; and providing the single transmission data stream to a multi-path serial interface, and outputting the single transmission data stream to N data lines in parallel by the multi-path serial interface so as to synchronously drive the N-path single-line return-to-zero code equipment. According to the method, parallel control can be efficiently and reliably performed on the multi-channel single-line return-to-zero code equipment.

Description

Technical Field

[0001] This invention relates to the field of multi-channel single-line return-to-zero code parallel control technology, specifically to a multi-channel single-line return-to-zero code parallel control method, system, and computer-readable storage medium. Background Technology

[0002] Single-wire return-to-zero (SZ) communication protocols are widely used in distributed electronic devices such as programmable light-emitting diode (LED) light strips and digital sensors because they require only a single data line to complete data transmission. In practical applications, to achieve complex dynamic display effects or to perform multi-point synchronous data acquisition, it is often necessary for a main controller to independently control multiple channels of such devices simultaneously.

[0003] In existing technologies, there are several methods for controlling multi-channel single-wire return-to-zero (RZ) code devices. One common method is to use the general-purpose input / output (GPIO) pins of the main controller to directly simulate the timing of each single-wire RZ code signal through software programming. However, when using this method, the generated signal timing is susceptible to significant jitter, which can lead to data transmission errors, causing the device to display an incorrect status or flicker. Another existing method is to use a standard serial communication interface to drive multi-channel devices in a serial cascade manner. A significant drawback of this method is that as the number of devices or channels increases, the time required to complete a single status update for all devices becomes excessively long. This results in a low overall refresh rate, causing dynamic visual effects to appear choppy or delayed.

[0004] Therefore, there is still a technical problem in the existing technology of how to efficiently and reliably perform parallel control of multi-channel single-line return-to-zero code devices. Summary of the Invention

[0005] The purpose of this invention is to overcome the aforementioned defects or problems in the prior art and to provide a multi-channel single-line return-to-zero code parallel control method, system, and computer-readable storage medium. This method can efficiently and reliably perform parallel control of multi-channel single-line return-to-zero code devices.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: Technical Solution 1: A multi-channel single-line return-to-zero code parallel control method, which is implemented based on a multi-channel serial interface with N parallel data lines, where N is an integer greater than 1. The method includes: for each of the N independent binary logic data streams, converting each individual bit in the data stream into a corresponding bit group consisting of multiple bits, thereby forming N encoded data streams; iteratively extracting one bit synchronously from each of the N encoded data streams and combining the extracted N bits into a bit unit to generate a single transmission data stream; and providing the single transmission data stream to the multi-channel serial interface, which then outputs the single transmission data stream in parallel to the N data lines to synchronously drive the N single-line return-to-zero code devices. Technical Solution 2, based on Technical Solution 1: The multi-channel serial interface is a four-channel serial peripheral interface, where N is 4. Technical Solution 3 based on Technical Solution 2: The step of converting each individual bit into a corresponding bit group consisting of multiple bits includes: converting binary logic "0" into a first bit group 1000 consisting of four bits; and converting binary logic "1" into a second bit group 1110 consisting of four bits. Technical Solution 4 based on Technical Solution 3: The operating clock frequency of the four serial peripheral interfaces is configured to be in the range of 3 MHz to 4 MHz. Technical Solution 5 based on Technical Solution 1: The step of providing the single transmit data stream to the multiplex serial interface is executed by a direct memory access controller; the direct memory access controller is configured to automatically transfer the single transmit data stream from a memory region to the multiplex serial interface. Technical Solution Six based on Technical Solution Five: The direct memory access controller operates in chained descriptor mode to sequentially and continuously transmit multiple non-contiguous data blocks in the memory region to the multiplexed serial interface. Technical solution seven based on technical solution one: the step of outputting to the N data lines in parallel generates N signal streams on the N data lines, wherein the N signal streams are clock-synchronized with each other, and the data content contained in each of the N signal streams is independent of each other. Furthermore, the present invention also provides technical solution eight: a multi-channel single-line return-to-zero code parallel control system, comprising: a multi-channel serial interface having N parallel data output lines, wherein N is an integer greater than 1; a processor communicatively coupled to the multi-channel serial interface; and a memory storing computer-executable instructions, wherein when the instructions are executed by the processor, the system performs the multi-channel single-line return-to-zero code parallel control method as described in any one of technical solutions one to seven. Technical Solution Nine based on Technical Solution Eight: The multi-channel serial interface is a four-channel serial peripheral interface, where N is 4; the system also includes four single-line return-to-zero code devices; wherein, each of the four data output lines of the four-channel serial peripheral interface is physically connected to the data input terminal of a corresponding device among the four single-line return-to-zero code devices. In addition, the present invention provides a tenth technical solution: a computer-readable storage medium storing computer program instructions, wherein the instructions, when executed by a processor, control the device where the computer-readable storage medium is located to execute the multi-channel single-line return-to-zero code parallel control method as described in any one of technical solutions one to seven. As can be seen from the above description of the present invention, compared with the prior art, the present invention has the following beneficial effects: Technical Solution 1 provides a multi-channel single-line return-to-zero code parallel control method, which improves the technical contradiction in the prior art of balancing parallel throughput, timing control accuracy and system resource consumption when controlling multi-channel single-line return-to-zero code devices.

[0007] In existing technologies, the timing jitter problem stems from the fact that the processor's execution flow is not continuous and focused. The processor needs to respond to interrupt requests from other parts of the system. These interrupts pause the current timing simulation task to execute higher-priority code, returning only after the interrupt service is complete. The time delay introduced by this task switching is uncertain, leading to random deviations in signal pulse width, i.e., timing jitter. This solution first converts logic bits into bit groups composed of multiple bits, then outputs them in parallel through a multiplexed serial interface. Specifically, the multiplexed serial interface is driven by a stable, independent hardware clock source, and the timing of its output signals depends entirely on the physical characteristics of this clock source, unaffected by processor interrupts. The aforementioned conversion steps pre-construct a structured bit sequence at the software level. When this sequence is output at a fixed rate by the hardware clock, it can accurately reproduce the waveform with a specific pulse width as defined by the single-wire return-to-zero code protocol at the physical level. Therefore, this collaborative mechanism of software-defined waveform structure and hardware-guaranteed time base utilizes the natural principle of high precision and high stability of hardware clock signals to transfer the task of timing generation from the interference-prone software execution level to the stable and reliable hardware physical level, thus enabling the generation of control signals with extremely low timing jitter.

[0008] Furthermore, the low refresh rate of existing technologies using cascaded standard serial interfaces is due to the serial nature of data transmission. In this mode, data from all channels must be arranged in a single long queue and transmitted sequentially on a single data channel, with the total transmission time being the sum of the transmission times of all channels. This solution iteratively extracts bits synchronously from N encoded data streams and combines them into bit units to generate a single transmit data stream, which is then output in parallel to N data lines by a multi-channel serial interface. Specifically, the multi-channel serial interface physically has N data lines capable of simultaneous data output. The aforementioned mapping step is essentially a data reassembly algorithm. This algorithm deeply utilizes the inherent hardware working principle of the multi-channel serial interface, which splits a single input data stream into N parallel lines. By performing a specific, reverse interleaving operation on the N independent data streams in advance at the software level, the output result of this interleaved single data stream on the N physical data lines after being split by the interface hardware is exactly the original N independent data streams. This collaborative mechanism, where software performs data spatial rearrangement and hardware performs parallel physical distribution, changes the original purpose of the multi-channel serial interface, transforming it from a transmission acceleration tool for a single device into a parallel controller for multiple independent devices. Because data is transmitted simultaneously on N lines, the theoretical data throughput is increased to N times that of a single-channel serial interface. This significantly shortens the total transmission time of a single frame of data and improves the refresh rate when driving the same number of devices.

[0009] This solution uses a specific software algorithm that is deeply coupled with the underlying working principle of the multi-channel serial interface hardware to enable a standard hardware interface to implement a brand-new system-level function. With a unified architecture, it overcomes the technical challenges of timing accuracy and parallel bandwidth, which usually require different solutions in existing technologies. This provides an efficient and reliable solution for the parallel control of multi-channel single-line return-to-zero code devices.

[0010] In technical solution two, the multi-channel serial interface is specifically defined as a four-channel serial peripheral interface, namely QSPI. As a standardized hardware component, the physical characteristics and operating protocol of a four-channel serial peripheral interface are well-defined. Therefore, this technical solution can directly utilize existing, mature hardware resources without the need to design dedicated interface circuits, thereby reducing the complexity and hardware cost of implementing this method. In technical solution three, logic 0 and logic 1 are defined as specific bit groups 1000 and 1110, respectively, consisting of four bits. These two bit groups are coordinated with the operating clock frequency of the hardware interface to reproduce, at the physical level, the precise time intervals required by a widely used single-line return-to-zero code protocol with a data rate of 800 kHz. In technical solution four, the operating clock frequency of the four serial peripheral interfaces is configured within a specific range of 3 to 4 MHz. When bit group 1000 or 1110 is output at a clock frequency of 3.2 MHz, the duration of each bit is fixed. The duration of the physical level formed by the output of these four bit sequences precisely matches the pulse width specified by the aforementioned 800 kHz single-line return-to-zero code protocol. Therefore, this clock frequency configuration ensures that the generated signal can be correctly recognized and decoded by the target device.

[0011] In technical solution five, a direct memory access controller (DMI) is introduced to perform the data stream provisioning step, solving the problem of excessive processor resource consumption that may occur when implementing the method of this invention. The aforementioned conversion and mapping steps require the processor to perform calculations to generate a single data stream, which consumes a certain number of processor cycles. If subsequent data transmission tasks are still performed by the processor, the processor will be tied to repetitive data handling work for a long time, thus unable to efficiently execute other application tasks. A DMI is a hardware unit specifically designed for autonomous data transfer between peripherals and memory. By having this controller perform data transfer, the processor's task is limited to the data generation phase. Once data generation is complete, the processor can activate the DMI and switch to executing other tasks. This division of labor and coordination mechanism, where the processor is responsible for data generation and the DMI is responsible for data transmission, decouples computational tasks from I / O tasks, significantly reducing the processor's continuous load and improving the parallel processing capability and response speed of the entire system. In technical solution six, the direct memory access controller's operating mode is limited to linked descriptor mode, solving the problem of low memory management efficiency when processing complex or dynamic data. In applications such as generating dynamic visual effects, the data constituting a complete frame may be stored in multiple physically non-contiguous data blocks in memory. If the standard direct memory access mode is used, the processor must first perform an additional memory copy operation to concatenate these scattered data blocks into a physically contiguous large data block before initiating transmission. This process introduces additional processing latency and memory overhead. Linked descriptor mode is a hardware feature of the direct memory access controller that allows the controller to autonomously read data from multiple non-contiguous memory addresses according to a preset descriptor linked list and form a seamless data stream at the output. Utilizing this hardware feature, the need for the processor to perform memory concatenation is eliminated, achieving zero-copy data transmission, thereby further reducing processing latency and improving the system's efficiency when processing dynamic data. In technical solution seven, the N signal streams generated on the N data lines simultaneously possess both clock synchronization and data content independence. The clock synchronization characteristic stems from the fact that all N signals are driven by a single hardware clock source from the same multi-channel serial interface, ensuring their clock references are completely consistent and there is no phase deviation. The data content independence characteristic arises from the aforementioned mapping step; this software algorithm guarantees that the information in each original data stream can be accurately and independently mapped to its corresponding physical output line. Existing technologies struggle to simultaneously achieve both characteristics. For example, multiple independent software timers can generate data-independent signals. The realization of these two characteristics provides an ideal foundation for multi-channel parallel applications requiring high-precision synchronous control. Technical Solution 8 provides a multi-channel single-line return-to-zero code parallel control system. By configuring the processor to execute instructions stored in memory, the system can function as a whole to implement the software algorithm steps such as data conversion and data mapping in the aforementioned methods. Simultaneously, the multi-channel serial interface hardware included in the system provides the physical basis for executing the parallel output step. By executing the above methods, this system can improve the technical contradiction in existing technologies where it is difficult to balance parallel throughput, timing control accuracy, and system resource consumption when controlling multi-channel single-line return-to-zero code devices.

[0012] Technical Solution Nine further defines the specific structure and physical connection method of the system, specifying that the multi-channel serial interface is a four-channel serial peripheral interface, and includes four single-wire return-to-zero code devices as controlled objects. The physical connection method of this system constructs a complete signal transmission path from the controller to the controlled end, ensuring that the multiple parallel control signals generated internally by the system can be accurately and without cross-interference transmitted to their respective predetermined target devices. Attached Figure Description To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments are briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the modules of the multi-channel single-line return-to-zero code parallel control system according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the multi-channel single-line return-to-zero code parallel control method according to an embodiment of the present invention. Detailed Implementation The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are preferred embodiments of the present invention and should not be considered as excluding other embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0014] Unless otherwise expressly defined, the use of terms such as "first," "second," or "third" in the claims, description, and accompanying drawings of this invention is for distinguishing different objects and not for describing a specific order.

[0015] In the claims, description and accompanying drawings of this invention, the terms "comprising," "having," and variations thereof are used to mean "including but not limited to."

[0016] Example This invention relates to a multi-channel single-line return-to-zero code parallel control system, with reference to... Figure 1 The system includes multiple serial interfaces, a processor, and memory. In a preferred embodiment, it also includes a direct memory access controller, i.e., DMA.

[0017] The following section will first describe the parallel control system.

[0018] The processor in this parallel control system is communicatively coupled to the multi-channel serial interface and the memory. The processor is the core control unit of the system, configured to execute computer-executable instructions stored in the memory to implement the parallel control method described in this invention. Specifically, the processor's functions include: first, initializing and configuring other hardware components within the system, such as configuring the operating mode and clock frequency of the multi-channel serial interface; second, executing the data processing algorithm in this invention, namely, performing a conversion step to convert N independent binary logic data streams into N encoded data streams, and performing a mapping step to reassemble the N encoded data streams into a single transmit data stream. In a preferred embodiment, if the system includes a direct memory access controller, the processor is also responsible for configuring the controller and initiating data transmission after data generation is complete.

[0019] The multiplexed serial interface in this system is a hardware interface with N parallel data output lines, where N is an integer greater than 1. This interface is responsible for the physical output of the method of the present invention. It receives a single transmit data stream generated by the processor or transmitted by the direct memory access controller, and outputs the data in the data stream in parallel to its N data output lines under the drive of its internal hardware clock. In a preferred embodiment, the multiplexed serial interface is a four-way serial peripheral interface, i.e., QSPI, where N is 4. The QSPI has four data output lines, which can be represented by IO0, IO1, IO2, and IO3 in the accompanying drawings.

[0020] The memory in this system is a non-transient computer-readable storage medium. It stores the computer program instructions required for processor execution, as well as the data to be processed during execution. Specifically, the stored data may include: program code for executing the method of this invention; N independent binary logical data streams as input data; intermediate data generated in the conversion step, i.e., N encoded data streams; and a single transmission data stream generated in the mapping step, which is ultimately to be transmitted. When the system employs a direct memory access controller, the memory region containing this single transmission data stream is the memory region described in the embodiment.

[0021] In a preferred embodiment, the system further includes a direct memory access controller. This controller is a separate hardware unit that has data paths with the processor, memory, and multiplexed serial interface. The direct memory access controller is configured to perform the step of providing a single transmit data stream to the multiplexed serial interface. Specifically, after the processor completes the generation of the single transmit data stream, it configures the source address (pointing to the start location of the data stream in memory), the destination address (pointing to the data transmit register of the multiplexed serial interface), and the transmission length of the direct memory access controller, and then starts the controller. After starting, the direct memory access controller is configured to automatically transfer the single transmit data stream from a memory region to the multiplexed serial interface, without further processor intervention.

[0022] Reference Figure 1The system of this invention may further include N single-line return-to-zero (RZ) code devices as controlled objects. In a preferred embodiment, the system includes four single-line RZ code devices, labeled as devices A, B, C, and D. Each of the four data output lines IO0, IO1, IO2, and IO3 of the four serial peripheral interfaces is physically connected to the data input terminal of a corresponding device among the four single-line RZ code devices. For example, IO0 is connected to device A, IO1 is connected to device B, and so on. This physical connection establishes a complete signal transmission path, ensuring that the four parallel control signals generated by the system can be accurately transmitted to their respective target devices.

[0023] The following describes the method executed by the parallel control system, which is a multi-channel single-line return-to-zero code parallel control method.

[0024] Reference Figure 2 The method of this invention is implemented based on a multi-channel serial interface with N parallel data lines, where N is an integer greater than 1. This method aims to convert N independent binary logic data streams into N physically parallel, clock-synchronized, and data-content-independent single-line return-to-zero (RZ) code signal streams through a series of processing steps. For clarity, a preferred embodiment with N equal to 4 will be described below, where the multi-channel serial interface is a four-channel serial peripheral interface, i.e., QSPI.

[0025] The method includes the following steps: Conversion step S10: First, the system receives four independent binary logical data streams as input. For each of these four independent binary logical data streams, a conversion step is performed, that is, each individual bit in the data stream is converted into a corresponding bit group consisting of multiple bits, thereby forming four encoded data streams.

[0026] The purpose of this step is to transform an abstract logical value (0 or 1) into a structured bit sequence that can physically reproduce a specific time pulse. In a preferred embodiment, this transformation step specifically includes: converting a binary logical "0" into a first bit group 1000 consisting of four bits; and converting a binary logical "1" into a second bit group 1110 consisting of four bits.

[0027] This specific conversion rule is closely related to the hardware clock frequency used in subsequent output steps. In one specific implementation, the operating clock frequency of the four serial peripheral interfaces is configured in the range of 3 MHz to 4 MHz, for example, 3.2 MHz. At this frequency, the duration of each bit is approximately 312.5 nanoseconds. When bit group 1000 is output, it forms a high level lasting approximately 312.5 nanoseconds, followed by a low level lasting approximately 937.5 nanoseconds, which matches the pulse width requirement of logic "0" in a single-wire return-to-zero code protocol with a data rate of 800 kHz. Similarly, bit group 1110 forms a high level lasting approximately 937.5 nanoseconds, followed by a low level lasting approximately 312.5 nanoseconds, matching the requirement of logic "1" in the same protocol.

[0028] Mapping step S20: After generating the four encoded data streams, the system performs a mapping step. This step involves iteratively extracting one bit synchronously from each of the four encoded data streams and combining the four extracted bits into a single bit unit to generate a single transmit data stream.

[0029] This step is the core data reassembly process for achieving parallel and independent output. In a specific implementation, this iterative operation is performed as follows: (i) In the first iteration, one bit is taken from the starting position of the four-way encoded data stream, i.e., the 0th bit, to obtain four bits.

[0030] (ii) Combine these four bits into a four-bit unit, or half-byte, in the reverse order of the QSPI hardware output pins. For example, if the four data lines IO0, IO1, IO2, and IO3 correspond to the first to fourth data streams respectively, then the bit unit can be formed by combining the bits taken from the fourth, third, second, and first streams in sequence.

[0031] (iii) In the second iteration, the bit-taking and combination operations are repeated from the next position of the four-way encoded data stream, i.e. the first bit, to generate the second four-bit bit unit.

[0032] (iv) Combine the two four-bit units into an eight-bit byte and store it as the first byte in the buffer in memory used to store the single transmitted data stream.

[0033] (v) Repeat the above iterative process until all bits in the encoded data stream have been processed, ultimately forming a complete, byte-aligned single transmit data stream.

[0034] Output step S30: After generating a single transmit data stream, the system performs an output step, which provides the single transmit data stream to the multi-channel serial interface, and the multi-channel serial interface outputs the single transmit data stream in parallel to the four data lines to synchronously drive the four single-line return-to-zero code devices.

[0035] Reference Figure 2 There are two preferred embodiments for performing this step: The first implementation involves the processor directly providing the data. In this mode, the processor executes program instructions to sequentially read each byte of the single transmit data stream from memory and writes it into the data transmit register of the four-way serial peripheral interface.

[0036] In a second preferred embodiment, the step of providing the single transmit data stream to the multiplexed serial interface is performed by a direct memory access controller. In this mode, the processor first configures the direct memory access controller, including the source address (pointing to the starting position of the single transmit data stream in memory), the destination address (pointing to the data transmit register of the four-way serial peripheral interface), and the total number of bytes to be transmitted. After configuration, the processor starts the controller, and then the direct memory access controller is configured to automatically transfer the single transmit data stream from one memory region to the four-way serial peripheral interface without continuous processor intervention.

[0037] When processing dynamic or complex visual data, the data constituting a frame may be stored in multiple non-contiguous blocks of physical memory. To improve processing efficiency, in a preferred embodiment, the direct memory access controller operates in a linked descriptor mode. The processor pre-builds a list of descriptors in memory, each descriptor pointing to a non-contiguous data block and its length. Upon startup, the controller uses this list to sequentially and consecutively transfer multiple non-contiguous data blocks from the memory region to the multiplexed serial interface, thereby forming a seamless data stream at the output. This process avoids additional memory copy operations by the processor.

[0038] By performing all the above steps, the method of the present invention ultimately achieves a specific technical effect at the physical level. The step of outputting in parallel to the four data lines generates four signal streams on the four data lines, wherein the four signal streams are clock-synchronized with each other because they are all driven by the same hardware clock source of QSPI. Simultaneously, the data content contained in each of the four signal streams is independent of each other because the mapping step S20 ensures that the information of each original binary logic data stream is uniquely and accurately reassembled onto its corresponding physical output line.

[0039] The following will use the example of a lighting device consisting of four independent single-line zero-code LED light strips (hereinafter referred to as light strips) to illustrate the method of the present invention in detail.

[0040] In this embodiment, the lighting device includes four light strips, namely light strip A, light strip B, light strip C, and light strip D. The goal of the control system is to send four independent control signals to these four light strips in parallel, so that they display different colors or brightness states. As an example, assume that the system needs to send four independent 8-bit raw binary data streams as shown in the table below:

[0041] To achieve parallel control of these four LED strips, the system first performs data processing internally. The first step is data conversion. In this step, for each of the four independent binary logic data streams, the system converts each individual bit in the data stream into a corresponding bit group consisting of multiple bits. In this embodiment, the conversion rule is: binary logic 0 is converted into a bit group 1000 consisting of four bits, and binary logic 1 is converted into a bit group 1110.

[0042] After this conversion, each of the original 8-bit data streams was transformed into a 32-bit encoded data stream. The conversion results for all four data streams are shown in the table below:

[0043] The second step in data processing is data mapping. In this step, the system iteratively extracts one bit synchronously from each of the four encoded data streams and combines the four extracted bits into a single bit unit to generate a single transmit data stream. This single transmit data stream is physically stored in a 16-byte transmit buffer.

[0044] The detailed rules of this mapping process are shown in the table below. The table defines which bit of each byte in the transmit buffer originates from which bit of the encoded data stream. The symbol Xn_m represents the m-th bit in the 32-bit encoded data stream corresponding to the n-th original byte of the light strip X (bits are counted from right to left, starting from 0).

[0045]

[0046] According to this mapping rule, the aforementioned four 32-bit encoded data streams are reassembled to generate a single 16-byte data stream, the hexadecimal representation of which is: 0xFF, 0xF0, 0xF8, 0x00, 0xF0, 0x00, 0xF4, 0x40, 0xFF, 0xF0, 0xFF, 0xF0, 0xF0, 0x00, 0xF2, 0x20.

[0047] After data processing is complete, the data output stage begins. The system provides the single transmit data stream to the four serial peripheral interfaces. In a preferred embodiment, this step is performed by a direct memory access controller, which automatically transfers the aforementioned 16 bytes of data from memory to the transmit FIFO of the four serial peripheral interfaces.

[0048] Finally, the four-channel serial peripheral interface outputs the single transmitted data stream in parallel to the four data lines. Driven by its configured operating clock frequency (e.g., 3.2 MHz), the interface splits the received single data stream and outputs it simultaneously on its four physical data lines IO0, IO1, IO2, and IO3. Due to the reverse reorganization of the data mapping step, the hardware's parallel distribution operation ultimately accurately reproduces four independent, correctly formatted single-line return-to-zero code signal streams on the four data lines, thereby synchronously driving LED strips A, B, C, and D.

[0049] This embodiment relates to a multi-channel single-line return-to-zero code parallel control method, which improves the technical contradiction in the prior art where it is difficult to balance parallel throughput, timing control accuracy and system resource consumption when controlling multi-channel single-line return-to-zero code devices.

[0050] In existing technologies, the timing jitter problem stems from the fact that the processor's execution flow is not continuous and focused. The processor needs to respond to interrupt requests from other parts of the system. These interrupts pause the current timing simulation task to execute higher-priority code, returning only after the interrupt service is complete. The time delay introduced by this task switching is uncertain, leading to random deviations in signal pulse width, i.e., timing jitter. This solution first converts logic bits into bit groups composed of multiple bits, then outputs them in parallel through a multiplexed serial interface. Specifically, the multiplexed serial interface is driven by a stable, independent hardware clock source, and the timing of its output signals depends entirely on the physical characteristics of this clock source, unaffected by processor interrupts. The aforementioned conversion steps pre-construct a structured bit sequence at the software level. When this sequence is output at a fixed rate by the hardware clock, it can accurately reproduce the waveform with a specific pulse width as defined by the single-wire return-to-zero code protocol at the physical level. Therefore, this collaborative mechanism of software-defined waveform structure and hardware-guaranteed time base utilizes the natural principle of high precision and high stability of hardware clock signals to transfer the task of timing generation from the interference-prone software execution level to the stable and reliable hardware physical level, thus enabling the generation of control signals with extremely low timing jitter.

[0051] Furthermore, the low refresh rate of existing technologies using cascaded standard serial interfaces is due to the serial nature of data transmission. In this mode, data from all channels must be arranged in a single long queue and transmitted sequentially on a single data channel, with the total transmission time being the sum of the transmission times of all channels. This solution iteratively extracts bits synchronously from N encoded data streams and combines them into bit units to generate a single transmit data stream, which is then output in parallel to N data lines by a multi-channel serial interface. Specifically, the multi-channel serial interface physically has N data lines capable of simultaneous data output. The aforementioned mapping step is essentially a data reassembly algorithm. This algorithm deeply utilizes the inherent hardware working principle of the multi-channel serial interface, which splits a single input data stream into N parallel lines. By performing a specific, reverse interleaving operation on the N independent data streams in advance at the software level, the output result of this interleaved single data stream on the N physical data lines after being split by the interface hardware is exactly the original N independent data streams. This collaborative mechanism, where software performs data spatial rearrangement and hardware performs parallel physical distribution, changes the original purpose of the multi-channel serial interface, transforming it from a transmission acceleration tool for a single device into a parallel controller for multiple independent devices. Because data is transmitted simultaneously on N lines, the theoretical data throughput is increased to N times that of a single-channel serial interface. This significantly shortens the total transmission time of a single frame of data and improves the refresh rate when driving the same number of devices.

[0052] The parallel control method involved in this embodiment uses a specific software algorithm that is deeply coupled with the underlying working principle of the multi-channel serial interface hardware. This enables a standard hardware interface to implement a brand-new system-level function. With a unified architecture, it overcomes the technical challenges of timing accuracy and parallel bandwidth, which usually require different solutions in the prior art. This provides an efficient and reliable solution for the parallel control of multi-channel single-line return-to-zero code devices.

[0053] Furthermore, this embodiment also relates to a computer-readable storage medium storing computer program instructions. When these instructions are executed by a processor, they control the device containing the computer-readable storage medium to perform the multi-channel single-line return-to-zero code parallel control method as described above. The computer program instructions in this memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. As a computer-readable storage medium, the memory can be configured to store software programs, computer-executable programs, such as the program instructions or modules corresponding to the methods in this embodiment. The processor executes functional applications and data processing by running the software programs, instructions, or modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created based on the use of the terminal device, etc. Furthermore, the memory may include high-speed random access memory and may also include non-volatile memory. For example, USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks are all media that can store program code, and can also be temporary storage media.

[0054] The foregoing description of the specifications and embodiments is intended to explain the scope of protection of this invention, but does not constitute a limitation on the scope of protection of this invention. Modifications, equivalent substitutions, or other improvements to the embodiments of this invention or a portion thereof that can be obtained by those skilled in the art through logical analysis, reasoning, or limited experimentation, based on the teachings of this invention or the foregoing embodiments, in conjunction with common knowledge, general technical knowledge, and / or existing technology, should all be included within the scope of protection of this invention.

Claims

1. A multi-channel single-line return-to-zero code parallel control method, which is implemented based on a multi-channel serial interface with N parallel data lines, where N is an integer greater than 1, characterized in that, include: For each of the N independent binary logical data streams, each individual bit in the data stream is converted into a corresponding bit group consisting of multiple bits, thereby forming the N encoded data streams; A single transmit data stream is generated by iteratively extracting one bit synchronously from each of the N encoded data streams and combining the extracted N bits into a bit unit. as well as The single transmit data stream is provided to the multi-channel serial interface, and the multi-channel serial interface outputs the single transmit data stream in parallel to the N data lines to synchronously drive the N single-line return-to-zero code devices.

2. The multi-channel single-line return-to-zero code parallel control method as described in claim 1, characterized in that, The multi-channel serial interface is a four-channel serial peripheral interface, where N is 4.

3. The multi-channel single-line return-to-zero code parallel control method as described in claim 2, characterized in that, The step of converting each individual bit into a corresponding bit group consisting of multiple bits includes: converting binary logic "0" into a first bit group 1000 consisting of four bits; and converting binary logic "1" into a second bit group 1110 consisting of four bits.

4. The multi-channel single-line return-to-zero code parallel control method as described in claim 3, characterized in that, The operating clock frequency of the four serial peripheral interfaces is configured to be in the range of 3 MHz to 4 MHz.

5. The multi-channel single-line return-to-zero code parallel control method as described in claim 1, characterized in that, The step of providing the single transmit data stream to the multiplex serial interface is performed by a direct memory access controller configured to automatically transfer the single transmit data stream from a memory region to the multiplex serial interface.

6. The multi-channel single-line return-to-zero code parallel control method as described in claim 5, characterized in that, The direct memory access controller operates in chained descriptor mode to sequentially and sequentially transmit multiple non-contiguous data blocks in the memory region to the multiplexed serial interface.

7. The multi-channel single-line return-to-zero code parallel control method as described in claim 1, characterized in that, The step of outputting in parallel to the N data lines generates N signal streams on the N data lines, wherein the N signal streams are clock-synchronized with each other, and the data content contained in each of the N signal streams is independent of each other.

8. A multi-channel single-line return-to-zero code parallel control system, characterized in that, include: A multi-channel serial interface with N parallel data output lines, where N is an integer greater than 1; A processor that is communicatively coupled to the multiplex serial interface; as well as A memory storing computer-executable instructions, which, when executed by the processor, cause the system to perform the multi-channel single-line return-to-zero code parallel control method as described in any one of claims 1-7.

9. A multi-channel single-line return-to-zero code parallel control system as described in claim 8, characterized in that, The multi-channel serial interface is a four-channel serial peripheral interface, where N is 4; the system also includes four single-line return-to-zero code devices; each of the four data output lines of the four-channel serial peripheral interface is physically connected to the data input terminal of a corresponding device in the four single-line return-to-zero code devices.

10. A computer-readable storage medium, characterized in that, It stores computer program instructions, which, when executed by a processor, control the device containing the computer scale storage medium to perform the multi-channel single-line return-to-zero code parallel control method as described in any one of claims 1-7.

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