Communication device and system based on single bus

Abstract

The invention discloses a communication device and system based on a single bus. The communication device based on the single bus comprises a sensor, a logic processing circuit, a modulation circuit, a demodulation circuit and an antenna, wherein the antenna is electrically connected with the modulation circuit and the demodulation circuit, the modulation circuit and the demodulation circuit are electrically connected with the logic processing circuit, and the logic processing circuit is electrically connected with the sensor through a single bus; the sensor sends and receives data in a time division multiplexing mode; in the data sending stage, first data sent by a sensor sequentially passes through a logic processing circuit and a modulation circuit and is radiated outwards by an antenna; in the data receiving stage, second data received by the antenna sequentially passes through the demodulation circuit and the logic processing circuit and is received by the sensor; and the logic processing circuit is used for isolating the first data and the second data. According to the scheme provided by the invention, data loopback can be avoided on the basis of realizing single-bus communication, so that the production cost is reduced, and the communication effect is improved.

Description

Technical Field

[0001] This invention relates to the field of sensor communication technology, and in particular to a communication device and system based on a single bus. Background Technology

[0002] One-wire interface (OWI) is an asynchronous half-duplex serial communication interface that can achieve bidirectional data communication using a single signal line. It is often used in some low-speed, low-cost sensor circuits.

[0003] Figure 1 It is an existing single-bus communication architecture. For example... Figure 1 As shown, this communication architecture includes a microcontroller unit (MCU), a transmit path, a receive path, and an antenna (or antenna system). Data reception and transmission share the same antenna, and the transmit and receive paths are connected to the same general-purpose input / output (GPIO) port of the MCU. This causes the received signal (RX signal) on the receive path to return to the antenna through the transmit path, creating a data loop and leading to communication disorder.

[0004] To ensure that transmitting and receiving signals do not conflict, Figure 2 It is another existing single-bus communication architecture. For example... Figure 2 As shown, the transmit and receive paths are connected to two GPIOs of the MCU, respectively, so that the discrete GPIOs can handle the RX signal and the transmit signal (TX signal) separately. However, at the sensor end, some simple sensor systems using OWI communication do not have an MCU that can physically isolate the TX and RX signals. Adding an extra MCU would also increase the system cost. Summary of the Invention

[0005] This invention provides a communication device and system based on a single bus, which can avoid data loops while realizing single-bus communication, thereby reducing production costs and improving communication performance.

[0006] According to one aspect of the present invention, a single-bus-based communication device is provided, comprising: a sensor, a logic processing circuit, a modulation circuit, a demodulation circuit, and an antenna; wherein the antenna is electrically connected to the modulation circuit and the demodulation circuit, the modulation circuit and the demodulation circuit are respectively electrically connected to the logic processing circuit, and the logic processing circuit is electrically connected to the sensor via the single bus; the sensor transmits and receives data using time-division multiplexing; in the data transmission phase, first data transmitted by the sensor passes sequentially through the logic processing circuit and the modulation circuit, and is radiated outward by the antenna; in the data reception phase, second data received by the antenna passes sequentially through the demodulation circuit and the logic processing circuit, and is received by the sensor; the logic processing circuit is used to isolate the first data and the second data.

[0007] Optionally, the logic processing circuit includes: a first comparator, a second comparator, a first resistor, a second resistor, a third resistor, and a buck converter; the positive input terminal of the first comparator is electrically connected to the demodulation circuit, the negative input terminal of the first comparator is connected to a reference voltage, and the input terminal of the first comparator is electrically connected to one end of the second resistor; one end of the first resistor is connected to the supply voltage, and the other end of the first resistor is electrically connected to the other end of the second resistor, one end of the third resistor, and one end of the buck converter, while the other end of the third resistor is grounded; the other end of the buck converter is electrically connected to the sensor via a single bus; the positive input terminal of the second comparator is electrically connected to the other end of the buck converter, the negative input terminal of the second comparator is electrically connected to one end of the buck converter, and the output terminal of the second comparator is electrically connected to the modulation circuit.

[0008] Optionally, the logic processing circuit may further include: a fourth resistor; one end of the fourth resistor is electrically connected to the positive input terminal of the second comparator, and the other end of the fourth resistor is grounded.

[0009] Optionally, the step-down element is a diode or a fifth resistor; when the step-down element is a diode, the positive terminal of the diode is electrically connected to the other end of the first resistor, and the negative terminal of the diode is electrically connected to the sensor through a single bus.

[0010] Optionally, the resistance of the second resistor is less than the resistance of the first resistor, and the resistance of the first resistor is less than the resistance of the third resistor.

[0011] Optionally, the resistance of the first resistor is at least 10 times that of the second resistor, and the resistance of the third resistor is at least 10 times that of the first resistor.

[0012] Optionally, when the step-down element is the fifth resistor, the resistance value of the fifth resistor is less than the resistance value of the first resistor.

[0013] Optionally, when the step-down element is a diode, the diode is a Schottky diode.

[0014] Optionally, it also includes: a reference voltage generating circuit; wherein the reference voltage generating circuit includes a sixth resistor and a seventh resistor, one end of the sixth resistor is connected to the power supply voltage, the other end of the sixth resistor is electrically connected to one end of the seventh resistor and the negative input terminal of the first comparator; the other end of the seventh resistor is grounded.

[0015] According to another aspect of the present invention, a single-bus-based communication system is provided, including the single-bus-based communication device of any of the above embodiments.

[0016] The technical solution of this invention involves designing a single-bus-based communication device, which includes a sensor, a logic processing circuit, a modulation circuit, a demodulation circuit, and an antenna. The antenna is electrically connected to the modulation and demodulation circuits, which are in turn electrically connected to the logic processing circuit. The logic processing circuit is electrically connected to the sensor via the single bus. On one hand, because the sensor uses time-division multiplexing to transmit and receive data, during the data transmission phase, the first data transmitted by the sensor passes sequentially through the logic processing circuit and the modulation circuit before being radiated outward by the antenna. During the data reception phase, the second data received by the antenna passes sequentially through the demodulation circuit and the logic processing circuit before being received by the sensor. The logic processing circuit can isolate the first and second data, preventing the second data from re-entering the modulation circuit and returning to the antenna. Therefore, data loopback is avoided while achieving single-bus communication, improving communication performance. On the other hand, the communication device does not require an MCU; the logic processing circuit is electrically connected to one interface of the sensor via the single bus, which does not increase production costs and facilitates widespread application.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 It is an existing single-bus communication architecture;

[0020] Figure 2 It is another existing single-bus communication architecture;

[0021] Figure 3 This is a schematic diagram of the structure of a communication device based on a single bus provided in Embodiment 1 of the present invention;

[0022] Figure 4 This is a schematic diagram of another communication device based on a single bus provided in Embodiment 1 of the present invention;

[0023] Figure 5 This is a schematic diagram of another communication device based on a single bus provided in Embodiment 1 of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of a logic processing circuit provided in Embodiment 1 of the present invention;

[0025] Figure 7 This is a schematic diagram of the structure of a logic processing circuit provided in Embodiment 1 of the present invention;

[0026] Figure 8 This is a schematic diagram of another communication device based on a single bus provided in Embodiment 1 of the present invention;

[0027] Figure 9 This is a voltage waveform diagram of a single-bus-based communication device during the data reception stage, as provided in Embodiment 1 of the present invention.

[0028] Figure 10 This is a voltage waveform diagram of a single-bus-based communication device during the data transmission phase, as provided in Embodiment 1 of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] Example 1

[0032] Figure 3 This is a schematic diagram of a single-bus-based communication device according to Embodiment 1 of the present invention. The single-bus-based communication device is suitable for systems requiring sensor communication. Figure 3 As shown, the single-bus-based communication device includes: a sensor 10, a logic processing circuit 20, a modulation circuit 30, a demodulation circuit 40, and an antenna 50. The antenna 50 is electrically connected to the modulation circuit 30 and the demodulation circuit 40. The modulation circuit 30 and the demodulation circuit 40 are respectively electrically connected to the logic processing circuit 20. The logic processing circuit 20 is electrically connected to the sensor 10 via the single bus.

[0033] Sensor 10 typically uses a GPIO interface to connect to a single bus. Sensor 10 is responsible for converting the acquired analog quantities (such as temperature, humidity, pressure, etc.) into digital signals and outputting them serially via the single bus protocol; it also receives data received by antenna 50.

[0034] Sensor 10 uses time-division multiplexing to send and receive data. During the data transmission phase, the first data sent by sensor 10 passes through logic processing circuit 20 and modulation circuit 30 in sequence and is radiated outward by antenna 50. During the data reception phase, the second data received by antenna 50 passes through demodulation circuit 40 and logic processing circuit 20 in sequence and is received by sensor 10.

[0035] The modulation circuit 30 uses modulation techniques to shift the spectrum of the signal (i.e., the first data) to a higher frequency, enabling it to be effectively radiated by the antenna and suitable for transmission in a designated wireless channel. Optionally, the modulation method of the modulation circuit 30 can be amplitude shift keying (ASK) modulation or frequency shift keying (FSK) modulation.

[0036] The demodulation circuit 40 extracts the original baseband digital signal from the modulated radio frequency signal (i.e., the second data) received by the antenna 50 using demodulation technology.

[0037] Antenna 50 is a transducer that converts guided waves propagating on a transmission line into electromagnetic waves propagating in an unbounded medium (typically free space), or vice versa. It is a component in wireless equipment used to transmit or receive electromagnetic waves. In this invention, there is only one antenna 50, and both the modulation circuit 30 and the demodulation circuit 40 are electrically connected to this antenna 50 to reduce cost and simultaneously achieve miniaturization of the single-bus-based communication device.

[0038] The logic processing circuit 20 is used to isolate the first data and the second data. Specifically, the logic processing circuit 20 can ensure that the transmission path is never open during the data reception phase, thereby avoiding data loops while achieving single-bus communication.

[0039] Figure 4 This is a schematic diagram of another single-bus-based communication device provided in Embodiment 1 of the present invention. Figure 4 As shown, the logic processing circuit 20 includes: a first comparator U1, a second comparator U2, a first resistor R1, a second resistor R2, a third resistor R3, and a step-down element 21.

[0040] Specifically, the positive input terminal of the first comparator U1 is electrically connected to the demodulation circuit 40, meaning the positive input terminal of the first comparator U1 receives the OWITX signal. The negative input terminal of the first comparator U1 is connected to the reference voltage Vref, and the input terminal of the first comparator U1 is electrically connected to one end of the second resistor R2. One end of the first resistor R1 is connected to the supply voltage VCC, and the other end of the first resistor R1 is electrically connected to the other end of the second resistor R2, one end of the third resistor R3, and one end of the step-down element 21. The other end of the third resistor R3 is grounded. The other end of the step-down element 21 is electrically connected to the sensor 10 via a single bus. The positive input terminal of the second comparator U2 is electrically connected to the other end of the step-down element 21, the negative input terminal of the second comparator U2 is electrically connected to one end of the step-down element 21, and the output terminal of the second comparator U2 is electrically connected to the modulation circuit 30, meaning the output terminal of the second comparator U2 outputs the OWITX signal.

[0041] The function of the step-down element 21 in the logic processing circuit 20 is to ensure that the voltage at one end of the step-down element 21 is less than the voltage at the other end. That is, the signal output from the second resistor R2 will have a lower voltage after passing through the step-down element 21. In this way, the voltage at the negative input terminal of the second comparator U2 is guaranteed to be higher than the voltage at the positive input terminal of the second comparator U2, and the modulation circuit 30 will not work, ensuring that the transmission path is always closed during the data reception stage and avoiding data loops.

[0042] Optional, Figure 5 This is a schematic diagram of another communication device based on a single bus provided in Embodiment 1 of the present invention. Figure 5 As shown, the logic processing circuit 20 also includes a fourth resistor R4.

[0043] Specifically, one end of the fourth resistor R4 is electrically connected to the positive input terminal of the second comparator U2, and the other end of the fourth resistor R4 is grounded. The function of the fourth resistor R4 is to ensure a stable voltage drop of the step-down component 21 and improve the stability of the communication device.

[0044] In one possible implementation, Figure 6This is a schematic diagram of a logic processing circuit provided in Embodiment 1 of the present invention. Figure 6 As shown, the step-down element 21 is a diode D1. Specifically, the positive terminal of diode D1 is electrically connected to the other end of the first resistor R1, and the negative terminal of diode D1 is electrically connected to sensor 10 through a single bus.

[0045] In another possible implementation Figure 7 This is a schematic diagram of another logic processing circuit provided in Embodiment 1 of the present invention. Figure 7 As shown, the step-down element 21 is the fifth resistor R5. Specifically, one end of the fifth resistor R5 is electrically connected to the other end of the first resistor R1, and the other end of the fifth resistor R5 is electrically connected to the sensor 10 through a single bus.

[0046] Both diode D1 and the fifth resistor R5 can reduce the voltage of the signal output from the second resistor R2 after passing through the step-down component 21. Compared with using a resistor to achieve the voltage drop, diode D1 has the advantage of a relatively stable voltage drop, is less affected by changes in load current, and can provide reverse isolation protection. Using the fifth resistor R5 to achieve the voltage drop is lower in cost and smaller in size.

[0047] In one embodiment, the first resistor R1, the second resistor R2, and the third resistor R3 satisfy the following relationship: , .

[0048] in, This is the power supply voltage.

[0049] Specifically, the resistance of the second resistor R2 is less than the resistance of the first resistor R1, and the resistance of the first resistor R1 is less than the resistance of the third resistor R3. Furthermore, the resistance of the first resistor R1 is at least 10 times the resistance of the second resistor R2, and the resistance of the third resistor R3 is at least 10 times the resistance of the first resistor R1, to ensure signal isolation and improve security.

[0050] In one embodiment, when the step-down element 21 is the fifth resistor R5, the resistance value of the fifth resistor R5 is less than the resistance value of the first resistor R1.

[0051] In one embodiment, when the step-down element 21 is a diode D1, the diode D1 is a Schottky diode. Compared with conventional diodes, Schottky diodes have higher step-down efficiency and lower energy loss, which can significantly improve the energy efficiency, stability and compactness of the device.

[0052] In one embodiment, Figure 8 This is a schematic diagram of another single-bus-based communication device provided in Embodiment 1 of the present invention. Figure 8As shown, the single-bus-based communication device also includes a reference voltage generation circuit 60.

[0053] Specifically, the reference voltage generation circuit 60 includes a sixth resistor R6 and a seventh resistor R7. One end of the sixth resistor R6 is connected to the supply voltage VCC, and the other end of the sixth resistor R6 is electrically connected to one end of the seventh resistor R7 and the negative input terminal of the first comparator U1; the other end of the seventh resistor R7 is grounded.

[0054] The working principle of a single-bus-based communication device is as follows:

[0055] During the data reception phase, the demodulation circuit 40 inputs the demodulated envelope signal OWIRX to the positive input of the first comparator U1 and compares it with the reference voltage Vref. The output of the first comparator U1 is either high or low: a high level is output when the voltage of the envelope signal OWIRX is greater than the reference voltage Vref; a low level is output when the voltage of the envelope signal OWIRX is less than the reference voltage Vref. For the high-level output, the first comparator U1 is either an open-drain output or an open-collector output, and the voltage output by the first comparator U1 is the result of the voltage division between the first resistor R1 and the third resistor R3. Simultaneously, the high-level output voltage is reduced by the step-down component 21. When receiving OWIRX, this ensures that the voltage at the negative input of the second comparator U2 is always higher than the voltage at its positive input, and the output of the second comparator U2 is low. That is, regardless of how the OWIRX level changes, the output of the second comparator U2 is low, the modulation circuit 30 does not operate, ensuring that the transmission path is always closed during the data reception phase, thus preventing data loopback. Figure 9 This is a voltage waveform diagram of a single-bus-based communication device during the data reception phase, as provided in Embodiment 1 of the present invention. Figure 9 As shown, during the data reception phase, the output of the second comparator U2 is always at a low level.

[0056] During the data transmission phase, when OWITX is high, the positive input of the second comparator U2 is the supply voltage VCC. Due to the voltage division between the first resistor R1 and the third resistor R3, the voltage at the positive input of the second comparator U2 is always greater than the voltage at its negative input, resulting in a high output from the second comparator U2. When OWITX is low, the positive input of the second comparator U2 is 0V. Because of the voltage division between the second resistor R2 and the first resistor R1, the voltage at the negative input of the second comparator U2 will not drop to 0V, ensuring that its voltage is always greater than the voltage at its positive input, resulting in a low output from the second comparator U2. Therefore, the output of the second comparator U2 is synchronized with the state of OWITX, thus achieving the purpose of transmitting data to the modulation circuit 30. Figure 10This is a voltage waveform diagram of a single-bus-based communication device during the data transmission phase, as provided in Embodiment 1 of the present invention. Figure 10 As shown, during the data transmission phase, the output of the second comparator U2 is synchronized with the state of OWITX. Even if a portion of the signal returns from the modulation circuit 30 to the positive input of the first comparator U1 via the demodulation circuit 40, it does not affect the transmission (no data loop is formed).

[0057] The technical solution of this invention involves designing a single-bus-based communication device, which includes a sensor, a logic processing circuit, a modulation circuit, a demodulation circuit, and an antenna. The antenna is electrically connected to the modulation and demodulation circuits, which are in turn electrically connected to the logic processing circuit. The logic processing circuit is electrically connected to the sensor via the single bus. On one hand, because the sensor uses time-division multiplexing to transmit and receive data, during the data transmission phase, the first data transmitted by the sensor passes sequentially through the logic processing circuit and the modulation circuit before being radiated outward by the antenna. During the data reception phase, the second data received by the antenna passes sequentially through the demodulation circuit and the logic processing circuit before being received by the sensor. The logic processing circuit can isolate the first and second data, preventing the second data from re-entering the modulation circuit and returning to the antenna. Therefore, data loopback is avoided while achieving single-bus communication, improving communication performance. On the other hand, the communication device does not require an MCU; the logic processing circuit is electrically connected to one interface of the sensor via the single bus, which does not increase production costs and facilitates widespread application.

[0058] Example 2

[0059] This invention also provides a single-bus-based communication system, including the single-bus-based communication device of any of the above embodiments.

[0060] In one embodiment, the single-bus-based communication system can be any system involving sensor communication, such as an electric vehicle.

[0061] In one embodiment, the electric vehicle can be an electric two-wheeler or an electric three-wheeler.

[0062] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A communication device based on a single bus, characterized in that, include: Sensors, logic processing circuits, modulation circuits, demodulation circuits, and antennas; among them, The antenna is electrically connected to the modulation circuit and the demodulation circuit. The modulation circuit and the demodulation circuit are respectively electrically connected to the logic processing circuit. The logic processing circuit is electrically connected to the sensor via a single bus. The sensor transmits and receives data using time-division multiplexing. During the data transmission phase, the first data transmitted by the sensor passes sequentially through the logic processing circuit and the modulation circuit, and is radiated outward by the antenna. During the data reception phase, the second data received by the antenna passes sequentially through the demodulation circuit and the logic processing circuit, and is received by the sensor. The logic processing circuit is used to isolate the first data and the second data.

2. The communication device based on a single bus according to claim 1, characterized in that, The logic processing circuit includes: a first comparator, a second comparator, a first resistor, a second resistor, a third resistor, and a step-down component; The positive input terminal of the first comparator is electrically connected to the demodulation circuit, the negative input terminal of the first comparator is connected to the reference voltage, and the input terminal of the first comparator is electrically connected to one end of the second resistor; One end of the first resistor is connected to the power supply voltage, and the other end of the first resistor is electrically connected to the other end of the second resistor, one end of the third resistor, and one end of the step-down element. The other end of the third resistor is grounded. The other end of the step-down element is electrically connected to the sensor through a single bus. The positive input terminal of the second comparator is electrically connected to the other end of the step-down element, the negative input terminal of the second comparator is electrically connected to one end of the step-down element, and the output terminal of the second comparator is electrically connected to the modulation circuit.

3. The communication device based on a single bus according to claim 2, characterized in that, The logic processing circuit further includes: a fourth resistor; One end of the fourth resistor is electrically connected to the positive input terminal of the second comparator, and the other end of the fourth resistor is grounded.

4. The single-bus based communication device according to claim 2 or 3, characterized in that, The step-down element is a diode or a fifth resistor; When the step-down element is a diode, the positive terminal of the diode is electrically connected to the other end of the first resistor, and the negative terminal of the diode is electrically connected to the sensor via a single bus.

5. The communication device based on a single bus according to claim 2, characterized in that, The resistance of the second resistor is less than the resistance of the first resistor, and the resistance of the first resistor is less than the resistance of the third resistor.

6. The communication device based on a single bus according to claim 5, characterized in that, The resistance of the first resistor is at least 10 times that of the second resistor, and the resistance of the third resistor is at least 10 times that of the first resistor.

7. The communication device based on a single bus according to claim 4, characterized in that, When the step-down element is the fifth resistor, the resistance value of the fifth resistor is less than the resistance value of the first resistor.

8. The communication device based on a single bus according to claim 4, characterized in that, When the step-down element is a diode, the diode is a Schottky diode.

9. The communication device based on a single bus according to claim 2, characterized in that, Also includes: Reference voltage generation circuit; wherein, The reference voltage generating circuit includes a sixth resistor and a seventh resistor. One end of the sixth resistor is connected to the power supply voltage, and the other end of the sixth resistor is electrically connected to one end of the seventh resistor and the negative input terminal of the first comparator; the other end of the seventh resistor is grounded.

10. A communication system based on a single bus, characterized in that, Includes a single-bus based communication device as described in any one of claims 1-9.

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