Equalizer

Abstract

The embodiment of the invention discloses an equalizer, and the equalizer comprises a first conversion circuit and a second conversion circuit which are set to convert an input common-mode voltage into the variable quantity of a differential current when the common-mode voltage inputted into the equalizer meets the working conditions of the respective conversion circuits; the first current compensation circuit and the second current compensation circuit are set to carry out current compensation on the conversion circuit when the common-mode voltage input into the equalizer only meets the working condition of one conversion circuit; the third conversion circuit is set to convert the variable quantity of the differential current into an output common-mode voltage to obtain the output common-mode voltage; and the control circuit is set to collect the output common-mode voltage in real time, calculate a voltage difference value between the output common-mode voltage at a target frequency and a reference voltage, and generate an adjusting signal according to the voltage difference value so as to adjust adjustable elements in the first conversion circuit, the second conversion circuit and the third conversion circuit. And the peak frequency and the peak gain of the equalizer are constant.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuit technology, and more specifically, to an equalizer. Background Technology

[0002] As high-speed serial interfaces (such as PCIe, USB4, MIPI, and SerDes) continue to increase in speed to tens of Gb / s or even higher, signals are affected by non-ideal factors such as skin effect, dielectric loss, and reflection in transmission media such as printed circuit board traces, backplanes, connectors, and cables, resulting in a significant low-pass characteristic of the overall channel. This frequency-dependent attenuation weakens the high-frequency components of the signal, leading to increased inter-symbol interference (ISI), eye diagram closure, and higher bit error rate (BER). To compensate for high-frequency attenuation, receivers typically introduce a continuous-time linear equalizer (CTLE). CTLE generates a "gain peak" at the high-frequency end by adding an adjustable zero-pole network in the amplifier path, thereby increasing the amplitude of high-frequency components and restoring signal integrity. In multi-standard transceivers, to be compatible with different protocols and channel conditions, CTLEs often need to have rail-to-rail input capability to adapt to changes in common-mode input. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides an equalizer, including a first conversion circuit, a second conversion circuit, a circuit adjustment unit, a power supply, a first current compensation circuit, a second current compensation circuit, a third conversion circuit, and a control circuit; The first conversion circuit is configured to operate when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. When the condition is met, the input common-mode voltage is converted into a change in differential current; The second conversion circuit is configured to, when the common-mode voltage meets the operating conditions of the second conversion circuit, convert... The change in input common-mode voltage is converted into differential current. The power supply is configured to drive the first conversion circuit and the second conversion circuit; The first current compensation circuit is configured to perform current compensation on the first conversion circuit when the common-mode voltage input to the equalizer only meets the operating conditions of the first conversion circuit. The second current compensation circuit is configured to perform current compensation on the second conversion circuit when the common-mode voltage only meets the operating conditions of the second conversion circuit. The third conversion circuit is configured to convert the change in the differential current into an output common-mode voltage. The control circuit is configured to calculate the voltage difference between the spectral component at the target frequency and the reference voltage based on the output common-mode voltage, and generate an adjustment signal based on the voltage difference to adjust the adjustable components in the first conversion circuit, the second conversion circuit and the third conversion circuit, so that the peak frequency and peak gain of the equalizer are constant. The second conversion circuit is a complementary circuit to the first conversion circuit; the input terminal of the common-mode voltage of the first conversion circuit and the input terminal of the common-mode voltage of the second conversion circuit are connected to each other as the input terminal of the input common-mode voltage; the output terminal of the third conversion circuit is connected to each other as the output terminal of the equalizer; the operating conditions of the first conversion circuit and the operating conditions of the second conversion circuit are set to ensure that at least one circuit can meet the operating conditions at any time.

[0005] In one exemplary embodiment, it further includes: The circuit adjustment unit is configured to adjust the zero and pole positions of the first conversion circuit, and to adjust the... The zero and pole locations of the second conversion circuit; The control circuit is further configured to adjust the adjustable element in the circuit adjustment unit according to the adjustment signal.

[0006] In one exemplary embodiment, the first conversion circuit includes a first differential pair transistor and two first current sources; the first differential pair transistor includes two first transistors; each first current source is configured to provide a bias current to the corresponding first transistor. The gate of each first transistor serves as one of the common-mode voltage input terminals of the first conversion circuit; The drain terminal of each first transistor serves as one of the differential current output terminals of the first conversion circuit; One end of each first current source is connected to the source terminal of a corresponding first transistor, and the other end of each first current source... One end is connected to the power supply terminal of the power source.

[0007] In one exemplary embodiment, the second conversion circuit includes two first current mirrors, a second differential pair transistor, and two second current sources; the second differential pair transistor includes two second transistors; each second current source is configured to provide a bias current to the corresponding second transistor. The gate of each second transistor serves as one of the common-mode voltage input terminals of the second conversion circuit; The drain terminal of each second transistor is connected to the input terminal of each first current mirror; the output terminal of each first current mirror serves as one of the differential current output terminals of the second conversion circuit. One end of each second current source is connected to the source terminal of a corresponding second transistor; the other end of each second current source... One end connects to the public end; The source terminal of each current mirror is connected to the power supply terminal of the power source; The first differential pair and the second differential pair are complementary.

[0008] In one exemplary embodiment, the first current compensation circuit includes: a third current mirror, a fourth current mirror, a first bias transistor, and a second bias transistor; The input terminal of the third current mirror is connected to the drain terminal of the first bias transistor, and the output terminal of the third current mirror is connected to the source terminal of a corresponding first transistor. The input terminal of the fourth current mirror is connected to the drain terminal of the second bias transistor, and the output terminal of the fourth current mirror is connected to the source terminal of a corresponding first transistor. The source terminal of the first bias transistor is connected to the source terminal of a corresponding second transistor; The gate of the first bias transistor is configured to receive a first bias signal; the first bias signal is valid when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. The source terminal of the second bias transistor is connected to the source terminal of a corresponding second transistor; The gate terminal of the second bias transistor is configured to receive the first bias signal; The source terminals of the third current mirror and the fourth current mirror are respectively connected to the power supply terminal of the power source.

[0009] In one exemplary embodiment, the second current compensation circuit includes: a fifth current mirror, a sixth current mirror, a third bias transistor, and a fourth bias transistor; The input terminal of the fifth current mirror is connected to the drain terminal of the third bias transistor, and the output terminal of the fifth current mirror is connected to the source terminal of a corresponding second transistor. The source terminal of the third bias transistor is connected to the source terminal of a corresponding first transistor. The gate of the third bias transistor is configured to receive a second bias signal; the second bias signal is valid when the common-mode voltage input to the equalizer meets the operating conditions of the second conversion circuit. The input terminal of the sixth current mirror is connected to the drain terminal of the fourth bias transistor, and the output terminal of the sixth current mirror is connected to the source terminal of the corresponding second transistor. The source terminal of the fourth bias transistor is connected to the source terminal of a first transistor corresponding to the output terminal of the fourth current mirror. The gate terminal of the fourth bias transistor is configured to receive the second bias signal; The source terminals of the fifth current mirror and the sixth current mirror are respectively connected to the common terminal.

[0010] In one exemplary embodiment, the control circuit includes a bandpass filter, a low-pass filter, an error amplifier, and a control circuit. The bandpass filter is connected to the output of the equalizer and is configured to extract the spectral component at the target frequency based on the output common-mode voltage. The low-pass filter is connected to the band-pass filter and is configured to filter the spectral components. The error amplifier is connected to the low-pass filter and is configured to calculate the voltage difference between the spectral component and the reference voltage. The control circuit is connected to the adjustable elements in the circuit adjustment unit and the third conversion circuit, respectively, and is configured to generate an adjustment signal based on the voltage difference to adjust the adjustable elements in the circuit adjustment unit and the third conversion circuit so that the peak frequency and peak gain of the equalizer are constant.

[0011] In one exemplary embodiment, the control circuit includes a sampling module, a digital filtering module, a control logic module, and a digital-to-analog converter module connected in sequence. The sampling module is connected to the output terminal of the equalizer and is configured to sample the output common-mode voltage. The digital filtering module is configured to filter the output common-mode voltage to obtain the digital quantity of the spectral component of the output common-mode voltage at the target frequency. The control logic module is configured to generate a digital adjustment signal based on the voltage difference between the digital quantity of the spectral component and the digital quantity corresponding to the reference voltage. The digital-to-analog converter module is configured to convert the digital adjustment signal into the adjustment signal.

[0012] In one exemplary embodiment, the control circuit includes a sampling module, a digital filtering module, and a control logic module connected in sequence. The sampling module is configured to sample the output common-mode voltage; The digital filtering module is configured to filter the output common-mode voltage to obtain the digital quantity of the spectral component of the output common-mode voltage signal at the target frequency. The control logic module is configured to generate the adjustment signal based on the difference between the digital value of the spectral component and the digital value corresponding to the reference voltage.

[0013] In one exemplary embodiment, the circuit adjustment unit includes a first adjustable resistor and a first adjustable capacitor connected in parallel, as well as a second adjustable resistor and a second adjustable capacitor connected in parallel, wherein the first adjustable resistor and the first adjustable capacitor are connected across a common node of each first current source and a corresponding first transistor. The parallel second adjustable resistor and second adjustable capacitor are connected across the common node of each second current source and the corresponding second transistor.

[0014] The equalizer in this embodiment of the present disclosure maintains a constant peak frequency and peak gain under different input common-mode voltages through current compensation and feedback adjustment.

[0015] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0016] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0017] Figure 1 This is one of the schematic diagrams of an equalizer according to an embodiment of the present disclosure; Figure 2 This is a second schematic diagram of an equalizer according to an embodiment of the present disclosure; Figure 3 This is a circuit diagram of the equalizer according to an embodiment of the present disclosure; Figure 4 for Figure 3 One of the schematic diagrams of the implementation circuit of the 400 section; Figure 5 for Figure 3 The second schematic diagram of the implementation circuit of the 400 part; Figure 6 for Figure 3 The third schematic diagram of the implementation circuit of the 400 part; Figure 7 for Figure 3 A schematic diagram of the partial implementation circuit of the 400 part; Figure 8 for Figure 3 The fourth schematic diagram of the implementation circuit of the 400 part. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0019] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0020] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0021] Currently, linear equalization has been achieved within the rail-to-rail input range. However, the inventors of this application have discovered that within the rail-to-rail input range, the peak frequency and peak gain of the equalizer vary with the input common-mode voltage, making it impossible to achieve constant linear equalization performance. This results in subsequent circuits being unable to maintain a fixed operating point. Therefore, there is an urgent need for a CTLE circuit structure that can better maintain constant linear equalization characteristics within the rail-to-rail input range, ensuring consistent peak position and peak gain under different input common-mode conditions, thereby stabilizing the output common-mode point and improving system reliability.

[0022] This application provides an equalizer that maintains a constant peak frequency and peak gain under different input common-mode voltages by compensating for the input stage bias current and adjusting the frequency selection network.

[0023] This application embodiment introduces a current mirror compensation branch and combines it with a frequency domain detection and adaptive adjustment mechanism to maintain the peak frequency and peak gain of the equalizer constant within the range of the input common-mode voltage from low track to high track, thereby keeping the output common-mode point stable and avoiding downstream interface drift.

[0024] Figure 1 This is one of the schematic diagrams of an equalizer according to an embodiment of the present disclosure, such as... Figure 1 As shown, the equalizer includes a first conversion circuit, a second conversion circuit, a circuit adjustment unit, a power supply, a first current compensation circuit, a second current compensation circuit, a third conversion circuit, and a control circuit. The first conversion circuit is configured to operate when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. When the condition is met, the input common-mode voltage is converted into a change in differential current; The second conversion circuit is configured to, when the common-mode voltage meets the operating conditions of the second conversion circuit, convert... The change in input common-mode voltage is converted into differential current. The power supply is configured to drive the first conversion circuit and the second conversion circuit; The first current compensation circuit is configured to perform current compensation on the first conversion circuit when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. The second current compensation circuit is configured to perform current compensation on the second conversion circuit when the common-mode voltage meets the operating conditions of the second conversion circuit; The third conversion circuit is configured to convert the change in the differential current into an output common-mode voltage. The control circuit is configured to calculate the voltage difference between the spectral component at the target frequency and the reference voltage based on the output common-mode voltage, and generate an adjustment signal based on the voltage difference to adjust the adjustable components in the first conversion circuit, the second conversion circuit and the third conversion circuit, so that the peak frequency and peak gain of the equalizer are constant. The second conversion circuit is a complementary circuit to the first conversion circuit; the input terminal of the common-mode voltage of the first conversion circuit and the input terminal of the common-mode voltage of the second conversion circuit are connected to each other as the input terminal of the common-mode voltage; the output terminal of the differential current of the first conversion circuit and the output terminal of the differential current of the second conversion circuit are connected to each other as the output terminal of the equalizer; the operating conditions of the first conversion circuit and the operating conditions of the second conversion circuit are set to ensure that at least one circuit can meet the operating conditions at any time.

[0025] The equalizer in this embodiment introduces a current mirror compensation branch and combines frequency domain detection and adaptive adjustment mechanisms to maintain the peak frequency and peak gain of the equalizer constant within the range of the input common-mode voltage from low to high rails, thus keeping the output common-mode point stable and avoiding downstream interface drift.

[0026] In one exemplary embodiment, the first conversion circuit includes a first differential pair transistor and two first current sources; the first differential pair transistor includes two first transistors; each first current source is configured to provide a bias current to the corresponding first transistor. The gate of each first transistor serves as one of the common-mode voltage input terminals of the first conversion circuit; The drain terminal of each first transistor serves as one of the differential current output terminals of the first conversion circuit; One end of each first current source is connected to the source terminal of a corresponding first transistor, and the other end of each first current source... One end is connected to the power supply terminal of the power source.

[0027] In one exemplary embodiment, the second conversion circuit includes two first current mirrors, a second differential pair transistor, and two second current sources; the second differential pair transistor includes two second transistors; each second current source is configured to provide a bias current to the corresponding second transistor. The gate of each second transistor serves as one of the common-mode voltage input terminals of the second conversion circuit; The drain terminal of each second transistor is connected to the input terminal of each first current mirror; the output terminal of each first current mirror serves as one of the differential current output terminals of the second conversion circuit. One end of each second current source is connected to the source terminal of a corresponding second transistor; the other end of each second current source... One end connects to the public end; The source terminal of each current mirror is connected to the power supply terminal of the power source; The first differential pair and the second differential pair are complementary.

[0028] In one exemplary embodiment, the first current compensation circuit includes: a third current mirror, a fourth current mirror, a first bias transistor, and a second bias transistor; The input terminal of the third current mirror is connected to the drain terminal of the first bias transistor, and the output terminal of the third current mirror is connected to the source terminal of a corresponding first transistor. The input terminal of the fourth current mirror is connected to the drain terminal of the second bias transistor, and the output terminal of the fourth current mirror is connected to the source terminal of a corresponding first transistor. The source terminal of the first bias transistor is connected to the source terminal of a corresponding second transistor; The gate of the first bias transistor is configured to receive a first bias signal; the first bias signal is valid when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. The source terminal of the second bias transistor is connected to the source terminal of a corresponding second transistor; The gate terminal of the second bias transistor is configured to receive the first bias signal; The source terminals of the third current mirror and the fourth current mirror are respectively connected to the power supply terminal of the power source.

[0029] In one exemplary embodiment, the second current compensation circuit includes: a fifth current mirror, a sixth current mirror, a third bias transistor, and a fourth bias transistor; The input terminal of the fifth current mirror is connected to the drain terminal of the third bias transistor, and the output terminal of the fifth current mirror is connected to the source terminal of a corresponding second transistor. The source terminal of the third bias transistor is connected to the source terminal of a corresponding first transistor. The gate of the third bias transistor is configured to receive a second bias signal; the second bias signal is valid when the common-mode voltage input to the equalizer meets the operating conditions of the second conversion circuit. The input terminal of the sixth current mirror is connected to the drain terminal of the fourth bias transistor, and the output terminal of the sixth current mirror is connected to the source terminal of the corresponding second transistor. The source terminal of the fourth bias transistor is connected to the source terminal of a first transistor corresponding to the output terminal of the fourth current mirror. The gate terminal of the fourth bias transistor is configured to receive the second bias signal; The source terminals of the fifth current mirror and the sixth current mirror are respectively connected to the common terminal.

[0030] In one exemplary embodiment, the control circuit includes a bandpass filter, a low-pass filter, an error amplifier, and a control circuit. The bandpass filter is connected to the output of the equalizer and is configured to extract the spectral component at the target frequency based on the output common-mode voltage. The low-pass filter is connected to the band-pass filter and is configured to filter the spectral components. The error amplifier is connected to the low-pass filter and is configured to calculate the voltage difference between the spectral component and the reference voltage. The control circuit is connected to the adjustable elements in the circuit adjustment unit and the third conversion circuit, respectively, and is configured to generate an adjustment signal based on the voltage difference to adjust the adjustable elements in the circuit adjustment unit and the third conversion circuit so that the peak frequency and peak gain of the equalizer are constant.

[0031] For example, the adjustable element can be an adjustable resistor, an adjustable capacitor, or an adjustable current source. The peak gain of a linearly balanced circuit is a function of the resistor R, capacitor C, and current I; therefore, changing these three quantities will cause a change in the peak gain. When the input common-mode voltage changes, causing a change in the circuit's peak gain, the peak gain can be adjusted and kept constant by changing the values ​​of R, C, and I.

[0032] In one exemplary embodiment, the control circuit includes a sampling module, a digital filtering module, a control logic module, and a digital-to-analog converter module connected in sequence. The sampling module is connected to the output terminal of the equalizer and is configured to sample the output common-mode voltage. The digital filtering module is configured to filter the output common-mode voltage to obtain the digital quantity of the spectral component of the output common-mode voltage at the target frequency. The control logic module is configured to generate a digital adjustment signal based on the voltage difference between the digital quantity of the spectral component and the digital quantity corresponding to the reference voltage. The digital-to-analog converter module is configured to convert the digital adjustment signal into the adjustment signal.

[0033] In one exemplary embodiment, the control circuit includes a sampling module, a digital filtering module, and a control logic module connected in sequence. The sampling module is configured to sample the output common-mode voltage; The digital filtering module is configured to filter the output common-mode voltage to obtain the digital quantity of the spectral component of the output common-mode voltage signal at the target frequency. The control logic module is configured to generate the adjustment signal based on the difference between the digital value of the spectral component and the digital value corresponding to the reference voltage.

[0034] In one exemplary embodiment, the circuit adjustment unit includes a first adjustable resistor and a first adjustable capacitor connected in parallel, as well as a second adjustable resistor and a second adjustable capacitor connected in parallel, wherein the first adjustable resistor and the first adjustable capacitor are connected across a common node of each first current source and a corresponding first transistor. The parallel second adjustable resistor and second adjustable capacitor are connected across the common node of each second current source and the corresponding second transistor.

[0035] The equalizer in this embodiment of the present disclosure maintains a constant peak frequency and peak gain under different input common-mode voltages through current compensation and feedback adjustment.

[0036] Figure 2 This is a second schematic diagram of an equalizer according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, with Figure 1 Compared to the equalizer shown, Figure 2 The equalizer shown also includes a circuit adjustment unit.

[0037] The circuit adjustment unit is configured to adjust the zero and pole positions of the first conversion circuit and the zero and pole positions of the second conversion circuit. The control circuit is further configured to adjust the adjustable element in the circuit adjustment unit according to the adjustment signal.

[0038] Compared to Figure 1 The equalizer shown Figure 2 The equalizer shown can adjust the zero and pole positions of the equalizer, and can maintain consistent linear equalization performance under different process, temperature and power supply conditions, retain the original zero and pole adjustment flexibility, and does not destroy the frequency domain compensation characteristics of CTLE.

[0039] Figure 3 One of the circuit diagrams of the equalizer in this embodiment of the present disclosure is shown below. Figure 3 As shown, it mainly includes 100, 200, 210, 300, and 400 sections. Among them: In section 100, transistors 101 and 102 serve as the input differential pair of PMOS transistors (differential transistors, also known as twin transistors or integrated differential pairs, are electronic devices consisting of two transistors with identical performance parameters packaged together). The gate of PMOS transistor 101 serves as the VIN input, and the gate of PMOS transistor 102 serves as the VIP input. The source of PMOS transistor 101 is connected to one end of current source 105, and the source of PMOS transistor 102 is connected to one end of current source 106. The other ends of current sources 105 and 106 are connected to the power supply VCC. The drain of PMOS transistor 101 serves as the VOP output, and the drain of PMOS transistor 102 serves as the VON output. The drains of PMOS transistors 101 and 102 are connected to VSS (i.e., grounded) through loads 301 and 302, respectively. Variable capacitor 103 and variable resistor 104 are connected in parallel, and then connected across the sources of PMOS transistors 101 and 102. NMOS transistors 111 and 112 are complementary NMOS input differential pairs to those 101 and 102. The gate of NMOS transistor 111 serves as the VIN input, and the gate of NMOS transistor 112 serves as the VIP input. The source of NMOS transistor 111 is connected to one end of current source 117, and the other end of current source 117 is connected to VSS. The drain of NMOS transistor 111 is connected to the input of a current mirror composed of PMOS transistors 113 and 115. The source of NMOS transistor 112 is connected to one end of current source 118, and the other end of current source 118 is connected to VSS. The drain of NMOS transistor 112 is connected to the input of a current mirror composed of PMOS transistors 114 and 116. The output of the current mirror composed of PMOS transistors 113 and 115 is connected to the drain of PMOS transistor 102. The source of PMOS transistor 113 is connected to the power supply VCC, and the source of PMOS transistor 115 is also connected to the power supply VCC. The output terminal of the current mirror formed by PMOS transistors 114 and 116 is connected to the drain of PMOS transistor 101. The source of PMOS transistor 114 and the source of PMOS transistor 116 are both connected to the power supply VCC. Variable resistor 209 and variable capacitor 210 are connected in parallel, and then connected across the source of PMOS transistors 111 and 112.

[0040] 103 is an adjustable resistor, and 104 is an adjustable capacitor. 103 and 104 are used to adjust the poles and zeros of the circuit, respectively. The resistance value of 103 and the capacitance value of 104 can be adjusted to change the position of the poles and zeros, or the resistance value can be set to 0 to achieve a short circuit. 105 and 106 are current sources that provide bias current to 101 and 102, respectively. Changes in the input voltage are converted into changes in current through 101 and 102, and then flow through load resistors 301 and 302 to convert them into a differential output voltage.

[0041] Current sources 117 and 118 provide bias current to 111 and 112, respectively. Changes in the input voltage are converted into changes in current through 111 and 112, and then superimposed with the changes in current of 102 and 101 through current mirrors composed of PMOS transistors 113 and 115 and PMOS transistors 114 and 116, respectively. The current then flows through load resistors 301 and 302, and is converted into a differential output voltage.

[0042] 209 is an adjustable resistor, and 210 is an adjustable capacitor. 209 and 210 are used to adjust the poles and zeros of the circuit. The resistance value of 209 and the capacitance value of 210 can be adjusted to change the position of the poles and zeros, or the resistance value can be set to 0 to achieve a short circuit.

[0043] Section 300 includes load resistors 301 and 302, which are used to convert the current signal flowing into 300 into differential output voltages vop and von. This can be implemented using resistors or a resistor and an inductor connected in series.

[0044] Either PMOS or NMOS transistors can be used as the input pair. If NMOS transistors are used as the input pair, a complementary PMOS structure needs to be added accordingly. The principle of part 100 is as follows: 1) Input common-mode voltage is less than VCC- Where vthp is the turn-on voltage of PMOS transistor 101 or 102. At this time, NMOS transistors 111 and 112 are in the off state, and the corresponding PMOS transistors 101 and 102 are in the on state and work normally. Therefore, the circuit has the function of a continuous-time linear equalizer. 2) The input common-mode voltage is greater than vcc-vthn, where vthn is the turn-on voltage of the second transistor. At this time, PMOS transistors 101 and 102 are in the off state, and the corresponding NMOS transistors 111 and 112 are in the on state and work normally. Therefore, the circuit has the function of a continuous-time linear equalizer. 3) When the input common-mode voltage is less than vcc-|vthp| and greater than vcc-vthn, NMOS transistors 111 and 112 and PMOS transistors 101 and 102 are all in the conducting state and working normally. The gain of the circuit is the sum of the two, so the circuit also has the function of a continuous-time linear equalizer.

[0045] Current sources 105 and 106 provide bias current to 101 and 102 respectively to generate a stable DC operating point. The input AC voltage signal is converted into a current signal through 101 and 102 and flows into the load resistors 301 and 302 in 300 respectively to generate differential output voltages vop and von.

[0046] In section 200, the gate of NMOS transistor 203 is configured to be connected to a first bias voltage. The source of NMOS transistor 203 is connected to the source of NMOS transistor 111, and the drain of NMOS transistor 203 is connected to the input terminal of a current mirror composed of PMOS transistors 201 and 202. The output terminal of the current mirror composed of PMOS transistors 201 and 202 is connected to current source 105. The sources of PMOS transistors 201 and 202 are respectively connected to power supply VCC. The gate of PMOS transistor 204 is configured to be connected to a second bias voltage. The source of PMOS transistor 204 is connected to the source of PMOS transistor 101, and the drain of PMOS transistor 204 is connected to the input terminal of a current mirror composed of NMOS transistors 205 and 206. The input terminal of the current mirror, composed of NMOS transistors 205 and 206, is connected to the source of NMOS transistor 111 and the common node of current source 117. The sources of NMOS transistors 205 and 206 are connected to VSS. Section 200 includes part of the first current compensation circuit and part of the second current compensation circuit.

[0047] In section 201, the gate of NMOS transistor 213 is configured to receive a first bias voltage. The source of NMOS transistor 213 is connected to the common node of the source of NMOS transistor 112 and the current mirror 118. The drain of NMOS transistor 213 is connected to the input terminal of the current mirror composed of PMOS transistors 211 and 212. The output terminal of the current mirror composed of PMOS transistors 211 and 212 is connected to the common node of the current source 106 and PMOS transistor 102. The sources of PMOS transistors 211 and 212 are connected to the power supply VCC. The gate of PMOS transistor 214 is configured to receive a second bias voltage. The source of PMOS transistor 214 is connected to the common node of the source of PMOS transistor 102 and the current source 106. The drain of PMOS transistor 214 is connected to the input terminal of the current mirror composed of NMOS transistors 215 and 216. The output terminal of the current mirror formed by NMOS transistors 215 and 216 is connected to the common node of the source of NMOS transistor 112 and the current source 118. The sources of NMOS transistors 215 and 216 are connected to VSS. Section 201 includes part of the first current compensation circuit and part of the second current compensation circuit.

[0048] When the input common-mode voltage is less than VCC- When NMOS transistors 111 and 112 are off, PMOS transistors 101 and 102 are on, making the first bias voltage effective. NMOS transistors 203 and 213 are on, and the current provided by current source 117 enters 201 through the on-circuit NMOS transistor 203, and is then mirrored by 202 to the branch corresponding to 101 of the pair of transistors 101 and 102. The current provided by current source 118 enters 211 through the on-circuit NMOS transistor 213, and is then mirrored by 212 to the branch corresponding to 102 of the pair of transistors 101 and 102. This increases the total current in the branches 101 and 102 to twice the original current (assuming the original current is I, then the total current is 2I), thus maintaining constant transconductance and keeping the output common-mode point unchanged.

[0049] When the input common-mode voltage is greater than vcc-vthn, PMOS transistors 101 and 102 are in the off state, while the corresponding NMOS transistors 111 and 112 are in the on state and operate normally, making the second bias voltage effective. PMOS transistors 204 and 214 are turned on, and the current provided by current source 105 enters 205 through the turned-on PMOS transistor 204, and is then mirrored by 206 to the branch corresponding to 111 of the pair of transistors 111 and 112. The current provided by current source 106 enters 215 through the turned-on PMOS transistor 214, and is then mirrored by 216 to the branch corresponding to 112 of the pair of transistors 111 and 112. This increases the total current in the 111 and 112 branches to twice the original value (total current is 2I), thereby maintaining constant transconductance and keeping the output common-mode point unchanged.

[0050] When the input common-mode voltage is less than vcc-|vthp| and greater than vcc-vthn, NMOS transistors 111 and 112, and PMOS transistors 101 and 102 are all in the conducting state and working normally. The total current of the circuit is the sum of the two (the total current is 2I), thus maintaining a constant transconductance and keeping the output common-mode point unchanged.

[0051] In section 200, 201 and 202 have the same dimensions, and 205 and 206 have the same dimensions to ensure equal mirror current. In section 201, 211 and 212 have the same dimensions, and 215 and 216 have the same dimensions to ensure equal mirror current.

[0052] The 400 section is used to detect changes in the spectral components of the output common-mode voltage at the target frequency in real time and generate a feedback signal to adjust the compensation current or RC parameters through the 200 and 210. It can be implemented in one of the following three forms.

[0053] 1) Simulation Implementation Method Figure 4The 401 circuit shown is an analog implementation of part 400. The 401 circuit includes a bandpass filter, a low-pass filter, an error amplifier, and a control circuit connected in sequence. The bandpass filter extracts the spectral component of the output common-mode voltage at the target frequency; the low-pass filter filters the spectral component; the error amplifier calculates the voltage difference between the filtered spectral component and the reference voltage, outputting the voltage difference Verr. The control circuit then generates signals based on the voltage difference Verr to adjust the currents of current sources 117 and 118, the resistances of resistors 103 and 109, the capacitances of capacitors 104 and 110, and the impedances of loads 301 and 302.

[0054] For example, current source 117 and current source 118 are voltage-controlled current sources, and the magnitude of the output current is determined by the voltage signal generated by the control circuit.

[0055] A typical implementation is to use a MOS transistor structure to realize a voltage-controlled current source. For example, Verr is connected to the gate of an NMOS transistor. When the voltage of Verr increases, the Vgs of the NMOS transistor (i.e., Verr) increases. The relationship between current and voltage is I = unCox(W / L)(Vgs-Vth). 2 / 2, meaning the current magnitude is positively correlated with Vgs.

[0056] The resistors and capacitors are voltage-controlled resistors, typically implemented using MOSFETs. For example, an NMOS resistor operating in the linear region has a resistance of R = 1 / (unCox(W / L)(Vgs-Vth-Vds / 2)), where Vgs is the gate voltage Verr at the control terminal. The typical implementation of capacitors is also a MOS capacitor. When the gate voltage (Verr) changes, the gate-source capacitance and gate-drain capacitance change accordingly. This is a common voltage-controlled capacitor method in PLLs.

[0057] In summary, when the filtered spectral components are greater than the reference voltage, the voltage difference Verr increases, thus it can be used to increase the current, decrease the resistance, or increase the capacitance; when the filtered spectral components are less than the reference voltage, the voltage difference Verr is low, and Vgs decreases, thus it can be used to decrease the current, increase the resistance, or decrease the capacitance; when the filtered spectral components are equal to the reference voltage, the error amplifier outputs an intermediate level, corresponding to the feedback lockout condition.

[0058] Figure 5 This is an example of a circuit diagram for a 401 microcontroller. Figure 5As shown, the function of 4011 is the same as that of the aforementioned bandpass filter. 4011 includes amplifier U1, amplifier U2, resistors R1 and R2, and capacitors C1 and C2. Amplifier U1 converts the output common-mode voltage to a single-ended voltage. One end of resistor R1 is connected to the output of amplifier U1, and the other end of resistor R1 is connected to one end of capacitors C1 and C2 respectively. The other end of capacitor C2 is connected to the non-inverting input of amplifier U2, and the other end of capacitor C1 is connected to the output of amplifier U2. Resistor R2 is connected across the non-inverting input and output of amplifier U2, and the inverting input of amplifier U2 is connected to a reference voltage. The function of 4012 is the same as that of the aforementioned low-pass filter. 4012 includes resistor R3 and capacitor C3. One end of resistor R3 is connected to the output of amplifier U2, and the other end of resistor R3 is connected to one end of capacitor C3 and the non-inverting input of amplifier U3 respectively. The other end of capacitor C3 is grounded. The function of 4013 is the same as that of the error amplifier described above. 4013 includes an inverting input terminal of amplifier U3 configured to connect to a reference voltage. The output terminal of amplifier U3 is connected to control circuit 4014. The function of control circuit 4014 is the same as that of the aforementioned control circuit.

[0059] 2) Digital Implementation Method Figure 6 The diagram shows the digital implementation of part 400. 402 includes a signal sampling module, a digital filtering module, a control logic module, and an analog-to-digital converter module. The signal sampling module samples the output common-mode voltage; the digital filtering module calculates the digital value of the spectral component of the output common-mode voltage at the target frequency; the control logic module generates a control word based on the deviation between the digital value of the spectral component at the target frequency and the digital value corresponding to the reference voltage; and the analog-to-digital converter module converts the control word into an analog control signal (corresponding to the aforementioned adjustment signal). The analog control signal is used to adjust the current of current sources 117 and 118, the resistance values ​​of resistors 103 and 109, the capacitance values ​​of capacitors 104 and 110, and the impedance of loads 301 and 302.

[0060] The control logic module decrements the control word by 1 when the digital value of the spectral component at the target frequency is greater than the digital value corresponding to the reference voltage, and increments the control word by 1 otherwise.

[0061] The digital value corresponding to the reference voltage corresponds to the ideal value during design. For example, a control word of 10000 corresponds to this design value, representing a fixed set of linear equalization characteristics. Therefore, when the control word obtained through the Discrete Fourier Transform (DFT) is higher than 10000, the control signal is decreased, and the values ​​of the digital control resistor, capacitor, and resistor are changed; when the control word obtained through the DFT is lower than 10000, the control signal is increased. Ultimately, through feedback, the control word obtained through the DFT is brought closer to the design value of 10000.

[0062] The signal sampling module is used to sample the output voltage of the equalizer. The sampling frequency can be the same as the signal transmission frequency. For example, if the signal transmission frequency is 1Gbps, then a frequency of 1GHz can be used for sampling.

[0063] Figure 7 This is a circuit diagram of the signal sampling module, such as... Figure 7 As shown, the circuit includes amplifier U4, a D flip-flop, and a serial-to-parallel converter. Amplifier U4 is used to convert the output common-mode voltage to a single-ended voltage. The clk of the D flip-flop is a clock signal with the same transmission rate.

[0064] 3) Digital Implementation Method Figure 8 The diagram shows the digital implementation of part 400. 403 includes a signal sampling module, a digital filtering module, and a control logic module. The signal sampling module samples the output common-mode signal; the digital filtering module calculates the deviation between the digital value of the spectral component at the target frequency and the digital value corresponding to the reference voltage; the control logic module generates a control word (corresponding to an adjustment signal) based on the deviation between the digital value of the spectral component at the target frequency and the digital value corresponding to the reference voltage. The control word is used to adjust the current of current sources 117 and 118, the resistance values ​​of resistors 103 and 109, the capacitance values ​​of capacitors 104 and 110, and the impedance of loads 301 and 302.

[0065] For example, resistors 103 and 109, as well as the resistors in loads 301 and 302, can be a controllable resistor array. This array consists of multiple resistors with different resistance values ​​and switches connected in parallel or series. The state of these switches is controlled by a digital control signal; for example, turning on some switches or connecting certain resistors in parallel results in an equivalent resistance value that changes with the digital control signal. The switches can be implemented using MOSFETs, and the digital control signal can be used as a gate signal to control the MOSFETs' on / off state.

[0066] Similarly, capacitors 104 and 110, as well as the capacitors in loads 301 and 302 (if any), can be a controllable capacitor array. A controllable capacitor array consists of multiple capacitors with different capacitance values ​​connected in parallel or series, each equipped with a switch. The capacitance values ​​are changed by controlling the state of the multiple switches using digital control signals.

[0067] Current sources 117 and 118 can be formed by multiple current sources with switches connected in parallel. The switching on and off of the switches is controlled by digital control signals to regulate the output current of current sources 117 and 118. For example, the output current I of current sources 117 and 118 is I = D0*I0 + D1*I1 + D2*I2, where D0, D1, and D2 are digital control quantities, taking values ​​of 1 or 0, and I0~I2 represent the current of a single current source connected in parallel.

[0068] Figure 3 The equalizer shown maintains the original zero-pole distribution and equalization characteristics, ensuring stability in both output level and frequency domain performance, and preserving the BER and eye performance of high-speed links. Figure 1 Consistency, significantly improving system stability and robustness.

[0069] Taking MIPI input as an example, its common-mode input voltage ranges from 70mV to 300mV. This voltage is less than the threshold voltage of the NMOS transistors, so NMOS transistors 111 and 112 cannot operate. However, PMOS transistors 101 and 102, as complementary structures, can operate normally. Therefore, the PMOS branch can conduct normally. Furthermore, due to the introduction of the current compensation branch, the current in the PMOS branch increases to twice its original value, and the circuit gain and common-mode output voltage also increase to twice their original value. By introducing a 400Ω section, the adjustable resistor, load resistor, current source, etc., are adjusted according to the output common-mode voltage. This not only achieves continuous-time linear balance of the circuit but also maintains the peak position of the output common-mode voltage and the gain while keeping the total current constant through the dual mechanisms of current mirror compensation and feedback detection. For example, if the linear balance gain at 1GHz is 10dB, then when the input changes, the feedback adjustment of the loop keeps the frequency and gain constant at 1GHz and 10dB, respectively. When the current source of the 400 section is changed, the gain and output common-mode voltage of the equalizer will change, but by adjusting the resistance, capacitor or current feedback, the overall linear equalization characteristics can still be maintained constant.

[0070] Taking LVDS input as an example, its common-mode input voltage is 1.25V. This voltage is greater than the threshold voltage of the NMOS transistor and less than the threshold voltage of the PMOS transistor. Therefore, both the NMOS and PMOS transistors can conduct normally, and their gain is the sum of the PMOS and NMOS branches. At this time, 203, 204, 213, and 214 are turned off, and the current branches 200 and 210 used for compensation are turned off. The circuit reverts to an equalizer composed of 100 and 300. The circuit gain and common-mode output voltage are the sum of the NMOS and PMOS branches, which is twice that when a single transistor is on. By introducing the 400 section, the adjustable resistor, load resistor, current source, etc. are adjusted according to the output common-mode voltage. This not only achieves continuous-time linear equalization of the circuit, but also maintains the peak position (i.e., frequency) and gain of the output common-mode voltage while keeping the total current constant through the dual mechanisms of current mirror compensation and feedback detection.

[0071] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0072] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0073] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0074] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0075] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0076] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0077] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0079] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An equalizer, characterized in that, It includes a first conversion circuit, a second conversion circuit, a circuit adjustment unit, a power supply, a first current compensation circuit, a second current compensation circuit, a third conversion circuit, and a control circuit; The first conversion circuit is configured to operate when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. When the condition is met, the input common-mode voltage is converted into a change in differential current; The second conversion circuit is configured to, when the common-mode voltage meets the operating conditions of the second conversion circuit, convert... The change in input common-mode voltage is converted into differential current. The power supply is configured to drive the first conversion circuit and the second conversion circuit; The first current compensation circuit is configured to perform current compensation on the first conversion circuit when the common-mode voltage input to the equalizer only meets the operating conditions of the first conversion circuit. The second current compensation circuit is configured to perform current compensation on the second conversion circuit when the common-mode voltage only meets the operating conditions of the second conversion circuit. The third conversion circuit is configured to convert the change in the differential current into an output common-mode voltage. The control circuit is configured to calculate the voltage difference between the spectral component at the target frequency and the reference voltage based on the output common-mode voltage, and generate an adjustment signal based on the voltage difference to adjust the adjustable components in the first conversion circuit, the second conversion circuit and the third conversion circuit, so that the peak frequency and peak gain of the equalizer are constant. The second conversion circuit is a complementary circuit to the first conversion circuit; the input terminal of the common-mode voltage of the first conversion circuit and the input terminal of the common-mode voltage of the second conversion circuit are connected to each other as the input terminal of the input common-mode voltage; the output terminal of the third conversion circuit is connected to each other as the output terminal of the equalizer; the operating conditions of the first conversion circuit and the operating conditions of the second conversion circuit are set to ensure that at least one circuit can meet the operating conditions at any time.

2. The equalizer as described in claim 1, characterized in that, Also includes: The circuit adjustment unit is configured to adjust the zero and pole positions of the first conversion circuit, and to adjust the... The zero and pole locations of the second conversion circuit; The control circuit is further configured to adjust the adjustable element in the circuit adjustment unit according to the adjustment signal.

3. The equalizer as described in claim 1, characterized in that, The first conversion circuit includes a first differential pair transistor and two first current sources; the first differential pair transistor includes two first transistors; each first current source is configured to provide a bias current to the corresponding first transistor. The gate of each first transistor serves as one of the common-mode voltage input terminals of the first conversion circuit; The drain terminal of each first transistor serves as one of the differential current output terminals of the first conversion circuit; One end of each first current source is connected to the source terminal of a corresponding first transistor, and the other end of each first current source... One end is connected to the power supply terminal of the power source.

4. The equalizer as described in claim 3, characterized in that, The second conversion circuit includes two first current mirrors, a second differential pair transistor, and two second current sources; the second differential pair transistor includes two second transistors; each second current source is configured to provide a bias current to the corresponding second transistor. The gate of each second transistor serves as one of the common-mode voltage input terminals of the second conversion circuit; The drain terminal of each second transistor is connected to the input terminal of each first current mirror; the output terminal of each first current mirror serves as one of the differential current output terminals of the second conversion circuit. One end of each second current source is connected to the source terminal of a corresponding second transistor; the other end of each second current source... One end connects to the public end; The source terminal of each current mirror is connected to the power supply terminal of the power source; The first differential pair and the second differential pair are complementary.

5. The equalizer as described in claim 4, characterized in that, The first current compensation circuit includes: a third current mirror, a fourth current mirror, a first bias transistor, and a second bias transistor; The input terminal of the third current mirror is connected to the drain terminal of the first bias transistor, and the output terminal of the third current mirror is connected to the source terminal of a corresponding first transistor. The input terminal of the fourth current mirror is connected to the drain terminal of the second bias transistor, and the output terminal of the fourth current mirror is connected to the source terminal of a corresponding first transistor. The source terminal of the first bias transistor is connected to the source terminal of a corresponding second transistor; The gate terminal of the first bias transistor is configured to receive a first bias signal; The first bias signal is valid when the common-mode voltage input to the equalizer meets the operating conditions of the first conversion circuit. The source terminal of the second bias transistor is connected to the source terminal of a corresponding second transistor; The gate terminal of the second bias transistor is configured to receive the first bias signal; The source terminals of the third current mirror and the fourth current mirror are respectively connected to the power supply terminal of the power source.

6. The equalizer as described in claim 5, characterized in that, The second current compensation circuit includes: a fifth current mirror, a sixth current mirror, a third bias transistor, and a fourth bias transistor; The input terminal of the fifth current mirror is connected to the drain terminal of the third bias transistor, and the output terminal of the fifth current mirror is connected to the source terminal of a corresponding second transistor. The source terminal of the third bias transistor is connected to the source terminal of a corresponding first transistor. The gate of the third bias transistor is configured to receive the second bias signal; The second bias signal is valid when the common-mode voltage input to the equalizer meets the operating conditions of the second conversion circuit. The input terminal of the sixth current mirror is connected to the drain terminal of the fourth bias transistor, and the output terminal of the sixth current mirror is connected to the source terminal of the corresponding second transistor. The source terminal of the fourth bias transistor is connected to the source terminal of a first transistor corresponding to the output terminal of the fourth current mirror. The gate terminal of the fourth bias transistor is configured to receive the second bias signal; The source terminals of the fifth current mirror and the sixth current mirror are respectively connected to the common terminal.

7. The equalizer as described in claim 1, characterized in that, The control circuit includes a bandpass filter, a low-pass filter, an error amplifier, and a control circuit. The bandpass filter is connected to the output of the equalizer and is configured to extract the spectral component at the target frequency based on the output common-mode voltage. The low-pass filter is connected to the band-pass filter and is configured to filter the spectral components. The error amplifier is connected to the low-pass filter and is configured to calculate the voltage difference between the spectral component and the reference voltage. The control circuit is connected to the adjustable elements in the circuit adjustment unit and the third conversion circuit, respectively, and is configured to generate an adjustment signal based on the voltage difference to adjust the adjustable elements in the circuit adjustment unit and the third conversion circuit so that the peak frequency and peak gain of the equalizer are constant.

8. The equalizer as described in claim 1, characterized in that, The control circuit includes a sampling module, a digital filtering module, a control logic module, and a digital-to-analog converter connected in sequence. The sampling module is connected to the output terminal of the equalizer and is configured to sample the output common-mode voltage. The digital filtering module is configured to filter the output common-mode voltage to obtain the digital quantity of the spectral component of the output common-mode voltage at the target frequency. The control logic module is configured to generate a digital adjustment signal based on the voltage difference between the digital quantity of the spectral component and the digital quantity corresponding to the reference voltage. The digital-to-analog converter module is configured to convert the digital adjustment signal into the adjustment signal.

9. The equalizer as described in claim 1, characterized in that, The control circuit includes a sampling module, a digital filtering module, and a control logic module connected in sequence. The sampling module is configured to sample the output common-mode voltage; The digital filtering module is configured to filter the output common-mode voltage to obtain the digital quantity of the spectral component of the output common-mode voltage signal at the target frequency. The control logic module is configured to generate the adjustment signal based on the difference between the digital value of the spectral component and the digital value corresponding to the reference voltage.

10. The equalizer as described in claim 4, characterized in that, The circuit adjustment unit includes a first adjustable resistor and a first adjustable capacitor connected in parallel, as well as a second adjustable resistor and a second adjustable capacitor connected in parallel. The first adjustable resistor and the first adjustable capacitor connected in parallel are connected across the common node of each first current source and a corresponding first transistor. The parallel second adjustable resistor and second adjustable capacitor are connected across the common node of each second current source and the corresponding second transistor.

Images