Semiconductor device

Abstract

A semiconductor device includes: a cell array region including unit memory cells two-dimensionally arranged along a first direction and a second direction intersecting each other; a first peripheral circuit region including first unit peripheral cells arranged along the second direction, the first peripheral circuit region and the cell array region being arranged along the first direction; and a second peripheral circuit region including second unit peripheral cells arranged along a second direction, the first peripheral circuit region being interposed between the cell array region and the second peripheral circuit region, a first unit cell height of each of the unit memory cells and a second unit cell height of each of the first unit peripheral cells are equal to each other, and a third unit cell height of each of the second unit peripheral cells is smaller than the second unit cell height.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0123691, filed on September 11, 2024, with the Korean Intellectual Property Office, and all benefits thereof, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices. More specifically, this disclosure relates to semiconductor devices that include SRAM (Static Random Access Memory) elements and / or logic elements. Background Technology

[0004] Semiconductor devices have gained attention as important components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that perform computational processing of logical data, and hybrid semiconductor devices that include both memory elements and logic elements.

[0005] With the rapid development of the electronics industry, the demands on the characteristics of semiconductor devices are increasing. For example, there is a growing need for high reliability, high speed, and / or versatility in semiconductor devices. To meet these required characteristics, the structures within semiconductor devices are becoming increasingly complex and highly integrated. Summary of the Invention

[0006] Some example embodiments of this disclosure provide semiconductor devices with improved performance and / or integration.

[0007] The exemplary embodiments disclosed herein are not limited to those mentioned herein, and other exemplary embodiments not mentioned may be clearly understood by those skilled in the art from the following description.

[0008] According to an example embodiment of this disclosure, a semiconductor device may include: a cell array region including a plurality of unit memory cells arranged in two dimensions along a first direction and a second direction that intersect each other; a first peripheral circuit region including a plurality of first unit peripheral cells arranged along a second direction, the first peripheral circuit region and the cell array region being arranged along the first direction; and a second peripheral circuit region including a plurality of second unit peripheral cells arranged along the second direction, the first peripheral circuit region being interposed between the cell array region and the second peripheral circuit region, wherein the height of a first unit cell in the second direction of each of the unit memory cells and the height of a second unit cell in the second direction of each of the first unit peripheral cells are equal to each other, and wherein the height of a third unit cell in the second direction of each of the second unit peripheral cells is less than the height of the second unit cell.

[0009] According to an example embodiment of this disclosure, a semiconductor device may be provided, comprising a memory cell, an upper peripheral cell, and a first lower peripheral cell arranged sequentially along a first direction. The semiconductor device may include: a substrate; a first active pattern and a second active pattern on a first region of the substrate, wherein the upper peripheral cell is provided in the first region, the first active pattern and the second active pattern extend in the first direction and are spaced apart from each other in a second direction intersecting the first direction; a first gate structure on the first active pattern and the second active pattern and extending in the second direction; a first lower active pattern and a second lower active pattern on a second region of the substrate, wherein the first lower peripheral cell is provided in the second region, the first lower active pattern and the second lower active pattern extend in the first direction and are spaced apart from each other in the second direction; and a second gate structure on the first lower active pattern and the second lower active pattern and extending in the second direction, wherein the first unit cell height of the memory cell in the second direction and the second unit cell height of the upper peripheral cell in the second direction are equal to each other, and wherein the first active pattern overlaps with at least a portion of the first lower active pattern and at least a portion of the second lower active pattern in the first direction.

[0010] According to an example embodiment of this disclosure, a semiconductor device may be provided, comprising a first region and a second region arranged along a first direction, and a third region between the first region and the second region. The semiconductor device may include: a substrate; a first active pattern and a second active pattern on a first portion of the substrate corresponding to the first region, the first active pattern and the second active pattern extending in a first direction and arranged along a second direction intersecting the first direction; a first gate structure on the first active pattern and the second active pattern and extending in the second direction; a first lower active pattern to a fourth lower active pattern on a second portion of the substrate corresponding to the second region, the first lower active pattern to the fourth lower active pattern extending in the first direction and arranged sequentially along the second direction; a second gate structure on the first lower active pattern to the fourth lower active pattern and extending in the second direction; and a first connection pattern on a third portion of the substrate corresponding to the third region, the first connection pattern connecting the first active pattern to the fourth active pattern. An upper active pattern, a first lower active pattern, and a second lower active pattern are interconnected; a second connection pattern on a third portion of a substrate corresponding to a third region, the second connection pattern connecting the second upper active pattern, the third lower active pattern, and the fourth lower active pattern are interconnected; a first power wiring extending in a first direction across the first region to the third region and configured to receive a first power voltage; and a second power wiring extending in a first direction across the first region to the third region and configured to receive a second power voltage different from the first power voltage, wherein each of the first upper active pattern, the first lower active pattern, and the fourth lower active pattern includes a channel region of an NFET, and wherein each of the second upper active pattern, the second lower active pattern, and the third lower active pattern includes a channel region of a PFET. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become clearer from a detailed description of some exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 This is an example block diagram illustrating a semiconductor device according to some example embodiments.

[0013] Figure 2 This is a conceptual plan view illustrating a semiconductor device according to some example embodiments.

[0014] Figure 3 It is shown Figure 2 Example circuit diagram of a unit memory cell.

[0015] Figure 4 It is shown Figure 2 Example layout diagram of semiconductor devices.

[0016] Figure 5A and Figure 5B They are along Figure 4 A schematic cross-sectional view taken from lines A1-A1 and B1-B1.

[0017] Figure 6A and Figure 6B They are along Figure 4 A schematic cross-sectional view taken from lines A2-A2 and B2-B2.

[0018] Figure 7A and Figure 7B They are along Figure 4 A schematic cross-sectional view taken from lines A3-A3 and B3-B3.

[0019] Figure 8 It is shown Figure 4 A partial layout diagram of the active pattern.

[0020] Figures 9 to 12 These are other various example layout diagrams used to illustrate semiconductor devices according to some example embodiments.

[0021] Figure 13 This is a conceptual plan view illustrating a semiconductor device according to some example embodiments.

[0022] Figure 14 and Figure 15 It is shown Figure 13 Various example layout diagrams of semiconductor devices.

[0023] Figure 16 This is a conceptual plan view illustrating a semiconductor device according to some example embodiments.

[0024] Figure 17 It is shown Figure 16 Example layout diagram of semiconductor devices. Detailed Implementation

[0025] Although the terms “same,” “equal,” or “identical” are used in the description of the example embodiments, it should be understood that some inaccuracies may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element within a range of expected manufacturing or operational tolerances (e.g., ±10%).

[0026] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include manufacturing or operational tolerances (e.g., ±10%) around said numerical values. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather the latitude of the shape is within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical values ​​or shapes.

[0027] As used herein, expressions such as “one of…”, “any one of…”, and “at least one of…” modify the entire list of elements when preceding it and do not modify any individual element in the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0028] In the following text, see references Figures 1 to 17 This describes a semiconductor device according to some example embodiments.

[0029] Figure 1 This is an example block diagram illustrating a semiconductor device according to some example embodiments.

[0030] refer to Figure 1 The semiconductor device according to some example embodiments includes a memory cell array 1, control logic 2, a row decoder 3, and input / output circuitry 4.

[0031] Memory cell array 1 may include multiple memory cells, each storing 1 bit of data. The following description illustrates an example where each memory cell is implemented as SRAM (Static Random Access Memory). However, this is merely an example. In another example, each memory cell may be implemented as one of a variety of other memory devices, such as DRAM (Dynamic Random Access Memory), NAND flash memory, NOR flash memory, RRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random Access Memory), PRAM (Phase Change Random Access Memory), or MRAM (Magnetic Random Access Memory).

[0032] Control logic 2 can receive commands (CMD), addresses (ADDR), and clock (CLK) from external devices (e.g., a host, a CPU (Central Processing Unit), or a memory controller). Commands (CMD) may include instructions indicating operations on memory cell array 1. Addresses (ADDR) may include a row address (ADDR_R) indicating the row of the memory cell to be operated on and a column address (ADDR_C) indicating the column of the memory cell to be operated on. Control logic 2 can provide the row address (ADDR_R) to the row decoder 3 and the column address (ADDR_C) to the input / output circuitry 4. Control logic 2 can control the operation of memory cell array 1 based on the clock (CLK) received from the external device.

[0033] The row decoder 3 can be connected to the memory cell array 1 via multiple word lines WL. The row decoder 3 can select at least one of the multiple word lines WL connected to the memory cell array 1 based on the row address ADDR_R provided from the control logic 2. For example, the row decoder 3 can apply a voltage to the selected word line WL to activate the selected word line WL.

[0034] The input / output circuit 4 can be connected to the memory cell array 1 via multiple bit lines BL and multiple complementary bit lines / BL. In some example embodiments, the input / output circuit 4 may include a column decoder, a sense amplifier, an input / output (I / O) buffer, a latch, and a write driver.

[0035] The column decoder of input / output circuit 4 can select at least one of a plurality of bit lines BL and / or at least one of a plurality of complementary bit lines / BL based on the column address ADDR_C provided from control logic 2. For example, the column decoder can apply a voltage to the selected bit line BL and / or the selected complementary bit line / BL to activate the selected bit line BL and / or the selected complementary bit line / BL.

[0036] When a write operation is performed in response to the command CMD and address ADDR, input / output circuit 4 can receive data DATA from an external device. The input / output buffer of input / output circuit 4 can temporarily store the received data DATA. The data DATA temporarily stored in the input / output buffer can be written to memory cell array 1 via the write driver of input / output circuit 4.

[0037] When a read operation is performed in response to the command CMD and address ADDR, the sense amplifier of input / output circuit 4 can detect and amplify the data DATA stored in memory cell array 1. The input / output buffer of input / output circuit 4 can temporarily store the data DATA detected by the sense amplifier. The data DATA temporarily stored in the input / output buffer can be provided to the external device in response to a request from the external device.

[0038] Figure 2 This is a conceptual plan view illustrating a semiconductor device according to some example embodiments. Figure 3 It is shown Figure 2 Example circuit diagram of a unit memory cell. Figure 4 It is shown Figure 2 Example layout diagram of semiconductor devices. Figure 5A and Figure 5B They are along Figure 4 A schematic cross-sectional view taken from lines A1-A1 and B1-B1. Figure 6A and Figure 6B They are along Figure 4 A schematic cross-sectional view taken from lines A2-A2 and B2-B2. Figure 7A and Figure 7B They are along Figure 4 A schematic cross-sectional view taken from lines A3-A3 and B3-B3. Figure 8 It is shown Figure 4 A partial layout diagram of the active pattern.

[0039] refer to Figure 1 and Figure 2 A semiconductor device according to some example embodiments includes a memory cell region (CELL) and a peripheral circuit region (PERI).

[0040] The memory cell region (CELL) may include a plurality of unit memory cells 10 arranged in a two-dimensional manner. For example, the plurality of unit memory cells 10 may be arranged in a matrix along a first direction X and a second direction Y that intersect each other. The memory cell region (CELL) may include... Figure 1 In memory cell array 1.

[0041] A peripheral circuit region (PERI) can be formed around a memory cell region (CELL). Control elements and dummy elements can be formed in the PERI to control the operation of the unit memory cell 10 formed in the memory cell region (CELL). For example, the PERI may include elements as used above. Figure 1 At least some of the control logic 2, line decoder 3, and / or input / output circuits 4.

[0042] In some example embodiments, the peripheral circuitry region PERI may include a first region I and a second region II arranged from the memory cell region CELL along a first direction X. The first region I and the second region II may be arranged sequentially from the memory cell region CELL. For example, the first region I may be located between the memory cell region CELL and the second region II in the first direction X.

[0043] The first region I may include a plurality of first unit peripheral units 20 arranged along the second direction Y. The second region II may include a plurality of second unit peripheral units 30 arranged along the second direction Y.

[0044] In some example embodiments, the first region I and the second region II may be included in Figure 1 In the input / output circuit 4. For example, the first region I and the second region II can be electrically connected to the memory cell region CELL via bit lines BL and complementary bit lines / BL extending in the first direction X.

[0045] Each of the unit memory cells 10 may have a first unit cell height CH1. Each of the first unit peripheral cells 20 may have a second unit cell height CH2. Each of the second unit peripheral cells 30 may have a third unit cell height CH3. In this respect, cell height means the length in the second direction Y of each of the unit memory cells 10 that are repeatedly arranged in the second direction Y, the length in the second direction Y of each of the first unit peripheral cells 20 that are repeatedly arranged in the second direction Y, and the length in the second direction Y of each of the second unit peripheral cells 30 that are repeatedly arranged in the second direction Y.

[0046] In some example embodiments, the first unit cell height CH1 and the second unit cell height CH2 can be equal to each other. In such cases, the number of unit memory cells 10 and the number of first unit peripheral cells 20 can have a one-to-one correspondence.

[0047] In some example embodiments, the height of the third unit cell CH3 can be less than the height of the second unit cell CH2. In such cases, the number of the first unit peripheral cells 20 and the number of the second unit peripheral cells 30 can have a correspondence of 1 to N. In this respect, N is a rational number greater than 1.

[0048] Reference Figures 3 to 8 The first unit peripheral unit 20 and the second unit peripheral unit 30 are described in more detail.

[0049] refer to Figures 1 to 3 In a semiconductor device according to some example embodiments, each unit memory cell 10 includes a pair of inverters INV1 and INV2, which are connected in parallel with each other and disposed at a power node V. DD and grounding node V SS And connected between and to power node V DD and grounding node V SS , and a first transfer transistor PS1 and a second transfer transistor PS2 respectively connected to the output nodes of inverters INV1 and INV2.

[0050] To configure a latching circuit, the input node of the first inverter INV1 can be connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 can be connected to the output node of the first inverter INV1.

[0051] The first inverter INV1 may include components connected in series and located at power node V. DD and grounding node V SS And connected between and to power node V DD and grounding node V SS The first pull-up transistor PU1 and the first pull-down transistor PD1. The second inverter INV2 may include transistors connected in series with each other and disposed at power node V. DD and grounding node V SS And connected between and to power node V DD and grounding node V SS The first pull-up transistor PU1 and the second pull-down transistor PD2 are provided. Each of the first pull-up transistor PU1 and the second pull-up transistor PU2 can be a P-type field-effect transistor (PFET), and each of the first pull-down transistor PD1 and the second pull-down transistor PD2 can be an N-type field-effect transistor (NFET).

[0052] The first transfer transistor PS1 can connect the bit line BL to the output node of the first inverter INV1. The second transfer transistor PS2 can connect the complementary bit line / BL to the output node of the second inverter INV2. The gates of the first transfer transistor PS1 and the second transfer transistor PS2 can be connected to the word line WL.

[0053] refer to Figures 1 to 8 A semiconductor device according to some example embodiments includes a substrate 100, a field insulating film 105, first active patterns A11 to A14, second active patterns A21 and A22, third active patterns A31 to A34, a first gate structure G1, a second gate structure G2, a third gate structure G3, a first source / drain region SD1, a second source / drain region SD2, a third source / drain region SD3, a source / drain contact 180, an interlayer insulating film 190, and a wiring structure WS.

[0054] The substrate 100 may be made of or comprise bulk silicon or SOI (silicon-on-insulator). In some example embodiments, the substrate 100 may be implemented as a silicon substrate, or may be made of or comprise materials other than silicon, such as silicon germanium, SGOI (silicon germanium-on-insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In some example embodiments, the substrate 100 may include a base substrate and an epitaxial layer formed on the base substrate.

[0055] The first memory cell 11 and the second memory cell 12 can be formed on the substrate 100 of the memory cell region CELL. The first memory cell 11 and the second memory cell 12 can be arranged sequentially along the second direction Y. The first memory cell 11 and the second memory cell 12 can correspond to Figure 2 Unit memory cell 10.

[0056] First active patterns A11 to A14 can be formed on the substrate 100 of the memory cell region CELL. For example, the first active patterns A11 to A14 can be formed in each of the first memory cell 11 and the second memory cell 12. The first active patterns A11 to A14 can be spaced apart from each other, can be parallel to each other, and can extend in the first direction X. For example, the first active patterns A11 to A14 can include a first memory active pattern A11, a second memory active pattern A12, a third memory active pattern A13, and a fourth memory active pattern A14 that extend in the first direction X and are arranged sequentially in the second direction Y.

[0057] Each of the first memory cell 11 and the second memory cell 12 may include an NFET region and a PFET region that are adjacent to each other in the second direction Y. For example, each of the first memory active pattern A11 and the fourth memory active pattern A14 may be used as a channel region for a PFET. Each of the second memory active pattern A12 and the third memory active pattern A13 may be used as a channel region for an NFET. Each of the first memory cell 11 and the second memory cell 12 may have a first unit cell height CH1 in the second direction Y.

[0058] In some example embodiments, the first memory cell 11 and the second memory cell 12 may have a face-to-face symmetrical relationship around a plane (XZ plane) intersecting the second direction Y. For example, the first active patterns A11 to A14 of the first memory cell 11 may be arranged sequentially along the second direction Y, while the first active patterns A11 to A14 of the second memory cell 12 may be arranged sequentially along a direction opposite to the second direction Y -Y.

[0059] The first upper peripheral unit 21 and the second upper peripheral unit 22 can be formed on the substrate 100 of the first region I of the peripheral circuit region PERI. The first upper peripheral unit 21 and the second upper peripheral unit 22 can be arranged sequentially along the second direction Y. In some example embodiments, the first upper peripheral unit 21 and the first memory unit 11 can be arranged along the first direction X, while the second upper peripheral unit 22 and the second memory unit 12 can be arranged along the first direction X. The first upper peripheral unit 21 and the second upper peripheral unit 22 can correspond to Figure 2 The first unit is the outermost unit 20.

[0060] Second active patterns A21 and A22 can be formed on the substrate 100 of the first region I. For example, second active patterns A21 and A22 can be formed within each of the first upper peripheral unit 21 and the second upper peripheral unit 22. Second active patterns A21 and A22 can be spaced apart from each other, can be parallel to each other, and can extend in the first direction X. For example, second active patterns A21 and A22 can include a first active pattern A21 and a second active pattern A22 that extend in the first direction X and are sequentially arranged in the second direction Y.

[0061] Each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may include an NFET region and a PFET region that are adjacent to each other in the second direction Y. For example, the first active pattern A21 may be used as the channel region of the NFET, and the second active pattern A22 may be used as the channel region of the PFET. Each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may have a second unit cell height CH2 in the second direction Y.

[0062] In some example embodiments, the first upper peripheral unit 21 and the second upper peripheral unit 22 may be in a face-to-face symmetrical relationship around a plane (XZ plane) intersecting the second direction Y. For example, the second active patterns A21 and A22 of the first upper peripheral unit 21 may be arranged sequentially along the second direction Y, while the second active patterns A21 and A22 of the second upper peripheral unit 22 may be arranged sequentially along a direction opposite to the second direction Y -Y.

[0063] In some example embodiments, the second unit cell height CH2 of each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may be equal to the first unit cell height CH1 of each of the first memory unit 11 and the second memory unit 12. In this disclosure, "equal" means not only "completely equal", but also includes minor differences that may arise due to process allowances, etc.

[0064] The first lower peripheral unit 31 to the fourth lower peripheral unit 34 can be formed on the substrate 100 of the second region II of the peripheral circuit region PERI. The first lower peripheral unit 31 to the fourth lower peripheral unit 34 can be arranged sequentially along the second direction Y. In some example embodiments, the first lower peripheral unit 31, the second lower peripheral unit 32, and the first upper peripheral unit 21 can be arranged along the first direction X, while the third lower peripheral unit 33, the fourth lower peripheral unit 34, and the second upper peripheral unit 22 can be arranged along the first direction X. The first lower peripheral unit 31 to the fourth lower peripheral unit 34 can correspond to Figure 2 The second unit, peripheral unit 30.

[0065] The third active patterns A31 to A34 can be formed on the substrate 100 of the second region II. For example, the third active patterns A31 to A34 can be formed within the first lower peripheral unit 31 to the fourth lower peripheral unit 34. The third active patterns A31 to A34 can be spaced apart from each other and extend in a parallel manner in the first direction X. For example, the third active patterns A31 to A34 can include a first lower active pattern A31, a second lower active pattern A32, a third lower active pattern A33, and a fourth lower active pattern A34 that extend in the first direction X and are arranged sequentially in the second direction Y.

[0066] Each of the first lower peripheral cells 31 to the fourth lower peripheral cells 34 may include an NFET region and a PFET region that are adjacent to each other in the second direction Y. For example, each of the first lower active pattern A31 and the fourth lower active pattern A34 may be used as a channel region for an NFET, and each of the second lower active pattern A32 and the third lower active pattern A33 may be used as a channel region for a PFET. Each of the first lower peripheral cells 31 to the fourth lower peripheral cells 34 may have a third unit cell height CH3 in the second direction Y.

[0067] In some example embodiments, the first lower peripheral unit 31 and the fourth lower peripheral unit 34 may be symmetrical about each other around a plane (XZ plane) intersecting the second direction Y. The second lower peripheral unit 32 and the third lower peripheral unit 33 may be symmetrical about each other around a plane (XZ plane) intersecting the second direction Y. For example, the third active patterns A31 to A34 of the first lower peripheral unit 31 and the second lower peripheral unit 32 may be arranged sequentially along the second direction Y, while the third active patterns A31 to A34 of the third lower peripheral unit 33 and the fourth lower peripheral unit 34 may be arranged sequentially along a direction opposite to the second direction Y -Y.

[0068] In some example embodiments, the third unit height CH3 of each of the first lower peripheral units 31 to the fourth lower peripheral units 34 may be less than the second unit height CH2 of each of the first upper peripheral unit 21 and the second upper peripheral unit 22. In some example embodiments, the ratio of the second unit height CH2 to the third unit height CH3 may be in the range of 1.5:1 to 3:1. For example, as shown in the figure, the ratio of the second unit height CH2 to the third unit height CH3 may be 2:1.

[0069] Each of the active patterns A11 to A14, A21, A22, and A31 to A34 may include an elemental semiconductor material, such as silicon (Si) or germanium (Ge). In some example embodiments, each of the active patterns A11 to A14, A21, A22, and A31 to A34 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. Group IV-IV compound semiconductors may include, for example, binary compounds comprising two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), ternary compounds comprising three of them, or compounds obtained by doping them with group IV elements. III-V compound semiconductors may include, for example, binary compounds obtained by combining one of aluminum (Al), gallium (Ga), or indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), or antimony (Sb), which are group V elements; ternary compounds obtained by combining two of aluminum (Al), gallium (Ga), and / or indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), or antimony (Sb), which are group V elements; or quaternary compounds obtained by combining one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), or antimony (Sb), which are group V elements.

[0070] In some example embodiments, each of the active patterns A11 to A14, A21, A22, and A31 to A34 may include a plurality of bridge patterns 111 to 114, which may be sequentially stacked on the substrate 100 and extend in a first direction X. The plurality of bridge patterns 111 to 114 may be spaced apart from each other in a third direction Z intersecting the first direction X and the second direction Y. The plurality of bridge patterns 111 to 114 can be used as a multi-bridge channel field-effect transistor (MBCFET) including a multi-bridge channel. ® The number of bridging patterns included in each of the active patterns A11 to A14, A21, A22, A31 to A34 is merely an example and is not limited to what is shown.

[0071] In some example embodiments, each of the active patterns A11 to A14, A21, A22, and A31 to A34 may include a fin pattern 110 that protrudes from the upper surface of the substrate 100 and extends in a first direction X. A stack of multiple bridging patterns 111 to 114 may be spaced apart from the fin pattern 110 in a third direction Z. The fin pattern 110 may be formed by etching a portion of the substrate 100, or may be an epitaxial layer grown from the substrate 100.

[0072] A field insulating film 105 may be formed on a substrate 100. The field insulating film 105 may cover at least a portion of the side surface of the fin pattern 110. The field insulating film 105 may be, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0073] A first gate structure G1 may be formed on a substrate 100 of a memory cell region CELL. The first gate structures G1 may extend in a second direction Y and may be spaced apart from each other in a first direction X. The first gate structures G1 may intersect with first active patterns A11 to A14. For example, bridging patterns 111 to 114 of each of the first active patterns A11 to A14 may extend in the first direction X to extend through the first gate structure G1. The number and arrangement of the first gate structures G1 are merely examples and are not limited to those shown.

[0074] The second gate structure G2 may be formed on the substrate 100 of the first region I. The second gate structures G2 may extend in the second direction Y and may be spaced apart from each other in the first direction X. The second gate structure G2 may intersect with the second active patterns A21 and A22. For example, bridging patterns 111 to 114 of each of the second active patterns A21 and A22 may extend in the first direction X to extend through the second gate structure G2. The number and arrangement of the second gate structures G2 are merely examples and are not limited to those shown.

[0075] A third gate structure G3 may be formed on the substrate 100 of the second region II. The third gate structures G3 may extend in the second direction Y and may be spaced apart from each other in the first direction X. The third gate structures G3 may intersect with the third active patterns A31 to A34. For example, bridging patterns 111 to 114 of each of the third active patterns A31 to A34 may extend in the first direction X to extend through the third gate structure G3. The number and arrangement of the third gate structures G3 are merely examples and are not limited to those shown.

[0076] In some example embodiments, a first cutting pattern CT1 may be formed to define the second gate structure G2 of each of the first upper peripheral unit 21 and the second upper peripheral unit 22. For example, a first cutting pattern CT1 may be positioned at the boundary between the first upper peripheral unit 21 and the second upper peripheral unit 22 to extend in the first direction X to cut the second gate structure G2. Furthermore, the second gate structure G2 of each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may be defined by two first cutting patterns CT1 that are adjacent to each other in the second direction Y. In such a case, the second unit height CH2 may be defined as the distance between the centers of two adjacent first cutting patterns CT1.

[0077] In some example embodiments, a first dicing pattern CT1 and a second dicing pattern CT2 may be formed to define the third gate structure G3 of each of the first lower peripheral units 31 to the fourth lower peripheral units 34. For example, a first dicing pattern CT1 may be positioned at the boundary between the second lower peripheral unit 32 and the third lower peripheral unit 33 to extend in the first direction X to cut the third gate structure G3. For example, a second dicing pattern CT2 may be positioned at the boundary between the first lower peripheral unit 31 and the second lower peripheral unit 32 to extend in the first direction X to cut the third gate structure G3, while another second dicing pattern CT2 may be positioned at the boundary between the third lower peripheral unit 33 and the fourth lower peripheral unit 34 to extend in the first direction X to cut the third gate structure G3. Furthermore, the third gate structure G3 of each of the first lower peripheral units 31 to the fourth lower peripheral unit 34 may be defined by a first dicing pattern CT1 and a second dicing pattern CT2 that are adjacent to each other in the second direction Y. In such a case, the third unit height CH3 may be defined as the distance between the centers of the adjacent first dicing pattern CT1 and the second dicing pattern CT2.

[0078] Each of the first cutting pattern CT1 and the second cutting pattern CT2 may include an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boronnitride, silicon carbon nitride, silicon oxycarbonitride, or combinations thereof. However, the exemplary embodiments of this disclosure are not limited thereto.

[0079] In some example embodiments, each of the gate structures G1 to G3 may include a gate dielectric film 120, a gate electrode 130, a gate spacer 140, and a gate capping film 150.

[0080] The gate dielectric film 120 may be located between each of the active patterns A11 to A14, A21, A22 and A31 to A34 and the gate electrode 130. The gate dielectric film 120 may include a dielectric material, such as at least one of silicon oxide, silicon oxynitride, silicon nitride or a high-k material with a dielectric constant greater than that of silicon oxide.

[0081] In some example embodiments, the gate dielectric film 120 may include an interfacial film 121 and a high-k dielectric film 122 sequentially stacked on each of the active patterns A11 to A14, A21, A22 and A31 to A34.

[0082] Interface film 121 may surround the perimeter of each of bridging patterns 111 to 114. For example, interface film 121 may extend conformally along the perimeter of each of bridging patterns 111 to 114. Interface film 121 may further extend along and over the fin pattern 110 not covered by field insulating film 105. In some example embodiments, interface film 121 may comprise an oxide film formed by oxidizing the surfaces of each of bridging patterns 111 to 114 and / or fin pattern 110. For example, when each of bridging patterns 111 to 114 is a silicon pattern, interface film 121 may comprise a silicon oxide film.

[0083] A high-k dielectric film 122 may surround the periphery of the interface film 121. Furthermore, a portion of the high-k dielectric film 122 may be located between the gate electrode 130 and the gate spacer 140. For example, the high-k dielectric film 122 may extend conformally along the contour of the inner surface of the gate spacer 140 and the periphery of the interface film 121. Additionally, the high-k dielectric film 122 may further extend along and on the upper surface of the field insulating film 105.

[0084] In some example embodiments, the high-k dielectric film 122 may comprise a high-k material with a dielectric constant greater than that of silicon oxide. High-k dielectric materials may include, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), and hafnium oxynitride (HfO2). x N y Zirconium oxynitride (ZrO) x N y ), Lanthanum oxide (La2O) x N y ), aluminum oxide (Al2O) x N y ), titanium oxynitride (TiO2) x N y ), SrTiO2 x N y ), Lanthanum aluminum oxynitride (LaAlO) x N y ), Yttrium oxynitride (Y2O) x Ny At least one of the following: (or a combination thereof). However, the exemplary embodiments of this disclosure are not limited thereto.

[0085] The gate electrode 130 may extend elongate in the second direction Y to intersect with a corresponding one of the active patterns A11 to A14, A21, A22, and A31 to A34. Bridging patterns 111 to 114 of each of the active patterns A11 to A14, A21, A22, and A31 to A34 may extend in the first direction X to extend through the gate electrode 130. The gate electrode 130 may comprise a conductive material, such as at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, or combinations thereof. However, the exemplary embodiments of this disclosure are not limited thereto. The gate electrode 130 may be formed in an alternative process. However, the exemplary embodiments of this disclosure are not limited thereto.

[0086] The gate electrode 130 is shown as a single film. However, this is merely an example, and the gate electrode 130 can be a multi-film structure formed by stacking multiple conductive films. For example, the gate electrode 130 may include a work function control film that controls the work function, and a filled conductive film that fills the space defined by the work function control film. The work function control film may include at least one of, for example, TiN, TaN, TiC, TaC, TiAlC, or combinations thereof. The filled conductive film may include, for example, W or Al.

[0087] Gate spacer 140 may extend along a side surface of gate electrode 130. Bridging patterns 111 to 114 of each of active patterns A11 to A14, A21, A22, and A31 to A34 may extend in a first direction X to extend through gate spacer 140. Gate spacer 140 may include an insulating material, including at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, or combinations thereof. However, exemplary embodiments of this disclosure are not limited thereto.

[0088] The gate cap film 150 may extend along and on the upper surface of the gate electrode 130. The gate cap film 150 may include an insulating material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, or combinations thereof. However, the exemplary embodiments of this disclosure are not limited thereto.

[0089] In some example embodiments, each of the gate structures G1 to G3 may further include an inner spacer 145. The inner spacer 145 may be formed on a portion of the side surface of the gate electrode 130 between adjacent bridging patterns 111 to 114. Furthermore, the inner spacer 145 may be formed on a portion of the side surface of the gate electrode 130 between the fin pattern 110 and the stack of bridging patterns 111 to 114.

[0090] In some example embodiments, a portion of the gate dielectric film 120 may be located between the gate electrode 130 and the inner spacer 145. For example, a portion of the high-k dielectric film 122 may further extend along and on the inner surface of the inner spacer 145.

[0091] The first source / drain regions SD1 can be respectively disposed in the first active patterns A11 to A14, and disposed on the side surface of each of the first gate structures G1. The bridging patterns 111 to 114 of the first active patterns A11 to A14 can extend through the gate electrode 130 and the gate spacer 140 to contact the first source / drain regions SD1. The first source / drain regions SD1 can be isolated from the gate electrode 130 of the first gate structure G1 via the gate dielectric film 120, the gate spacer 140 and / or the inner spacer 145.

[0092] The second source / drain region SD2 can be disposed in the second active patterns A21 and A22, respectively, and on the side surface of each of the second gate structure G2. The bridging patterns 111 to 114 of the second active patterns A21 and A22 can extend through the gate electrode 130 and the gate spacer 140 to contact the second source / drain region SD2. The second source / drain region SD2 can be isolated from the gate electrode 130 of the second gate structure G2 via the gate dielectric film 120, the gate spacer 140, and / or the inner spacer 145.

[0093] The third source / drain region SD3 can be respectively disposed in the third active patterns A31 to A34, and disposed on the side surface of each of the third gate structure G3. The bridging patterns 111 to 114 of the third active patterns A31 to A34 can extend through the gate electrode 130 and the gate spacer 140 to contact the third source / drain region SD3. The third source / drain region SD3 can be isolated from the gate electrode 130 of the third gate structure G3 through the gate dielectric film 120, the gate spacer 140 and / or the inner spacer 145.

[0094] In some example embodiments, each of the first source / drain regions SD1 to the third source / drain regions SD3 may include an epitaxial layer doped with impurities. For example, the first source / drain region SD1 may include an epitaxial pattern grown from first active patterns A11 to A14 using an epitaxial growth method. For example, the second source / drain region SD2 may include an epitaxial pattern grown from second active patterns A21 and A22 using an epitaxial growth method. For example, the third source / drain region SD3 may include an epitaxial pattern grown from third active patterns A31 to A34 using an epitaxial growth method.

[0095] In some example embodiments, each of the first source / drain regions SD1 to the third source / drain regions SD3 may include a first epitaxial layer 161 and a second epitaxial layer 162 sequentially stacked. The first epitaxial layer 161 may extend along the upper surface of the fin pattern 110 and the side surface of each of the bridging patterns 111 to 114 and on the side surface of each of the bridging patterns 111 to 114. The first epitaxial layer 161 may be used as a seed layer for growing the second epitaxial layer 162. The impurity concentration of the second epitaxial layer 162 may be greater than the impurity concentration of the first epitaxial layer 161.

[0096] An interlayer insulating film 190 may be formed on the substrate 100 and the field insulating film 105. The interlayer insulating film 190 may be formed to fill the space on the outer surface of each of the gate structures G1 to G3. The interlayer insulating film 190 may cover the first source / drain region SD1 to the third source / drain region SD3.

[0097] The interlayer insulating film 190 may include at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, or a low-k material with a dielectric constant lower than that of silicon oxide. Low-k materials can include, but are not limited to, FOX (Flowable Oxide), TOSZ (Tonene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, and OSG (Organopolymer). Silicate Glass, parylene, bis-benzocyclobutene (BCB), SiLK, polyimide, porous polymeric material, or combinations thereof.

[0098] The source / drain contact 180 can contact the first source / drain region SD1 to the third source / drain region SD3. For example, the source / drain contact 180 can extend in the third direction Z to extend through the interlayer insulating film 190 and can contact the first source / drain region SD1 to the third source / drain region SD3.

[0099] The wiring structure WS can be formed on the interlayer insulating film 190. The wiring structure WS can include an interlayer insulating film ID and a wiring pattern WP within the interlayer insulating film ID. The wiring patterns WP can be insulated from each other via the interlayer insulating film ID. The number, shape, and arrangement of the wiring patterns WP are merely examples and are not limited to those shown.

[0100] Wiring patterns WP can be electrically connected to source / drain contacts 180 and / or gate electrode 130. For example, via patterns VP can be formed to connect some of the wiring patterns WP to the source / drain contacts 180. In some example embodiments, for example, other wiring patterns WP in the wiring patterns WP can be formed to connect to the gate contact GC of the gate electrode 130.

[0101] In some example embodiments, the width of each of the second active patterns A21 and A22 may be greater than the width of each of the third active patterns A31 to A34. In this regard, width refers to the length in the second direction Y. For example, as... Figure 8 As shown, the width W11 of the first upper active pattern A21 can be greater than the width W21 of the first lower active pattern A31 and the width W22 of the second lower active pattern A32.

[0102] In some example embodiments, the width W11 of the first active pattern A21 and the width W12 of the second active pattern A22 can be equal to each other. It is shown that a first distance D11 between the first active pattern A21 of the second upper peripheral unit 22 and the second active pattern A22 of the second upper peripheral unit 22 is equal to a second distance D12 between the second active patterns A22 of the first upper peripheral unit 21 and the second active pattern A22 of the second upper peripheral unit 22. However, this is only an example. In another example, the first distance D11 and the second distance D12 can be different from each other as needed.

[0103] In some example embodiments, the width W21 of the first lower active pattern A31 and the width W22 of the second lower active pattern A32 may be equal to each other. A third distance D21 separating the first lower active pattern A31 and the second lower active pattern A32 from each other is shown to be equal to a fourth distance D22 separating the second lower active pattern A32 and the third lower active pattern A33 from each other. However, this is merely an example. It should be understood that, as needed, the third distance D21 and the fourth distance D22 may be different from each other.

[0104] In some example embodiments, the first upper active pattern A21 may overlap with at least a portion of the first lower active pattern A31 and at least a portion of the second lower active pattern A32 in the first direction X. In some example embodiments, the second upper active pattern A22 may overlap with at least a portion of the third lower active pattern A33 and at least a portion of the fourth lower active pattern A34 in the first direction X.

[0105] In some example embodiments, the first upper active pattern A21 can be connected to the first lower active pattern A31 and the second lower active pattern A32 in the first direction X. For example, the peripheral circuit region PERI may include a third region III located between the first region I and the second region II. Furthermore, a first connection pattern CP1 can be formed on the substrate 100 of the third region III. The first connection pattern CP1 can connect the first upper active pattern A21, the first lower active pattern A31, and the second lower active pattern A32 to each other. For example, as... Figure 8 As shown, the first connection pattern CP1 may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 may extend in a first direction X to connect the first upper active pattern A21 and the first lower active pattern A31 to each other. The second portion P2 may extend in the first direction X to connect the first upper active pattern A21 and the second lower active pattern A32 to each other. The third portion P3 may extend in a second direction Y to connect the first portion P1 and the second portion P2 to each other. Although not specifically shown, the first connection pattern CP1 may include the fin pattern 110 and / or bridging patterns 111 to 114 as described above.

[0106] In some example embodiments, the second upper active pattern A22 can be connected to the third lower active pattern A33 and the fourth lower active pattern A34 in the first direction X. For example, a second connection pattern CP2 can be formed on the substrate 100 of the third region III. The second connection pattern CP2 can connect the second upper active pattern A22, the third lower active pattern A33, and the fourth lower active pattern A34 to each other. Because the second connection pattern CP2 can be similar to the first connection pattern CP1, its detailed description will be omitted below.

[0107] In some example embodiments, a dummy gate structure (DG) may be formed on the substrate 100 of the third region III. The dummy gate structure DG may extend in the second direction Y to intersect with the first connection pattern CP1 and the second connection pattern CP2. Although not specifically shown, the dummy gate structure DG may include the gate dielectric film 120, gate electrode 130, gate spacer 140, inner spacer 145, gate capping film 150, etc., as described above. The number and arrangement of the dummy gate structures DG are merely examples and are not limited to those shown.

[0108] In some example embodiments, the width of the third region III in the first direction X can be in the range of 1 CPP to 3 CPP. In this regard, CPP (Contact Poly Pitch) can be defined as the sum of the spacing between adjacent gate structures and the width of one gate structure in the adjacent gate structures, or the spacing between the center of one gate structure and the center of another gate structure adjacent to it. For example, the number of dummy gate structures DG arranged in the third region III can be in the range of 1 to 3.

[0109] Since the second unit cell height CH2 and the third unit cell height CH3 are different from each other, the third region III can include the transition region of the NFET and / or the transition region of the PFET. For example, within the third region III, the NFET region and the PFET region may partially overlap in the first direction X.

[0110] In one example, as described above, each of the first upper active pattern A21 and the first lower active pattern A31 can be used as the channel region of an NFET. The second lower active pattern A32 can be used as the channel region of a PFET. In such a case, each of the first portion P1 and the third portion P3 of the first connection pattern CP1 may include an n-type impurity (e.g., P, Sb, or As), and the second portion P2 of the first connection pattern CP1 may include a p-type impurity (e.g., B, In, Ga, or Al).

[0111] In one example, as described above, each of the second upper active pattern A22 and the third lower active pattern A33 can be used as the channel region of a PFET, and the fourth lower active pattern A34 can be used as the channel region of an NFET. In such a case, each of the second portion P2 and the third portion P3 of the second connection pattern CP2 may include a p-type impurity (e.g., B, In, Ga, or Al), and the first portion P1 of the second connection pattern CP2 may include an n-type impurity (e.g., P, Sb, or As).

[0112] In some example embodiments, the wiring pattern WP may include a first power wiring PW1 and a second power wiring PW2 in the peripheral circuit region PERI. Each of the first power wiring PW1 and the second power wiring PW2 may extend in a first direction X. A first power voltage (e.g., V) may be applied. SS ) is applied to the first power wiring PW1, and a second power voltage (e.g., V) different from the first power voltage can be applied. DDA first power cable PW1 can be electrically connected to the first region I and the second region II and supply them with a first power voltage. A second power cable PW2 can be electrically connected to the first region I and the second region II and supply them with a second power voltage.

[0113] In some example embodiments, the first power wiring PW1 can be connected to Figure 3 The ground node V of each of the unit memory cells 10 SS And the second power cable PW2 can be connected to Figure 3 The power node V of each of the unit memory cells 10 DD .

[0114] In some example embodiments, the first power wiring PW1 and the second power wiring PW2 may be arranged alternately along the second direction Y.

[0115] In some example embodiments, a first active pattern A21 and a second active pattern A22 may be disposed between two first power lines PW1 that are adjacent to each other in the second direction Y. The first power lines PW1 may extend across a first region I and a second region II to connect together to the first region I and the second region II. For example, in a plan view, a first power line PW1 may be located at the boundary between a first upper peripheral unit 21 and a second upper peripheral unit 22, and at the boundary between a second lower peripheral unit 32 and a third lower peripheral unit 33.

[0116] In some example embodiments, two first active patterns A21 (or two second active patterns A22) may be disposed between two second power lines PW2 that are adjacent to each other in the second direction Y. The second power lines PW2 may extend across the first region I and the second region II to connect together to the first region I and the second region II. For example, in a plan view, a second power line PW2 may be disposed in the region between the first active patterns A21 and the second active patterns A22 in the first upper peripheral unit 21 and at the boundary between the first lower peripheral unit 31 and the second lower peripheral unit 32.

[0117] As the integration level of standard cells used in semiconductor devices continues to improve, integrated peripheral circuit cells relative to a single memory cell can be used. For example, semiconductor memory devices with a cell height ratio of 4:6 or 4:6.5 for the single memory cell to the single peripheral circuit cell have been proposed. However, in such a single peripheral circuit cell, a relatively large area may be required as a virtual area to form the peripheral circuitry. Furthermore, the single peripheral circuit cell may not meet the desired performance. For example, in the input / output circuitry of SRAM (e.g., ... Figure 1 In section 4), with memory cell arrays (e.g., Figure 1 1) The adjacent upper input / output circuit (upper I / O circuit) region may require a higher current drive than the lower input / output circuit (lower I / O circuit) region, which is relatively far from the memory cell array. However, the problem is that a higher NOF (Number of Fingers) is expected in the integrated unit peripheral circuit cell to meet such a higher current drive for the upper input / output circuit.

[0118] According to some example embodiments, a semiconductor device can provide a first region I offering relatively high current drive capability and a second region II with relatively higher integration, thereby providing optimized or improved peripheral circuitry regions as needed. Specifically, as described above, second active patterns A21 and A22 with relatively larger widths W11 and W12 can be formed in the first region I adjacent to the memory cell region CELL, while third active patterns A31 to A34 with relatively smaller widths W21 and W22 can be formed in the second region II, which is further apart from the memory cell region CELL than the first region I. Thus, for example, the first region I can provide high current drive capability in the upper input / output circuitry of the SRAM, while the second region II can improve the integration level in the lower input / output circuitry of the SRAM. Therefore, a semiconductor device with improved performance and integration level can be provided.

[0119] Figures 9 to 12 These are various other example layout diagrams used to illustrate semiconductor devices according to some example embodiments. For ease of description, a brief description is used as described above. Figures 1 to 8 The description contains repeated content or omits its description.

[0120] refer to Figures 1 to 3 and Figure 9 In a semiconductor device according to some example embodiments, a first distance D11 between the first upper active pattern A21 and the second upper active pattern A22 may be greater than a fourth distance D22 between the second lower active pattern A32 and the third lower active pattern A33.

[0121] In some example embodiments, the width W11 of the first upper active pattern A21 may be less than the sum of the third distance D21 between the first lower active pattern A31 and the second lower active pattern A32, the width W21 of the first lower active pattern A31, and the width W22 of the second lower active pattern A32.

[0122] refer to Figures 1 to 3 and Figure 10In a semiconductor device according to some example embodiments, each of the first lower peripheral unit 31 and the fourth lower peripheral unit 34 may include a first lower active pattern A31 to a fourth lower active pattern A34, while each of the second lower peripheral unit 32 and the third lower peripheral unit 33 may include a fifth lower active pattern A35 to an eighth lower active pattern A38.

[0123] The first active pattern A31 to the fourth active pattern A34 can be connected to the first active pattern A21 in the first direction X. The fifth active pattern A35 to the eighth active pattern A38 can be connected to the second active pattern A22 in the first direction X.

[0124] For example, each of the first lower active pattern A31, the second lower active pattern A32, the seventh lower active pattern A37, and the eighth lower active pattern A38 can be used as a channel region for an NFET. Each of the third lower active pattern A33, the fourth lower active pattern A34, the fifth lower active pattern A35, and the sixth lower active pattern A36 can be used as a channel region for a PFET.

[0125] refer to Figures 1 to 3 and Figure 11 In a semiconductor device according to some example embodiments, a first distance D11 between the first upper active pattern A21 and the second upper active pattern A22 may be smaller than a fourth distance D22 between the second lower active pattern A32 and the third lower active pattern A33.

[0126] In some example embodiments, the width W11 of the first upper active pattern A21 may be greater than the sum of the third distance D21 between the first lower active pattern A31 and the second lower active pattern A32, the width W21 of the first lower active pattern A31, and the width W22 of the second lower active pattern A32.

[0127] refer to Figures 1 to 3 and Figure 12 In a semiconductor device according to some example embodiments, each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may include a first active pattern A21 to a third active pattern A23.

[0128] The first upper active pattern A21 can be connected to the first lower active pattern A31 in the first direction X. The second upper active pattern A22 can be connected to the second lower active pattern A32 and the third lower active pattern A33 in the first direction X. The third upper active pattern A23 can be connected to the fourth lower active pattern A34 in the first direction X.

[0129] In some example embodiments, a portion of the second power cabling PW2 may be located at the boundary between the first upper peripheral unit 21 and the second upper peripheral unit 22. The second power cabling PW2 located at the boundary between the first upper peripheral unit 21 and the second upper peripheral unit 22, and the first power cabling PW1 located at the boundary between the second lower peripheral unit 32 and the third lower peripheral unit 33, may be arranged along a first direction X.

[0130] In some example embodiments, each of the second power wiring PW2 located at the boundary between the first lower peripheral unit 31 and the second lower peripheral unit 32 and the second power wiring PW2 located at the boundary between the third lower peripheral unit 33 and the fourth lower peripheral unit 34 may not extend along the first region I.

[0131] Figure 13 This is a conceptual plan view illustrating a semiconductor device according to some example embodiments. Figure 14 and Figure 15 It is shown Figure 13 Various example layout diagrams of semiconductor devices are shown. For ease of description, a brief description is provided using the above. Figures 1 to 8 The description contains repeated content or omits its description.

[0132] refer to Figures 1 to 3 as well as Figures 13 to 15 In some example embodiments of semiconductor devices, the ratio of the second unit cell height CH2 to the third unit cell height CH3 can be 3:1.

[0133] For example, such as Figure 14 and Figure 15 As shown, the first region I may include a first upper peripheral unit 21 and a second upper peripheral unit 22 arranged sequentially along the second direction Y. The second region II may include a first lower peripheral unit 31 to a sixth lower peripheral unit 36 ​​arranged sequentially along the second direction Y, corresponding to the first upper peripheral unit 21 and the second upper peripheral unit 22. Furthermore, the first lower active pattern A31 to the sixth lower active pattern A36 may be formed within the first lower peripheral unit 31 to the sixth lower peripheral unit 36.

[0134] refer to Figures 1 to 3 , Figure 13 and Figure 14 In a semiconductor device according to some example embodiments, each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may include a first active pattern A21 to a fourth active pattern A24.

[0135] The first upper active pattern A21 can be connected to the first lower active pattern A31 in the first direction X. The second upper active pattern A22 can be connected to the second lower active pattern A32 and the third lower active pattern A33 in the first direction X. The third upper active pattern A23 can be connected to the fourth lower active pattern A34 and the fifth lower active pattern A35 in the first direction X. The fourth upper active pattern A24 can be connected to the sixth lower active pattern A36 in the first direction X.

[0136] refer to Figures 1 to 3 , Figure 13 and Figure 15 In a semiconductor device according to some example embodiments, each of the first upper peripheral unit 21 and the second upper peripheral unit 22 may include a first active pattern A21 and a second active pattern A22.

[0137] The first upper active pattern A21 can be connected in the first direction X to the first lower active pattern A31 to the third lower active pattern A33. The second upper active pattern A22 can be connected in the first direction X to the fourth lower active pattern A34 to the sixth lower active pattern A36.

[0138] Figure 16 This is a conceptual plan view illustrating a semiconductor device according to some example embodiments. Figure 17 It is shown Figure 16 An example layout diagram of a semiconductor device. For ease of description, a brief description is provided above. Figures 1 to 15 The description contains repeated content or omits its description.

[0139] refer to Figures 1 to 3 , Figure 16 and Figure 17 In some example embodiments of semiconductor devices, the ratio of the second unit cell height CH2 to the third unit cell height CH3 can be 1.5:1.

[0140] For example, such as Figure 17 As shown, the first region I may also include first upper peripheral units 21 to fourth upper peripheral units 24 arranged sequentially along the second direction Y. The second region II may include first lower peripheral units 31 to sixth lower peripheral units 36 corresponding to the first upper peripheral units 21 to fourth upper peripheral units 24 and arranged sequentially along the second direction Y. Furthermore, first active patterns A21 to fourth active patterns A24 may be formed within the first upper peripheral units 21 to fourth upper peripheral units 24. For example, first active pattern A21 and second active pattern A22 may be formed within the first upper peripheral unit 21. Third active pattern A23 and fourth active pattern A24 may be formed within the second upper peripheral unit 22.

[0141] The first upper active pattern A21 can be connected to the first lower active pattern A31 in the first direction X. The second upper active pattern A22 can be connected to the second lower active pattern A32 and the third lower active pattern A33 in the first direction X. The third upper active pattern A23 can be connected to the fourth lower active pattern A34 and the fifth lower active pattern A35 in the first direction X. The fourth upper active pattern A24 can be connected to the sixth lower active pattern A36 in the first direction X.

[0142] Any functional blocks shown in the accompanying drawings and described above can be implemented in processing circuitry, such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0143] Although some exemplary embodiments of this disclosure have been described with reference to the accompanying drawings, this disclosure is not limited to the exemplary embodiments described above, but can be implemented in various different forms. Those skilled in the art will understand that this disclosure can be practiced in other specific forms without changing the technical spirit or essential characteristics of this disclosure. Therefore, it should be understood that the exemplary embodiments described above are illustrative in all respects and are not limiting.

Claims

1. A semiconductor device, comprising: The cell array region includes multiple unit memory cells arranged in two dimensions along a first direction and a second direction that intersect each other; The first peripheral circuit region includes a plurality of first unit peripheral cells arranged along the second direction, and the first peripheral circuit region and the cell array region are arranged along the first direction; as well as The second peripheral circuit region includes a plurality of second unit peripheral cells arranged along the second direction, and the first peripheral circuit region is located between the cell array region and the second peripheral circuit region. Wherein, the height of the first unit cell in the second direction of each of the unit memory cells and the height of the second unit cell in the second direction of each of the first unit peripheral cells are equal to each other, and In this case, the height of the third unit in each of the second unit peripheral units in the second direction is less than the height of the second unit unit.

2. The semiconductor device according to claim 1, further comprising: Bit lines and complementary bit lines extend in a manner parallel to each other and in the first direction; as well as The letter line extends in the second direction. Each of the unit memory cells includes: The first and second inverters constitute the latch circuit. The first transmission transistor connects the output node of the first inverter to the bit line, and The second transmission transistor connects the output node of the second inverter to the complementary bit line, and The word line is connected to the gate of the first transmission transistor and the gate of the second transmission transistor.

3. The semiconductor device according to claim 2, wherein, The first peripheral circuit region is electrically connected to the cell array region via the bit line and the complementary bit line.

4. The semiconductor device according to claim 1, wherein, The ratio of the height of the second unit to the height of the third unit is in the range of 1.5:1 to 3:

1.

5. The semiconductor device according to claim 4, wherein, The ratio of the height of the second unit to the height of the third unit is 2:

1.

6. The semiconductor device according to claim 1, wherein, Each of the first unit peripheral cells includes a first active pattern and a second active pattern extending in the first direction and spaced apart from each other in the second direction. Each of the second unit peripheral cells includes a first lower active pattern and a second lower active pattern extending in the first direction and spaced apart from each other in the second direction, and The width of each of the first upper active pattern and the second upper active pattern in the second direction is greater than the width of each of the first lower active pattern and the second lower active pattern in the second direction.

7. The semiconductor device according to claim 6, wherein, Each of the first upper active pattern and the first lower active pattern includes the channel region of the NFET. Each of the second upper active pattern and the second lower active pattern includes the channel region of the PFET.

8. The semiconductor device according to claim 6, wherein, Each of the first upper active pattern, the second upper active pattern, the first lower active pattern, and the second lower active pattern includes a plurality of bridging patterns spaced apart from each other in a third direction intersecting the first direction and the second direction.

9. The semiconductor device according to claim 6, wherein, The first upper active pattern is connected to the first lower active pattern and the second lower active pattern in the first direction.

10. The semiconductor device according to claim 1, further comprising: The first power wiring and the second power wiring extend in the first peripheral circuit region and the second peripheral circuit region, and in the first direction. The first power wiring and the second power wiring are arranged alternately in the second direction.

11. A semiconductor device comprising a memory cell, an upper peripheral cell, and a first lower peripheral cell arranged sequentially along a first direction, the semiconductor device comprising: Base; A first active pattern and a second active pattern are provided on a first region of the substrate, wherein the upper peripheral unit is provided at the first region, the first active pattern and the second active pattern extend in the first direction and are spaced apart from each other in a second direction intersecting the first direction; A first gate structure extends on the first active pattern and the second active pattern and in the second direction; A first lower active pattern and a second lower active pattern on a second region of the substrate, wherein a first lower peripheral unit is provided in the second region, and the first lower active pattern and the second lower active pattern extend in the first direction and are spaced apart from each other in the second direction; and The second gate structure extends on the first lower active pattern and the second lower active pattern and in the second direction. Wherein, the height of the first unit cell of the memory cell in the second direction and the height of the second unit cell of the upper peripheral cell in the second direction are equal to each other, and Wherein, the first upper active pattern overlaps with at least a portion of the first lower active pattern and at least a portion of the second lower active pattern in the first direction.

12. The semiconductor device according to claim 11, further comprising: The second lower outer perimeter unit is arranged such that the first lower outer perimeter unit and the second lower outer perimeter unit are arranged along the second direction; as well as A third and a fourth lower active pattern are provided on a third region of the substrate, wherein a second lower peripheral unit is provided in the third region, the third and fourth lower active patterns extend in the first direction and are spaced apart from each other in the second direction, and Wherein, the second upper active pattern overlaps with at least a portion of the third lower active pattern and at least a portion of the fourth lower active pattern in the first direction.

13. The semiconductor device according to claim 12, wherein, Each of the first upper active pattern, the first lower active pattern, and the fourth lower active pattern includes a channel region of the NFET, and Each of the second upper active pattern, the second lower active pattern, and the third lower active pattern includes a channel region of the PFET.

14. The semiconductor device according to claim 11, wherein, The width of each of the first upper active pattern and the second upper active pattern in the second direction is greater than the width of each of the first lower active pattern and the second lower active pattern in the second direction.

15. The semiconductor device according to claim 11, wherein, The first upper active pattern is connected to the first lower active pattern and the second lower active pattern in the first direction.

16. The semiconductor device of claim 11, further comprising: A first power wiring extends in the first direction and is configured to receive a first power voltage; as well as A second power cable extends in the first direction and is configured to receive a second power voltage different from the first power voltage. In the plan view of the semiconductor device, the first upper active pattern, the first lower active pattern, and the second lower active pattern are located between the first power wiring and the second power wiring. In the plan view, the second power wiring is located between the first active pattern and the second active pattern.

17. A semiconductor device comprising a first region and a second region arranged along a first direction, and a third region between the first region and the second region, the semiconductor device comprising: Base; A first active pattern and a second active pattern are provided on a first portion of the substrate corresponding to the first region, the first active pattern and the second active pattern extending in the first direction and arranged along a second direction intersecting the first direction; A first gate structure extends on the first active pattern and the second active pattern and in the second direction; A first to a fourth lower active pattern on a second portion of the substrate corresponding to the second region, the first to the fourth lower active patterns extending in the first direction and arranged sequentially along the second direction; The second gate structure extends over the first lower active pattern to the fourth lower active pattern and in the second direction; A first connection pattern on the third portion of the substrate corresponding to the third region, the first connection pattern connecting the first upper active pattern, the first lower active pattern and the second lower active pattern to each other; A second connection pattern on the third portion of the substrate corresponding to the third region, the second connection pattern connecting the second upper active pattern, the third lower active pattern and the fourth lower active pattern to each other; A first power cabling extends across the first region to the third region in the first direction and is configured to receive a first power voltage; as well as A second power cabling extends in the first direction across the first region to the third region and is configured to receive a second power voltage different from the first power voltage. Wherein, each of the first upper active pattern, the first lower active pattern, and the fourth lower active pattern includes the channel region of the NFET, and Each of the second upper active pattern, the second lower active pattern, and the third lower active pattern includes a channel region of the PFET.

18. The semiconductor device according to claim 17, wherein, In the plan view of the semiconductor device The first upper active pattern, the first lower active pattern, and the second lower active pattern are located between the first power wiring and the second power wiring. The second power wiring is located between the first active pattern and the second active pattern, and between the second lower active pattern and the third lower active pattern.

19. The semiconductor device of claim 17, further comprising: A virtual gate structure extending in the second direction on the first connection pattern and the second connection pattern.

20. The semiconductor device according to claim 17, wherein, Each of the first upper active pattern and the second upper active pattern, the first lower active pattern to the fourth lower active pattern, and the first connecting pattern and the second connecting pattern includes a plurality of bridging patterns spaced apart from each other in a third direction intersecting the first direction and the second direction.

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