Dynamic random access memory array and forming method thereof

Abstract

The invention discloses a dynamic random access memory array and a forming method thereof, and the dynamic random access memory array comprises a plurality of first channel column groups which comprise a plurality of first channel columns; the plurality of second channel column groups comprise a plurality of second channel columns, and the first channel columns and the corresponding second channel columns have overlapped areas; a plurality of first word line grids, wherein each first word line grid controls each first channel column in one first channel column group; a plurality of second word line grids, wherein each second word line grid controls each second channel column in one second channel column group; each first bit line is electrically connected with the corresponding first channel column in each first channel column group; and a plurality of second bit lines, wherein each second bit line is electrically connected with the corresponding second channel column in each second channel column group. The projection of the first channel column and the projection of the corresponding second channel column have an overlapping area, so that the first channel column and the second channel column have more forming space, and the problem of channel inclination or bending can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access memory array and a method for forming the same. Background Technology

[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] Typically, dynamic random access memory (DRAM) consists of multiple memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through word lines and bit lines.

[0004] However, existing dynamic random access memory still has many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a dynamic random access memory array and a method for forming the same, so as to reduce the problem of channel tilting or bending.

[0006] To address the aforementioned problems, this invention provides a dynamic random access memory (DRAM) array, comprising: a plurality of first channel pillar groups, each first channel pillar group including a plurality of first channel pillars arranged along a first direction; a plurality of second channel pillar groups, each second channel pillar group including a plurality of second channel pillars arranged along the first direction, the first channel pillar groups and the second channel pillar groups being alternately arranged along a second direction, the projections of the first channel pillars and the corresponding second channel pillars along the second direction having an overlapping region, the first direction being perpendicular to the second direction; and a plurality of first word line grids, the first word line grids extending along the first direction, each first word line grid controlling... Each of the first channel posts in a first channel post group is provided; a plurality of second word line grids are provided, extending along the first direction, each second word line grid controlling each of the second channel posts in a second channel post group; a plurality of first bit lines are provided, extending along the second direction, each first bit line electrically connected to a corresponding first channel post in each first channel post group; a plurality of second bit lines are provided, extending along the second direction, each second bit line electrically connected to a corresponding second channel post in each second channel post group, the first bit lines and the second bit lines being arranged alternately along the first direction.

[0007] Optionally, it further includes: a first edge portion and a second edge portion corresponding to each of the first channel posts, wherein the first edge portion is connected to the corresponding first channel post and the second edge portion is separated from the first channel post; and a third edge portion and a fourth edge portion corresponding to each of the second channel posts, wherein the fourth edge portion is connected to the corresponding second channel post and the third edge portion is separated from the second channel post.

[0008] Optionally, each first bit line includes a first edge portion corresponding to each first channel post and a third edge portion corresponding to each second channel post; each second bit line includes a fourth edge portion corresponding to each second channel post and a second edge portion corresponding to each first channel post.

[0009] Optionally, it may also include: a plurality of bit line isolation layers, the bit line isolation layers extending along the second direction, each bit line isolation layer being located between adjacent first bit lines and second bit lines.

[0010] Optionally, it may also include: a first isolation layer, the first isolation layer covering the first edge portion, the second edge portion, the third edge portion, the fourth edge portion, and a portion of the sidewalls of the first channel post and the second channel post.

[0011] Optionally, the first word line grid and the second word line grid are located on the first isolation layer; the first word line grid is connected to a portion of the sidewall of the first channel post; the second word line grid is connected to a portion of the sidewall of the second channel post.

[0012] Optionally, it further includes: a second isolation layer, the second isolation layer being located on the first isolation layer, the second isolation layer covering a portion of the sidewalls of the first channel post and the second channel post, and the first word grid and the second word grid being covered by the first isolation layer and the second isolation layer.

[0013] Optionally, it further includes: a first source / drain doped layer located within the first channel pillars on both sides of the first word gate along the extension direction of the first channel pillar, wherein each first bit line is electrically connected to the first source / drain doped layer within each of the first channel pillars; and a second source / drain doped layer located within the second channel pillars on both sides of the second word gate along the extension direction of the second channel pillar, wherein each second bit line is electrically connected to the second source / drain doped layer within each of the second channel pillars.

[0014] Optionally, the first word line gate includes a gate-around structure, a dual-gate structure, or a single-gate structure; the second word line gate includes a gate-around structure, a dual-gate structure, or a single-gate structure.

[0015] Optionally, the materials of the first bit line and the second bit line include: metal silicide; the metal silicide includes: nickel silicon, cobalt silicon or titanium silicon.

[0016] Accordingly, the present invention also provides a method for forming a dynamic random access memory array, comprising: forming a plurality of first channel pillar groups, each first channel pillar group including a plurality of first channel pillars arranged along a first direction; forming a plurality of second channel pillar groups, each second channel pillar group including a plurality of second channel pillars arranged along the first direction, the first channel pillar groups and the second channel pillar groups being alternately arranged along a second direction, the projections of the first channel pillars and the corresponding second channel pillars along the second direction having an overlapping area, the first direction being perpendicular to the second direction; forming a plurality of first word line grids, the first word line grids extending along the first direction, each first... A word line grid controls each of the first channel posts in one first channel post group; a plurality of second word line grids are formed, the second word line grids extending along the first direction, each second word line grid controlling each of the second channel posts in one second channel post group; a plurality of first bit lines are formed, the first bit lines extending along the second direction, each first bit line electrically connected to the corresponding first channel post in each first channel post group; a plurality of second bit lines are formed, the second bit lines extending along the second direction, each second bit line electrically connected to the corresponding second channel post in each second channel post group, the first bit lines and the second bit lines being arranged alternately along the first direction.

[0017] Optionally, a method for forming a plurality of first channel pillars and a plurality of second channel pillars includes: providing a substrate, the substrate including a base and a plurality of active regions arranged in parallel along a first direction on the base, the active regions extending along a second direction; and performing patterned etching on the active regions to form a plurality of first channel pillars and a plurality of second channel pillars.

[0018] Optionally, after patterning etching of the active region, a plurality of first pre-processed bodies and a plurality of second pre-processed bodies are formed. Each first channel post is located on one first pre-processed body, and each second channel post is located on one second pre-processed body. The projection of the first channel post toward the substrate is within the projection range of the first pre-processed body toward the substrate, and the projection of the second channel post toward the substrate is within the projection range of the second pre-processed body toward the substrate.

[0019] Optionally, the projections of the first preprocessor and the corresponding second preprocessor along the second direction coincide.

[0020] Optionally, along the second direction, the first pretreatment body includes: a first edge portion, a first middle portion, and a second edge portion, wherein the first middle portion is located between the first edge portion and the second edge portion, the first edge portion is connected to the first channel post, and the second edge portion is separated from the first channel post; along the second direction, the second pretreatment body includes: a third edge portion, a second middle portion, and a fourth edge portion, wherein the second middle portion is located between the third edge portion and the fourth edge portion, the fourth edge portion is connected to the second channel post, and the third edge portion is separated from the second channel post.

[0021] Optionally, the method for forming the first bit line and the second bit line includes: depositing a sidewall layer covering the first edge portion, the second edge portion, the third edge portion, and the second edge portion; using the sidewall layer as a mask, etching away the first intermediate portion and the second intermediate portion until the first channel pillar and the second channel pillar are exposed, forming a plurality of bit line isolation trenches, the bit line isolation trenches extending along the second direction; forming a bit line isolation layer within the bit line isolation trenches; after forming the bit line isolation layer, removing the sidewall layer to form a plurality of first bit line grooves and a plurality of second bit line grooves, the first bit line grooves extending along the second direction. The first bit groove exposes the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts. Each second bit groove exposes the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts. The first bit line is formed based on the first edge groove exposing the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts. The second bit line is formed based on the second bit groove exposing the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts.

[0022] Optionally, the method for forming a first bit line based on the first bit groove exposing the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts, and forming a second bit line based on the second bit groove exposing the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts, includes: forming a metal layer in the first bit groove and the second bit groove; after forming the metal layer, performing an annealing process such that the metal layer and the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts generate the first bit line, and the metal layer and the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts generate the second bit line.

[0023] Optionally, the material of the sidewall layer is different from the materials of the first pre-processed body, the second pre-processed body, and the bit line isolation layer.

[0024] Optionally, the materials of the first bit line and the second bit line include: metal silicide; the metal silicide includes: nickel silicon, cobalt silicon or titanium silicon.

[0025] Optionally, after performing patterned etching on the active region, the method further includes: forming a first isolation layer, the first isolation layer covering the first pre-processed body, the second pre-processed body, and a portion of the sidewalls of the first channel post and the second channel post.

[0026] Optionally, the first word line grid and the second word line grid are formed on the first isolation layer; the first word line grid is connected to a portion of the sidewall of the first channel post; and the second word line grid is connected to a portion of the sidewall of the second channel post.

[0027] Optionally, after forming the first word grid and the second word grid, the method further includes: forming a second isolation layer on the first isolation layer, the second isolation layer covering a portion of the sidewalls of the first channel post and the second channel post, and the first word grid and the second word grid being covered by the first isolation layer and the second isolation layer.

[0028] Optionally, after forming the first word line gate and the second word line gate, the method further includes: forming a first source / drain doped layer in the first channel pillars on both sides of the first word line gate along the extension direction of the first channel pillars, wherein each first bit line is electrically connected to the first source / drain doped layer in each of the first channel pillars; and forming a second source / drain doped layer in the second channel pillars on both sides of the second word line gate along the extension direction of the second channel pillars, wherein each second bit line is electrically connected to the second source / drain doped layer in each of the second channel pillars.

[0029] Optionally, the first word line gate includes a gate-around structure, a dual-gate structure, or a single-gate structure; the second word line gate includes a gate-around structure, a dual-gate structure, or a single-gate structure.

[0030] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0031] In the dynamic random access memory array of the present invention, the transistors corresponding to the enabled bit lines (the first bit line or the second bit line) and the transistors corresponding to the disabled bit lines (the second bit line or the first bit line) are controlled by different word line gates (the first word line gate or the second word line gate). When the bit line interval is activated, the transistors corresponding to the disabled bit lines do not need to be turned on. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. In addition, the projections of the first channel pillar and the corresponding second channel pillar along the second direction have an overlapping area, which allows the first channel pillar and the second channel pillar to have more formation space. When the product of the first channel pillar and the second channel pillar increases, the problem of channel tilting or bending can be reduced.

[0032] Furthermore, the materials of the first bit line and the second bit line include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line and the first channel post, and also reduce the contact resistance between the second bit line and the second channel post.

[0033] In the method for forming a dynamic random access memory array according to the technical solution of the present invention, the transistors corresponding to the enabled bit lines (the first bit line or the second bit line) and the transistors corresponding to the disabled bit lines (the second bit line or the first bit line) are controlled by different word line gates (the first word line gate or the second word line gate). When the bit line interval is activated, the transistors corresponding to the disabled bit lines do not need to be turned on. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. In addition, the projections of the first channel pillar and the corresponding second channel pillar along the second direction have an overlapping area, which allows the first channel pillar and the second channel pillar to have more forming space. When the product of the first channel pillar and the second channel pillar increases, the problem of channel tilting or bending can be reduced.

[0034] Furthermore, the method for forming the first bit line and the second bit line includes: depositing a sidewall layer to form a sidewall layer covering the first edge portion, the second edge portion, the third edge portion, and the second edge portion; using the sidewall layer as a mask, etching away the first intermediate portion and the second intermediate portion until the first channel pillar and the second channel pillar are exposed, forming a plurality of bit line isolation trenches, the bit line isolation trenches extending along the second direction; forming a bit line isolation layer within the bit line isolation trenches; after forming the bit line isolation layer, removing the sidewall layer to form a plurality of first bit line grooves and a plurality of second bit line grooves, the first bit line grooves extending along the second direction. The first bit line is formed by exposing the first edge portion corresponding to each of the first channel pillars and the third edge portion corresponding to each of the second channel pillars, and the second bit line is formed by exposing the fourth edge portion corresponding to each of the second channel pillars and the second edge portion corresponding to each of the first channel pillars. The first bit line and the second bit line are formed by self-alignment based on the deposited sidewall layer, which allows the width of the first bit line and the second bit line along the second direction to be very small, resulting in a larger overlap area between the projections of the first channel pillars and the corresponding second channel pillars along the second direction. This further increases the formation space of the first channel pillars and the second channel pillars, reducing the problem of channel tilting or bending. Furthermore, the self-aligned formation process effectively reduces the photomask required to form the first bit line and the second bit line, thereby reducing the production cost of the device structure.

[0035] Furthermore, the materials of the first bit line and the second bit line include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line and the first channel post, and also reduce the contact resistance between the second bit line and the second channel post. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a dynamic random access memory array.

[0037] Figure 2 This is a schematic diagram of another type of dynamic random access memory array;

[0038] Figures 3 to 35 This is a schematic diagram of the structure of each step in the method for forming a dynamic random access memory array in an embodiment of the present invention. Detailed Implementation

[0039] As described in the background section, existing dynamic random access memory (DRAM) arrays still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of a dynamic random access memory array.

[0041] Please refer to Figure 1 A dynamic random access memory array includes: a plurality of channel pillar groups 100, each of the channel pillar groups 100 including a plurality of channel pillars 1001 arranged along a first direction X, the plurality of channel pillar groups 100 being arranged along a second direction Y, the projections of corresponding channel pillars 1001 in each of the channel pillar groups 100 coinciding along the second direction Y, the first direction X being perpendicular to the second direction Y; a plurality of word line gates 101 extending along the first direction X, each of the word line gates 101 controlling each of the channel pillars 1001 in one of the channel pillar groups 100; and a plurality of bit lines 102 extending along the second direction Y, each of the bit lines 102 being electrically connected to a corresponding channel pillar 1001 in each of the channel pillar groups 100.

[0042] In this embodiment, when the bit line 102 (BL) interval is activated to prevent the sensing margin from being reduced due to bit line 102 coupling (BL-BL coupling), the data stored in the transistors that do not need to be activated (the transistors corresponding to the unactivated bit line 102) is lost because a word line gate 101 (WL) can turn on all transistors (including the transistors corresponding to the bit line 102 that are turned on and the transistors corresponding to the unactivated bit line 102).

[0043] Therefore, in order to avoid data loss, the dynamic random access memory array uses all the bit lines 102 to be enabled. However, this will cause the bit lines 102 to be coupled, resulting in a reduction in the sensing tolerance.

[0044] To address the aforementioned problems, another type of dynamic random access memory array has been provided in the prior art. This will be described in detail below with reference to the accompanying drawings.

[0045] Figure 2 This is a schematic diagram of another type of dynamic random access memory array.

[0046] Please refer to Figure 2A dynamic random access memory (DRAM) array includes: a plurality of first channel pillar groups 200, each first channel pillar group 200 including a plurality of first channel pillars 2001 arranged along a first direction X; a plurality of second channel pillar groups 201, each second channel pillar group 201 including a plurality of second channel pillars 2011 arranged along the first direction X, the first channel pillar groups 200 and the second channel pillar groups 201 alternating along a second direction Y, the first direction X being perpendicular to the second direction Y; a plurality of first word line gates 202 extending along the first direction X, each first word line gate 202 controlling each first channel pillar 2001 in one of the first channel pillar groups 200; and a plurality of second word line gates 202 extending along the first direction X. A wire grid 203 extends along the first direction X, and each second word wire grid 203 controls each second channel post 2011 in a second channel post group 201; a plurality of first bit lines 204 extend along the second direction Y, and each first bit line 204 is electrically connected to a corresponding first channel post 2001 in each first channel post group 200; a plurality of second bit lines 205 extend along the second direction Y, and each second bit line 205 is electrically connected to a corresponding second channel post 2011 in each second channel post group 201, and the first bit lines 204 and the second bit lines 205 are arranged alternately along the first direction X.

[0047] In this embodiment, the transistors corresponding to the enabled bit lines (the first bit line 204 or the second bit line 205) and the transistors corresponding to the disabled bit lines (the second bit line 205 or the first bit line 204) are controlled by different word line gates (the first word line gate 202 or the second word line gate 203). When the bit line interval is activated, the transistors corresponding to the disabled bit lines can remain off. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss from the transistors corresponding to the disabled bit lines.

[0048] Please continue to refer to this. Figure 2 However, since the width dimensions of the first bit line 204 and the second bit line 205 along the second direction Y are basically the same as the width dimensions of the first channel post 2001 and the second channel post 2011 along the second direction Y, in order to avoid electrical connection between the transistors corresponding to the enabled bit lines and the unenabled bit lines, the transistors corresponding to the enabled bit lines and the unenabled bit lines need to be completely offset in the column-up channel in the design, that is, the projections of the first channel post 2001 and the corresponding second channel post 2011 along the second direction Y do not have overlapping areas.

[0049] Since the projections of the first channel pillar 2001 and the corresponding second channel pillar 2011 along the second direction Y do not overlap, the transistors in the dynamic random access memory array can be divided into more columns along the first direction X (the number of columns is...). Figure 1 The dynamic random access memory array shown is twice the size of the dynamic random access memory array, without reducing the storage density of the dynamic random access memory array (i.e., Figure 1 and Figure 2 The dynamic random access memory array shown has the same number of transistors in the same area. This will cause the volume of the first channel pillar 2001 and the second channel pillar 2011 in the dynamic random access memory array to be halved. When the volume of the first channel pillar 2001 and the second channel pillar 2011 is reduced, the channel tilting or bending problem is likely to occur.

[0050] Based on this, the present invention provides a dynamic random access memory array and its formation method. The transistors corresponding to the enabled bit lines (the first bit line or the second bit line) and the transistors corresponding to the disabled bit lines (the second bit line or the first bit line) are controlled by different word line gates (the first word line gate or the second word line gate). When the bit line interval is activated, the transistors corresponding to the disabled bit lines do not need to be turned on. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. Furthermore, the projections of the first channel pillar and the corresponding second channel pillar along the second direction have an overlapping area, providing more formation space for the first and second channel pillars. As the product of the first and second channel pillars increases, the problem of channel tilting or bending can be reduced.

[0051] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] Figures 3 to 35 This is a schematic diagram of the steps in a method for forming a dynamic random access memory array according to an embodiment of the present invention.

[0053] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 A schematic cross-sectional view along line AA shows a substrate 300, which includes a base 3001 and a plurality of active regions 3002 arranged parallel to a first direction X on the base 3001. The active regions 3002 extend along a second direction Y, and the first direction X is perpendicular to the second direction Y.

[0054] In this embodiment, the substrate 300 is made of silicon.

[0055] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0056] In this embodiment, the substrate 300 includes a first surface 300a and a second surface 300b opposite to each other, the first surface 300a exposing the surface of the active region 3002, and the second surface 300b exposing the surface of the substrate 3001.

[0057] Please refer to Figure 5 , Figure 5 and Figure 4 With the view direction consistent, a first initial isolation layer 301 is formed on the substrate 300, the first initial isolation layer 301 covers the active region 3002 and exposes the surface of the active region 3002.

[0058] The first initial isolation layer 301 is made of insulating material.

[0059] In this embodiment, the material of the first initial isolation layer 301 is silicon oxide.

[0060] Please refer to Figures 6 to 8 , Figure 7 yes Figure 6 Schematic diagram of the cross section along line BB. Figure 8 yes Figure 6 A cross-sectional diagram along the CC line shows the formation of several first channel column groups 302, each first channel column group 302 including several first channel columns 3021 arranged along the first direction X; and several second channel column groups 303, each second channel column group 303 including several second channel columns 3031 arranged along the first direction X. The first channel column groups 302 and the second channel column groups 303 are alternately arranged along the second direction Y, and the projections of the first channel column 3021 and the corresponding second channel column 3031 along the second direction Y have an overlapping area.

[0061] In this embodiment, the method for forming a plurality of first channel pillars 3021 and a plurality of second channel pillars 3031 includes: etching the active region 3002 from the first surface 300a to the second surface 300b to form a plurality of first channel pillars 3021 and a plurality of second channel pillars 3031.

[0062] In this embodiment, after the active region 3002 is patterned and etched, a plurality of first pre-processed bodies 3022 and a plurality of second pre-processed bodies 3032 are formed. Each first channel post 3021 is located on one first pre-processed body 3022, and each second channel post 3031 is located on one second pre-processed body 3032. The projection of the first channel post 3021 toward the substrate 3001 is within the projection range of the first pre-processed body toward the substrate 3001, and the projection of the second channel post 3031 toward the substrate 3001 is within the projection range of the second pre-processed body toward the substrate 3001.

[0063] In this embodiment, along the second direction Y, the first pretreatment body 3022 includes: a first edge portion 3022a, a first middle portion 3022c, and a second edge portion 3022b. The first middle portion 3022c is located between the first edge portion 3022a and the second edge portion 3022b. The first edge portion 3022a is connected to the first channel post 3021, and the second edge portion 3022b is separated from the first channel post. Along the second direction Y, the second pretreatment body 3032 includes: a third edge portion 3032a, a second middle portion 3032c, and a fourth edge portion 3032b. The second middle portion 3032c is located between the third edge portion 3032a and the fourth edge portion 3032b. The fourth edge portion 3032b is connected to the second channel post 3031, and the third edge portion 3032a is separated from the second channel post 3021.

[0064] In this embodiment, the first pretreatment body 3022 is located between the first channel post 3021 and the substrate 3001, and the second pretreatment body 3032 is located between the second channel post 3031 and the substrate 3001.

[0065] In this embodiment, the projections of the first preprocessing body 3022 and the corresponding second preprocessing body 3032 along the second direction Y coincide.

[0066] In this embodiment, since the substrate 300 is made of silicon, the first channel pillar 3021 and the second channel pillar 3031 are also made of silicon.

[0067] In other embodiments, the materials of the first channel pillar and the second channel pillar may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0068] In this embodiment, since the substrate 300 is made of silicon, the first pretreatment body 3022 and the second pretreatment body 3032 are also made of silicon.

[0069] In other embodiments, the materials of the first pretreatment body and the second pretreatment body may also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium galliumide.

[0070] In this embodiment, the interface morphology of the first channel post 3021 and the second channel post 3031 is elliptical, and the cross section is a plane parallel to the first surface 300a and the second surface 300b.

[0071] In other embodiments, the interface morphology of the first channel post and the second channel post may also be circular, trapezoidal, rectangular, rhomboid, or irregular polygon, etc., and the cross section is a plane parallel to the first surface and the second surface.

[0072] It should be noted that after etching the active region 3002, the formed opening will be filled with insulating material again, so that the first initial isolation layer 301 can cover each of the first channel post 3021, the second channel post 3031, the first pre-treatment body 3022 and the second pre-treatment body 3032, and the first initial isolation layer 301 exposes the surfaces of the first channel post 3021 and the second channel post 3031.

[0073] Please refer to Figure 9 and Figure 10 , Figure 9 and Figure 7 The view orientation is consistent. Figure 10 and Figure 8 With the view direction consistent, the first initial isolation layer 301 is etched back from the first surface 300a to the second surface 300b to form the first isolation layer 304.

[0074] In this embodiment, since the material of the first initial isolation layer 301 is silicon oxide, the material of the first isolation layer 304 is also silicon oxide.

[0075] In this embodiment, the first isolation layer 304 is formed to cover part of the sidewalls of the first pretreatment body 3022, the second pretreatment body 3032, the first channel post 3021, and the second channel post 3031, and the surface of the first isolation layer 304 is lower than the first surface 300a.

[0076] Please refer to Figures 11 to 13 , Figure 12 yes Figure 11 Schematic diagram of the cross section along the DD line. Figure 13 yes Figure 11A cross-sectional diagram along the EE line shows the formation of several first word line grids 305, each extending along the first direction X, with each first word line grid 305 controlling each first channel post 3021 in a first channel post group 302; and several second word line grids 306, each extending along the first direction X, with each second word line grid 306 controlling each second channel post 3031 in a second channel post group 303.

[0077] In this embodiment, the first word line gate 305 adopts a gate all around (GAA) structure, that is, each first word line gate 305 surrounds and covers each of the first channel pillars 3021 in the first channel pillar group 302.

[0078] In other embodiments, the first word line gate may also employ a dual gate structure or a single gate structure.

[0079] In this embodiment, the second word line gate 306 adopts a gate-around structure, that is, each second word line gate 306 surrounds each of the second channel pillars 3031 in the second channel pillar group 303.

[0080] In other embodiments, the second word line gate may also employ a dual-gate structure or a single-gate structure.

[0081] The first character line grid 305 and the second character line grid 306 are formed on the first isolation layer 304; the first character line grid 305 is connected to a portion of the sidewall of the first channel post 3021; ​​the second character line grid 306 is connected to a portion of the sidewall of the second channel post 3031.

[0082] In this embodiment, the first word line grid 305 and the second word line grid 306 are formed on the first isolation layer 304; the first word line grid 305 surrounds and covers a portion of the sidewall of the first channel post 3021; ​​the second word line grid 306 surrounds and covers a portion of the sidewall of the second channel post 3031.

[0083] In this embodiment, both the first word line gate 305 and the second word line gate 306 include a gate dielectric layer and a gate layer (not shown), wherein the gate dielectric layer forms part of the sidewalls of each of the first channel pillars 3021 and the second channel pillars 3031, and the gate layer surrounds and covers the gate dielectric layer.

[0084] Please refer to Figure 14 and Figure 15 , Figure 14 and Figure 12 The view orientation is consistent. Figure 15 and Figure 13 With the view direction consistent, after forming the first word line grid 305 and the second word line grid 306, a second isolation layer 307 is formed on the first isolation layer 304. The second isolation layer 307 covers part of the sidewalls of the first channel post 3021 and the second channel post 3031, and the first isolation layer 304 and the second isolation layer 307 cover the first word line grid 305 and the second word line grid 306.

[0085] The second isolation layer 307 is made of insulating material.

[0086] In this embodiment, the material of the second isolation layer 307 is silicon oxide.

[0087] In this embodiment, the second isolation layer 307 exposes the surfaces of the first channel post 3021 and the second channel post 3031.

[0088] Please refer to Figure 16 and Figure 17 , Figure 16 and Figure 14 The view orientation is consistent. Figure 17 and Figure 15 With the view direction consistent, after the second isolation layer 307 is formed, a first source / drain doped layer 308 is formed in the first channel pillar 3021 on one side of the first word line gate 305 along the extension direction of the first word line gate 305; and a second source / drain doped layer 309 is formed in the second channel pillar 3031 on one side of the second word line gate 306 along the extension direction of the second word line gate 306.

[0089] In this embodiment, the first surface 300a exposes the first source / drain doped layer 308 in the first channel post 3021 on the side of the first word gate 305, and the second source / drain doped layer 309 in the second channel post 3031 on the side of the second word gate 306.

[0090] In this embodiment, the method for forming the first source / drain doped layer 308 in the first channel post 3021 on the side of the first word gate 305 and the second source / drain doped layer 309 in the second channel post 3031 on the side of the second word gate 306 includes: performing ion implantation from the first surface 300a to the second surface 300b to form the first source / drain doped layer 308 and the second source / drain doped layer 309.

[0091] Please refer to Figure 18 and Figure 19 , Figure 18 and Figure 16 The view orientation is consistent. Figure 19 and Figure 17 With the view direction consistent, after forming the first source / drain doped layer 308 and the second source / drain doped layer 309 on one side of the first channel pillar 3021 and the second channel pillar 3031, the substrate 300 is thinned from the second surface 300b toward the first surface 300a to remove the substrate 3001 until the first isolation layer 304 is exposed.

[0092] The process of thinning the substrate 300 from the second surface 300b toward the first surface 300a includes: physical mechanical polishing, chemical mechanical polishing, or wet etching.

[0093] In this embodiment, the process of thinning the substrate 300 from the second surface 300b to the first surface 300a is a chemical mechanical polishing process.

[0094] Please refer to Figure 20 and Figure 21 , Figure 20 and Figure 18 The view orientation is consistent. Figure 21 and Figure 19 With the view direction consistent, after the thinning process, along the extension direction of the first word line gate 305, a first source / drain doped layer 308 is formed in the first channel pillar 3021 on the other side of the first word line gate 305; along the extension direction of the second word line gate 306, a second source / drain doped layer 309 is formed in the second channel pillar 3031 on the other side of the second word line gate 306.

[0095] In this embodiment, the method for forming the first source / drain doped layer 308 in the first channel post 3021 on the other side of the first word line gate 305 and the second source / drain doped layer 309 in the second channel post 3031 on the other side of the second word line gate 306 includes: performing ion implantation from the second surface 300b to the first surface 300a to form the first source / drain doped layer 308 and the second source / drain doped layer 309.

[0096] At this point, the manufacturing process for each transistor in the dynamic random access memory array is complete.

[0097] Please refer to Figures 22 to 24 , Figure 23 yes Figure 22 Schematic diagram of the cross section along the FF line. Figure 24 yes Figure 22A cross-sectional diagram along the GG line shows that after the first source / drain doped layer 308 and the second source / drain doped layer 309 are formed on the other side of the first channel pillar 3021 and the second channel pillar 3031, a plurality of positioning trenches 310 are formed. The positioning trenches 310 extend along the second direction Y, and the second trench exposes the first pretreatment body 3022 and the second pretreatment body 3032.

[0098] In this embodiment, the method for forming the positioning trench 310 includes etching a portion of the first pretreatment body 3022, a portion of the second pretreatment body 3032, and a portion of the first isolation layer 304 from the second surface 300b to the first surface 300a to form the positioning trench 310.

[0099] It should be noted that the positioning groove 310 is used to position the first and second position lines formed subsequently.

[0100] Following the positioning groove 310, a plurality of first position lines are formed, each extending along the second direction Y, and each first position line is electrically connected to a corresponding first channel post 3021 in each first channel post group 302. A plurality of second position lines are also formed, each extending along the second direction Y, and each second position line is electrically connected to a corresponding second channel post 3031 in each second channel post group 303. The first and second position lines are alternately arranged along the first direction X. For the specific formation process of the first and second position lines, please refer to [reference needed]. Figures 25 to 35 .

[0101] Please refer to Figure 25 and Figure 26 , Figure 25 and Figure 23 The view orientation is consistent. Figure 26 and Figure 24 With the view direction consistent, a sidewall layer 311 is deposited to form a sidewall layer 311, which covers the first edge portion 3022a, the second edge portion 3022b, the third edge portion 3032a, and the second edge portion 3022b.

[0102] In this embodiment, the method for forming the sidewall layer 311 includes: forming a sidewall material layer (not shown) on the sidewall, bottom surface and surface of the positioning groove 310 and the first isolation layer 304; removing the sidewall material layer from the bottom surface of the positioning groove and the surface of the first isolation layer 304 to form the sidewall layer 311.

[0103] In this embodiment, the process for forming the sidewall material layer includes: atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0104] Please refer to Figure 27 and Figure 28 , Figure 27 and Figure 25 The view orientation is consistent. Figure 28 and Figure 26 With the view direction consistent, using the sidewall layer 311 as a mask, the first intermediate portion 3022c and the second intermediate portion 3032c are etched away until the first channel post 3021 and the second channel post 3031 are exposed, forming a plurality of bit line isolation trenches 312, which extend along the second direction Y.

[0105] It should be noted that, in this embodiment, the process of removing the first intermediate portion 3022c and the second intermediate portion 3032c also includes: using the sidewall layer 311 as a mask to etch and remove a portion of the first isolation layer 304.

[0106] It should be noted that, in this embodiment, etching away the first intermediate portion 3022c and the second intermediate portion 3032c until the first channel post 3021 and the second channel post 3031 are exposed specifically means: etching the first intermediate portion 3022c and the second intermediate portion 3032c requires exposing at least the first channel post 3021 and the second channel post 3031, so that the second edge portion 3022b and the first channel post 3021 are completely separated, and the third edge portion 3032a and the second channel post 3031 are completely separated; at the same time, the etching depth cannot reach the positions of the first word line gate 305 and the second word line gate 306, and the specific etching depth can be determined by the performance requirements of the device structure.

[0107] It should be noted that, in this embodiment, since the sidewall layer 311 is used as a mask to etch the first channel post 3021, the second channel post 3031, the first pretreatment body 3022, the second pretreatment body 3032, and the first isolation layer 304, in order to increase the etching selectivity of the sidewall layer 311 with respect to the first channel post 3021, the second channel post 3031, the first pretreatment body 3022, the second pretreatment body 3032, and the first isolation layer 304, the material of the sidewall layer 311 needs to be different from the material of the first channel post 3021, the second channel post 3031, the first pretreatment body 3022, the second pretreatment body 3032, and the first isolation layer 304.

[0108] In this embodiment, the material of the sidewall layer 311 can be silicon nitride, or metals and other metal oxides, such as tungsten or aluminum oxide.

[0109] Please refer to Figure 29 and Figure 30 , Figure 29 and Figure 27 The view orientation is consistent. Figure 30 and Figure 28 With the view direction consistent, after forming the bit line isolation trench 312, a bit line isolation layer 313 is formed in the bit line isolation trench 312.

[0110] It should be noted that, in this embodiment, the bit line isolation layer 313 is also formed within the positioning groove 310.

[0111] The bit line isolation layer 313 is made of insulating material. Since the sidewall layer 311 needs to be removed later, in order to prevent damage to the bit line isolation layer 313 during the removal of the sidewall layer 311, the material of the bit line isolation layer 313 also needs to be different from the material of the sidewall layer 311.

[0112] In this embodiment, the bit line isolation layer 313 is made of silicon oxide.

[0113] Please refer to Figure 31 and Figure 32 , Figure 31 and Figure 29 The view orientation is consistent. Figure 32 and Figure 30 With the view direction consistent, after forming the bit line isolation layer 313, the sidewall layer 311 is removed to form a plurality of first bit line grooves 314 and a plurality of second bit line grooves 315. The first bit line grooves 314 extend along the second direction Y, and the first bit line grooves 314 expose the first edge portion 3022a corresponding to each of the first channel posts 3021 and the third edge portion 3032a corresponding to each of the second channel posts 3031. Each second bit line groove 315 exposes the fourth edge portion 3032b corresponding to each of the second channel posts 3031 and the second edge portion 3022b corresponding to each of the first channel posts 3021.

[0114] It should be noted that, in this embodiment, the first positioning groove 314 is formed by removing the sidewall layer 311 of one sidewall of the positioning groove 310, and the second positioning groove 315 is formed by removing the sidewall layer 311 of the other sidewall of the positioning groove 310.

[0115] Please refer to Figures 33 to 35 , Figure 33 This is a top view of the dynamic random access memory array, omitting the first and second isolation layers. Figure 34 yes Figure 33 Schematic diagram of the cross section along line HH in the middle. Figure 35 yes Figure 33 A cross-sectional diagram along line II shows that the first edge portion 3022a corresponding to each of the first channel posts 3021 and the third edge portion 3032a corresponding to each of the second channel posts 3031 are exposed based on the first bit groove 314 to form the first bit line 316, and the fourth edge portion 3032b corresponding to each of the second channel posts 3031 and the second edge portion 3022b corresponding to each of the first channel posts 3021 are exposed based on the second bit groove 315 to form the second bit line 317.

[0116] Since the transistors corresponding to the enabled bit lines (first bit line 316 or second bit line 317) and the transistors corresponding to the disabled bit lines (second bit line 317 or first bit line 316) are controlled by different word line gates (first word line gate 305 or second word line gate 306), when the bit line interval is activated, the transistors corresponding to the disabled bit lines do not need to be turned on. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. In addition, the projections of the first channel post 3021 and the corresponding second channel post 3031 along the second direction Y have an overlapping area, which allows the first channel post 3021 and the second channel post 3031 to have more forming space. When the product of the first channel post 3021 and the second channel post 3031 increases, the problem of channel tilting or bending can be reduced.

[0117] The first bit line 316 and the second bit line 317 are formed by self-alignment based on the deposited sidewall layer 311. This allows the width of the first bit line 316 and the second bit line 317 along the second direction Y to be very small, resulting in a larger overlap area between the projections of the first channel pillar 3021 and the corresponding second channel pillar 3031 along the second direction Y. This further increases the formation space of the first channel pillar 3021 and the second channel pillar 3031, reducing the problem of channel tilting or bending. In addition, the self-aligned formation process can effectively reduce the photomask required to form the first bit line 316 and the second bit line 317, thereby reducing the production cost of the device structure.

[0118] In this embodiment, the method of forming a first bit line 316 based on the first bit line groove 314 exposing the first edge portion 3022a corresponding to each of the first channel posts 3021 and the third edge portion 3032a corresponding to each of the second channel posts 3031, and forming a second bit line 317 based on the second bit line groove 315 exposing the fourth edge portion 3032b corresponding to each of the second channel posts 3031 and the second edge portion 3022b corresponding to each of the first channel posts 3021, includes: exposing the first edge portion 3022a corresponding to each of the first channel posts 3021 and the third edge portion 3032a corresponding to each of the second channel posts 3031. A metal layer (not shown) is formed in the second bit groove 315; after the metal layer is formed, an annealing process is performed so that the metal layer and the first edge portion 3022a corresponding to each of the first channel posts 3021 and the third edge portion 3032a corresponding to each of the second channel posts 3031 generate the first bit line 316, and the metal layer and the fourth edge portion 3032b corresponding to each of the second channel posts 3031 and the second edge portion 3022b corresponding to each of the first channel posts 3021 generate the second bit line 317.

[0119] In this embodiment, the materials of the first bit line 316 and the second bit line 317 include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line 316 and the first channel post 3021, and reduce the contact resistance between the second bit line 317 and the second channel post 3031.

[0120] In this embodiment, each first bit line 316 is electrically connected to the first source / drain doped layer 308 within each first channel post 3021; ​​each second bit line 317 is electrically connected to the second source / drain doped layer 309 within each second channel post 3031.

[0121] Accordingly, this embodiment of the invention also provides a dynamic random access memory array, please refer to [link / reference needed]. Figures 33 to 35The system includes: a plurality of first channel post groups 302, each first channel post group 302 including a plurality of first channel posts 3021 arranged along a first direction X; a plurality of second channel post groups 303, each second channel post group 303 including a plurality of second channel posts 3031 arranged along the first direction X, the first channel post groups 302 and the second channel post groups 303 being alternately arranged along a second direction Y, the projections of the first channel posts 3021 and the corresponding second channel posts 3031 along the second direction Y having an overlapping area, the first direction X being perpendicular to the second direction Y; and a plurality of first word line grids 305, the first word line grids 305 extending along the first direction X, each first word line grid 305 controlling each of the first channel post groups 302. A first channel post 3021; ​​a plurality of second word line grids 306, the second word line grids 306 extending along the first direction X, each second word line grid 306 controlling each second channel post 3031 in a second channel post group 303; a plurality of first bit lines 316, the first bit lines 316 extending along the second direction Y, each first bit line 316 electrically connected to a corresponding first channel post 3021 in each first channel post group 302; a plurality of second bit lines 317, the second bit lines 317 extending along the second direction Y, each second bit line 317 electrically connected to a corresponding second channel post 3031 in each second channel post group 303, the first bit lines 316 and the second bit lines 317 being arranged alternately along the first direction X.

[0122] Since the transistors corresponding to the enabled bit lines (first bit line 316 or second bit line 317) and the transistors corresponding to the disabled bit lines (second bit line 317 or first bit line 316) are controlled by different word line gates (first word line gate 305 or second word line gate 306), when the bit line interval is activated, the transistors corresponding to the disabled bit lines do not need to be turned on. This solves both the problem of reduced sensing tolerance caused by bit line coupling and the problem of data loss of the transistors corresponding to the disabled bit lines. In addition, the projections of the first channel post 3021 and the corresponding second channel post 3031 along the second direction Y have an overlapping area, which allows the first channel post 3021 and the second channel post 3031 to have more forming space. When the product of the first channel post 3021 and the second channel post 3031 increases, the problem of channel tilting or bending can be reduced.

[0123] In this embodiment, it further includes: a first edge portion 3022a and a second edge portion 3022b corresponding to each first channel post 3021, wherein the first edge portion 3022a is connected to the corresponding first channel post 3021 and the second edge portion 3022b is separated from the first channel post; and a third edge portion 3032a and a fourth edge portion 3032b corresponding to each second channel post 3031, wherein the fourth edge portion 3032b is connected to the corresponding second channel post 3031 and the third edge portion 3032a is separated from the second channel post 3031.

[0124] In this embodiment, each first bit line 316 includes a first edge portion 3022a corresponding to each first channel post 3021 and a third edge portion 3032a corresponding to each second channel post 3031; each second bit line 317 includes a fourth edge portion 3032b corresponding to each second channel post 3031 and a second edge portion 3022b corresponding to each first channel post 3021.

[0125] In this embodiment, it further includes: a plurality of bit line isolation layers 313, the bit line isolation layers 313 extending along the second direction Y, and each bit line isolation layer 313 being located between adjacent first bit lines 316 and second bit lines 317.

[0126] In this embodiment, it further includes: a first isolation layer 304, which covers the first edge portion 3022a, the second edge portion 3022b, the third edge portion 3032a, the fourth edge portion 3032b, and a portion of the sidewalls of the first channel post 3021 and the second channel post 3031.

[0127] In this embodiment, the first word line gate 305 adopts a gate all around (GAA) structure, that is, each first word line gate 305 surrounds and covers each of the first channel pillars 3021 in the first channel pillar group 302.

[0128] In other embodiments, the first word line gate may also employ a dual gate structure or a single gate structure.

[0129] In this embodiment, the second word line gate 306 adopts a gate-around structure, that is, each second word line gate 306 surrounds each of the second channel pillars 3031 in the second channel pillar group 303.

[0130] In other embodiments, the second word line gate may also employ a dual-gate structure or a single-gate structure.

[0131] The first word line grid 305 and the second word line grid 306 are located on the first isolation layer 304; the first word line grid 305 surrounds and covers a portion of the sidewall of the first channel post 3021; ​​the second word line grid 306 surrounds and covers a portion of the sidewall of the second channel post 3031.

[0132] In this embodiment, the first word line grid 305 and the second word line grid 306 are formed on the first isolation layer 304; the first word line grid 305 surrounds and covers a portion of the sidewall of the first channel post 3021; ​​the second word line grid 306 surrounds and covers a portion of the sidewall of the second channel post 3031.

[0133] In this embodiment, it further includes: a second isolation layer 307, which is located on the first isolation layer 304. The second isolation layer 307 covers part of the sidewalls of the first channel post 3021 and the second channel post 3031, and the first word line grid 305 and the second word line grid 306 are covered by the first isolation layer 304 and the second isolation layer 307.

[0134] In this embodiment, it further includes: a first source / drain doped layer 308 located within the first channel pillars 3021 on both sides of the first word line gate 305 along the extending direction of the first word line gate 305, wherein each first bit line 316 is electrically connected to the first source / drain doped layer 308 within each first channel pillar 3021; ​​and a second source / drain doped layer 309 located within the second channel pillars 3031 on both sides of the second word line gate 306 along the extending direction of the second word line gate 306, wherein each second bit line 317 is electrically connected to the second source / drain doped layer 309 within each second channel pillar 3031.

[0135] In this embodiment, the first word line gate 305 includes a gate-around structure, a dual-gate structure, or a single-gate structure; the second word line gate 306 includes a gate-around structure, a dual-gate structure, or a single-gate structure.

[0136] In this embodiment, the materials of the first bit line 316 and the second bit line 317 include metal silicides; the metal silicides include nickel silicon, cobalt silicon, or titanium silicon. Using metal silicide materials can effectively reduce the contact resistance between the first bit line 316 and the first channel post 3021, and reduce the contact resistance between the second bit line 317 and the second channel post 3031.

[0137] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A dynamic random access memory array, characterized in that, include: A plurality of first trench column groups, each first trench column group comprising a plurality of first trench columns arranged along a first direction; A plurality of second channel column groups, each second channel column group including a plurality of second channel columns arranged along the first direction, the first channel column group and the second channel column group are arranged alternately along the second direction, the projections of the first channel column and the corresponding second channel column along the second direction have an overlapping area, and the first direction is perpendicular to the second direction; A plurality of first word grids, the first word grids extending along the first direction, each first word grid controlling each of the first channel posts in one first channel post group; A plurality of second word grids, the second word grids extending along the first direction, each second word grid controlling each second channel post in one second channel post group; A plurality of first bit lines, the first bit lines extending along the second direction, each of the first bit lines being electrically connected to the corresponding first channel post in each of the first channel post groups; A plurality of second bit lines, the second bit lines extending along the second direction, each second bit line being electrically connected to a corresponding second channel post in each second channel post group, the first bit lines and the second bit lines being arranged alternately along the first direction.

2. The dynamic random access memory array as described in claim 1, characterized in that, Also includes: Each of the first groove posts has a first edge portion and a second edge portion, wherein the first edge portion is connected to the corresponding first groove post and the second edge portion is separated from the first groove post; each of the second groove posts has a third edge portion and a fourth edge portion, wherein the fourth edge portion is connected to the corresponding second groove post and the third edge portion is separated from the second groove post.

3. The dynamic random access memory array as described in claim 2, characterized in that, Each first bit line includes a first edge portion corresponding to each first channel post and a third edge portion corresponding to each second channel post; each second bit line includes a fourth edge portion corresponding to each second channel post and a second edge portion corresponding to each first channel post.

4. The dynamic random access memory array as described in claim 2, characterized in that, Also includes: A plurality of bit line isolation layers, the bit line isolation layers extending along the second direction, each bit line isolation layer being located between adjacent first bit lines and second bit lines.

5. The dynamic random access memory array as described in claim 2, characterized in that, Also includes: A first isolation layer covers the first edge portion, the second edge portion, the third edge portion, the fourth edge portion, and a portion of the sidewalls of the first channel post and the second channel post.

6. The dynamic random access memory array as described in claim 5, characterized in that, The first word line grid and the second word line grid are located on the first isolation layer; the first word line grid is connected to a portion of the sidewall of the first channel post; the second word line grid is connected to a portion of the sidewall of the second channel post.

7. The dynamic random access memory array as described in claim 6, characterized in that, Also includes: A second isolation layer is located on top of the first isolation layer. The second isolation layer covers part of the sidewalls of the first channel post and the second channel post, and the first word grid and the second word grid are covered by the first isolation layer and the second isolation layer.

8. The dynamic random access memory array as described in claim 1, characterized in that, Also includes: Along the extension direction of the first channel pillar, a first source / drain doped layer is located within the first channel pillar on both sides of the first word line gate, and each first bit line is electrically connected to the first source / drain doped layer within each of the first channel pillars; along the extension direction of the second channel pillar, a second source / drain doped layer is located within the second channel pillar on both sides of the second word line gate, and each second bit line is electrically connected to the second source / drain doped layer within each of the second channel pillars.

9. The dynamic random access memory array as described in claim 1, characterized in that, The first word line gate includes: a gate-around structure, a dual-gate structure, or a single-gate structure; the second word line gate includes: a gate-around structure, a dual-gate structure, or a single-gate structure.

10. The dynamic random access memory array as described in claim 1, characterized in that, The materials of the first bit line and the second bit line include: metal silicides; metal silicides include: nickel silicon, cobalt silicon or titanium silicon.

11. A method for forming a dynamic random access memory array, characterized in that, include: A plurality of first trench column groups are formed, each first trench column group comprising a plurality of first trench columns arranged along a first direction; A plurality of second channel column groups are formed, each second channel column group including a plurality of second channel columns arranged along the first direction, the first channel column group and the second channel column group are arranged alternately along the second direction, the projections of the first channel column and the corresponding second channel column along the second direction have an overlapping area, and the first direction is perpendicular to the second direction; A plurality of first word grids are formed, the first word grids extending along the first direction, and each first word grid controls each first channel post in one first channel post group; A plurality of second word grids are formed, the second word grids extending along the first direction, and each second word grid controls each second channel post in one second channel post group; A plurality of first bit lines are formed, the first bit lines extend along the second direction, and each first bit line is electrically connected to the corresponding first channel post in each first channel post group. A plurality of second bit lines are formed, the second bit lines extend along the second direction, each second bit line is electrically connected to the corresponding second channel post in each second channel post group, and the first bit lines and the second bit lines are arranged alternately along the first direction.

12. The method for forming a dynamic random access memory array as described in claim 11, characterized in that, A method for forming a plurality of first channel pillars and a plurality of second channel pillars includes: providing a substrate, the substrate including a base and a plurality of active regions arranged parallel to each other along a first direction on the base, the active regions extending along a second direction; and performing patterned etching on the active regions to form a plurality of first channel pillars and a plurality of second channel pillars.

13. The method for forming a dynamic random access memory array as described in claim 12, characterized in that, After the active region is patterned and etched, a plurality of first pre-processed bodies and a plurality of second pre-processed bodies are formed. Each first channel pillar is located on one first pre-processed body, and each second channel pillar is located on one second pre-processed body. The projection of the first channel pillar toward the substrate is within the projection range of the first pre-processed body toward the substrate, and the projection of the second channel pillar toward the substrate is within the projection range of the second pre-processed body toward the substrate.

14. The method for forming a dynamic random access memory array as described in claim 13, characterized in that, The projection of the first preprocessor and the corresponding second preprocessor along the second direction coincide.

15. The method for forming a dynamic random access memory array as described in claim 13, characterized in that, Along the second direction, the first pretreatment body includes: a first edge portion, a first middle portion, and a second edge portion, wherein the first middle portion is located between the first edge portion and the second edge portion, the first edge portion is connected to the first channel post, and the second edge portion is separated from the first channel post; along the second direction, the second pretreatment body includes: a third edge portion, a second middle portion, and a fourth edge portion, wherein the second middle portion is located between the third edge portion and the fourth edge portion, the fourth edge portion is connected to the second channel post, and the third edge portion is separated from the second channel post.

16. The method for forming a dynamic random access memory array as described in claim 15, characterized in that, The method for forming the first bit line and the second bit line includes: depositing a sidewall layer covering the first edge portion, the second edge portion, the third edge portion, and the second edge portion; using the sidewall layer as a mask, etching away the first intermediate portion and the second intermediate portion until the first channel pillar and the second channel pillar are exposed, forming a plurality of bit line isolation trenches, the bit line isolation trenches extending along a second direction; forming a bit line isolation layer within the bit line isolation trenches; and after forming the bit line isolation layer, removing the sidewall layer to form a plurality of first bit line grooves and a plurality of second bit line grooves, the first bit line grooves extending along the second direction. Furthermore, the first bit slot exposes the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts, and each second bit slot exposes the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts; the first bit line is formed based on the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts exposed by the first bit slot, and the second bit line is formed based on the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts exposed by the second bit slot.

17. The method for forming a dynamic random access memory array as described in claim 16, characterized in that, The method for forming a first bit line based on the first bit slot exposing the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts, and for forming a second bit line based on the second bit slot exposing the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts, includes: forming a metal layer in the first bit slot and the second bit slot; after forming the metal layer, performing an annealing process such that the metal layer and the first edge portion corresponding to each of the first channel posts and the third edge portion corresponding to each of the second channel posts generate the first bit line, and the metal layer and the fourth edge portion corresponding to each of the second channel posts and the second edge portion corresponding to each of the first channel posts generate the second bit line.

18. The method for forming a dynamic random access memory array as described in claim 16, characterized in that, The materials of the sidewall layers are different from those of the first pre-processed body, the second pre-processed body, and the bit line isolation layer.

19. The method for forming a dynamic random access memory array as described in claim 16, characterized in that, The materials of the first bit line and the second bit line include: metal silicides; metal silicides include: nickel silicon, cobalt silicon or titanium silicon.

20. The method for forming a dynamic random access memory array as described in claim 13, characterized in that, After performing patterned etching on the active region, the method further includes: forming a first isolation layer, the first isolation layer covering the first pre-processed body, the second pre-processed body, and a portion of the sidewalls of the first channel post and the second channel post.

21. The method for forming a dynamic random access memory array as described in claim 20, characterized in that, The first word line grid and the second word line grid are formed on the first isolation layer; the first word line grid is connected to a portion of the sidewall of the first channel post; the second word line grid is connected to a portion of the sidewall of the second channel post.

22. The method for forming a dynamic random access memory array as described in claim 21, characterized in that, After forming the first word grid and the second word grid, the method further includes: forming a second isolation layer on the first isolation layer, the second isolation layer covering a portion of the sidewalls of the first channel post and the second channel post, and the first word grid and the second word grid being covered by the first isolation layer and the second isolation layer.

23. The method for forming a dynamic random access memory array as described in claim 11, characterized in that, After forming the first word line gate and the second word line gate, the method further includes: forming a first source / drain doped layer in the first channel pillars on both sides of the first word line gate along the extension direction of the first channel pillars, wherein each first bit line is electrically connected to the first source / drain doped layer in each of the first channel pillars; and forming a second source / drain doped layer in the second channel pillars on both sides of the second word line gate along the extension direction of the second channel pillars, wherein each second bit line is electrically connected to the second source / drain doped layer in each of the second channel pillars.

24. The method for forming a dynamic random access memory array as described in claim 11, characterized in that, The first word line gate includes: a gate-around structure, a dual-gate structure, or a single-gate structure; the second word line gate includes: a gate-around structure, a dual-gate structure, or a single-gate structure.

Images