Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a first region, a second region and a third region, and the substrate comprises a plurality of first active regions located in the first region, the third region and a part of the second region, and a plurality of second active regions located in the first region, the second region and a part of the third region, the first active region comprises a first branch, a second branch and a third branch, and the second active region comprises a fourth branch, a fifth branch and a sixth branch; the word line gate structure is positioned in the first region; a first cut-off structure within the substrate; a second severing structure within the substrate; the bit line structure comprises a first bit line, a second bit line, a third bit line and a fourth bit line which are electrically connected with the first branch part, the second branch part, the fourth branch part and the fifth branch part respectively; a first connection structure electrically connected to the first bit line and a third connection structure electrically connected to the third bit line on the second region; and a second connection structure electrically connected to the second bit line and a fourth connection structure electrically connected to the fourth bit line on the third region. The semiconductor structure is easy to realize independent control of the spaced bit lines.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] A basic memory cell in Dynamic Random Access Memory (DRAM) consists of a transistor and a storage capacitor, while a memory array consists of multiple memory cells. As semiconductor devices become smaller, to reduce the area of ​​a single memory cell, the bit line structures of the capacitor and control transistor are typically placed on opposite sides of the semiconductor substrate to save planar area.

[0004] However, as the size of semiconductor devices continues to shrink, dynamic random access memory still faces many challenges that need to be addressed. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to continuously improve the performance of dynamic random access memory.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region, the third region, and a portion of the second region, the second active regions being located in the first region, the second region, and a portion of the third region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately. The first direction is perpendicular to the second direction; a first cutting structure is formed within a portion of the first active region, the first cutting structure including a first cutting layer located on the second region, a second cutting layer located on the third region, and a third cutting layer, the first cutting structure cutting into a portion of the first active region from the second direction, the first cutting structure located on the third region and the first cutting structure located on the second region being located on opposite sides of the first active region along the second direction; a second cutting structure is formed within a portion of the second active region, the second cutting structure including a fourth cutting layer and a fifth cutting layer located on the second region, and a sixth cutting layer located on the third region, the second cutting structure cutting into a portion of the second active region from the second direction. The source region, the second cut structure located on the third region and the second cut structure located on the second region are respectively located on both sides of the second active region along the second direction, and the first cut layer is located between the fourth cut layer and the fifth cut layer in the first direction; a word line gate structure is formed in the first region, the word line gate structure is parallel to the second direction; a portion of the active region exposed on the second surface of the substrate is removed, exposing the surfaces of the first cut structure and the second cut structure, the first cut structure causes the first active region to be formed into a first portion, a second portion and a third portion that are mutually separate, the third portion being located between the second cut layer and the third cut layer, and the second cut structure causes the second active region to be formed into a mutually separate portion. The substrate comprises a fourth, fifth, and sixth portion, the sixth portion being located between the fourth and fifth severing layers; a bit line structure is formed on the second surface of the substrate, the bit line structure including: a first bit line electrically connected to the first portion, a second bit line electrically connected to the second portion, a third bit line electrically connected to the fourth portion, and a fourth bit line electrically connected to the fifth portion; a first connection structure and a third connection structure are formed on the second region, the first connection structure being electrically connected to the first bit line, and the third connection structure being electrically connected to the third bit line; a second connection structure and a fourth connection structure are formed on the third region, the second connection structure being electrically connected to the second bit line, and the fourth connection structure being electrically connected to the fourth bit line.

[0007] Optionally, the first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface, the word line gate structure is adjacent to the first channel region and the second channel region; the first portion and the second portion are connected to the first channel region, and the fourth portion and the fifth portion are connected to the second channel region.

[0008] Optionally, the depth of the first cutting structure is greater than the depth of the first channel region, and the depth of the first cutting structure is less than the depth of the first active region; the depth of the second cutting structure is greater than the depth of the second channel region, and the depth of the second cutting structure is less than the depth of the second active region.

[0009] Optionally, the first active region includes a first side and a second side opposite to each other along the second direction, and the second active region includes a first side and a second side opposite to each other along the second direction; the first cutting layer, the fourth cutting layer and the fifth cutting layer located on the second region are located on the first side of the first active region and the second active region; the second cutting layer, the third cutting layer and the sixth cutting layer located on the third region are located on the second side of the first active region and the second active region.

[0010] Optionally, the projections of the first, second, and third cutting layers in the first direction may at most partially overlap; the projections of the fourth, fifth, and sixth cutting layers in the first direction may at most partially overlap.

[0011] Optionally, in the first direction, the first cutting layer is located between the fourth and fifth cutting layers; in the first direction, the sixth cutting layer is located between the second and third cutting layers.

[0012] Optionally, the dimension of the first cutting structure in the second direction is greater than the width of the first portion, and the dimension of the first cutting structure in the second direction is greater than the width of the second portion; the dimension of the second cutting structure in the second direction is greater than the width of the fourth portion, and the dimension of the second cutting structure in the second direction is greater than the width of the fifth portion.

[0013] Optionally, the first, second, third, fourth, fifth, and sixth portions are formed simultaneously; the formation process of the first, second, third, fourth, fifth, and sixth portions includes: etching back the first active region exposed on the second surface of the substrate to form a first groove in the substrate, the first groove extending from the second surface of the substrate to the first surface; etching back the second active region exposed on the second surface of the substrate to form a second groove in the substrate, the second groove extending from the second surface of the substrate to the first surface; forming sidewalls on the sidewalls of the first and second grooves, the sidewall located on the sidewall of the first groove exposing a portion of the surface of the first active region, and the sidewall located on the sidewall of the second groove exposing a portion of the surface of the first active region. The surface of the second active region is partially exposed; the exposed first active region is removed using the sidewall as a mask, and a third groove is formed in the first active region; the exposed second active region is removed using the sidewall as a mask, and a fourth groove is formed in the second active region; a second isolation layer is formed in the third groove and the fourth groove, and the second isolation layer is in contact with the first cut-off structure and the second cut-off structure; the first active region and the second active region exposed on the second surface of the substrate are removed until the surfaces of the first cut-off structure and the second cut-off structure are exposed, so that the first active region is formed into a first part, a second part and a third part that are mutually independent, and the second active region is formed into a fourth part, a fifth part and a sixth part that are mutually independent.

[0014] Optionally, forming a sidewall on the surface of the first groove sidewall and the second groove sidewall includes: forming a sidewall material layer on the surface and bottom surface of the first groove sidewall, the surface and bottom surface of the second groove sidewall, and the second surface of the substrate; etching back the sidewall material layer until the surfaces of the first active region and the second active region are exposed, thereby forming a sidewall on the first groove sidewall and the second groove sidewall.

[0015] Optionally, the third groove and the fourth groove are formed simultaneously; the formation process of the third groove and the fourth groove includes: removing the exposed first active area using the sidewall as a mask until the surface of the first channel area is exposed, forming a third groove in the first active area; removing the exposed second active area using the sidewall as a mask until the surface of the second channel area is exposed, forming a fourth groove in the second active area.

[0016] Optionally, the process of forming the second isolation layer, the first segment, the second segment, the third segment, the fourth segment, the fifth segment, and the sixth segment includes: after removing the sidewall, forming an isolation material layer in the first groove, the second groove, the third groove, the fourth groove, and the second surface of the substrate; planarizing the isolation material layer, the first active region, and the second active region until the surfaces of the first cut-off structure and the second cut-off structure are exposed; forming the second isolation layer in the third groove and the fourth groove, so that the first active region is formed into mutually independent first, second, and third segments, and the second active region is formed into mutually independent fourth, fifth, and sixth segments.

[0017] Optionally, the process of forming the second isolation layer, the first segment, the second segment, the third segment, the fourth segment, the fifth segment, and the sixth segment includes: after removing the sidewall, removing the first active region and the second active region exposed on the second surface of the substrate until the remaining first active region is lower than or flush with the surface of the first cut structure, and until the surface of the remaining second active region is lower than or flush with the surface of the second cut structure; forming an isolation material layer in the first groove, the second groove, the third groove, the fourth groove, and on the second surface of the substrate; planarizing the isolation material layer until the surfaces of the first active region and the second active region are exposed; forming a second isolation layer in the third groove and the fourth groove, such that the first active region is formed into mutually independent first, second, and third segments, and the second active region is formed into mutually independent fourth, fifth, and sixth segments.

[0018] Optionally, the projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; the projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate; and the projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fifth portion on the substrate.

[0019] Optionally, the process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion to form a first opening in the substrate; etching back the second portion to form a second opening in the substrate; etching back the fourth portion to form a third opening in the substrate; etching back the fifth portion to form a fourth opening in the substrate; forming a bit line material layer in the first opening, the second opening, the third opening, the fourth opening, and on the second surface of the substrate; planarizing the bit line material layer until the surface of the second surface of the substrate is exposed; forming the first bit line in the first opening; forming the second bit line in the second opening; forming the third bit line in the third opening; and forming the fourth bit line in the fourth opening.

[0020] Optionally, the first and second cutting structures are formed simultaneously. The formation process of the first and second cutting structures includes: forming a mask structure on a first surface of a substrate, the mask structure having a plurality of openings, the plurality of openings exposing a portion of the surface of the first active region and a portion of the surface of the second active region; etching the exposed first and second active regions using the mask structure as a mask to form a plurality of grooves in the substrate; forming a cutting material layer in the grooves and on the first surface of the substrate; planarizing the cutting material layer until the surfaces of the first and second active regions are exposed, forming a first cutting layer, a fourth cutting layer and a fifth cutting layer in a second region, and forming a second cutting layer, a third cutting layer and a sixth cutting layer in a third region.

[0021] Optionally, there is a first spacing between the first bit line and the second bit line, and the first active region has a first width, wherein the ratio of the first spacing to the first width is in the range of 1:2 to 1:4.

[0022] Optionally, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0023] Optionally, there is a second spacing between the third bit line and the fourth bit line, and the second active region has a second width, wherein the ratio of the second spacing to the second width is in the range of 1:2 to 1:4.

[0024] Optionally, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0025] Optionally, the first, second, third, and fourth connection structures are formed simultaneously. The formation process of the first, second, third, and fourth connection structures includes: forming a dielectric structure on a second surface of a substrate; forming a fifth, sixth, seventh, and eighth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the first bit line surface on the second region, the sixth opening exposes at least a portion of the second bit line surface on the third region, the seventh opening exposes at least a portion of the third bit line surface on the second region, and the eighth opening exposes at least a portion of the fourth bit line surface on the third region; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall and bottom surfaces of the fifth opening, the sixth opening, the seventh opening, the eighth opening, and the dielectric structure surface; planarizing the conductive material layer and the barrier material layer until the dielectric structure surface is exposed; forming a first connection structure within the fifth opening, a second connection structure within the sixth opening, a third connection structure within the seventh opening, and a fourth connection structure within the eighth opening.

[0026] Optionally, the substrate further includes: a first isolation layer located between adjacent first active regions and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; the substrate formation process includes: providing an initial substrate, the initial substrate including a first region, a second region and a third region distributed along a first direction parallel to the surface of the initial substrate, the first region being located between the second region and the third region, the initial substrate including: a substrate, a plurality of initial first active regions and a plurality of initial second active regions located on the substrate, and a first isolation layer located between adjacent initial first active regions and initial second active regions, the plurality of initial first active regions and the plurality of second initial active regions being distributed along a first direction parallel to the surface of the initial substrate. The initial first active region and the initial second active region are arranged in parallel directions, and are alternately arranged. The first surface of the initial substrate exposes the surface of the first isolation layer. A portion of the initial first active region of the second region is removed to form a first active region located in the first region, the third region, and a portion of the second region. A seventh groove is formed in the initial substrate, and the seventh groove extends from the first surface of the initial substrate to the second surface. A portion of the initial second active region of the third region is removed to form a second active region located in the first region, the second region, and a portion of the third region. An eighth groove is formed in the initial substrate, and the eighth groove extends from the first surface of the initial substrate to the second surface. A third isolation layer is formed in the seventh groove and the eighth groove.

[0027] Optionally, the substrate formation process further includes: before removing a portion of the first active region and the second active region exposed on the second surface of the substrate, removing the substrate to expose the surface of the first isolation layer, the surface of the first active region, and the surface of the second active region to form the substrate.

[0028] Optionally, after forming the word line gate structure in the first region, the method further includes: forming a plurality of capacitor structures on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the first active regions or the second active region.

[0029] Optionally, before forming several capacitor structures, the method further includes: performing a first ion implantation on a first active region and a second active region exposed on the first surface of the substrate to form a first source-drain doped region, wherein the capacitor structure is electrically connected to the first source-drain doped region.

[0030] Optionally, before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first, second, fourth, and fifth portions to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0031] Optionally, before forming the word line grid structure located in the first region, the method further includes: etching the first channel region of the first active region to form a plurality of discrete first channel pillars located in the first region; and etching the second channel region of the second active region to form a plurality of discrete second channel pillars located in the first region.

[0032] Optionally, the word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction, the first word line gate and the second word line gate being parallel to the second direction, the first word line gate and the second word line gate being located within the substrate, and adjacent first word line gates and second word line gates being electrically isolated from each other.

[0033] Optionally, the central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

[0034] Optionally, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0035] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second region and the third region, the substrate including opposing first and second surfaces, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region, the third region, and a portion of the second region, the second active regions being located in the first region, the second region, and a portion of the third region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active region being located in the third region, the second active region, and a portion of the third region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active region being located in the third region, the second active region being located in the third region, the third ... An active region and a second active region are alternately arranged, with the first direction perpendicular to the second direction. The first active region exposed on the second surface of the substrate includes mutually independent first, second, and third portions, and the second active region exposed on the second surface of the substrate includes mutually independent fourth, fifth, and sixth portions. A word line gate structure is located within the first region, and the word line gate structure is parallel to the second direction. A first cut-off structure is located within the substrate, comprising a first cut-off layer on the second region, a second cut-off layer on the third region, and a third cut-off layer. The first cut-off structure cuts into a portion of the first active region from the second direction, and the first cut-off structure on the third region and the first cut-off structure on the second region are respectively located on both sides of the first active region along the second direction. A second cut-off structure is located within the substrate, comprising a fourth and fifth cut-off layer on the second region, and a sixth cut-off layer on the third region. The second cut-off structure cuts into a portion of the second active region from the second direction, and the second cut-off structure on the third region and the second cut-off structure on the second region are respectively located on both sides of the second active region along the second direction. The first cut-off layer is located on the fourth cut-off layer in the first direction. Between the cutting layer and the fifth cutting layer; a bit line structure located on the second surface of the substrate, the bit line structure including: a first bit line electrically connected to the first portion, a second bit line electrically connected to the second portion, a third bit line electrically connected to the fourth portion, and a fourth bit line electrically connected to the fifth portion; a first connection structure and a third connection structure located on the second region, the first connection structure being electrically connected to the first bit line, and the third connection structure being electrically connected to the third bit line; a second connection structure and a fourth connection structure located on the third region, the second connection structure being electrically connected to the second bit line, and the fourth connection structure being electrically connected to the fourth bit line.

[0036] Optionally, the first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface, the word line gate structure is adjacent to the first channel region and the second channel region; the first portion and the second portion are connected to the first channel region, and the fourth portion and the fifth portion are connected to the second channel region.

[0037] Optionally, the depth of the first cutting structure is greater than the depth of the first channel region, and the depth of the first cutting structure is less than the depth of the first active region; the depth of the second cutting structure is greater than the depth of the second channel region, and the depth of the second cutting structure is less than the depth of the second active region.

[0038] Optionally, the first active region includes a first side and a second side opposite to each other along the second direction, and the second active region includes a first side and a second side opposite to each other along the second direction; the first cutting layer, the fourth cutting layer and the fifth cutting layer located on the second region are located on the first side of the first active region and the second active region; the second cutting layer, the third cutting layer and the sixth cutting layer located on the third region are located on the second side of the first active region and the second active region.

[0039] Optionally, the projections of the first, second, and third cutting layers in the first direction may at most partially overlap; the projections of the fourth, fifth, and sixth cutting layers in the first direction may at most partially overlap.

[0040] Optionally, in the first direction, the first cutting layer is located between the fourth and fifth cutting layers; in the first direction, the sixth cutting layer is located between the second and third cutting layers.

[0041] Optionally, the dimension of the first cutting structure in the second direction is greater than the width of the first portion, and the dimension of the first cutting structure in the second direction is greater than the width of the second portion; the dimension of the second cutting structure in the second direction is greater than the width of the fourth portion, and the dimension of the second cutting structure in the second direction is greater than the width of the fifth portion.

[0042] Optionally, the projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; the projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate; and the projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fifth portion on the substrate.

[0043] Optionally, there is a first spacing between the first bit line and the second bit line, and the first active region has a first width, wherein the ratio of the first spacing to the first width is in the range of 1:2 to 1:4.

[0044] Optionally, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0045] Optionally, there is a second spacing between the third bit line and the fourth bit line, and the second active region has a second width, wherein the ratio of the second spacing to the second width is in the range of 1:2 to 1:4.

[0046] Optionally, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0047] Optionally, the substrate further includes: a first isolation layer located between adjacent first and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; and a third isolation layer located in a portion of the second region and a portion of the third region, the third isolation layer located in the second region being in contact with the first active region and the first isolation layer, and the third isolation layer located in the third region being in contact with the second active region and the first isolation layer.

[0048] Optionally, it also includes: a second isolation layer located between the first and second portions; and a second isolation layer located between the fourth and fifth portions, the second isolation layer being parallel to the first direction.

[0049] Optionally, it may also include: a plurality of capacitor structures located on the first surface of the substrate, one of the capacitor structures being electrically connected to a first active region or a second active region.

[0050] Optionally, it further includes: a first source / drain doped region located within a first active region and a second active region exposed on the first surface of the substrate, wherein the capacitor structure is electrically connected to the first source / drain doped region.

[0051] Optionally, it also includes: a second source / drain doped region located in the first, second, fourth, and fifth sections, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0052] Optionally, the first channel area includes a plurality of separate first channel columns located in the first area; the second channel area includes a plurality of separate second channel columns located in the first area.

[0053] Optionally, the word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction, the first word line gate and the second word line gate being parallel to the second direction, the first word line gate and the second word line gate being located within the substrate, and adjacent first word line gates and second word line gates being electrically isolated from each other.

[0054] Optionally, the central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

[0055] Optionally, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0056] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0057] In the formation method of the present invention, the first cutting structure forms the first active region into a first portion, a second portion, and a third portion that are mutually independent, the third portion being located between the second cutting layer and the third cutting layer. The second cutting structure forms the second active region into a fourth portion, a fifth portion, and a sixth portion that are mutually independent, the sixth portion being located between the fourth cutting layer and the fifth cutting layer. Subsequently, a first connection structure and a third connection structure are formed on the second region. When forming the second connection structure and the fourth connection structure on the third region, the first connection structure is located between the fourth cutting layer and the fifth cutting layer, and the sixth portion is completely isolated by the fourth cutting layer and the fifth cutting layer. Even if the first connection structure is offset in the second direction, adjacent bit lines will not be short-circuited. The fourth connection structure is located between the second cutting layer and the third cutting layer, and the third portion is completely isolated by the second cutting layer and the third cutting layer. Even if the fourth connection structure is offset in the second direction, adjacent bit lines will not be short-circuited. This increases the process window for the formation of the first, third, second, and fourth connection structures. The first, third, second, and fourth connection structures are easy to form, making it easier for the first bit line to be connected to an external circuit through the first connection structure, the second bit line to be connected to an external circuit through the second connection structure, the third bit line to be connected to an external circuit through the third connection structure, and the fourth bit line to be connected to an external circuit through the fourth connection structure. It also makes it easier to achieve individual control of the phase-spaced bit lines and avoids the situation of capacitive coupling that can easily occur when two adjacent bit lines are energized at the same time.

[0058] Furthermore, by etching back the first portion, a first opening is formed in the substrate; by etching back the second portion, a second opening is formed in the substrate; by etching back the fourth portion, a third opening is formed in the substrate; by etching back the fifth portion, a fourth opening is formed in the substrate. Then, the first bit line is formed within the first opening, the second bit line is formed within the second opening, the third bit line is formed within the third opening, and the fourth bit line is formed within the fourth opening. This process enables self-alignment to form the bit line structure, further reducing the spacing between the bit line structures and saving on the use of a photomask.

[0059] Furthermore, the depth of the first cutting structure is greater than the depth of the first channel region and less than the depth of the first isolation layer, and the depth of the second cutting layer structure is greater than the depth of the second channel region and less than the depth of the first isolation layer. Therefore, when the surfaces of the first and second cutting structures are exposed, and the first cutting structure forms the first active region into mutually separate first, second, and third portions, the bottom of the first channel post will not be exposed, ensuring that the first and second portions are connected to the first channel post. Similarly, when the second cutting structure forms the second active region into mutually separate fourth, fifth, and sixth portions, the bottom of the second channel post will not be exposed, ensuring that the fourth and fifth portions are connected to the second channel post.

[0060] In the semiconductor structure of the present invention, the first connection structure is located between the fourth and fifth cleaving layers, and the sixth portion is completely isolated by the fourth and fifth cleaving layers. Even if the first connection structure is offset in the second direction, adjacent bit lines will not be short-circuited. The fourth connection structure is located between the second and third cleaving layers, and the third portion is completely isolated by the second and third cleaving layers. Even if the fourth connection structure is offset in the second direction, adjacent bit lines will not be short-circuited. This increases the process window for the formation of the first, third, second, and fourth connection structures. The first, third, second, and fourth connection structures are easy to form, making it easy for the first bit line to be connected to an external circuit through the first connection structure, the second bit line to be connected to an external circuit through the second connection structure, the third bit line to be connected to an external circuit through the third connection structure, and the fourth bit line to be connected to an external circuit through the fourth connection structure. It also facilitates individual control of spaced-apart bit lines and avoids capacitive coupling when two adjacent bit lines are energized simultaneously. Attached Figure Description

[0061] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure in one embodiment;

[0062] Figures 3 to 33 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0063] As described in the background section, dynamic random access memory (DRAM) still has many problems that need to be solved. These will now be analyzed and explained in conjunction with specific embodiments.

[0064] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure in one embodiment.

[0065] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a storage cell in a dynamic random access memory (DRAM). Figure 2 The diagram shows the bit line distribution on the substrate surface. The memory cell of the dynamic random access memory includes: a channel post 101, which is parallel to a first direction; a word line gate structure 102 located on the sidewall surface of the channel post 101, which is parallel to a second direction and perpendicular to the first and second directions; a bit line structure 104 and a capacitor structure 103 electrically connected to both ends of the channel post 101, respectively, with the bit line structure 104 parallel to the first direction.

[0066] The dynamic random access memory (DRAM) includes several parallel bit line structures 104, each connected to an external circuit via a connection structure 105. As semiconductor devices become increasingly smaller, the spacing between adjacent bit line structures 104 also decreases. When multiple bit line structures 104 are simultaneously powered, capacitive coupling can easily occur between adjacent structures, generating parasitic capacitance and causing performance degradation in the DRAM.

[0067] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. A first severing structure divides the first active region into three mutually independent portions: a first portion, a second portion, and a third portion. The third portion is located between a second severing layer and a third severing layer. The second severing structure further divides the second active region into three mutually independent portions: a fourth portion, a fifth portion, and a sixth portion. The sixth portion is located between the fourth and fifth severing layers. Subsequently, a first connection structure and a third connection structure are formed on the second region. When forming the second and fourth connection structures on the third region, the first connection structure is located between the fourth and fifth severing layers, and the sixth portion is completely isolated by the fourth and fifth severing layers. Even if the first connection structure shifts in the second direction, adjacent bit lines will not be short-circuited. The fourth connection structure is located between the second and third severing layers, and the third portion is completely isolated by the second and third severing layers. Even if the fourth connection structure shifts in the second direction, adjacent bit lines will not be short-circuited. This increases the process window for the formation of the first, third, second, and fourth connection structures. The first, third, second, and fourth connection structures are easy to form, making it easier for the first bit line to be connected to an external circuit through the first connection structure, the second bit line to be connected to an external circuit through the second connection structure, the third bit line to be connected to an external circuit through the third connection structure, and the fourth bit line to be connected to an external circuit through the fourth connection structure. It also makes it easier to achieve individual control of the phase-spaced bit lines and avoids the situation of capacitive coupling that can easily occur when two adjacent bit lines are energized at the same time.

[0068] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0069] Figures 3 to 33 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0070] A substrate is provided, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region, the third region, and a portion of the second region, the second active regions being located in the first region, the second region, and a portion of the third region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other.

[0071] The substrate further includes a first isolation layer located between adjacent first and second active regions, wherein a first surface of the substrate exposes the surface of the first isolation layer.

[0072] Please refer to the substrate formation process. Figures 3 to 6 .

[0073] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 Top view of the first surface of the initial substrate. Figure 4 for Figure 3 A schematic diagram along the section line AA1 shows an initial substrate. The initial substrate includes a first region I, a second region II, and a third region III distributed along a first direction Y parallel to the surface of the initial substrate. The first region I is located between the second region II and the third region III. The initial substrate includes a substrate 200, a plurality of initial first active regions 201 and a plurality of initial second active regions 251 located on the substrate 200, and a first isolation layer 202 located between adjacent initial first active regions 201 and initial second active regions 251. The plurality of initial first active regions 201 and the plurality of initial second active regions 251 are arranged in parallel along a second direction X parallel to the surface of the initial substrate. The initial first active regions 201 and the initial second active regions 251 are arranged alternately. The first surface of the initial substrate exposes the surface of the first isolation layer 202.

[0074] In this embodiment, the material of the substrate 200 is the same as the material of the initial first active region 201 and the initial second active region 251. In other embodiments, the material of the substrate may be different from the material of the initial first active region and the initial second active region.

[0075] In this embodiment, the substrate 200, the initial first active region 201, and the initial second active region 251 are made of silicon.

[0076] In other embodiments, the materials of the substrate, the initial first active region, and the initial second active region include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0077] The material of the first isolation layer 202 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0078] In this embodiment, the material of the first isolation layer 202 includes silicon oxide.

[0079] The method for forming the initial substrate includes: providing a substrate material; forming a patterned mask layer on the substrate material; etching the substrate material using the patterned mask layer as a mask to form a plurality of grooves parallel to the first direction Y in the substrate material layer, forming a substrate 200 and an initial first active region 201 and an initial second active region 251 located on the substrate 200; forming a first isolation layer 202 in the grooves to form the initial substrate.

[0080] In this embodiment, the initial first active region 201 and the initial second active region 251 have the same width in the second direction X; the grooves have the same width in the second direction X.

[0081] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 Top view of the first surface of the initial substrate. Figure 6 for Figure 5 A schematic diagram along the cross-section line AA1 shows the following: A portion of the initial first active region 201 in the second region II is removed to form a first active region 204 located in the first region I, the third region III, and a portion of the second region II. A seventh groove (not shown) is formed within the initial substrate, extending from the first surface of the initial substrate to the second surface. A portion of the initial second active region 205 in the third region III is removed to form a second active region 205 located in the first region I, the second region II, and a portion of the third region III. An eighth groove (not shown) is formed within the initial substrate, extending from the first surface of the initial substrate to the second surface. A third isolation layer 203 is formed within the seventh and eighth grooves.

[0082] The method for removing a portion of the initial first active region 201 of the second region II and a portion of the initial second active region 205 of the third region III includes: forming a mask structure on a first surface of the initial substrate, the mask structure exposing a portion of the surface of the initial first active region 201 on the second region II and a portion of the surface of the initial second active region 201 on the third region III; using the mask structure as a mask, removing a portion of the initial first active region 201 of the second region II to form a first active region 204 located in the first region I, the third region III and a portion of the second region II, and forming a seventh groove in the initial substrate, the seventh groove extending from the first surface of the initial substrate to the second surface; using the mask structure as a mask, removing a portion of the initial second active region 205 of the third region III to form a second active region 205 located in the first region I, the second region II and a portion of the third region III, and forming an eighth groove (not shown) in the initial substrate, the eighth groove extending from the first surface of the initial substrate to the second surface.

[0083] The seventh groove exposes the surface of the substrate 200, and the eighth groove exposes the surface of the substrate 200.

[0084] The first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, and the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface. The first and second channel regions are used to subsequently form word line gate structures on their surfaces. The first and second channel regions are close to the first surface of the initial substrate and do not contact the substrate 200; that is, the depth of the first and second channel regions is less than the depth of the first isolation layer 202.

[0085] The material of the third isolation layer 203 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0086] In this embodiment, the material of the third isolation layer 203 includes silicon oxide.

[0087] Please refer to Figure 7 and Figure 8 , Figure 7 for Figure 8 Top view of the first surface of the initial substrate. Figure 8 for Figure 7A structural schematic diagram along section line AA1 shows a first cutting structure formed within a portion of the first active region 204. This first cutting structure includes a first cutting layer 206 located in the second region II, a second cutting layer 207 located in the third region III, and a third cutting layer 208. The first cutting structure cuts into a portion of the first active region 204 from the second direction X. The first cutting structure located in the third region III and the first cutting structure located in the second region II are respectively located on both sides of the first active region 204 along the second direction X. A second cutting structure is formed within a portion of the second active region 205. The second cutting structure includes... The fourth cutting layer 209 and the fifth cutting layer 210 are located in the second region II, and the sixth cutting layer 211 is located in the third region III. The second cutting structure cuts into the second active region 205 from the second direction X. The second cutting structure located in the third region III and the second cutting structure located in the second region II are respectively located on both sides of the second active region 205 along the second direction X. In the first direction Y, the first cutting layer 206 is located between the fourth cutting layer 209 and the fifth cutting layer 210. In the first direction Y, the sixth cutting layer 211 is located between the second cutting layer 207 and the third cutting layer 208.

[0088] In this embodiment, the first cutting layer 206, the fourth cutting layer 209, and the fifth cutting layer 210 located in the second region II have projections that do not coincide with each other in the second direction X.

[0089] In other embodiments, the first cutting layer coincides with the projection portion of the fourth cutting layer in the second direction X, or the first cutting layer coincides with the projection portion of the fifth cutting layer in the second direction X.

[0090] In this embodiment, the sixth cutting layer 211, the second cutting layer 207, and the third cutting layer 208 are located in the third region III. The projections of the sixth cutting layer 211 and the second cutting layer 207 in the second direction X do not coincide, and the projections of the sixth cutting layer 211 and the third cutting layer 208 in the second direction X do not coincide.

[0091] In other embodiments, the sixth cutting layer coincides with the projection portion of the second cutting layer in the second direction X, or the sixth cutting layer coincides with the projection portion of the third cutting layer in the second direction X.

[0092] In this embodiment, the depth of the first cutting structure is greater than the depth of the first channel region, and the depth of the first cutting structure is less than the depth of the first active region 204. That is, the depths of the first cutting layer 206, the second cutting layer 207, and the third cutting layer 208 are greater than the depth of the first channel region, and the depths of the first cutting layer 206, the second cutting layer 207, and the third cutting layer 208 are less than the depth of the first active region 204.

[0093] In this embodiment, the depth of the second cutting structure is greater than the depth of the second channel region, and the depth of the second cutting structure is less than the depth of the second active region 205. That is, the depths of the fourth cutting layer 209, the fifth cutting layer 210, and the sixth cutting layer 211 are greater than the depth of the second channel region, and the depths of the fourth cutting layer 209, the fifth cutting layer 210, and the sixth cutting layer 211 are less than the depth of the second active region 205.

[0094] The first active region 204 includes a first side and a second side opposite to each other along the second direction X, and the second active region 205 includes a first side and a second side opposite to each other along the second direction X. The first cutting layer 206 located in the second region II is located on the first side of the first active region 204, and the fourth cutting layer 209 and the fifth cutting layer 210 located in the second region II are located on the first side of the second active region 205; the second cutting layer 207 and the third cutting layer 208 located in the third region III are located on the second side of the first active region 204, and the sixth cutting layer 211 located in the third region III is located on the second side of the second active region 205.

[0095] In this embodiment, the projections of the first cutting layer 206, the second cutting layer 207, and the third cutting layer 208 in the first direction Y at most partially overlap; the projections of the fourth cutting layer 209, the fifth cutting layer 210, and the sixth cutting layer 211 in the first direction Y at most partially overlap. That is, the first cutting layer 206, the second cutting layer 207, and the third cutting layer 208 only remove a portion of the first active region 204 along the second direction X; the fourth cutting layer 209, the fifth cutting layer 210, and the sixth cutting layer 211 only remove a portion of the second active region 205 along the second direction X.

[0096] In this embodiment, the first active region 204 is located at one end of the second region II, situated in the first direction Y between the fourth cutting layer 209 and the fifth cutting layer 210; the second active region 205 is located at one end of the third region III, situated in the first direction Y between the second cutting layer 207 and the third cutting layer 208. This allows the first connecting structure 241 to be formed between the fourth cutting layer 209 and the fifth cutting layer 210 in the first direction Y, and the fourth connecting structure 244 to be formed between the second cutting layer 207 and the third cutting layer 208 in the first direction Y.

[0097] In this embodiment, a portion of the first cutting structure and a portion of the second cutting structure are also located within the first isolation layer 202.

[0098] In other embodiments, the first cutting structure is located only within the first active region; the second cutting structure is located only within the second active region.

[0099] In this embodiment, the first cutting structure and the second cutting structure are formed simultaneously.

[0100] The formation process of the first and second cutting structures includes: forming a mask structure (not shown) on a first surface of a substrate, the mask structure having a plurality of openings (not shown), the plurality of openings exposing a portion of the surface of the first active region 204 and a portion of the surface of the second active region 205; etching the exposed first active region 204 and second active region 205 using the mask structure as a mask to form a plurality of grooves (not shown) in the substrate; forming a cutting material layer in the grooves and on the first surface of the substrate; planarizing the cutting material layer until the surfaces of the first active region 204 and second active region 205 are exposed; forming a first cutting layer 206, a fourth cutting layer 209 and a fifth cutting layer 210 in a second region II; and forming a second cutting layer 207, a third cutting layer 208 and a sixth cutting layer 211 in a third region III.

[0101] In this embodiment, the first cutting structure and the second cutting structure are made of the same material.

[0102] The materials of the first cutting structure and the second cutting structure include dielectric materials, which include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0103] In this embodiment, the materials of the first cutting structure and the second cutting structure include silicon oxide.

[0104] Please refer to Figures 9 to 11 , Figure 9 for Figure 10 and Figure 11Top view, Figure 10 for Figure 9 A schematic diagram of the structure along section line BB1. Figure 11 for Figure 9 The schematic diagram along the cross-section line CC1 shows that the first channel region of the first active region 204 is etched to form a plurality of discrete first channel pillars 212 located in the first region I; the second channel region of the second active region 205 is etched to form a plurality of discrete second channel pillars 213 located in the first region I.

[0105] In this embodiment, the central axes of two adjacent first channel posts 212 do not coincide in the first direction Y; the central axes of two adjacent second channel posts 213 do not coincide in the first direction Y. In the second direction X, a plurality of first channel posts 212 and second channel posts 213 are located on the same straight line.

[0106] In this embodiment, the depth of the first channel post 212 is less than the depth of the first isolation layer 202; the depth of the second channel post 213 is less than the depth of the first isolation layer 202. That is, the first channel post 212 is located on the first active region 204 other than the first channel region, and the second channel post 213 is located on the second active region 205 other than the second channel region.

[0107] In this embodiment, one first channel post 212, another adjacent first channel post 212 in the first direction Y, and a second channel post 213 adjacent in the second direction X form a triangle; one second channel post 213, another adjacent second channel post 213 in the first direction Y, and a first channel post 212 adjacent in the second direction X form a triangle. This allows the positions of the capacitor structures to be staggered when a plurality of capacitor structures electrically connected to the first channel post 212 or the second channel post 213 are subsequently formed on the first surface, thus increasing the process window.

[0108] The cross-sectional shapes of the first channel post 212 and the second channel post 213 include polygons, rectangles, circles, or ellipses with a side length greater than or equal to 5. In this embodiment, the cross-sectional shapes of the first channel post 212 and the second channel post 213 include rectangles.

[0109] In this embodiment, after forming the first channel post 212 and the second channel post 213, the method further includes filling the openings of the first active region 204 and the second active region 205 with a filling layer 214.

[0110] In this embodiment, the first channel post 212 and the second channel post 213 are formed simultaneously.

[0111] Please refer to Figure 12 and Figure 13 , Figure 12 for Figure 13 Top view, Figure 13 for Figure 12 A schematic diagram of the structure along the cross-sectional line BB1 ​​shows a word line gate structure located in the first region I, the word line gate structure being parallel to the second direction X.

[0112] The word line grid structure is adjacent to the first channel region and the second channel region.

[0113] The word line grid structure includes: a first word line grid 215 and a second word line grid 216. The first word line grid 215 and the second word line grid 216 are respectively located on the two side walls of the first channel post 212 along the first direction Y, and respectively located on the two side walls of the second channel post 213 along the first direction Y. The first word line grid 215 and the second word line grid 216 are parallel to the second direction X. The first word line grid 215 and the second word line grid 216 are located within the first isolation layer 202 and the filling layer 214. The first isolation layer 202 and the filling layer 214 electrically isolate the adjacent first word line grid 215 and the second word line grid 216.

[0114] The first word line gate 215 includes: a first gate dielectric layer located on the surface of the first channel pillar 212 and the surface of the second channel pillar 213, and a first gate layer located on the surface of the first gate dielectric layer. The second word line gate 216 includes: a second gate dielectric layer located on the surface of the first channel pillar 212 and the surface of the second channel pillar 213, and a second gate layer located on the surface of the second gate dielectric layer.

[0115] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include silicon oxide or low-K (K less than 3.9) materials; the materials of the first gate layer and the second gate layer include polysilicon.

[0116] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include a high dielectric constant material, the high dielectric constant material having a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the materials of the first gate layer and the second gate layer include metals, the metal including tungsten.

[0117] The top surface of the word line grid structure is lower than or flush with the first surface of the substrate. The figure schematically illustrates that the top surface of the word line grid structure is flush with the first surface of the substrate.

[0118] In another embodiment, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0119] In another embodiment, the cross-section of the first channel post includes a circular or elliptical shape; the cross-section of the second channel post includes a circular or elliptical shape.

[0120] Please refer to Figure 14 and Figure 15 , Figure 14 for Figure 15 Top view, Figure 15 for Figure 14 A schematic diagram of the structure along the cross-sectional line BB1 ​​shows that several capacitor structures 217 are formed on the first surface of the substrate, and one of the capacitor structures 217 is electrically connected to a first channel post 212 or a second channel post 213.

[0121] Before forming several capacitor structures, the method further includes: performing a first ion implantation on the first channel pillar 212 and the second channel pillar 213 exposed on the first surface of the substrate to form a first source-drain doped region, and the capacitor structure 217 is electrically connected to the first source-drain doped region.

[0122] Next, a portion of the active region exposed on the second surface of the substrate is removed, exposing the surfaces of the first and second severing structures. The first severing structure forms the first active region into three mutually independent portions: a first portion, a second portion, and a third portion. The third portion is located between the second and third severing layers. The second severing structure forms the second active region into three mutually independent portions: a fourth portion, a fifth portion, and a sixth portion. The sixth portion is located between the fourth and fifth severing layers. The formation process of the first, second, third, fourth, fifth, and sixth portions is described in [reference needed]. Figures 16 to 28 .

[0123] Please refer to Figures 16 to 18 , Figure 16 for Figure 17 and Figure 18 Top view, Figure 17 for Figure 16 A schematic diagram of the structure along section line BB1. Figure 18 for Figure 16 A schematic diagram along the cross-sectional line CC1 shows the substrate 200 being removed, exposing the surfaces of the first isolation layer 202, the first active region 204, and the second active region 205, thus forming the substrate.

[0124] It should be noted that since the depth of the first channel region and the depth of the second channel region are less than the depth of the first isolation layer 202, after removing the substrate 200, the second surface of the substrate will not expose the first channel pillar 212 and the second channel pillar 213, but will expose the first active region 204 at the bottom of the first channel pillar 212 and the second active region 205 at the bottom of the second channel pillar 213.

[0125] In this embodiment, the process for removing the substrate 200 includes a chemical mechanical polishing process.

[0126] Please refer to Figures 19 to 22 , Figure 19 for Figure 20 , Figure 21 and Figure 22 Top view, Figure 20 for Figure 19 A schematic diagram of the structure along section line AA1. Figure 21 for Figure 19 A schematic diagram of the structure along section line BB1. Figure 22 for Figure 19 A schematic diagram along the cross-sectional line CC1 shows the following: the first active region 204 exposed on the second surface of the substrate is etched back to form a first groove 259 within the substrate, extending from the second surface of the substrate to the first surface; the second active region 205 exposed on the second surface of the substrate is etched back to form a second groove 219 within the substrate, extending from the second surface of the substrate to the first surface; sidewalls 218 are formed on the sidewalls of the first groove 259 and the second groove 219, with the sidewall 218 on the sidewall of the first groove 259 exposing a portion of the surface of the first active region 204, and the sidewall 218 on the sidewall of the second groove 219 exposing a portion of the surface of the second active region 205.

[0127] Forming a sidewall 218 on the sidewalls of the first groove 259 and the second groove 219 includes: forming a sidewall material layer on the surface and bottom surface of the sidewall of the first groove 259, the surface and bottom surface of the sidewall of the second groove 219, and the second surface of the substrate; etching back the sidewall material layer until the surfaces of the first active region 204 and the second active region 205 are exposed, thereby forming a sidewall 218 on the sidewalls of the first groove 259 and the second groove 219.

[0128] The sidewall 218 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0129] In this embodiment, the material of the sidewall 218 includes silicon nitride.

[0130] Please refer to Figure 23 and Figure 24 , Figure 23 In order to be in Figure 20 A basic diagram. Figure 24 In order to be in Figure 22 Based on the schematic diagram, the first active region 204 exposed by the sidewall 218 is removed, and a third groove 220 is formed in the first active region 204; the second active region 205 exposed by the sidewall 218 is removed, and a fourth groove 260 is formed in the second active region 205.

[0131] The third groove 220 exposes the surface of the first channel post 212, and the fourth groove 260 exposes the surface of the second channel post 213.

[0132] In this embodiment, the third groove 220 and the fourth groove 260 are formed simultaneously. In other embodiments, the third groove and the fourth groove may be formed asynchronously.

[0133] The formation process of the third groove 220 and the fourth groove 260 includes: removing the exposed first active region 204 using the sidewall 218 as a mask until the surface of the first channel region is exposed, forming the third groove 220 in the first active region; removing the exposed second active region 205 using the sidewall 218 as a mask until the surface of the second channel region is exposed, forming the fourth groove 260 in the second active region 205.

[0134] Please refer to Figures 25 to 28 , Figure 25 for Figure 26 , Figure 27 and Figure 28 Top view, Figure 26 for Figure 25 A schematic diagram of the structure along section line AA1. Figure 27 for Figure 25 A schematic diagram of the structure along section line BB1. Figure 28 for Figure 25 A schematic diagram along the cross-sectional line CC1 shows that a second isolation layer 221 is formed in the third groove 220 and the fourth groove 260, and the second isolation layer 221 is in contact with the first cut-off structure and the second cut-off structure; the first active region 204 and the second active region 205 exposed on the second surface of the substrate are removed until the surfaces of the first cut-off structure and the second cut-off structure are exposed, so that the first active region 204 is formed into a first part 222, a second part 223 and a third part 224 that are mutually independent, and the second active region 205 is formed into a fourth part 225, a fifth part 226 and a sixth part 227 that are mutually independent.

[0135] The first part 222, the second part 223, the third part 224, the fourth part 225, the fifth part 226 and the sixth part 227 are formed simultaneously.

[0136] In one embodiment, the process of forming the second isolation layer 221, the first portion 222, the second portion 223, the third portion 224, the fourth portion 225, the fifth portion 226, and the sixth portion 227 includes: after removing the sidewall 218, forming an isolation material layer in the first groove 259, the second groove 219, the third groove 220, the fourth groove 260, and the second surface of the substrate; planarizing the isolation material layer, the first active region 204, and the second active region 205 until the surfaces of the first cut structure and the second cut structure are exposed; forming the second isolation layer 221 in the third groove 220 and the fourth groove 260, such that the first active region 204 is formed into mutually independent first portions 222, second portions 223, and third portions 224, and that the second active region 205 is formed into mutually independent fourth portions 225, fifth portions 226, and sixth portions 227.

[0137] In another embodiment, the process of forming the second isolation layer 221, the first portion 222, the second portion 223, the third portion 224, the fourth portion 225, the fifth portion 226, and the sixth portion 227 includes: after removing the sidewall 218, removing the first active region 204 and the second active region 205 exposed on the second surface of the substrate until the remaining first active region 204 is lower than or flush with the surface of the first cut structure, and until the surface of the remaining second active region 205 is lower than or flush with the surface of the second cut structure; within the first groove 259 An isolation material layer is formed in the second groove 219, the third groove 220, the fourth groove 260, and the second surface of the substrate; the isolation material layer is planarized until the surfaces of the first active region 204 and the second active region 205 are exposed; a second isolation layer 221 is formed in the third groove 220 and the fourth groove 260, so that the first active region 204 is formed into a first part 222, a second part 223, and a third part 224 that are mutually independent, and the second active region 205 is formed into a fourth part 225, a fifth part 226, and a sixth part 227 that are mutually independent.

[0138] In this embodiment, the first active region 204 includes a first channel region distributed along a direction perpendicular to the substrate surface. The first portion 222, the second portion 223, and the third portion 224 are connected to the first channel region, that is, the first portion 222 and the second portion 223 are connected to the first channel post 212. The third portion 224 is located in the third region III, therefore the third portion 224 is not connected to the first channel post 212.

[0139] In this embodiment, the second active region 205 includes a second channel region distributed along a direction perpendicular to the substrate surface. The fourth portion 225, the fifth portion 226, and the sixth portion 227 are connected to the second channel region, that is, the fourth portion 225 and the fifth portion 226 are connected to the second channel pillar 213. The sixth portion 227 is located in the second region II, therefore the sixth portion 227 is not connected to the second channel pillar 213.

[0140] In this embodiment, the depth of the first cutting structure is greater than the depth of the first channel region, that is, the depths of the first cutting layer 206, the second cutting layer 207, and the third cutting layer 208 are greater than the depth of the first channel post 212. The depth of the second cutting layer structure is greater than the depth of the second channel region, that is, the depths of the fourth cutting layer 209, the fifth cutting layer 210, and the sixth cutting layer 211 are greater than the depth of the second channel post 213. Therefore, when the surfaces of the first and second cutting structures are exposed, and the first cutting structure forms the first active region 204 into mutually separate first portions 222, second portions 223 and third portions 224, the bottom of the first channel post 212 is not exposed, and the first portions 222 and second portions 223 are connected to the first channel post 212; when the second cutting structure forms the second active region 205 into mutually separate fourth portions 225, fifth portions 226 and sixth portions 227, the bottom of the second channel post 213 is not exposed, and the fourth portions 225 and fifth portions 226 are connected to the second channel post 213.

[0141] The first cutting structure located within the first active region 204 has a dimension in the second direction X that is larger than the width of the first portion 222, and the dimension in the second direction X that is larger than the width of the second portion 223; the second cutting structure located within the second active region 205 has a dimension in the second direction X that is larger than the width of the fourth portion 225, and the dimension in the second direction X that is larger than the width of the fifth portion 226. This is to ensure that the first cutting structure can cut through the first active region 204 to form mutually independent first portions 222, second portions 223, and third portions 224, and to ensure that the second cutting structure can cut through the second active region 205 to form mutually independent fourth portions 225, fifth portions 226, and sixth portions 227.

[0142] The material of the second isolation layer 221 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0143] In this embodiment, the material of the second isolation layer 221 includes silicon oxide.

[0144] Please refer to Figures 29 to 32 , Figure 29 for Figure 30 , Figure 31 and Figure 32 Top view, Figure 30 for Figure 29 A schematic diagram of the structure along section line AA1. Figure 31 for Figure 29 A schematic diagram of the structure along section line BB1. Figure 32 for Figure 29 A schematic diagram of the structure along the cross-section line CC1 shows that a bit line structure is formed on the second surface of the substrate. The bit line structure includes: a first bit line 231 electrically connected to the first portion 222, a second bit line 232 electrically connected to the second portion 223, a third bit line 234 electrically connected to the fourth portion 225, and a fourth bit line 235 electrically connected to the fifth portion 226.

[0145] In this embodiment, while forming the bit line structure, it also includes: forming a first pseudo bit line 233 electrically connected to the third portion 224, and a second pseudo bit line 236 electrically connected to the sixth portion 227.

[0146] The projected area of ​​the first bit line 231 on the substrate is less than or equal to the projected area of ​​the first portion 222 on the substrate; the projected area of ​​the second bit line 232 on the substrate is less than or equal to the projected area of ​​the second portion 223 on the substrate; the projected area of ​​the third bit line 234 on the substrate is less than or equal to the projected area of ​​the fourth portion 225 on the substrate; the projected area of ​​the fourth bit line 235 on the substrate is less than or equal to the projected area of ​​the fifth portion 226 on the substrate; the projected area of ​​the first pseudo bit line 233 on the substrate is less than or equal to the projected area of ​​the third portion 224 on the substrate; and the projected area of ​​the second pseudo bit line 236 on the substrate is less than or equal to the projected area of ​​the sixth portion 227 on the substrate.

[0147] In this embodiment, the projected area of ​​the first bit line 231 on the substrate is equal to the projected area of ​​the first portion 222 on the substrate; the projected area of ​​the second bit line 232 on the substrate is equal to the projected area of ​​the second portion 223 on the substrate; the projected area of ​​the third bit line 234 on the substrate is equal to the projected area of ​​the fourth portion 225 on the substrate; the projected area of ​​the fourth bit line 235 on the substrate is equal to the projected area of ​​the fifth portion 226 on the substrate; the projected area of ​​the first pseudo bit line 233 on the substrate is equal to the projected area of ​​the third portion 224 on the substrate; and the projected area of ​​the second pseudo bit line 236 on the substrate is equal to the projected area of ​​the sixth portion 227 on the substrate.

[0148] The process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion 222 to form a first opening in the substrate; etching back the second portion 223 to form a second opening in the substrate; etching back the fourth portion 225 to form a third opening in the substrate; etching back the fifth portion 226 to form a fourth opening in the substrate; forming a bit line material layer in the first opening, the second opening, the third opening, the fourth opening, and on the second surface of the substrate; planarizing the bit line material layer until the surface of the second surface of the substrate is exposed; forming the first bit line 231 in the first opening; forming the second bit line 232 in the second opening; forming the third bit line 234 in the third opening; and forming the fourth bit line 235 in the fourth opening.

[0149] A first opening is formed in the substrate by etching back the first portion 222; a second opening is formed in the substrate by etching back the second portion 223; a third opening is formed in the substrate by etching back the fourth portion 225; a fourth opening is formed in the substrate by etching back the fifth portion 226; then the first bit line 231 is formed in the first opening, the second bit line 232 is formed in the second opening, the third bit line 234 is formed in the third opening, and the fourth bit line 235 is formed in the fourth opening. This process enables self-alignment to form the bit line structure, further reducing the spacing between the bit line structures and saving on the use of a photomask.

[0150] Before forming bit line structures within the first opening, second opening, third opening, and fourth opening, the method further includes: performing second ion implantation on the first portion 222, second portion 223, fifth portion 226, and fourth portion 225 to form second source / drain doped regions, wherein the bit line structures are electrically connected to the second source / drain doped regions.

[0151] In this embodiment, there is a first gap between the first bit line 231 and the second bit line 232, and the first active region 204 has a first width. The ratio of the first gap to the first width is between 1:2 and 1:4.

[0152] In this embodiment, the range of the first spacing is 5 nanometers to 50 nanometers; the range of the first width is 10 nanometers to 100 nanometers.

[0153] In this embodiment, there is a second spacing between the third bit line 234 and the fourth bit line 235, and the second active region has a second width. The ratio of the second spacing to the second width is between 1:2 and 1:4.

[0154] In this embodiment, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0155] In this embodiment, the ratio of the width of the first isolation layer 202 in the second direction X to the width of the active region is in the range of 1:2 to 1:4.

[0156] In this embodiment, the width of the first isolation layer 202 ranges from 5 nanometers to 50 nanometers.

[0157] The material of the bitline structure includes metal silicides, which include nickel silicon or titanium silicon.

[0158] Please refer to Figure 33 A first connection structure 241 and a third connection structure 243 are formed on the second region II. The first connection structure 241 is electrically connected to the first bit line 231, and the third connection structure 243 is electrically connected to the third bit line 234. A second connection structure 242 and a fourth connection structure 244 are formed on the third region III. The second connection structure 242 is electrically connected to the second bit line 232, and the fourth connection structure 244 is electrically connected to the fourth bit line 235.

[0159] In this embodiment, the projections of adjacent first connecting structures 241 and third connecting structures 243 in the second direction X do not overlap, and the projections of adjacent second connecting structures 242 and fourth connecting structures 244 in the second direction X do not overlap, so that the first connecting structure 241, third connecting structure 243, second connecting structure 242 and fourth connecting structure 244 can have a large process window during the formation process.

[0160] In this embodiment, in the first direction Y, the first connection structure 241 is located between the fourth cut layer 209 and the fifth cut layer 210. The second pseudo-bit line 236 between the fourth cut layer 209 and the fifth cut layer 210 is completely isolated from the third bit line 234 and the fourth bit line 235 by the fourth cut layer 209 and the fifth cut layer 210. Therefore, the forming process window of the first connection structure 241 is increased. Even if the first connection structure 241 is offset in the second direction X, and the second pseudo-bit line 236 between the first connection structure 241 and the fourth cut layer 209 and the fifth cut layer 210 makes electrical contact, a short circuit will not occur between the adjacent first bit line 231 and the fourth bit line 235.

[0161] In this embodiment, in the first direction Y, the fourth connection structure 244 is located between the second cut-off layer 207 and the third cut-off layer 208. The first pseudo-position line 233 between the second cut-off layer 207 and the third cut-off layer 208 is completely isolated from the first position line 231 and the second position line 232 by the second cut-off layer 207 and the third cut-off layer 208. Therefore, the forming process window of the fourth connection structure 244 is increased. Even if the fourth connection structure 244 is offset in the second direction X, and the first pseudo-position line 233 between the fourth connection structure 244 and the second cut-off layer 207 and the third cut-off layer 208 makes electrical contact, a short circuit will not occur between the adjacent first position line 231 and the fourth position line 235.

[0162] In this embodiment, the range between the second cutting layer 207 and the third cutting layer 208 is the range within which the fourth connecting structure 244 can be offset in the first direction Y. The range between the fourth cutting layer 209 and the fifth cutting layer 210 is the range within which the first connecting structure 241 can be offset in the first direction Y.

[0163] In this embodiment, the first connection structure 241, the second connection structure 242, the third connection structure 243 and the fourth connection structure 244 are formed simultaneously.

[0164] The formation process of the first connection structure 241, the second connection structure 242, the third connection structure 243, and the fourth connection structure 244 includes: forming a dielectric structure (not shown) on the second surface of the substrate; forming a fifth opening, a sixth opening, a seventh opening, and an eighth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the surface of the first bit line 231 on the second region II, the sixth opening exposes at least a portion of the surface of the second bit line 232 on the third region III, the seventh opening exposes at least a portion of the surface of the third bit line 234 on the second region II, and the eighth opening exposes at least a portion of the surface of the third region II. The fourth bit line 235 on I; a barrier material layer and a conductive material layer on the barrier material layer are formed on the sidewall and bottom surfaces of the fifth opening, the sidewall and bottom surfaces of the sixth opening, the sidewall and bottom surfaces of the seventh opening, the sidewall and bottom surfaces of the eighth opening, and the dielectric structure surface; the conductive material layer and the barrier material layer are planarized until the dielectric structure surface is exposed; a first connection structure 241 is formed in the fifth opening, a second connection structure 242 is formed in the sixth opening, a third connection structure 243 is formed in the seventh opening, and a fourth connection structure 244 is formed in the eighth opening.

[0165] The barrier material layer is made of a metal nitride, including titanium nitride or tantalum nitride; the conductive material layer is made of a metal, including tungsten.

[0166] The semiconductor structure formed by the method has a smaller spacing between adjacent first bit lines 231 and second bit lines 232, and a smaller spacing between adjacent third bit lines 234 and fourth bit lines 235. This increases the process window for forming the first connection structure 241, third connection structure 243, second connection structure 242, and fourth connection structure 244, making them easier to form. This facilitates the connection of the first bit line 231 to an external circuit via the first connection structure 241, the second bit line 232 to an external circuit via the second connection structure 242, the third bit line 234 to an external circuit via the third connection structure 243, and the fourth bit line 235 to an external circuit via the fourth connection structure 244. It also facilitates individual control of spaced-apart bit lines, avoiding capacitive coupling when two adjacent bit lines are simultaneously energized.

[0167] Individual control is applied to the spaced-apart bit lines. Specifically, for the first bit lines 231, second bit lines 232, third bit lines 234, and fourth bit lines 235 arranged along the second direction X, the first bit lines 231, second bit lines 232, third bit lines 234, and fourth bit lines 235 in the odd-numbered sequence are energized, or the first bit lines 231, second bit lines 232, third bit lines 234, and fourth bit lines 235 in the even-numbered sequence are energized. In this way, there is a bit line without working voltage between each pair of adjacent bit lines that are energized. The bit line without working voltage acts as a metal shield, avoiding the situation where capacitive coupling easily occurs when two adjacent bit lines are energized at the same time.

[0168] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 29 to 33 ,include:

[0169] The substrate includes a first region I, a second region II, and a third region III distributed along a first direction Y parallel to the substrate surface. The first region I is located between the second region II and the third region III. The substrate includes opposing first and second surfaces. The substrate includes a plurality of first active regions 204 and a plurality of second active regions 205. The first active regions 204 are located in the first region I, the third region III, and a portion of the second region II. The second active regions 205 are located in the first region I, the second region II, and a portion of the third region III. A first active region 204 and a plurality of second active regions 205 are arranged in parallel along a second direction X parallel to the substrate surface. The first active region 204 and the second active regions 205 are arranged alternately. The first direction Y is perpendicular to the second direction X. The first active region 204 exposed on the second surface of the substrate includes a first portion 222, a second portion 223 and a third portion 224 that are mutually independent. The second active regions 205 exposed on the second surface of the substrate include a fourth portion 225, a fifth portion 226 and a sixth portion 227 that are mutually independent.

[0170] A word line gate structure located in the first region I, wherein the word line gate structure is parallel to the second direction X;

[0171] A first cutting structure located within a substrate, the first cutting structure including a first cutting layer 206 located on a second region II, a second cutting layer 207 located on a third region III and a third cutting layer 208, the first cutting structure cutting into the first active region 204 from a second direction X, the first cutting structure located on the third region III and the first cutting structure located on the second region II are respectively located on both sides of the first active region 204 along the second direction X.

[0172] The second cutting structure is located within the substrate. The second cutting structure includes a fourth cutting layer 209 and a fifth cutting layer 210 located on the second region II, and a sixth cutting layer 211 located on the third region III. The second cutting structure cuts into the second active region 205 from the second direction X. The second cutting structure located on the third region III and the second cutting structure located on the second region II are respectively located on both sides of the second active region 205 along the second direction X. In the first direction Y, the first cutting layer 206 is located between the fourth cutting layer 209 and the fifth cutting layer 210.

[0173] The bit line structure located on the second surface of the substrate includes: a first bit line 231 electrically connected to the first portion 222, a second bit line 232 electrically connected to the second portion 223, a third bit line 234 electrically connected to the fourth portion 225, and a fourth bit line 235 electrically connected to the fifth portion 226.

[0174] A first connection structure 241 and a third connection structure 243 are located in the second region II. The first connection structure 241 is electrically connected to the first bit line 231, and the third connection structure 243 is electrically connected to the third bit line 234.

[0175] The second connection structure 242 and the fourth connection structure 244 are located in the third region III. The second connection structure 242 is electrically connected to the second bit line 232, and the fourth connection structure 244 is electrically connected to the fourth bit line 235.

[0176] In the semiconductor structure described, the spacing between adjacent first bit lines 231 and second bit lines 232 is small, as is the spacing between adjacent third bit lines 234 and fourth bit lines 235. This increases the process window for forming the first connection structure 241, third connection structure 243, second connection structure 242, and fourth connection structure 244, making them easier to form. This facilitates the connection of the first bit line 231 to an external circuit via the first connection structure 241, the second bit line 232 to an external circuit via the second connection structure 242, the third bit line 234 to an external circuit via the third connection structure 243, and the fourth bit line 235 to an external circuit via the fourth connection structure 244. It also facilitates individual control of the spaced-apart bit lines, avoiding capacitive coupling when two adjacent bit lines are simultaneously energized.

[0177] In this embodiment, the first active region 204 includes a first channel region distributed along a direction perpendicular to the substrate surface, the second active region 205 includes a second channel region distributed along a direction perpendicular to the substrate surface, the word line gate structure is adjacent to the first channel region and the second channel region; the first portion 222 and the second portion 223 are connected to the first channel region, and the fourth portion 225 and the fifth portion 226 are connected to the second channel region.

[0178] In this embodiment, the depth of the first cutting structure is greater than the depth of the first channel region, and the depth of the first cutting structure is less than the depth of the first active region 204; the depth of the second cutting structure is greater than the depth of the second channel region, and the depth of the second cutting structure is less than the depth of the second active region 205.

[0179] In this embodiment, the first active region 204 includes a first side and a second side opposite to each other along the second direction, and the second active region 205 includes a first side and a second side opposite to each other along the second direction; the first cutting layer 206, the fourth cutting layer 209 and the fifth cutting layer 210 located on the second region II are located on the first side of the first active region 204 and the second active region 205; the second cutting layer 207 and the third cutting layer 208 and the sixth cutting layer 211 located on the third region III are located on the second side of the first active region 204 and the second active region 205.

[0180] In this embodiment, the projections of the first cutting layer 206, the second cutting layer 207, and the third cutting layer 208 in the first direction Y at most partially overlap; the projections of the fourth cutting layer 209, the fifth cutting layer 210, and the sixth cutting layer 211 in the first direction Y at most partially overlap.

[0181] In this embodiment, the dimension of the first cutting structure in the second direction X is greater than the width of the first portion 222, and the dimension of the first cutting structure in the second direction X is greater than the width of the second portion 223; the dimension of the second cutting structure in the second direction X is greater than the width of the fourth portion 225, and the dimension of the second cutting structure in the second direction X is greater than the width of the fifth portion 226.

[0182] In this embodiment, the projected area of ​​the first bit line 231 on the substrate is less than or equal to the projected area of ​​the first portion 222 on the substrate; the projected area of ​​the second bit line 232 on the substrate is less than or equal to the projected area of ​​the second portion 223 on the substrate; the projected area of ​​the third bit line 234 on the substrate is less than or equal to the projected area of ​​the fourth portion 225 on the substrate; and the projected area of ​​the fourth bit line 235 on the substrate is less than or equal to the projected area of ​​the fifth portion 226 on the substrate.

[0183] In this embodiment, there is a first gap between the first bit line 231 and the second bit line 232, and the first active region 204 has a first width. The ratio of the first gap to the first width is between 1:2 and 1:4.

[0184] In this embodiment, the range of the first spacing is 5 nanometers to 50 nanometers; the range of the first width is 10 nanometers to 100 nanometers.

[0185] In this embodiment, there is a second spacing between the third bit line 234 and the fourth bit line 235, and the second active region has a second width. The ratio of the second spacing to the second width is between 1:2 and 1:4.

[0186] In this embodiment, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0187] In this embodiment, the substrate further includes: a first isolation layer 202 located between adjacent first active regions 204 and second active regions 205, the first surface of the substrate exposing the surface of the first isolation layer 202; and a third isolation layer 203 located in a portion of the second region II and a portion of the third region III, the third isolation layer 203 located in the second region II being in contact with the first active region 204 and the first isolation layer 202, and the third isolation layer 203 located in the third region III being in contact with the second active region 205 and the first isolation layer 202.

[0188] In this embodiment, it further includes: a third isolation layer 221 located between the first portion 222 and the second portion 223; and a third isolation layer 221 located between the fourth portion 225 and the fifth portion 226, wherein the third isolation layer 221 is parallel to the first direction Y.

[0189] In this embodiment, it also includes: a plurality of capacitor structures 217 located on the first surface of the substrate, wherein one of the capacitor structures 217 is electrically connected to a first active region 204 or a second active region 205.

[0190] In this embodiment, it further includes: a first source / drain doped region located within the first active region 204 and the second active region 205 exposed on the first surface of the substrate, and the capacitor structure 217 is electrically connected to the first source / drain doped region.

[0191] In this embodiment, it further includes a second source / drain doped region located in the first section 222, the second section 223, the fourth section 225 and the fifth section 226, and the bit line structure is electrically connected to the second source / drain doped region.

[0192] In this embodiment, the first channel region includes a plurality of discrete first channel pillars 212 located in the first region I; the second channel region includes a plurality of discrete second channel pillars 213 located in the first region I.

[0193] In this embodiment, the word line gate structure includes: a first word line gate 215 and a second word line gate 216. The first word line gate 215 and the second word line gate 216 are respectively located on the two sidewalls of the first channel post 212 along the first direction Y and on the two sidewalls of the second channel post 213 along the first direction Y. The first word line gate 215 and the second word line gate 216 are parallel to the second direction X. The first word line gate 215 and the second word line gate 216 are located in the substrate, and adjacent first word line gates 215 and second word line gates 216 are electrically isolated from each other.

[0194] In this embodiment, the central axes of two adjacent first channel posts 212 in the first direction Y do not coincide; the central axes of two adjacent second channel posts 213 in the first direction Y do not coincide.

[0195] In other embodiments, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0196] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second region and the third region, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region, the third region, and a portion of the second region, the second active regions being located in the first region, the second region, and a portion of the third region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other; A first cutting structure is formed in a portion of the first active region. The first cutting structure includes a first cutting layer located on a second region, a second cutting layer located on a third region, and a third cutting layer. The first cutting structure cuts into a portion of the first active region from a second direction. The first cutting structure located on the third region and the first cutting structure located on the second region are respectively located on both sides of the first active region along the second direction. A second cutting structure is formed in a portion of the second active region. The second cutting structure includes a fourth cutting layer and a fifth cutting layer located on the second region, and a sixth cutting layer located on the third region. The second cutting structure cuts into a portion of the second active region from a second direction. The second cutting structure located on the third region and the second cutting structure located on the second region are respectively located on both sides of the second active region along the second direction. In the first direction, the first cutting layer is located between the fourth cutting layer and the fifth cutting layer. A word line gate structure is formed in the first region, the word line gate structure being parallel to the second direction; The active region exposed on the second surface of the substrate is removed, exposing the surfaces of the first cut structure and the second cut structure. The first cut structure forms the first active region into a first portion, a second portion, and a third portion that are mutually independent, with the third portion located between the second cut layer and the third cut layer. The second cut structure forms the second active region into a fourth portion, a fifth portion, and a sixth portion that are mutually independent, with the sixth portion located between the fourth cut layer and the fifth cut layer. A bit line structure is formed on the second surface of the substrate, the bit line structure including: a first bit line electrically connected to the first portion, a second bit line electrically connected to the second portion, a third bit line electrically connected to the fourth portion, and a fourth bit line electrically connected to the fifth portion; A first connection structure and a third connection structure are formed on the second region. The first connection structure is electrically connected to the first bit line, and the third connection structure is electrically connected to the third bit line. A second connection structure and a fourth connection structure are formed on the third region. The second connection structure is electrically connected to the second bit line, and the fourth connection structure is electrically connected to the fourth bit line.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, and the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface. The word line gate structure is adjacent to the first channel region and the second channel region. The first portion and the second portion are connected to the first channel region, and the fourth portion and the fifth portion are connected to the second channel region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The depth of the first cutting structure is greater than the depth of the first channel region, and the depth of the first cutting structure is less than the depth of the first active region. The depth of the second cut-off structure is greater than the depth of the second channel region, and the depth of the second cut-off structure is less than the depth of the second active region.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first active region includes a first side and a second side opposite to each other along a second direction, and the second active region includes a first side and a second side opposite to each other along a second direction; the first cutting layer, the fourth cutting layer and the fifth cutting layer located on the second region are located on the first side of the first active region and the second active region; The second and third cutting layers and the sixth cutting layer located in the third region are located on the second side of the first active region and the second active region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projections of the first, second, and third cutting layers in the first direction may at most partially overlap; the projections of the fourth, fifth, and sixth cutting layers in the first direction may at most partially overlap.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the first direction, the first cutting layer is located between the fourth and fifth cutting layers; in the first direction, the sixth cutting layer is located between the second and third cutting layers.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dimension of the first cutting structure in the second direction is greater than the width of the first portion, and the dimension of the first cutting structure in the second direction is greater than the width of the second portion; The second cutting structure is larger in the second direction than the width of the fourth portion, and the second cutting structure is larger in the second direction than the width of the fifth portion.

8. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first, second, third, fourth, fifth, and sixth portions are formed simultaneously. The formation process of the first, second, third, fourth, fifth, and sixth portions includes: etching back the first active region exposed on the second surface of the substrate to form a first groove within the substrate, the first groove extending from the second surface of the substrate to the first surface; etching back the second active region exposed on the second surface of the substrate to form a second groove within the substrate, the second groove extending from the second surface of the substrate to the first surface; forming sidewalls on the sidewalls of the first and second grooves, the sidewall on the sidewall of the first groove exposing a portion of the surface of the first active region, and the sidewall on the sidewall of the second groove exposing a portion of the surface of the first active region. The surface of the second active region is divided; the exposed first active region is removed using the sidewall as a mask, and a third groove is formed in the first active region; the exposed second active region is removed using the sidewall as a mask, and a fourth groove is formed in the second active region; a second isolation layer is formed in the third groove and the fourth groove, and the second isolation layer is in contact with the first cut-off structure and the second cut-off structure; the first active region and the second active region exposed on the second surface of the substrate are removed until the surfaces of the first cut-off structure and the second cut-off structure are exposed, so that the first active region is formed into a first part, a second part and a third part that are mutually independent, and the second active region is formed into a fourth part, a fifth part and a sixth part that are mutually independent.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, Forming a sidewall on the surfaces of the first and second groove sidewalls includes: forming a sidewall material layer on the surface and bottom surface of the first groove sidewall, the surface and bottom surface of the second groove sidewall, and the second surface of the substrate; and etching back the sidewall material layer until the surfaces of the first and second active regions are exposed, thereby forming a sidewall on the first and second groove sidewalls.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The third groove and the fourth groove are formed simultaneously; The formation process of the third and fourth grooves includes: removing the exposed first active area using the sidewall as a mask until the surface of the first channel area is exposed, forming a third groove in the first active area; removing the exposed second active area using the sidewall as a mask until the surface of the second channel area is exposed, forming a fourth groove in the second active area.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process of forming the second isolation layer, the first segment, the second segment, the third segment, the fourth segment, the fifth segment, and the sixth segment includes: after removing the sidewall, forming an isolation material layer in the first groove, the second groove, the third groove, the fourth groove, and the second surface of the substrate; planarizing the isolation material layer, the first active region, and the second active region until the surfaces of the first cut-off structure and the second cut-off structure are exposed; forming the second isolation layer in the third groove and the fourth groove, so that the first active region is formed into mutually independent first, second, and third segments, and the second active region is formed into mutually independent fourth, fifth, and sixth segments.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process of forming the second isolation layer, the first segment, the second segment, the third segment, the fourth segment, the fifth segment, and the sixth segment includes: after removing the sidewall, removing the first active region and the second active region exposed on the second surface of the substrate until the remaining first active region is lower than or flush with the surface of the first cut structure, and until the surface of the remaining second active region is lower than or flush with the surface of the second cut structure; forming an isolation material layer in the first groove, the second groove, the third groove, the fourth groove, and on the second surface of the substrate; planarizing the isolation material layer until the surfaces of the first active region and the second active region are exposed; forming a second isolation layer in the third groove and the fourth groove, such that the first active region is formed into mutually independent first, second, and third segments, and the second active region is formed into mutually independent fourth, fifth, and sixth segments.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; The projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate; The projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fifth part on the substrate.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion to form a first opening in the substrate; etching back the second portion to form a second opening in the substrate; etching back the fourth portion to form a third opening in the substrate; etching back the fifth portion to form a fourth opening in the substrate; forming a bit line material layer in the first opening, the second opening, the third opening, the fourth opening, and on the second surface of the substrate; planarizing the bit line material layer until the surface of the second surface of the substrate is exposed; forming the first bit line in the first opening; forming the second bit line in the second opening; forming the third bit line in the third opening; and forming the fourth bit line in the fourth opening.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first and second cutting structures are formed simultaneously. The formation process of the first and second cutting structures includes: forming a mask structure on a first surface of a substrate, the mask structure having a plurality of openings, the plurality of openings exposing a portion of the surface of the first active region and a portion of the surface of the second active region; etching the exposed first and second active regions using the mask structure as a mask to form a plurality of grooves in the substrate; forming a cutting material layer in the grooves and on the first surface of the substrate; planarizing the cutting material layer until the surfaces of the first and second active regions are exposed, forming a first cutting layer, a fourth cutting layer and a fifth cutting layer in the second region, and forming a second cutting layer, a third cutting layer and a sixth cutting layer in the third region.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, There is a first spacing between the first bit line and the second bit line, and the first active region has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:

4.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The third bit line and the fourth bit line have a second spacing, the second active region has a second width, and the ratio of the second spacing to the second width is in the range of 1:2 to 1:

4.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first connection structure, the second connection structure, the third connection structure, and the fourth connection structure are formed simultaneously; The formation process of the first connection structure, the second connection structure, the third connection structure, and the fourth connection structure includes: forming a dielectric structure on a second surface of a substrate; forming a fifth opening, a sixth opening, a seventh opening, and an eighth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the first bit line surface on the second region, the sixth opening exposes at least a portion of the second bit line surface on the third region, the seventh opening exposes at least a portion of the third bit line surface on the second region, and the eighth opening exposes at least a portion of the fourth bit line surface on the third region; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall surface and bottom surface of the fifth opening, the sidewall surface and bottom surface of the sixth opening, the sidewall surface and bottom surface of the seventh opening, the sidewall surface and bottom surface of the eighth opening, and the surface of the dielectric structure; planarizing the conductive material layer and the barrier material layer until the surface of the dielectric structure is exposed; forming a first connection structure within the fifth opening, a second connection structure within the sixth opening, a third connection structure within the seventh opening, and a fourth connection structure within the eighth opening.

21. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a first isolation layer located between adjacent first active regions and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; the substrate formation process includes: providing an initial substrate, the initial substrate including a first region, a second region and a third region distributed along a first direction parallel to the surface of the initial substrate, the first region being located between the second region and the third region, the initial substrate including: a substrate, a plurality of initial first active regions and a plurality of initial second active regions located on the substrate, and a first isolation layer located between adjacent initial first active regions and initial second active regions, the plurality of initial first active regions and the plurality of second initial active regions being distributed along a second direction parallel to the surface of the initial substrate. The initial first active region and the initial second active region are arranged in parallel directions, alternating between each other. The first surface of the initial substrate exposes the surface of the first isolation layer. A portion of the initial first active region in the second region is removed to form a first active region located in the first region, the third region, and a portion of the second region. A seventh groove is formed in the initial substrate, extending from the first surface of the initial substrate to the second surface. A portion of the initial second active region in the third region is removed to form a second active region located in the first region, the second region, and a portion of the third region. An eighth groove is formed in the initial substrate, extending from the first surface of the initial substrate to the second surface. A third isolation layer is formed in the seventh groove and the eighth groove.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The substrate formation process further includes: before removing a portion of the first active region and the second active region exposed on the second surface of the substrate, the process further includes: removing the substrate to expose the surface of the first isolation layer, the surface of the first active region, and the surface of the second active region, thereby forming the substrate.

23. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the word line gate structure in the first region, the method further includes: forming a plurality of capacitor structures on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the first active regions or the second active region.

24. The method for forming a semiconductor structure as described in claim 22, characterized in that, Before forming several capacitor structures, the method further includes: performing a first ion implantation on a first active region and a second active region exposed on the first surface of the substrate to form a first source-drain doped region, wherein the capacitor structure is electrically connected to the first source-drain doped region.

25. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first, second, fourth, and fifth portions to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

26. The method for forming a semiconductor structure as described in claim 2, characterized in that, Before forming the word line grid structure located in the first region, the method further includes: etching the first channel region of the first active region to form a plurality of discrete first channel pillars located in the first region; and etching the second channel region of the second active region to form a plurality of discrete second channel pillars located in the first region.

27. The method for forming a semiconductor structure as described in claim 26, characterized in that, The word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction. The first word line gate and the second word line gate are parallel to the second direction. The first word line gate and the second word line gate are located within the substrate, and adjacent first word line gates and second word line gates are electrically isolated from each other.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, The central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

29. The method for forming a semiconductor structure as described in claim 26, characterized in that, The word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

30. A semiconductor structure, characterized in that, include: A substrate comprising a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region, the third region, and a portion of the second region, the second active regions being located in the first region, the second region, and a portion of the third region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other, the first active regions exposed on the second surface of the substrate comprising mutually separate first portions, second portions, and third portions, the second active regions exposed on the second surface of the substrate comprising mutually separate fourth portions, fifth portions, and sixth portions; A word line gate structure located in the first region, the word line gate structure being parallel to the second direction; A first cutting structure located within a substrate, the first cutting structure including a first cutting layer on a second region, a second cutting layer and a third cutting layer on a third region, the first cutting structure cutting into a portion of the first active region from a second direction, the first cutting structure on the third region and the first cutting structure on the second region being located on opposite sides of the first active region along the second direction; a second cutting structure located within a substrate, the second cutting structure including a fourth cutting layer and a fifth cutting layer on a second region, and a sixth cutting layer on a third region, the second cutting structure cutting into a portion of the second active region from a second direction, the second cutting structure on the third region and the second cutting structure on the second region being located on opposite sides of the second active region along the second direction, the first cutting layer being located between the fourth cutting layer and the fifth cutting layer in a first direction; A bit line structure located on the second surface of a substrate, the bit line structure comprising: a first bit line electrically connected to a first portion, a second bit line electrically connected to a second portion, a third bit line electrically connected to a fourth portion, and a fourth bit line electrically connected to a fifth portion; A first connection structure and a third connection structure are located in the second region, wherein the first connection structure is electrically connected to the first bit line, and the third connection structure is electrically connected to the third bit line; The second connection structure and the fourth connection structure are located in the third region. The second connection structure is electrically connected to the second bit line, and the fourth connection structure is electrically connected to the fourth bit line.

31. The semiconductor structure as described in claim 30, characterized in that, The first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, and the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface. The word line gate structure is adjacent to the first channel region and the second channel region. The first portion and the second portion are connected to the first channel region, and the fourth portion and the fifth portion are connected to the second channel region.

32. The semiconductor structure as described in claim 31, characterized in that, The depth of the first cutting structure is greater than the depth of the first channel region, and the depth of the first cutting structure is less than the depth of the first active region. The depth of the second cut-off structure is greater than the depth of the second channel region, and the depth of the second cut-off structure is less than the depth of the second active region.

33. The semiconductor structure as described in claim 30, characterized in that, The first active region includes a first side and a second side opposite to each other along a second direction, and the second active region includes a first side and a second side opposite to each other along a second direction; the first cutting layer, the fourth cutting layer and the fifth cutting layer located on the second region are located on the first side of the first active region and the second active region; The second and third cutting layers and the sixth cutting layer located in the third region are located on the second side of the first active region and the second active region.

34. The semiconductor structure as described in claim 30, characterized in that, The projections of the first, second, and third cutting layers in the first direction may at most partially overlap; the projections of the fourth, fifth, and sixth cutting layers in the first direction may at most partially overlap.

35. The semiconductor structure as described in claim 30, characterized in that, In the first direction, the first cutting layer is located between the fourth and fifth cutting layers; in the first direction, the sixth cutting layer is located between the second and third cutting layers.

36. The semiconductor structure as described in claim 30, characterized in that, The dimension of the first cutting structure in the second direction is greater than the width of the first portion, and the dimension of the first cutting structure in the second direction is greater than the width of the second portion; The second cutting structure is larger in the second direction than the width of the fourth portion, and the second cutting structure is larger in the second direction than the width of the fifth portion.

37. The semiconductor structure as described in claim 30, characterized in that, The projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; The projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate; The projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fifth part on the substrate.

38. The semiconductor structure as described in claim 30, characterized in that, There is a first spacing between the first bit line and the second bit line, and the first active region has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:

4.

39. The semiconductor structure as described in claim 38, characterized in that, The first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

40. The semiconductor structure as claimed in claim 30, characterized in that, The third bit line and the fourth bit line have a second spacing, the second active region has a second width, and the ratio of the second spacing to the second width is in the range of 1:2 to 1:

4.

41. The semiconductor structure as described in claim 40, characterized in that, The second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

42. The semiconductor structure as described in claim 30, characterized in that, The substrate further includes: a first isolation layer located between adjacent first active regions and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; and a third isolation layer located in a portion of the second region and a portion of the third region, the third isolation layer located in the second region being in contact with the first active region and the first isolation layer, and the third isolation layer located in the third region being in contact with the second active region and the first isolation layer.

43. The semiconductor structure as described in claim 30, characterized in that, Also includes: A second isolation layer located between the first and second divisions; A second isolation layer is located between the fourth and fifth sections, and the second isolation layer is parallel to the first direction.

44. The semiconductor structure as described in claim 30, characterized in that, Also includes: A plurality of capacitor structures located on a first surface of a substrate, wherein one of the capacitor structures is electrically connected to a first active region or a second active region.

45. The semiconductor structure as described in claim 44, characterized in that, Also includes: The capacitor structure is electrically connected to the first source / drain doped region located within the first and second active regions exposed on the first surface of the substrate.

46. ​​The semiconductor structure as described in claim 30, characterized in that, Also includes: The second source / drain doped region is located in the first, second, fourth, and fifth sections, and the bit line structure is electrically connected to the second source / drain doped region.

47. The semiconductor structure as claimed in claim 31, characterized in that, The first trench area includes a plurality of separate first trench columns located in the first area; the second trench area includes a plurality of separate second trench columns located in the first area.

48. The semiconductor structure as claimed in claim 47, characterized in that, The word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction. The first word line gate and the second word line gate are parallel to the second direction. The first word line gate and the second word line gate are located within the substrate, and adjacent first word line gates and second word line gates are electrically isolated from each other.

49. The semiconductor structure as described in claim 48, characterized in that, The central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

50. The semiconductor structure as claimed in claim 47, characterized in that, The word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

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