Semiconductor structure, forming method thereof and memory array

Abstract

A semiconductor structure and a forming method thereof, and a memory array, the forming method comprising: providing a substrate, the substrate having a bit line direction and a word line direction which are arranged in a vertically crossing manner, the substrate comprising a plurality of active regions arranged in parallel along the bit line direction and isolation regions located between the active regions, and the substrate comprising a first surface; forming a photoresist layer on the first surface; exposing and developing the photoresist layer to form a photoresist layer with a vertical transistor pattern; and etching a part of the active region and a part of the isolation region along the first surface by taking the photoresist layer with the vertical transistor pattern as a mask to form a vertical transistor. A photoresist layer with a vertical transistor pattern is formed on a first surface, and the photoresist layer is located on the first surface of an active region in a staggered and spaced manner along a bit line direction and a word line direction, so that after a subsequent etching process, spaced distribution among a plurality of vertical transistors is realized, and the yield of the vertical transistors is improved. The coupling effect between adjacent bit lines can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its formation method, and a memory array. Background Technology

[0002] Memory is a storage device used in modern information technology to store information. As storage device technology continues to iterate, the demand for storage cell density is increasing, requiring the size parameters of various parts of the device to be continuously reduced, such as SN-SN distance (distance between storage nodes) and BLC-BLC distance (distance between bit line contacts).

[0003] However, the storage efficiency of current storage units has decreased. Summary of the Invention

[0004] The technical problem solved by this invention is how to improve the storage efficiency of storage units.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having a bit line direction and a word line direction arranged perpendicularly and intersectingly, the substrate including a plurality of active regions arranged parallel to each other along the bit line direction and isolation regions located between the active regions, and the substrate including a first surface; forming a photoresist layer on the first surface; exposing and developing the photoresist layer to form a photoresist layer having a vertical transistor pattern, the photoresist layer having the vertical transistor pattern being staggered along the bit line direction and the word line direction on the first surface of the active regions; using the photoresist layer having the vertical transistor pattern as a mask, etching a portion of the active regions and a portion of the isolation regions along the first surface to form a vertical transistor and a bit line located at the bottom of the vertical transistor.

[0006] Optionally, the substrate further includes adjacent first and second regions arranged along the bit line direction; the vertical transistor on the same active region and the bit line located at the bottom of the vertical transistor are located on the first region or the second region, the vertical transistor on the same first region and the bit line located at the bottom of the vertical transistor are located on one of the adjacent active regions, and the vertical transistor on the same second region and the bit line located at the bottom of the vertical transistor are located on one of the adjacent active regions.

[0007] Optionally, the etching process for removing the active region and the isolation region can be a dry etching process or a wet etching process.

[0008] Optionally, the etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

[0009] Optionally, a first trench is formed between adjacent vertical transistors; after the step of forming the vertical transistor, the method includes: filling the first trench with a first interlayer dielectric layer; planarizing the first interlayer dielectric layer to expose the top surface of the vertical transistor; and continuing to etch the first interlayer dielectric layer to form a second trench located on the first interlayer dielectric layer.

[0010] Optionally, after forming the second trench located on the first interlayer dielectric layer, the method includes: forming a first annular word line gate oxide layer on the sidewall surface of the second trench, the first annular word line gate oxide layer surrounding a portion of the vertical transistor; using an atomic layer deposition process, forming a first annular word line gate layer and a third trench on the bottom surface of the second trench and the sidewall surface of the first annular word line gate oxide layer, the first annular word line gate layer surrounding the first annular word line gate oxide layer; filling the third trench with an insulating layer, the first annular word line gate layer, the first annular word line gate oxide layer and the insulating layer constituting a first word line; and etching the top of the first annular word line gate layer and the insulating layer to form the first word line.

[0011] Optionally, the thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, the material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, and the first annular word line gate oxide layer and the first annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular or polygonal annular.

[0012] Optionally, after forming the second trench located on the first interlayer dielectric layer, the method includes: forming a second annular word line gate oxide layer on the sidewall surface of the second trench, the second annular word line gate oxide layer surrounding a portion of the vertical transistor; filling the second trench with the second annular word line gate oxide layer using atomic layer deposition, PVD, or CVD processes, the second annular word line gate oxide layer surrounding the second annular word line gate oxide layer, the second annular word line gate oxide layer and the second annular word line gate oxide layer constituting a second word line; and etching the top of the second annular word line gate oxide layer and the second annular word line gate oxide layer to form the second word line.

[0013] Optionally, the thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular, or polygonal annular.

[0014] Optionally, the substrate includes a second surface, and the first surface and the second surface are two opposite surfaces of the substrate; after forming the first word line and the second word line, the method further includes: forming a second interlayer dielectric layer on top of the first word line and the second word line, the second interlayer dielectric layer being flush with the top of the vertical transistor; forming a hard mask layer on the substrate, the hard mask layer extending along the word line direction and covering all the vertical transistors along the word line direction, the hard mask layers being discretely arranged along the bit line direction, and exposing a portion between adjacent hard mask layers in the bit line direction. The top surface of the second interlayer dielectric layer is described; using the hard mask layer as a mask, the second interlayer dielectric layer and the first word line and the second word line are etched sequentially until the first interlayer dielectric layer is exposed, forming a plurality of discrete first word lines, second word lines and a fourth trench, and the plurality of discrete first word lines and second word lines are arranged along the bit line direction; a third interlayer dielectric layer is filled into the fourth trench, and the third interlayer dielectric layer is flush with the top of the vertical transistor; the second surface of the substrate is thinned, and part of the substrate and part of the bit lines are etched away to form a plurality of discrete bit lines.

[0015] Optionally, a first trench is formed between adjacent vertical transistors; after forming the vertical transistor, the method includes: filling the first trench with a first interlayer dielectric layer; planarizing the first interlayer dielectric layer to expose the top surface of the vertical transistor; forming a hard mask layer on the substrate, the hard mask layer extending along the word line direction and covering the vertical transistor along the word line direction, the hard mask layers being discretely arranged along the bit line direction, and exposing a portion of the top surface of the first interlayer dielectric layer between adjacent hard mask layers in the bit line direction; etching the first interlayer dielectric layer using the hard mask layer as a mask to form discrete first interlayer dielectric layers and a second trench, the second trench being located between adjacent first interlayer dielectric layers and the vertical transistor; and removing the hard mask layer.

[0016] Optionally, after forming the discrete first interlayer dielectric layer and second trench, the method includes: using atomic layer deposition (ALD) to form an initial first word line gate oxide layer on the surface of the second trench and an initial first word line gate layer on the surface of the initial first word line gate oxide layer; using a dry etching process to remove the initial first word line gate oxide layer and the initial first word line gate layer on the bottom surface of the second trench, forming a first word line gate oxide layer on the sidewall surface of the second trench and a first word line gate layer on the sidewall surface of the first word line gate oxide layer, the first word line gate layer spanning the substrate along the word line direction, the first word line gate layer and the first word line gate oxide layer constituting a third word line, the third word line being discretely arranged along the bit line direction, and the second trench being between adjacent third word lines; filling the second trench with a second interlayer dielectric layer, the top of the second interlayer dielectric layer being flush with the vertical transistor; and etching the top of the first word line gate oxide layer, the first word line gate layer, the first interlayer dielectric layer and the second interlayer dielectric layer to form the third word line.

[0017] Optionally, the width of the first word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the first word line gate layer along the bit line direction ranges from 1 to 10 nanometers, the depth of the first word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the first word line gate layer is one of TIN, a combination of TIN and W, or Mo.

[0018] Optionally, after forming the third word line, the method further includes: forming a third interlayer dielectric layer on top of the third word line, the third interlayer dielectric layer being flush with the top of the vertical transistor; thinning the second surface of the substrate, etching away a portion of the substrate and a portion of the bit line to form a plurality of discrete bit lines.

[0019] Optionally, a first trench is formed between adjacent vertical transistors; after the step of forming the vertical transistor, the method includes: filling the first trench with a first interlayer dielectric layer; planarizing the first interlayer dielectric layer to expose the top surface of the vertical transistor; using a dry etching process with an etch selectivity, sequentially etching the vertical transistor and the isolation regions located on both sides of the vertical transistor to form a second trench; using an epitaxial growth process, forming the first vertical transistor in the second trench; forming a hard mask layer on the substrate, the hard mask layer extending along the word line direction and covering the first vertical transistor along the word line direction, the hard mask layers being discretely arranged along the bit line direction, and exposing a portion of the top surface of the first interlayer dielectric layer between adjacent hard mask layers in the bit line direction; etching the first interlayer dielectric layer using the hard mask layer as a mask to form discrete first interlayer dielectric layers and a third trench, the third trench being located between adjacent first interlayer dielectric layers and the first vertical transistor.

[0020] Optionally, the etching process for the vertical transistor and the active regions located on both sides of the vertical transistor is dry etching or wet etching, and the width of the first vertical transistor along the word line direction ranges from 15 nanometers to 100 nanometers.

[0021] Optionally, after forming the discrete first interlayer dielectric layer and the third trench, the method includes: using atomic layer deposition to form an initial second word line gate oxide layer and an initial second word line gate layer on the surface of the third trench; using a dry etching process to remove the initial second word line gate oxide layer and the initial second word line gate layer on the bottom surface of the third trench, forming a second word line gate oxide layer on the sidewall surface of the third trench and a second word line gate layer on the sidewall surface of the second word line gate oxide layer, the second word line gate layer spanning the substrate along the word line direction, the second word line gate layer and the second word line gate oxide layer constituting a fourth word line, the fourth word line being discretely arranged along the bit line direction, and the third trench being between adjacent fourth word lines; filling the third trench with a second interlayer dielectric layer, the top of the second interlayer dielectric layer being flush with the first vertical transistor; and etching the top of the second word line gate oxide layer, the second word line gate layer and the second interlayer dielectric layer to form the fourth word line.

[0022] Optionally, the width of the second word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the second word line gate layer along the bit line direction ranges from 1 to 10 nanometers, the depth of the second word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the second word line gate layer is one of TIN, a combination of TIN and W, or Mo.

[0023] Optionally, after forming the fourth word line, the method further includes: forming a third interlayer dielectric layer on top of the fourth word line, the third interlayer dielectric layer being flush with the top of the first vertical transistor; thinning the second surface of the substrate, etching away a portion of the substrate and a portion of the bit line to form a plurality of discrete bit lines.

[0024] Accordingly, the present invention also provides a semiconductor structure comprising: a substrate having a bit line direction and a word line direction arranged in a perpendicular cross configuration, the substrate including a plurality of active regions arranged in parallel along the bit line direction and an isolation region located between the active regions, and the substrate including a first surface; a vertical transistor formed on the first surface of the active regions that are staggered in the bit line direction and the word line direction; and a bit line located at the bottom of the vertical transistor.

[0025] Optionally, the active region includes adjacent first and second regions arranged along the bit line direction; the vertical transistor on the same active region and the bit line located at the bottom of the vertical transistor are located on the first region or the second region; the vertical transistor on the same first region and the bit line located at the bottom of the vertical transistor are located on one of the adjacent active regions; the vertical transistor on the same second region and the bit line located at the bottom of the vertical transistor are located on one of the adjacent active regions.

[0026] Optionally, the semiconductor structure further includes: a first word line, the first word line being discretely arranged along the bit line direction, the first word line including: a first annular word line gate oxide layer, a first annular word line gate layer and an insulating layer, the first annular word line gate oxide layer surrounding a portion of the vertical transistor, and the first annular word line gate oxide layer being located on the sidewall surface of the vertical transistor and the substrate surface, the first annular word line gate layer surrounding the first annular word line gate oxide layer, and the insulating layer being located in a third trench between adjacent first annular word line gate layers.

[0027] Optionally, the semiconductor structure further includes: a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer, wherein the first word lines are located within a first trench between adjacent vertical transistors, the first interlayer dielectric layer is located at the bottom of the first word lines, the second interlayer dielectric layer is located at the top of the first word lines, and the third interlayer dielectric layer is located within the first word lines and the second interlayer dielectric layer.

[0028] Optionally, the thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, the material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, and the first annular word line gate oxide layer and the first annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular or polygonal annular.

[0029] Optionally, the semiconductor structure further includes: a second word line, the second word line being discretely arranged along the bit line direction, the second word line including: a second annular word line gate oxide layer and a second annular word line gate layer, the second annular word line gate oxide layer surrounding a portion of the vertical transistor, and the second annular word line gate oxide layer being located on the sidewall surface of the vertical transistor and the substrate surface, the second annular word line gate layer surrounding the second annular word line gate oxide layer, and the second annular word line gate layer filling a second trench between adjacent second annular word line gate oxide layers.

[0030] Optionally, the semiconductor structure further includes: a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer, wherein the second word lines are located within a first trench between adjacent vertical transistors, the first interlayer dielectric layer is located at the bottom of the second word lines, the second interlayer dielectric layer is located at the top of the second word lines, and the third interlayer dielectric layer is located within the second word lines and the second interlayer dielectric layer.

[0031] Optionally, the thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular, or polygonal annular.

[0032] Optionally, the semiconductor structure further includes: a third word line, the third word line being discretely arranged along the bit line direction, the third word line including: a first word line gate oxide layer and a first word line gate layer, the first word line gate oxide layer being located on the sidewall surface adjacent to the vertical transistor, the first word line gate layer being located on the sidewall surface of the first word line gate oxide layer, and the first word line gate layer spanning the substrate along the word line direction.

[0033] Optionally, the semiconductor structure further includes: a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer, wherein the first interlayer dielectric layer is located on the substrate, and a portion of the first interlayer dielectric layer is located between adjacent first word line gate oxide layers; the second interlayer dielectric layer is located between the first interlayer dielectric layer and the vertical transistor; and the third interlayer dielectric layer is located on top of the first interlayer dielectric layer and on top of the third word line, and the third interlayer dielectric layer is flush with the top of the vertical transistor.

[0034] Optionally, the width of the first word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the first word line gate layer along the bit line direction ranges from 1 nanometer to 10 nanometers, the depth of the first word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the first word line gate layer is one of TIN, a combination of TIN and W, or Mo.

[0035] Optionally, the semiconductor structure further includes: a first vertical transistor, the first vertical transistor being discretely located on the substrate, the width of the first vertical transistor along the word line direction ranging from 15 nanometers to 100 nanometers.

[0036] Optionally, the semiconductor structure further includes: a fourth word line, the fourth word line being discretely arranged along the bit line direction, the fourth word line including: a second word line gate oxide layer and a second word line gate layer, the second word line gate oxide layer being located on the sidewall surface adjacent to the first vertical transistor and a portion of the isolation region surface, the second word line gate layer being located on the sidewall surface of the second word line gate oxide layer, and the second word line gate layer spanning the substrate along the word line direction.

[0037] Optionally, the width of the second word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the second word line gate layer along the bit line direction ranges from 1 nanometer to 10 nanometers, the depth of the second word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the second word line gate layer is one of TIN, a combination of TIN and W, or Mo.

[0038] Accordingly, the present invention also provides a memory array, comprising: a plurality of bit lines arranged along word line direction; a plurality of word lines arranged along bit line direction, wherein the plurality of bit lines intersect with the plurality of word lines in a grid-like arrangement; a plurality of dual-gate vertical transistors, wherein the plurality of dual-gate vertical transistors are arranged in an array at intervals in the grid formed by the intersection of the plurality of bit lines and the plurality of word lines, wherein in any row of grids formed by the intersection of any word line and the plurality of bit lines, the dual-gate vertical transistor is located in one of two adjacent grids, and in any column of grids formed by the intersection of any bit line and the plurality of word lines, the dual-gate vertical transistor is located in one of two adjacent grids, wherein the source / drain of the dual-gate vertical transistor is connected to the bit line, and the gate of the dual-gate vertical transistor is connected to the word line; and a plurality of memory capacitors, wherein the first end of the memory capacitor is connected to the source / drain of the dual-gate vertical transistor, and the second end of the memory capacitor is grounded.

[0039] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0040] In this invention, a photoresist layer with a vertical transistor pattern is formed on the first surface. The photoresist layer is staggered along the bit line direction and word line direction on the first surface of the active region. This ensures that after subsequent etching, only one active region among adjacent active regions is retained, forming several discrete and spaced vertical transistors. Since the vertical transistors are connected to the bit lines, the spacing between the bit lines is achieved, effectively reducing the coupling between adjacent bit lines and improving the storage efficiency of the memory cell. Furthermore, the staggered distribution of the photoresist layer along the bit line direction ensures that after subsequent etching, the vertical transistors are also staggered along the bit line direction, increasing the arrangement density compared to the rectangular arrangement in the prior art.

[0041] Furthermore, the present invention achieves process diversity of word lines by filling the trench between adjacent vertical transistors to form a first word line and a second word line, and the first word line and the second word line have different structures.

[0042] Furthermore, the present invention forms a first interlayer dielectric layer at the bottom of the trench between adjacent vertical transistors, etches the first interlayer dielectric layer while retaining the bottom portion of the first interlayer dielectric layer, forms word lines on the first interlayer dielectric layer, and etches the top of the word lines, so that the depth of the subsequently formed word lines can be precisely defined, thereby ensuring the performance of the formed dual-gate vertical transistors.

[0043] Furthermore, by forming a hard mask layer on the substrate before forming the third or fourth word line, and defining the shape of the third or fourth word line through the hard mask layer, the present invention can form the third or fourth word line discretely arranged along the bit line direction without etching the third or fourth word line along the bit line direction, thereby simplifying the process steps and increasing the diversity of process steps.

[0044] Furthermore, the present invention removes part of the vertical transistor and the isolation regions located on both sides of the vertical transistor by etching, and forms the first vertical transistor in the trench formed by etching, thereby increasing the width of the first vertical transistor, increasing the support performance of the first vertical transistor, and increasing the stability of the structure. Attached Figure Description

[0045] Figure 1 A schematic diagram of a storage array structure;

[0046] Figures 2 to 27 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention;

[0047] Figures 28 to 38 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention;

[0048] Figures 39 to 51 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention;

[0049] Figures 52 to 69 A schematic diagram of the semiconductor structure formation process in another embodiment of the invention;

[0050] Figure 70 This is a schematic diagram of the structure of a storage array in one embodiment of the present invention. Detailed Implementation

[0051] As the demand for memory cell density increases, the size parameters of various parts of the device are constantly shrinking, such as SN-SN distance (distance between memory nodes) and BLC-BLC distance (distance between bit line contacts).

[0052] The current memory array structure is shown in Figure 1. The memory array includes several bit lines BL, which are arranged along the word line direction X; several word lines WL, which are arranged along the bit line direction Y, and the bit lines BL and word lines WL intersect in a grid pattern; several dual-gate vertical transistors 101, which are arrayed in the grid formed by the intersection of the bit lines BL and word lines WL, with the source / drain of the dual-gate vertical transistors 101 connected to the bit lines BL and the gate of the dual-gate vertical transistors 101 connected to the word lines WL; and several memory capacitors 102, with the first end of the memory capacitors 102 connected to the source / drain of the dual-gate vertical transistors 101 and the second end of the memory capacitors 102 grounded.

[0053] As can be seen, the dual-gate vertical transistors 101 in the above scheme are arranged in an array. The density of the dual-gate vertical transistors 101 is relatively large, which leads to increased coupling between adjacent bit lines BL when the dual-gate vertical transistors 101 are working, thereby affecting the storage performance.

[0054] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure. By forming bit lines arranged alternately along the bit line direction and word line direction on the first surface, the coupling effect between adjacent bit lines can be effectively reduced, the storage efficiency of the memory cell can be improved, and the arrangement density is increased compared with the rectangular arrangement of the prior art.

[0055] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] The following example uses the formation of the first character line, combined with... Figures 2 to 27 The formation process of semiconductor structures is explained in detail.

[0057] Please refer to Figure 2 and Figure 3 , Figure 2 It is a top view. Figure 3 yes Figure 2 A cross-sectional view along the AA1 direction is provided, the substrate 200 having a bit line direction Y and a word line direction X arranged perpendicularly, the substrate 200 including a plurality of active regions 201 arranged in parallel along the bit line direction Y and an isolation region located between the active regions 201, and the substrate 200 including a first surface a.

[0058] In this embodiment, the substrate 200 is made of silicon.

[0059] In other embodiments, the substrate 200 may be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate 200 may be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0060] In some embodiments of the present invention, the method of forming the isolation region includes: etching away the substrate 200 between adjacent active regions 201 to form a shallow trench 202.

[0061] Please refer to Figure 4 and Figure 5 , Figure 4 It is a top view. Figure 5 yes Figure 4 A cross-sectional view along the AA1 direction shows that a bit line gate oxide layer 2022 is formed on the surface of the shallow trench 202; an insulating material is filled into the shallow trench 202 to form an isolation layer 2021.

[0062] In this embodiment, the material of the isolation layer 2021 is silicon nitride.

[0063] In this embodiment, the bit line gate oxide layer 2022 is made of silicon dioxide.

[0064] Please refer to Figure 6 and Figure 7 , Figure 6 It is a top view. Figure 7 yes Figure 6 A cross-sectional view along the AA1 direction shows that a photoresist layer (not shown in the figure) is formed on the first surface a; the photoresist layer (not shown in the figure) is exposed and developed to form a photoresist layer 203 with a vertical transistor pattern, the photoresist layer 203 with the vertical transistor pattern being staggered along the bit line direction Y and the word line direction X on the first surface a of the active region 201.

[0065] In this embodiment, the substrate 200 further includes adjacent first region I and second region II arranged along the bit line direction Y.

[0066] The staggered arrangement of the photoresist layer 203 with vertical transistor pattern is characterized as follows: the vertical transistor 204 on the same active region 201 and the bit line 2042 located at the bottom of the vertical transistor 204 are located on the first region I or the second region II; the vertical transistor 204 on the same first region I and the bit line 2042 located at the bottom of the vertical transistor 204 are located on one of the adjacent active regions 201; and the vertical transistor 204 on the same second region II and the bit line 2042 located at the bottom of the vertical transistor 204 are located on one of the adjacent active regions 201.

[0067] In a specific embodiment, Figure 6 The seven photoresist layers 203 with vertical transistor patterns are arranged in a hexagonal pattern on the substrate 200, and Figure 6 The two photoresist layers 203 with vertical transistor patterns on the second region II and the one photoresist layer 203 with vertical transistor patterns on the first region I are arranged in an equilateral triangle.

[0068] The number of photoresist layers 203 with vertical transistor patterns is the same as the number of vertical transistors 204.

[0069] The present invention does not limit the number of photoresist layers 203 with vertical transistor patterns. Other numbers of photoresist layers 203 with vertical transistor patterns are all within the protection scope of the present invention, and the photoresist layers 203 with vertical transistor patterns are arranged in a honeycomb pattern on the substrate 200.

[0070] In this embodiment, the vertical transistor 204 is made of silicon.

[0071] Since the photoresist layer 203 with vertical transistor pattern defines the shape of the vertical transistor 204 on the substrate 200, the shape and arrangement of the subsequently formed vertical transistor 204 are the same as those of the photoresist layer 203 with vertical transistor pattern. Therefore, the photoresist layer 203 with vertical transistor pattern is arranged in an alternating manner on the first surface a of the substrate 200, so that the arrangement of the subsequently formed vertical transistor 204 is also alternating, thereby reducing the coupling effect between adjacent bit lines 2042. Furthermore, the arrangement of the photoresist layer 203 with vertical transistor pattern determines the arrangement of the capacitor, increasing the density of the capacitor arrangement and the capacitance.

[0072] Please refer to Figure 8 , Figure 9 and Figure 10 , Figure 8 It is a top view. Figure 9 yes Figure 8 Cross-sectional view along the AA1 direction. Figure 10 yes Figure 8 A cross-sectional view along the BB1 ​​direction shows that, using the photoresist layer 203 with the vertical transistor pattern as a mask, a portion of the active region 201 and a portion of the isolation region are etched along the first surface a to form a vertical transistor 204 and a bit line 2042 located at the bottom of the vertical transistor 204.

[0073] In some embodiments of the present invention, the etching process for removing the active region 201 and the isolation region is a dry etching process or a wet etching process.

[0074] In this embodiment, the etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

[0075] In this embodiment, a first trench 2041 is provided between adjacent vertical transistors 204.

[0076] The first groove 2041 is used to accommodate the first word line formed subsequently.

[0077] In some embodiments of the present invention, the width of the vertical transistor 204 along the word line direction X ranges from 5 nanometers to 50 nanometers.

[0078] In the above solution, the present invention forms a photoresist layer 203 with a vertical transistor pattern on the first surface a, and the photoresist layer is staggered along the bit line direction Y and the word line direction X on the first surface a of the active region 201. This allows only one of the adjacent active regions 201 to be retained after the subsequent etching process, forming a plurality of discrete vertical transistors 204. This achieves a spacing distribution between the plurality of vertical transistors 204, which can effectively reduce the coupling effect between adjacent bit lines 2042 and improve the storage efficiency of the memory cell. Furthermore, the staggered distribution of the photoresist layer along the bit line direction Y ensures that the vertical transistors 204 are also staggered along the bit line direction Y after the subsequent etching process, which increases the arrangement density compared to the rectangular arrangement of the prior art.

[0079] Please refer to Figure 11 and Figure 12 , Figure 11 View direction and Figure 9 same, Figure 12 View direction and Figure 10 Similarly, a first interlayer dielectric layer 205 is filled into the first trench 2041; the first interlayer dielectric layer 205 is planarized until the top surface of the vertical transistor 204 is exposed.

[0080] In this embodiment, the material of the first interlayer dielectric layer 205 is silicon dioxide.

[0081] In this embodiment, the planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical mechanical polishing, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nanoscale.

[0082] Please refer to Figure 13 and Figure 14 , Figure 13 View direction and Figure 11 same, Figure 14 View direction and Figure 12 Similarly, the first interlayer dielectric layer 205 is etched to form a second trench 2051 located on the first interlayer dielectric layer 205.

[0083] The second groove 2051 is used to accommodate the first word line that is subsequently formed.

[0084] The present invention etches the first interlayer dielectric layer 205 and retains the bottom portion of the first interlayer dielectric layer 205, so that the depth of the subsequently formed first word line can be precisely defined, thereby ensuring the performance of the formed dual-gate vertical transistor.

[0085] Please refer to Figure 15 and Figure 16 , Figure 15 View direction and Figure 13 same, Figure 16 View direction and Figure 14 Similarly, a first annular word line gate oxide layer 2061 is formed on the sidewall surface of the second trench 2051; using an atomic layer deposition process, a first annular word line gate layer 2062 and a third trench 2063 are formed on the bottom surface of the second trench 2051 and the sidewall surface of the first annular word line gate oxide layer 2061.

[0086] In this embodiment, the first annular word line gate oxide layer 2061 surrounds a portion of the vertical transistor 204, and the first annular word line gate layer 2062 surrounds the first annular word line gate oxide layer 2061.

[0087] The third trench 2063 is used to accommodate the subsequently formed insulating layer 2064.

[0088] The material of the first annular word line gate oxide layer 2061 is one of silicon dioxide, nitrogen-doped silicon dioxide, and HK.

[0089] Please refer to Figure 17 and Figure 18 , Figure 17 View direction and Figure 15 same, Figure 18 View direction and Figure 16 Similarly, an insulating layer 2064 is filled into the third trench 2063.

[0090] The first annular word line gate layer 2062, the first annular word line gate oxide layer 2061, and the insulating layer 2064 constitute the first word line 206.

[0091] The insulating layer 2064 is made of silicon dioxide.

[0092] Please refer to Figure 19 and Figure 20 , Figure 19 View direction and Figure 17 same, Figure 20 View direction and Figure 18 Similarly, the top of the first annular word line gate oxide layer 2061, the first annular word line gate layer 2062, and the insulating layer 2064 are etched to form the first word line 206.

[0093] The thickness of the first annular word line gate layer 2062 along the word line direction X ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer 2062 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers.

[0094] The material of the first annular word line gate layer 2062 is one of TIN, a combination of TIN and W, or Mo.

[0095] Wherein, the first annular word line gate oxide layer 2061 and the first annular word line gate layer 2062 are closed rings, wherein the ring is a circular ring, an elliptical ring, a square ring or a polygonal ring.

[0096] In this embodiment, the ring is an elliptical ring.

[0097] In this embodiment, since the first annular word line gate oxide layer 2061 surrounds part of the vertical transistor 204, based on the positional relationship between the first word line 206 and the vertical transistor 204, the device formed by the substrate 200 is determined to be a dual-gate vertical transistor. The gate of the dual-gate vertical transistor is shared with the first word line 206, and the source / drain of the dual-gate vertical transistor is shared with the bit line 2042.

[0098] The present invention etches the top of the first word line 206, so that the depth of the subsequently formed first word line 206 can be precisely defined, thereby ensuring the performance of the formed dual-gate vertical transistor.

[0099] Please refer to Figure 21 and Figure 22 , Figure 21 View direction and Figure 19 same, Figure 22 View direction and Figure 20 Similarly, a second interlayer dielectric layer 207 is formed on top of the first word line 206.

[0100] The second interlayer dielectric layer 207 is flush with the top of the vertical transistor 204.

[0101] The material of the second interlayer dielectric layer 207 is silicon dioxide.

[0102] Please refer to Figure 23 and Figure 24 , Figure 23 It is a top view. Figure 24 yes Figure 23 A cross-sectional view along the BB1 ​​direction shows that a hard mask layer 208 is formed on the substrate 200. Using the hard mask layer 208 as a mask, the second interlayer dielectric layer 207, the first word line 206, and the second word line are etched sequentially until the first interlayer dielectric layer 205 is exposed, forming a plurality of discrete first word lines 206 and a fourth trench 2091, and the plurality of discrete first word lines 206 are arranged along the bit line direction Y.

[0103] The hard mask layer 208 extends along the word line direction X and covers all the vertical transistors 204 along the word line direction X. The hard mask layers 208 are arranged discretely along the bit line direction Y, and the top surface of the second interlayer dielectric layer 207 is exposed between adjacent hard mask layers 208 in the bit line direction Y.

[0104] The present invention forms a hard mask layer 208 and uses the hard mask layer 208 as a mask to etch the second interlayer dielectric layer 207 and the first word line 206 in sequence, so that the first word line 206 is etched apart in the bit line direction Y, thereby making the first word line 206 arranged sequentially in the bit line direction Y. Any first word line 206 can control the opening or closing of a row of memory cells, and adjacent first word lines 206 do not interfere with each other and work independently.

[0105] Please refer to Figure 25 , Figure 25 View direction and Figure 24 Similarly, a third interlayer dielectric layer 209 is filled into the fourth trench 2091, and the third interlayer dielectric layer 209 is flush with the top of the vertical transistor 204.

[0106] The material of the third interlayer dielectric layer 209 is silicon dioxide.

[0107] In other embodiments, after forming the third interlayer dielectric layer, processes such as storage node contact (SNC) and storage node (SN) are also performed.

[0108] Please refer to Figure 26 and Figure 27 , Figure 26 View direction and Figure 21 same, Figure 27 View direction and Figure 25 Similarly, the second surface b of the substrate 200 is thinned, and a portion of the substrate 200 and a portion of the bit line 2042 are etched away to form a plurality of discrete bit lines 2042.

[0109] The substrate 200 includes a second surface b, and the first surface a and the second surface b are two opposite surfaces of the substrate 200.

[0110] This invention thins the second surface b, allowing the thinner wafer to conduct heat away more quickly, preventing chip overheating, improving the wafer's heat dissipation performance, and thus enhancing the reliability and performance of the device.

[0111] The following example uses the formation of the second character line 306, combined with... Figures 28 to 36 The formation process of semiconductor structures is explained in detail.

[0112] Please Figure 13 and Figure 14 Based on reference Figure 28 and Figure 29 , Figure 28 View direction and Figure 13 same, Figure 29 View direction and Figure 14 Similarly, a second annular word line gate oxide layer 3061 is formed on the sidewall surface of the second trench, and the second annular word line gate oxide layer 3061 surrounds a portion of the vertical transistor 204; the second annular word line gate layer 3062 is filled into the second trench using an atomic layer deposition process, or a PVD process, or a CVD process.

[0113] In this embodiment, the second annular word line gate layer 3062 surrounds the second annular word line gate oxide layer 3061, and the second annular word line gate layer 3062 and the second annular word line gate oxide layer 3061 constitute the second word line 306.

[0114] The material of the second annular word line gate oxide layer 3061 is one of silicon dioxide, nitrogen-doped silicon dioxide, and HK.

[0115] The material of the second annular word line gate layer 3062 is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si, or a combination of Mo and Si.

[0116] In one embodiment of the present invention, when the material of the second annular word line gate layer 3062 is TIN, that is, along the word line direction X, the second annular word line gate layer 3062 is filled with TIN material in the second trench. At this time, along the bit line direction Y, the second annular word line gate layer 3062 in the second trench has two filling situations: one is that along the bit line direction Y, the second annular word line gate layer 3062 is filled with TIN material in the second trench; the other is that along the bit line direction Y, a layer of TIN material is deposited on the surface of the second trench.

[0117] In this embodiment, the material of the second annular word line gate layer 3062 formed by atomic layer deposition process is one of TIN, a combination of TIN and W, or Mo.

[0118] Please refer to Figure 30 and Figure 31 , Figure 30 View direction and Figure 28 same, Figure 31 View direction and Figure 29 Similarly, the top of the second annular word line gate oxide layer 3061 and the second annular word line gate layer 3062 are etched to form the second word line 306; and a second interlayer dielectric layer 307 is formed on the top of the second word line 306.

[0119] The second interlayer dielectric layer 307 is flush with the top of the vertical transistor 204.

[0120] The thickness of the second annular word line gate layer 3062 along the word line direction X ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer 3062 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers.

[0121] The second annular word line gate oxide layer 3061 and the second annular word line gate layer 3062 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring or a polygonal annular ring.

[0122] In this embodiment, since the second annular word line gate oxide layer 3061 surrounds part of the vertical transistor 204, based on the positional relationship between the second word line 306 and the vertical transistor 204, the device formed by the substrate 200 is determined to be a dual-gate vertical transistor. The gate of the dual-gate vertical transistor is shared with the first word line, and the source / drain of the dual-gate vertical transistor is shared with the bit line 2042.

[0123] This invention etches the top of the second word line 306, so that the depth of the subsequently formed second word line 306 can be precisely defined, thereby ensuring the performance of the formed dual-gate vertical transistor.

[0124] In another embodiment, please refer to Figure 32 and Figure 33 , Figure 32 The direction of the diagram and Figure 30 Consistent Figure 33 The direction of the diagram and Figure 31 Consistent, when the material of the second annular word line gate layer is TIN and Si, that is, when the second annular word line gate layer includes a silicon layer 3102 and titanium nitride layers 3101 located on the upper and lower surfaces of the silicon layer 3102, the second word line 310 is a composite structure, and the structure of the second word line 306 is a sandwich structure.

[0125] In this embodiment, the material of the second annular word line gate layer formed by PVD or CVD process is one of the following: a combination of TIN and Si, or a combination of Mo and Si.

[0126] In this embodiment, the method for forming the second annular word line gate layer includes: using PVD or CVD process, sequentially depositing a titanium nitride layer 3101, a silicon layer 3102, and a titanium nitride layer 3101 along a direction perpendicular to the substrate.

[0127] In this embodiment, a second interlayer dielectric layer 307 is also included on the titanium nitride layer 3101.

[0128] In specific embodiments, the subsequent process steps are the same whether the material of the second annular word line gate layer is TIN material or the second annular word line gate layer is a composite structure. The following scheme is described with the material of the second annular word line gate layer being TIN material as an example. The process steps of the second annular word line gate layer being a composite structure will not be repeated here.

[0129] Please refer to Figure 34 and Figure 35 , Figure 34 It is a top view. Figure 35 yes Figure 34 A cross-sectional view along the BB1 ​​direction shows that a hard mask layer 308 is formed on the substrate 200; using the hard mask layer 308 as a mask, the second interlayer dielectric layer 307 and the second word line 306 are etched sequentially until the first interlayer dielectric layer 205 is exposed, forming a plurality of discrete second word lines 306 and a fourth trench 3091, and the plurality of discrete second word lines 306 are arranged along the bit line direction Y.

[0130] The hard mask layer 308 extends along the word line direction X and covers all the vertical transistors 204 along the word line direction X. The hard mask layers 308 are arranged discretely along the bit line direction Y, and a portion of the top surface of the second interlayer dielectric layer 307 is exposed between adjacent hard mask layers 308 in the bit line direction Y.

[0131] The present invention forms a hard mask layer 308 and uses the hard mask layer 308 as a mask to etch the second interlayer dielectric layer 307 and the second word line 306 in sequence, so that the second word line 306 is separated in the bit line direction Y, thereby making the second word line 306 arranged sequentially in the bit line direction Y. Any second word line 306 can control the opening or closing of a row of memory cells, and adjacent second word lines 306 do not interfere with each other and work independently.

[0132] Please refer to Figure 36 , Figure 36 View direction and Figure 33 Similarly, a third interlayer dielectric layer 309 is filled into the fourth trench 3091, and the third interlayer dielectric layer 309 is flush with the top of the vertical transistor 204.

[0133] The material of the third interlayer dielectric layer 309 is silicon dioxide.

[0134] In other embodiments, after forming the third dielectric layer, processes such as storage node contact (SNC) and storage node (SN) are also performed.

[0135] Please refer to Figure 37 and Figure 38 , Figure 37 View direction and Figure 30 same, Figure 38 View direction and Figure 36 Similarly, the second surface b of the substrate 200 is thinned, and a portion of the substrate 200 and a portion of the bit line 2042 are etched away to form a plurality of discrete bit lines 2042.

[0136] The substrate 200 includes a second surface b, and the first surface a and the second surface b are two opposite surfaces of the substrate 200.

[0137] This invention thins the second surface b, allowing the thinner wafer to conduct heat away more quickly, preventing chip overheating, improving the wafer's heat dissipation performance, and thus enhancing the reliability and performance of the device.

[0138] In the above scheme, the present invention forms a first word line and a second word line 306 by filling the trench between adjacent vertical transistors 204, and the first word line and the second word line 306 have different structures, thereby achieving process diversity of word lines.

[0139] The following example uses the formation of the third line 408, combined with... Figures 37 to 49 The formation process of semiconductor structures is explained in detail.

[0140] Please Figure 11 and Figure 12 Based on reference Figure 39 , Figure 40 and Figure 41 , Figure 39 It is a top view. Figure 40 yes Figure 39 Cross-sectional view along the AA1 direction. Figure 41 yes Figure 40 A cross-sectional view along the BB1 ​​direction shows a hard mask layer 406 formed on the substrate 200; the first interlayer dielectric layer 205 is etched using the hard mask layer 406 as a mask to form a discrete first interlayer dielectric layer 205 and a second trench 4071; the hard mask layer 406 is then removed.

[0141] The second trench 4071 is located between the adjacent first interlayer dielectric layer 205 and the vertical transistor 204.

[0142] The hard mask layer 406 extends along the word line direction X and covers the vertical transistor 204 along the word line direction X. The hard mask layers 406 are arranged discretely along the bit line direction Y, and a portion of the top surface of the first interlayer dielectric layer 205 is exposed between adjacent hard mask layers 406 in the bit line direction Y.

[0143] The present invention forms a hard mask layer 406 on the substrate 200 before forming the third word line 408, and defines the shape of the third word line 408 through the hard mask layer 406. This eliminates the need to etch the third word line 408 along the bit line direction Y, thus forming the third word line 408 discretely arranged along the bit line direction Y. This simplifies the process steps and increases the diversity of process steps.

[0144] Specifically, compared to the structure of the first word line and the second word line, the third word line 408 structure in this solution does not require etching along the bit line direction Y to achieve the sequential arrangement of the third word line 408 in the bit line direction Y. Any third word line 408 can control the opening or closing of a row of memory cells, and adjacent third word lines 408 do not interfere with each other and work independently.

[0145] Please refer to Figure 42 , Figure 43 and Figure 44 , Figure 42 It is a top view. Figure 43 yes Figure 42 Cross-sectional view along the AA1 direction. Figure 44 yes Figure 42 A cross-sectional view along the BB1 ​​direction shows that an initial first word line gate oxide layer (not shown) and an initial first word line gate layer (not shown) are formed on the surface of the second trench 4071 using an atomic layer deposition process. The initial first word line gate oxide layer and the initial first word line gate layer are then removed using a dry etching process to form a first word line gate oxide layer 4081 on the sidewall surface of the second trench 4071 and a first word line gate layer 4082 on the sidewall surface of the first word line gate oxide layer 4081. The first word line gate layer 4082 spans the substrate 200 along the word line direction X.

[0146] The first word line gate layer 4082 and the first word line gate oxide layer 4081 constitute the third word line 408.

[0147] The third character lines 408 are arranged separately along the Y direction of the position line, and the second groove 4071 is between adjacent third character lines 408.

[0148] The material of the first word line gate layer 4082 is one of TIN, a combination of TIN and W, or Mo.

[0149] The material of the first word line gate oxide layer 4081 is one of silicon dioxide, nitrogen-doped silicon dioxide, or HK.

[0150] Please refer to Figure 43 , Figure 43 View direction and Figure 42 Similarly, a second interlayer dielectric layer 407 is filled into the second trench 4071, and the top of the second interlayer dielectric layer 407 is flush with the vertical transistor 204.

[0151] The material of the second interlayer dielectric layer 407 is silicon dioxide.

[0152] Please refer to Figure 46 and Figure 47 , Figure 46 View direction and Figure 43 same, Figure 47 View direction and Figure 45 Similarly, the top of the first word line gate oxide layer 4081, the first word line gate layer 4082, the first interlayer dielectric layer 205, and the second interlayer dielectric layer 407 are etched to form the third word line 408.

[0153] The width of the first word line gate oxide layer 4081 along the word line direction X ranges from 1 nanometer to 15 nanometers, the thickness of the first word line gate layer 4082 along the bit line direction Y ranges from 1 to 10 nanometers, and the depth of the first word line gate layer 4082 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers.

[0154] This invention etches the top of the third word line 408, so that the depth of the subsequently formed third word line 408 can be precisely defined, thereby ensuring the performance of the formed dual-gate vertical transistor.

[0155] Please refer to Figure 48 and Figure 49 , Figure 48 View direction and Figure 46 same, Figure 49 View direction and Figure 47 Similarly, a third interlayer dielectric layer 409 is formed on top of the third word line 408, and the third interlayer dielectric layer 409 is flush with the top of the vertical transistor 204.

[0156] The material of the third interlayer dielectric layer 409 is silicon dioxide.

[0157] In other embodiments, after forming the third interlayer dielectric layer 409, processes such as storage node contact SNC and storage node SN are also performed.

[0158] Please refer to Figure 50 and Figure 51 , Figure 50 View direction and Figure 48 same, Figure 51 View direction and Figure 49 Similarly, the second surface of the substrate 200 is thinned, and a portion of the substrate 200 and a portion of the bit lines 2042 are etched away to form a plurality of discrete bit lines 2042.

[0159] This invention thins the second surface b, allowing the thinner wafer to conduct heat away more quickly, preventing chip overheating, improving the wafer's heat dissipation performance, and thus enhancing the reliability and performance of the device.

[0160] The following example uses the formation of the fourth word line 508 and the first vertical transistor 506 as an example, combined with... Figures 50 to 67 The formation process of semiconductor structures is explained in detail.

[0161] Please Figure 11 and Figure 12 Based on reference Figure 52 and Figure 53 , Figure 52 View direction and Figure 11 same, Figure 53View direction and Figure 12 Similarly, a dry etching process with etching selectivity is used to sequentially etch the vertical transistor 204 and the isolation regions located on both sides of the vertical transistor 204 to form the second trench 5061.

[0162] Because the dry etching process has a certain etching selectivity, it can remove vertical transistors without damaging the interlayer dielectric layer on the substrate, thus saving the number of photomask layers.

[0163] In this embodiment, the etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

[0164] The second trench 5061 is used to accommodate the subsequently formed first vertical transistor 506.

[0165] Please refer to Figure 54 , Figure 55 and Figure 56 , Figure 54 It is a top view. Figure 55 yes Figure 54 Cross-sectional view along the AA1 direction. Figure 56 yes Figure 54 A cross-sectional view along the BB1 ​​direction shows that an epitaxial growth process is used to form a first vertical transistor 506 within the second trench 5061.

[0166] The width of the first vertical transistor 506 along the word line direction X ranges from 15 nanometers to 100 nanometers.

[0167] The present invention removes part of the vertical transistor 204 and the isolation regions located on both sides of the vertical transistor 204 by etching, and forms the first vertical transistor 506 in the trench formed by etching, thereby increasing the width of the first vertical transistor 506, increasing the support performance of the first vertical transistor 506, and increasing the stability of the structure.

[0168] Please refer to Figure 57 , Figure 58 and Figure 59 , Figure 57 It is a top view. Figure 58 yes Figure 57 Cross-sectional view along the AA1 direction. Figure 59 yes Figure 57A cross-sectional view along the BB1 ​​direction shows a hard mask layer 507 formed on the substrate 200; the first interlayer dielectric layer 205 is etched using the hard mask layer 507 as a mask to form a discrete first interlayer dielectric layer 205 and a third trench 5081, the third trench 5081 being located between adjacent first interlayer dielectric layers 205 and the first vertical transistor 506.

[0169] The hard mask layer 507 extends along the word line direction X and covers the first vertical transistor 506 along the word line direction X. The hard mask layers 507 are arranged discretely along the bit line direction Y, and a portion of the top surface of the first interlayer dielectric layer 205 is exposed between adjacent hard mask layers 507 in the bit line direction Y.

[0170] The present invention forms a hard mask layer 507 on the substrate 200 before forming the fourth word line 508, and defines the shape of the fourth word line 508 through the hard mask layer 507. This eliminates the need to etch the fourth word line 508 along the bit line direction Y, thus forming the fourth word line 508 discretely arranged along the bit line direction Y. This simplifies the process steps and increases the diversity of process steps.

[0171] Specifically, compared to the structure of the first word line and the second word line, the fourth word line 508 structure in this solution does not require etching along the bit line direction Y of the fourth word line 508. The fourth word line 508 can be arranged sequentially in the bit line direction Y. Any fourth word line 508 can control the opening or closing of a row of memory cells, and adjacent fourth word lines 508 do not interfere with each other and work independently.

[0172] Please refer to Figure 60 , Figure 61 and Figure 62 , Figure 60 It is a top view. Figure 61 yes Figure 60 Cross-sectional view along the AA1 direction. Figure 62 yes Figure 60 A cross-sectional view along the BB1 ​​direction shows that an initial second word line gate oxide layer (not shown in the figure) and an initial second word line gate layer (not shown in the figure) are formed on the surface of the third trench 5081 using an atomic layer deposition process. The initial second word line gate oxide layer and the initial second word line gate layer on the bottom surface of the third trench 5081 are removed using a dry etching process to form a second word line gate oxide layer 5082 on the sidewall surface of the third trench 5081 and a second word line gate layer 5083 on the sidewall surface of the second word line gate oxide layer 5082.

[0173] The second word line gate layer 5083 extends across the substrate 200 along the word line direction X, and the second word line gate layer 5083 and the second word line gate oxide layer 5082 constitute the fourth word line 508.

[0174] The fourth character line 508 is arranged separately along the Y direction of the position line, and the third groove 5081 is between adjacent fourth character lines 508.

[0175] The material of the second word line gate layer 5083 is one of TIN, a combination of TIN and W, or Mo.

[0176] The material of the second word line gate oxide layer 5082 is one of silicon dioxide, nitrogen-doped silicon dioxide, or HK.

[0177] Please refer to Figure 63 , Figure 63 View direction and Figure 62 Similarly, a second interlayer dielectric layer 509 is filled into the third trench 5081, and the top of the second interlayer dielectric layer 509 is flush with the first vertical transistor 506.

[0178] The material of the second interlayer dielectric layer 509 is silicon dioxide.

[0179] Please refer to Figure 64 and Figure 65 , Figure 64 View direction and Figure 61 same, Figure 65 View direction and Figure 63 Similarly, the top of the second word line gate oxide layer 5082, the second word line gate layer 5083, and the second interlayer dielectric layer 509 are etched to form the fourth word line 508.

[0180] The width of the second word line gate oxide layer 5082 along the word line direction X ranges from 1 nanometer to 15 nanometers, the thickness of the second word line gate layer 5083 along the bit line direction Y ranges from 1 nanometer to 10 nanometers, and the depth of the second word line gate layer 5083 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers.

[0181] This invention etches the top of the fourth word line 508, so that the depth of the subsequently formed fourth word line 508 can be precisely defined, thereby ensuring the performance of the formed dual-gate vertical transistor.

[0182] Please refer to Figure 66 and Figure 67 , Figure 66 View direction and Figure 64 same, Figure 67 View direction and Figure 65Similarly, a third interlayer dielectric layer 510 is formed on top of the fourth word line 508, and the third interlayer dielectric layer 510 is flush with the top of the first vertical transistor 506.

[0183] The material of the third interlayer dielectric layer 510 is silicon dioxide.

[0184] In other embodiments, after forming the third interlayer dielectric layer, processes such as storage node contact (SNC) and storage node (SN) are also performed.

[0185] Please refer to Figure 68 and Figure 69 , Figure 68 View direction and Figure 66 same, Figure 69 View direction and Figure 67 Similarly, the second surface of the substrate 200 is thinned, and a portion of the substrate 200 and a portion of the first vertical transistor 506 are etched away to form a plurality of discrete first vertical transistors 506.

[0186] This invention thins the second surface b, allowing the thinner wafer to conduct heat away more quickly, preventing chip overheating, improving the wafer's heat dissipation performance, and thus enhancing the reliability and performance of the device.

[0187] Accordingly, please refer to Figure 9 The present invention also provides a semiconductor structure, comprising: a substrate 200 having a bit line direction Y and a word line direction X arranged perpendicularly, the substrate 200 including a plurality of active regions 201 arranged in parallel along the bit line direction Y and an isolation region located between the active regions 201, and the substrate 200 including a first surface a; a vertical transistor 204 formed on the first surface a of the active regions 201 that are staggered in the bit line direction Y and the word line direction X; and a bit line located at the bottom of the vertical transistor.

[0188] In this embodiment, the active region 201 includes adjacent first region I and second region II arranged along the bit line direction Y; the vertical transistor 204 on the same active region 201 and the bit line 2042 located at the bottom of the vertical transistor 204 are located on the first region I or the second region II; the vertical transistor 204 on the same first region I and the bit line 2042 located at the bottom of the vertical transistor 204 are located on one of the adjacent active regions 201; the vertical transistor 204 on the same second region II and the bit line 2042 located at the bottom of the vertical transistor 204 are located on one of the adjacent active regions 201.

[0189] In this embodiment, the semiconductor structure further includes: a first word line 206, which is discretely arranged along the bit line direction Y. The first word line 206 includes: a first annular word line gate oxide layer 2061, a first annular word line gate layer 2062, and an insulating layer 2064. The first annular word line gate oxide layer 2061 surrounds a portion of the vertical transistor 204 and is located on the sidewall surface of the vertical transistor 204 and the surface of the substrate 200. The first annular word line gate layer 2062 surrounds the first annular word line gate oxide layer 2061. The insulating layer 2064 is located in a third trench 2063 between adjacent first annular word line gate layers 2062.

[0190] In this embodiment, the semiconductor structure further includes: a first interlayer dielectric layer 205, a second interlayer dielectric layer 207, and a third interlayer dielectric layer 209. The first word lines 206 are located within a first trench 2041 between adjacent vertical transistors 204. The first interlayer dielectric layer 205 is located at the bottom of the first word lines 206, the second interlayer dielectric layer 207 is located at the top of the first word lines 206, and the third interlayer dielectric layer 209 is located within the first word lines 206 and the second interlayer dielectric layer 207.

[0191] In this embodiment, the thickness of the first annular word line gate layer 2062 along the word line direction X ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer 2062 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers. The material of the first annular word line gate layer 2062 is one of TIN, a combination of TIN and W, or Mo. The first annular word line gate oxide layer 2061 and the first annular word line gate layer 2062 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

[0192] In this embodiment, the semiconductor structure further includes a second word line 306, which is discretely arranged along the bit line direction Y. The second word line 306 includes a second annular word line gate oxide layer 3061 and a second annular word line gate layer 3062. The second annular word line gate oxide layer 3061 surrounds a portion of the vertical transistor 204 and is located on the sidewall surface of the vertical transistor 204 and the surface of the substrate 200. The second annular word line gate layer 3062 surrounds the second annular word line gate oxide layer 3061 and fills the second trench between adjacent second annular word line gate oxide layers 3061.

[0193] In this embodiment, the semiconductor structure further includes: a first interlayer dielectric layer 205, a second interlayer dielectric layer 307, and a third interlayer dielectric layer 309. The second word lines 306 are located within a first trench 2041 between adjacent vertical transistors 204. The first interlayer dielectric layer 205 is located at the bottom of the second word lines 306, the second interlayer dielectric layer 307 is located at the top of the second word lines 306, and the third interlayer dielectric layer 309 is located within the second word lines 306 and the second interlayer dielectric layer 307.

[0194] In this embodiment, the thickness of the second annular word line gate layer 3062 along the word line direction X ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer 3062 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer 3062 is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si, or a combination of Mo and Si. The second annular word line gate oxide layer 3061 and the second annular word line gate layer 3062 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

[0195] In this embodiment, the semiconductor structure further includes a third word line 408, which is discretely arranged along the bit line direction Y. The third word line 408 includes a first word line gate oxide layer 4081 and a first word line gate layer 4082. The first word line gate oxide layer 4081 is located on the sidewall surface adjacent to the vertical transistor 204, and the first word line gate layer 4082 is located on the sidewall surface of the first word line gate oxide layer 4081. The first word line gate layer 4082 spans the substrate 200 along the word line direction X.

[0196] In this embodiment, the semiconductor structure further includes: a first interlayer dielectric layer 205, a second interlayer dielectric layer 407, and a third interlayer dielectric layer 409. The first interlayer dielectric layer 205 is located on the substrate 200, and a portion of the first interlayer dielectric layer 205 is located between adjacent first word line gate oxide layers 4081. The second interlayer dielectric layer 407 is located between the first interlayer dielectric layer 205 and the vertical transistor 204. The third interlayer dielectric layer 409 is located on top of the first interlayer dielectric layer 205 and on top of the third word line 408, and the third interlayer dielectric layer 409 is flush with the top of the vertical transistor 204.

[0197] In this embodiment, the width of the first word line gate oxide layer 4081 along the word line direction X ranges from 1 nanometer to 15 nanometers, the thickness of the first word line gate layer 4082 along the bit line direction Y ranges from 1 nanometer to 10 nanometers, the depth of the first word line gate layer 4082 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers, and the material of the first word line gate layer 4082 is one of TIN, a combination of TIN and W, or Mo.

[0198] In this embodiment, the semiconductor structure further includes: a first vertical transistor 506, which is discretely located on the substrate 200, and the width range of the first vertical transistor 506 along the word line direction X is [value missing].

[0199] In this embodiment, the semiconductor structure further includes a fourth word line 508, which is discretely arranged along the bit line direction Y. The fourth word line 508 includes a second word line gate oxide layer 5082 and a second word line gate layer 5083. The second word line gate oxide layer 5082 is located on the sidewall surface adjacent to the first vertical transistor 506 and part of the isolation region surface. The second word line gate layer 5083 is located on the sidewall surface of the second word line gate oxide layer 5082 and spans the substrate 200 along the word line direction X.

[0200] In this embodiment, the width of the second word line gate oxide layer 5082 along the word line direction X ranges from 1 nanometer to 15 nanometers, the thickness of the second word line gate layer 5083 along the bit line direction Y ranges from 1 nanometer to 10 nanometers, the depth of the second word line gate layer 5083 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers, and the material of the second word line gate layer 5083 is one of TIN, a combination of TIN and W, or Mo.

[0201] In summary, the bit lines in the technical solution of this invention are staggered along the bit line direction and word line direction on the first surface of the active region, realizing the spacing distribution between several bit lines, which can effectively reduce the coupling effect between adjacent bit lines and improve the storage efficiency of the memory cell; and it increases the arrangement density compared with the rectangular arrangement of the prior art.

[0202] Accordingly, please refer to Figure 70The present invention also provides a memory array, comprising: a plurality of bit lines arranged along the word line direction X; a plurality of word lines arranged along the bit line direction Y, wherein the bit lines intersect with the word lines in a grid-like arrangement; a plurality of dual-gate vertical transistors 601, wherein the dual-gate vertical transistors 601 are arranged in an array at intervals in the grid formed by the intersection of the bit lines and the word lines, wherein in any row of grids formed by the intersection of a word line and the bit lines, the dual-gate vertical transistors 601 are located in one of two adjacent grids, and in any column of grids formed by the intersection of a bit line and the word lines, the dual-gate vertical transistors 601 are located in one of two adjacent grids, wherein the source / drain of the dual-gate vertical transistors 601 is connected to the bit lines, and the gate of the dual-gate vertical transistors 601 is connected to the word lines; and a plurality of memory capacitors 602, wherein the first end of the memory capacitors 602 is connected to the source / drain of the dual-gate vertical transistors 601, and the second end of the memory capacitors 602 is grounded.

[0203] In a specific embodiment, the memory array consists of a first word line WL0, a second word line WL1, a third word line WL2, a fourth word line WL3, a fifth word line WL4, a first bit line BL0, a second bit line BL1, a third bit line BL2, a fourth bit line BL3, a fifth bit line BL4, and a plurality of dual-gate vertical transistors 601 and memory capacitors 602.

[0204] Depend on Figure 70 It can be seen that in the first row of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the first bit line BL0 and the third bit line BL2; in the second row of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the second bit line BL1 and the fourth bit line BL3; in the third row of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the first bit line BL0 and the third bit line BL2; and in the fourth row of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the second bit line BL1 and the fourth bit line BL3.

[0205] In the first column of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the first word line WL0 and the third word line WL2. In the second column of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the second word line WL1 and the fourth word line WL3. In the third column of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the first word line WL0 and the third word line WL2. In the fourth column of the memory array, the plurality of dual-gate vertical transistors 601 are connected to the second word line WL1 and the fourth word line WL3.

[0206] The working principle of the above-mentioned memory array is as follows: an enable voltage is applied to any of the word lines, which selects the dual-gate vertical transistor on the word line. Then, an operating voltage is applied to the bit line connected to the dual-gate vertical transistor 601, and a default voltage (e.g., VCC / 2) is applied to the bit lines not connected to the dual-gate vertical transistor 601, so that the adjacent bit lines play a shielding role and greatly reduce the coupling between adjacent bit lines.

[0207] In a specific embodiment, an enable voltage is applied to the first word line WL0, and an operating voltage is applied to the first bit line BL0 and the third bit line BL2 to perform storage or read operations on the dual-gate vertical transistor 601.

[0208] In a specific embodiment, an enable voltage is applied to the second word line WL1, and an operating voltage is applied to the second bit line BL1 and the fourth bit line BL3 to perform storage or read operations on the dual-gate vertical transistor 601.

[0209] In a specific embodiment, an enable voltage is applied to the third word line WL2, and an operating voltage is applied to the first bit line BL0 and the third bit line BL2 to perform storage or read operations on the dual-gate vertical transistor 601.

[0210] In a specific embodiment, an enable voltage is applied to the fourth word line WL3, and an operating voltage is applied to the second bit line BL1 and the fourth bit line BL3 to perform storage or read operations on the dual-gate vertical transistor 601.

[0211] As can be seen, in the above-mentioned storage array, the bit lines are arranged in an alternating pattern, which achieves a shielding effect between adjacent bit lines and greatly reduces the coupling between adjacent bit lines.

[0212] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a bit line direction and a word line direction arranged in a perpendicular cross configuration, the substrate including a plurality of active regions arranged in parallel along the bit line direction and an isolation region located between the active regions, and the substrate including a first surface. A photoresist layer is formed on the first surface; The photoresist layer is exposed and developed to form a photoresist layer with a vertical transistor pattern, wherein the photoresist layer with the vertical transistor pattern is staggered along the bit line direction and word line direction on the first surface of the active region. Using the photoresist layer with the vertical transistor pattern as a mask, a portion of the active region and a portion of the isolation region are etched along the first surface to form a vertical transistor and a bit line located at the bottom of the vertical transistor.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes adjacent first and second regions arranged along the bit line direction; The vertical transistors on the same active region and the bit lines located at the bottom of the vertical transistors are located on the first region or the second region. The vertical transistors on the same first region and the bit lines located at the bottom of the vertical transistors are located on one of the adjacent active regions. The vertical transistors on the same second region and the bit lines located at the bottom of the vertical transistors are located on one of the adjacent active regions.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for removing the active region and the isolation region is either a dry etching process or a wet etching process.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, A first trench exists between adjacent vertical transistors; After the step of forming the vertical transistor, the following is included: Fill the first trench with a first interlayer dielectric layer; The first interlayer dielectric layer is planarized until the top surface of the vertical transistor is exposed; Continue etching the first interlayer dielectric layer to form a second trench located on the first interlayer dielectric layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, After the step of forming the second trench located on the first interlayer dielectric layer, the following steps are included: A first annular word line gate oxide layer is formed on the sidewall surface of the second trench, the first annular word line gate oxide layer surrounding a portion of the vertical transistor; Using atomic layer deposition (ALD) technology, a first annular word line gate layer and a third trench are formed on the bottom surface of the second trench and the sidewall surface of the first annular word line gate oxide layer, wherein the first annular word line gate layer surrounds the first annular word line gate oxide layer. An insulating layer is filled into the third trench, and the first annular word line gate layer, the first annular word line gate oxide layer and the insulating layer constitute the first word line; The top of the first annular word line gate layer and the insulating layer are etched to form the first word line.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo. The first annular word line gate oxide layer and the first annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

8. The method for forming a semiconductor structure as described in claim 5, characterized in that, After the step of forming the second trench located on the first interlayer dielectric layer, the following steps are included: A second annular word line gate oxide layer is formed on the sidewall surface of the second trench, the second annular word line gate oxide layer surrounding a portion of the vertical transistor; A second annular word line gate layer is filled into the second trench using atomic layer deposition, PVD, or CVD processes. The second annular word line gate layer surrounds the second annular word line gate oxide layer, and the second annular word line gate layer and the second annular word line gate oxide layer constitute the second word line. The second annular word line gate oxide layer and the top of the second annular word line gate layer are etched to form the second word line.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or a combination of TIN and Si, or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

10. The method for forming a semiconductor structure as described in claim 6 or 8, characterized in that, The substrate includes a second surface, and the first surface and the second surface are two opposite surfaces of the substrate; After the first and second letter lines are formed, the following is also included: A second interlayer dielectric layer is formed on top of the first word line and the second word line, and the second interlayer dielectric layer is flush with the top of the vertical transistor; A hard mask layer is formed on the substrate, the hard mask layer extends along the word line direction and covers all the vertical transistors along the word line direction, the hard mask layers are discretely arranged along the bit line direction, and a portion of the top surface of the second interlayer dielectric layer is exposed between adjacent hard mask layers in the bit line direction. Using the hard mask layer as a mask, the second interlayer dielectric layer and the first word line and the second word line are etched sequentially until the first interlayer dielectric layer is exposed, forming a plurality of discrete first word lines, second word lines and a fourth trench, and the plurality of discrete first word lines and second word lines are arranged along the bit line direction; A third interlayer dielectric layer is filled into the fourth trench, and the third interlayer dielectric layer is flush with the top of the vertical transistor; The second surface of the substrate is thinned, and a portion of the substrate and a portion of the bit lines are etched away to form a plurality of discrete bit lines.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, A first trench exists between adjacent vertical transistors; After the step of forming the vertical transistor, the following is included: Fill the first trench with a first interlayer dielectric layer; The first interlayer dielectric layer is planarized until the top surface of the vertical transistor is exposed; A hard mask layer is formed on the substrate, the hard mask layer extends along the word line direction and covers the vertical transistor along the word line direction, the hard mask layers are discretely arranged along the bit line direction, and a portion of the top surface of the first interlayer dielectric layer is exposed between adjacent hard mask layers in the bit line direction. The first interlayer dielectric layer is etched using the hard mask layer as a mask to form a discrete first interlayer dielectric layer and a second trench, wherein the second trench is located between an adjacent first interlayer dielectric layer and the vertical transistor. Remove the hard mask layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, After the step of forming the discrete first interlayer dielectric layer and second trench, the method includes: An initial first word line gate oxide layer and an initial first word line gate layer located on the surface of the initial first word line gate oxide layer are formed on the surface of the second trench using an atomic layer deposition process. The initial first word line gate oxide layer and the initial first word line gate layer on the bottom surface of the second trench are removed by a dry etching process to form a first word line gate oxide layer on the sidewall surface of the second trench and a first word line gate layer on the sidewall surface of the first word line gate oxide layer. The first word line gate layer spans the substrate along the word line direction. The first word line gate layer and the first word line gate oxide layer constitute a third word line. The third word lines are arranged separately along the bit line direction, and the second trench is between adjacent third word lines. A second interlayer dielectric layer is filled into the second trench, and the top of the second interlayer dielectric layer is flush with the vertical transistor. The top of the first word line gate oxide layer, the first word line gate layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are etched to form the third word line.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The width of the first word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the first word line gate layer along the bit line direction ranges from 1 to 10 nanometers, the depth of the first word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the first word line gate layer is one of TIN, a combination of TIN and W, or Mo.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the third digit, the process also includes: A third interlayer dielectric layer is formed at the top of the third word line, and the third interlayer dielectric layer is flush with the top of the vertical transistor; The second surface of the substrate is thinned, and a portion of the substrate and a portion of the bit lines are etched away to form a plurality of discrete bit lines.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, A first trench exists between adjacent vertical transistors; After the step of forming the vertical transistor, the following is included: Fill the first trench with a first interlayer dielectric layer; The first interlayer dielectric layer is planarized until the top surface of the vertical transistor is exposed; A dry etching process with etching selectivity is used to sequentially etch the vertical transistor and the isolation regions located on both sides of the vertical transistor to form a second trench; A first vertical transistor is formed in the second trench using an epitaxial growth process; A hard mask layer is formed on the substrate, the hard mask layer extends along the word line direction and covers the first vertical transistor along the word line direction, the hard mask layers are discretely arranged along the bit line direction, and a portion of the top surface of the first interlayer dielectric layer is exposed between adjacent hard mask layers in the bit line direction. The first interlayer dielectric layer is etched using the hard mask layer as a mask to form a discrete first interlayer dielectric layer and a third trench, wherein the third trench is located between an adjacent first interlayer dielectric layer and the first vertical transistor. Remove the hard mask layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The etching process for the vertical transistor and the active regions located on both sides of the vertical transistor is dry etching or wet etching, and the width of the first vertical transistor along the word line direction ranges from 15 nanometers to 100 nanometers.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, After the step of forming the discrete first interlayer dielectric layer and the third trench, the method includes: An initial second word line gate oxide layer and an initial second word line gate layer located on the surface of the initial second word line gate oxide layer are formed on the surface of the third trench using an atomic layer deposition process. The initial second word line gate oxide layer and the initial second word line gate layer on the bottom surface of the third trench are removed by a dry etching process to form a second word line gate oxide layer on the sidewall surface of the third trench and a second word line gate layer on the sidewall surface of the second word line gate oxide layer. The second word line gate layer spans the substrate along the word line direction. The second word line gate layer and the second word line gate oxide layer constitute a fourth word line. The fourth word lines are arranged separately along the bit line direction, and the third trench is between adjacent fourth word lines. A second interlayer dielectric layer is filled into the third trench, and the top of the second interlayer dielectric layer is flush with the first vertical transistor. The top of the second word line gate oxide layer, the second word line gate layer, and the second interlayer dielectric layer are etched to form the fourth word line.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The width of the second word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the second word line gate layer along the bit line direction ranges from 1 nanometer to 10 nanometers, the depth of the second word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the second word line gate layer is one of TIN, a combination of TIN and W, or Mo.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, After forming the fourth letter line, the process also includes: A third interlayer dielectric layer is formed at the top of the fourth word line, and the third interlayer dielectric layer is flush with the top of the first vertical transistor; The second surface of the substrate is thinned, and a portion of the substrate and a portion of the bit lines are etched away to form a plurality of discrete bit lines.

20. A semiconductor structure, characterized in that, include: A substrate having a bit line direction and a word line direction arranged in a perpendicular cross configuration, the substrate including a plurality of active regions arranged in parallel along the bit line direction and an isolation region located between the active regions, and the substrate including a first surface. A vertical transistor is formed on the first surface of an active region that is alternately spaced in the bit line direction and word line direction; Bit lines are located at the bottom of the vertical transistor.

21. The semiconductor structure as claimed in claim 20, characterized in that, The active region includes adjacent first and second regions arranged along the bit line direction; The vertical transistors on the same active region and the bit lines located at the bottom of the vertical transistors are located on the first region or the second region. The vertical transistors on the same first region and the bit lines located at the bottom of the vertical transistors are located on one of the adjacent active regions. The vertical transistors on the same second region and the bit lines located at the bottom of the vertical transistors are located on one of the adjacent active regions.

22. The semiconductor structure as claimed in claim 20, characterized in that, Also includes: The first word line is discretely arranged along the bit line direction. The first word line includes: a first annular word line gate oxide layer, a first annular word line gate layer, and an insulating layer. The first annular word line gate oxide layer surrounds a portion of the vertical transistor, and the first annular word line gate oxide layer is located on the sidewall surface of the vertical transistor and the substrate surface. The first annular word line gate layer surrounds the first annular word line gate oxide layer. The insulating layer is located in a third trench between adjacent first annular word line gate layers.

23. The semiconductor structure as described in claim 22, characterized in that, It also includes a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer, wherein the first word lines are located in a first trench between adjacent vertical transistors, the first interlayer dielectric layer is located at the bottom of the first word lines, the second interlayer dielectric layer is located at the top of the first word lines, and the third interlayer dielectric layer is located within the first word lines and the second interlayer dielectric layer.

24. The semiconductor structure as claimed in claim 23, characterized in that, The thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo. The first annular word line gate oxide layer and the first annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

25. The semiconductor structure as claimed in claim 20, characterized in that, Also includes: The second word line is discretely arranged along the bit line direction. The second word line includes a second annular word line gate oxide layer and a second annular word line gate layer. The second annular word line gate oxide layer surrounds a portion of the vertical transistor and is located on the sidewall surface of the vertical transistor and the substrate surface. The second annular word line gate layer surrounds the second annular word line gate oxide layer and fills the second trench between adjacent second annular word line gate oxide layers.

26. The semiconductor structure as described in claim 25, characterized in that, It also includes a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer, wherein the second word lines are located in a first trench between adjacent vertical transistors, the first interlayer dielectric layer is located at the bottom of the second word lines, the second interlayer dielectric layer is located at the top of the second word lines, and the third interlayer dielectric layer is located within the second word lines and the second interlayer dielectric layer.

27. The semiconductor structure as claimed in claim 26, characterized in that, The thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or a combination of TIN and Si, or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

28. The semiconductor structure as claimed in claim 20, characterized in that, It also includes a third word line, which is discretely arranged along the bit line direction. The third word line includes a first word line gate oxide layer and a first word line gate layer. The first word line gate oxide layer is located on the sidewall surface adjacent to the vertical transistor, and the first word line gate layer is located on the sidewall surface of the first word line gate oxide layer and spans the substrate along the word line direction.

29. The semiconductor structure as described in claim 28, characterized in that, It also includes a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer, wherein the first interlayer dielectric layer is located on the substrate and a portion of the first interlayer dielectric layer is located between adjacent first word line gate oxide layers, the second interlayer dielectric layer is located between the first interlayer dielectric layer and the vertical transistor, and the third interlayer dielectric layer is located on top of the first interlayer dielectric layer and on top of the third word line, and the third interlayer dielectric layer is flush with the top of the vertical transistor.

30. The semiconductor structure as claimed in claim 29, characterized in that, The width of the first word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the first word line gate layer along the bit line direction ranges from 1 nanometer to 10 nanometers, the depth of the first word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the first word line gate layer is one of TIN, a combination of TIN and W, or Mo.

31. The semiconductor structure as described in claim 20, characterized in that, It also includes a first vertical transistor, which is discretely located on the substrate, and the width of the first vertical transistor along the word line direction ranges from 15 nanometers to 100 nanometers.

32. The semiconductor structure as described in claim 31, characterized in that, Also includes: The fourth word line is discretely arranged along the bit line direction. The fourth word line includes: a second word line gate oxide layer and a second word line gate layer. The second word line gate oxide layer is located on the sidewall surface adjacent to the first vertical transistor and on a portion of the isolation region surface. The second word line gate layer is located on the sidewall surface of the second word line gate oxide layer and spans the substrate along the word line direction.

33. The semiconductor structure as described in claim 32, characterized in that, The width of the second word line gate oxide layer along the word line direction ranges from 1 nanometer to 15 nanometers, the thickness of the second word line gate layer along the bit line direction ranges from 1 nanometer to 10 nanometers, the depth of the second word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, and the material of the second word line gate layer is one of TIN, a combination of TIN and W, or Mo.

34. A storage array, characterized in that, include: Several bit lines, the several bit lines are arranged along the word line direction; A plurality of word lines are arranged along the bit line direction, and the plurality of bit lines intersect with the plurality of word lines in a grid pattern. A plurality of dual-gate vertical transistors are arranged in an array at intervals in a grid formed by the intersection of a plurality of bit lines and a plurality of word lines. In a row of grids formed by the intersection of any word line and a plurality of bit lines, the dual-gate vertical transistor is located in one of two adjacent grids. In a column of grids formed by the intersection of any bit line and a plurality of word lines, the dual-gate vertical transistor is located in one of two adjacent grids. The source / drain of the dual-gate vertical transistor is connected to the bit line, and the gate of the dual-gate vertical transistor is connected to the word line. A plurality of storage capacitors, wherein the first end of the storage capacitors is connected to the source / drain of the dual-gate vertical transistor, and the second end of the storage capacitors is grounded.

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