Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a first region, a second region and a third region, the substrate comprises a plurality of active regions, and the active region exposed out of the second surface of the substrate comprises a first part and a second part which are separated from each other; the first isolation layer is positioned between the adjacent active regions; a plurality of first cut-off layers located in the second area, wherein the first cut-off layers cut off the spaced first isolation layers; a plurality of second cut-off layers located in the third area and used for cutting off the spaced first isolation layers; the word line gate structure is positioned in the first region; the bit line structure is positioned on the second surface of the substrate and comprises a first bit line electrically connected with the first branch part and a second bit line electrically connected with the second branch part; a first connection structure located on the second region and electrically connected with the first bit line; and a second connection structure located on the third region and electrically connected with the second bit line. The semiconductor structure is easy to realize independent control of the spaced bit lines.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] A basic memory cell in Dynamic Random Access Memory (DRAM) consists of a transistor and a storage capacitor, while a memory array consists of multiple memory cells. As semiconductor devices become smaller, to reduce the area of ​​a single memory cell, the bit line structures of the capacitor and control transistor are typically placed on opposite sides of the semiconductor substrate to save planar area.

[0004] However, as the size of semiconductor devices continues to shrink, dynamic random access memory still faces many challenges that need to be addressed. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to continuously improve the performance of dynamic random access memory.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second region and the third region, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of active regions, the plurality of active regions being arranged in parallel along a second direction parallel to the substrate surface, the first direction being perpendicular to the second direction; an initial first isolation layer located between adjacent active regions, the first surface of the substrate exposing the surface of the initial first isolation layer; cutting the spaced initial first isolation layer in a second region to form a plurality of first cut layers penetrating the initial first isolation layer along a second direction in the second region, the first surface of the substrate exposing the surface of the first cut layers; cutting the spaced initial first isolation layer in a third region, in... The third region forms a plurality of second cut-off layers penetrating the initial first isolation layer along a second direction. The first cut-off layer and the second cut-off layer respectively penetrate two adjacent initial first isolation layers. The first surface of the substrate exposes the surface of the second cut-off layer. A word line gate structure is formed in the first region, and the word line gate structure is parallel to the second direction. A portion of the active region exposed on the second surface of the substrate is removed, exposing the surfaces of the first cut-off layer and the second cut-off layer. The first cut-off layer and the second cut-off layer form the active region into a first portion and a second portion that are mutually discrete. A bit line structure is formed on the second surface of the substrate. The bit line structure includes a first bit line electrically connected to the first portion and a second bit line electrically connected to the second portion. A first connection structure is formed on the second region, and the first connection structure is electrically connected to the first bit line. A second connection structure is formed on the third region, and the second connection structure is electrically connected to the second bit line.

[0007] Optionally, the first cutting layer has a dimension larger than the width of the initial first isolation layer in the second direction, and the first cutting layer is also located in the active regions on both sides adjacent to the initial first isolation layer; the second cutting layer has a dimension larger than the width of the initial first isolation layer in the second direction, and the second cutting layer is also located in the active regions on both sides adjacent to the initial first isolation layer.

[0008] Optionally, the dimension of the first cutting layer in the second direction is greater than the sum of the widths of the initial first isolation layer, the first portion, and the second portion; the dimension of the second cutting layer in the second direction is greater than the sum of the widths of the initial first isolation layer, the first portion, and the second portion.

[0009] Optionally, the first cutting layer and the second cutting layer are located in the active regions on adjacent sides of the initial first isolation layer, the projections of the two ends of the first cutting layer in the second direction onto the substrate are located between the first portion and the second portion, and the projections of the two ends of the second cutting layer in the second direction onto the substrate are located between the first portion and the second portion.

[0010] Optionally, the first and second cutting layers are formed simultaneously. The formation process of the first and second cutting layers includes: forming a mask structure on a first surface of a substrate, the mask structure having a plurality of first openings, the first openings exposing a portion of the initial first isolation layer and a portion of the active region surface on both sides of the initial first isolation layer; etching the exposed initial first isolation layer and active region using the mask structure as a mask to form a first groove and a second groove in the substrate, the first groove being located in a second region and the second groove being located in a third region; forming a cutting material layer in the first groove, the second groove, and the first surface of the substrate; planarizing the cutting material layer until the active region surface is exposed, forming a first cutting layer in the first groove, and forming a second cutting layer in the second groove.

[0011] Optionally, the depth of the first cutting layer is less than the depth of the initial first isolation layer; the depth of the second cutting layer is less than the depth of the initial first isolation layer.

[0012] Optionally, the size of the first cutting layer in the first direction is smaller than the size of the second region; the size of the second cutting layer in the first direction is smaller than the size of the third region.

[0013] Optionally, the first portion is located at least in the first area and the second area; the second portion is located at least in the first area and the third area.

[0014] Optionally, a portion of the first portion is also located in the third region; a portion of the second portion is also located in the second region.

[0015] Optionally, the first portion includes: a first vertical portion located in the first region and the second region, a first horizontal portion located in the second region, and a second vertical portion located in the second region, wherein the first vertical portion and the second vertical portion are parallel to a first direction, the first horizontal portion is parallel to a second direction, and the first horizontal portion connects the first vertical portion and the second vertical portion; the first connecting structure is electrically connected to the first line on the second region, including: the projection of the first connecting structure on the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion on the second region.

[0016] Optionally, the second portion includes: a third vertical portion located in the first region and the third region, a second horizontal portion located in the third region, and a fourth vertical portion located in the third region, wherein the third vertical portion and the fourth vertical portion are parallel to the first direction, the second horizontal portion is parallel to the second direction, and the second horizontal portion connects the third vertical portion and the fourth vertical portion; the second connection structure is electrically connected to a second bit line on the third region, including: the projection of the second connection structure on the substrate coincides with a portion of at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion on the third region.

[0017] Optionally, the active region includes a channel region distributed along a direction perpendicular to the substrate surface, and the word line gate structure is adjacent to the channel region; the first portion and the second portion are connected to the channel region.

[0018] Optionally, removing a portion of the active region exposed on the second surface of the substrate to expose the surfaces of the first and second cut-off layers, wherein the first and second cut-off layers form the active region into mutually separate first and second portions, includes: etching back the active region exposed on the second surface of the substrate to form a third groove within an initial first isolation layer; forming a sidewall on the sidewall surface of the third groove, the sidewall exposing a portion of the active region surface; removing the exposed active region using the sidewall as a mask to form a fourth groove within the active region; removing the sidewall to form a second isolation layer within the fourth groove, the second isolation layer being in contact with the first and second cut-off layers; and removing the active region exposed on the second surface of the substrate until the surfaces of the first and second cut-off layers are exposed, thereby forming the active region into mutually separate first and second portions.

[0019] Optionally, forming a sidewall on the surface of the third groove sidewall includes: forming a sidewall material layer on the surface of the third groove sidewall, the bottom surface, and the second surface of the substrate; and etching back the sidewall material layer until the surface of the active region is exposed, thereby forming a sidewall on the third groove sidewall.

[0020] Optionally, the process of forming the fourth groove includes: removing the exposed active region using the sidewall as a mask until the surface of the channel region is exposed, thereby forming a fourth groove in the active region; the projections of the two ends of the first cutting layer on the substrate are located within the range of the fourth groove; the projections of the two ends of the second cutting layer on the substrate are located within the range of the fourth groove.

[0021] Optionally, the process of forming the second isolation layer, the first portion, and the second portion includes: after removing the sidewall, forming an isolation material layer in the third groove, the fourth groove, and the second surface of the substrate; planarizing the isolation material layer, the active region, and the initial first isolation layer until the surfaces of the first cut-off layer and the second cut-off layer are exposed; forming the second isolation layer in the fourth groove; forming the active region into mutually separate first and second portions; and forming the initial first isolation layer into the first isolation layer.

[0022] Optionally, the process of forming the second isolation layer, the first portion, and the second portion includes: after removing the sidewall, removing a portion of the active region exposed on the second surface of the substrate until the surface of the remaining active region is lower than or flush with the surfaces of the first cut-off layer and the second cut-off layer; forming an isolation material layer in the third groove, the fourth groove, and on the second surface of the substrate; planarizing the isolation material layer and the initial first isolation layer until the surface of the active region is exposed; forming a second isolation layer in the fourth groove, so that the active region is formed into a first portion and a second portion that are mutually independent, and so that the initial first isolation layer is formed into a first isolation layer.

[0023] Optionally, the projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate.

[0024] Optionally, the process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion to form a third opening in the substrate; etching back the second portion to form a fourth opening in the substrate; forming a bit line material layer in the third opening, the fourth opening, and on the initial first isolation layer; planarizing the bit line material layer until the surface of the initial first isolation layer is exposed, forming the first bit line in the third opening, and forming the second bit line in the fourth opening.

[0025] Optionally, there is a first spacing between the first bit line and the second bit line, and the active region has a first width, wherein the ratio of the first spacing to the first width is in the range of 1:2 to 1:4.

[0026] Optionally, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0027] Optionally, the first connection structure and the second connection structure are formed simultaneously; the formation process of the first connection structure and the second connection structure includes: forming a dielectric structure on a second surface of a substrate; forming a fifth opening and a sixth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the first bit line surface on the second region, and the sixth opening exposes at least a portion of the second bit line surface on the third region; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall surface and bottom surface of the fifth opening, the sidewall surface and bottom surface of the sixth opening, and the surface of the dielectric structure; planarizing the conductive material layer and the barrier material layer until the surface of the dielectric structure is exposed; forming a first connection structure within the fifth opening; and forming a second connection structure within the sixth opening.

[0028] Optionally, the substrate formation process includes: providing an initial substrate, the initial substrate including a first region, a second region, and a third region distributed along a first direction parallel to the surface of the initial substrate, the initial substrate including: a substrate, a plurality of active regions located on the substrate, the plurality of active regions being arranged in parallel along a second direction parallel to the surface of the initial substrate, the first direction being perpendicular to the second direction, an initial first isolation layer located between adjacent active regions, the first surface of the initial substrate exposing the surface of the initial first isolation layer; after forming a word line gate structure located in the first region, the process further includes: removing the substrate to expose the surface of the initial first isolation layer and the surface of the active regions, thereby forming the substrate.

[0029] Optionally, after forming the word line gate structure in the first region, the method further includes: forming a plurality of capacitor structures on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the active regions.

[0030] Optionally, before forming several capacitor structures, the method further includes: performing a first ion implantation on the active region exposed on the first surface of the substrate to form a first source / drain doped region, wherein the capacitor structure is electrically connected to the first source / drain doped region.

[0031] Optionally, before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first portion and the second portion to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0032] Optionally, before forming the word line grid structure located in the first region, the method further includes: etching the channel region of the active region to form the channel region into a plurality of discrete channel pillars located in the first region.

[0033] Optionally, the word line grid structure includes: a first word line grid and a second word line grid, the first word line grid and the second word line grid are respectively located on the two side walls of the channel post along the first direction, the first word line grid and the second word line grid are parallel to the second direction, the first word line grid and the second word line grid are located within the initial first isolation layer, and the initial first isolation layer electrically isolates adjacent first word line grids and second word line grids.

[0034] Optionally, the central axes of two adjacent trench columns do not coincide in the first direction.

[0035] Optionally, the word line grid structure includes: a plurality of word line grids surrounding the channel post, wherein the plurality of word line grids are connected along a second direction and are parallel to the second direction.

[0036] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of active regions, the plurality of active regions being arranged in parallel along a second direction parallel to the substrate surface, the first direction being perpendicular to the second direction, the active regions exposed on the second surface of the substrate including mutually separate first portions and second portions; a first isolation layer located between adjacent active regions, the first surface and the second surface of the substrate exposing the surface of the first isolation layer; a plurality of first cutting layers located in the second region, the plurality of first cutting layers cutting the spaced-apart first isolation layers, the... A first cutting layer penetrates the first isolation layer along a second direction, and the first surface of the substrate exposes the surface of the first cutting layer; a plurality of second cutting layers are located in a third region, the plurality of second cutting layers cutting the spaced first isolation layer, the second cutting layers penetrating the first isolation layer along a second direction, and the first surface of the substrate exposes the surface of the second cutting layer; a word line gate structure is located in a first region, the word line gate structure being parallel to the second direction; a bit line structure is located on a second surface of the substrate, the bit line structure including: a first bit line electrically connected to a first portion, and a second bit line electrically connected to a second portion; a first connection structure is located on a second region, the first connection structure being electrically connected to the first bit line; and a second connection structure is located on a third region, the second connection structure being electrically connected to the second bit line.

[0037] Optionally, the first cutting layer has a dimension larger than the width of the first isolation layer in the second direction, and the first cutting layer is also located within the active regions on both sides of the first isolation layer; the second cutting layer has a dimension larger than the width of the first isolation layer in the second direction, and the second cutting layer is also located within the active regions on both sides of the first isolation layer.

[0038] Optionally, the dimension of the first cutting layer in the second direction is greater than the sum of the widths of the first isolation layer, the first segment, and the second segment; the dimension of the second cutting layer in the second direction is greater than the sum of the widths of the first isolation layer, the first segment, and the second segment.

[0039] Optionally, the first cutting layer and the second cutting layer are located in the active regions on adjacent sides of the first isolation layer, the projections of the two ends of the first cutting layer in the second direction onto the substrate are located between the first portion and the second portion, and the projections of the two ends of the second cutting layer in the second direction onto the substrate are located between the first portion and the second portion.

[0040] Optionally, the size of the first cutting layer in the first direction is smaller than the size of the second region; the size of the second cutting layer in the first direction is smaller than the size of the third region.

[0041] Optionally, the first portion is located at least in the first area and the second area; the second portion is located at least in the first area and the third area.

[0042] Optionally, a portion of the first portion is also located in the third region; a portion of the second portion is also located in the second region.

[0043] Optionally, the first portion includes: a first vertical portion located in the first region and the second region, a first horizontal portion located in the second region, and a second vertical portion located in the second region, wherein the first vertical portion and the second vertical portion are parallel to a first direction, the first horizontal portion is parallel to a second direction, and the first horizontal portion connects the first vertical portion and the second vertical portion; the first connecting structure is electrically connected to the first line on the second region, including: the projection of the first connecting structure on the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion on the second region.

[0044] Optionally, the second portion includes: a third vertical portion located in the first region and the third region, a second horizontal portion located in the third region, and a fourth vertical portion located in the third region, wherein the third vertical portion and the fourth vertical portion are parallel to the first direction, the second horizontal portion is parallel to the second direction, and the second horizontal portion connects the third vertical portion and the fourth vertical portion; the second connection structure is electrically connected to a second bit line on the third region, including: the projection of the second connection structure on the substrate coincides with a portion of at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion on the third region.

[0045] Optionally, it may also include a second isolation layer located between the first and second sections.

[0046] Optionally, the projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate.

[0047] Optionally, there is a first spacing between the first bit line and the second bit line, and the active region has a first width, wherein the ratio of the first spacing to the first width is in the range of 1:2 to 1:4.

[0048] Optionally, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0049] Optionally, it may also include: a plurality of capacitor structures located on the first surface of the substrate, one of the capacitor structures being electrically connected to one of the active regions.

[0050] Optionally, it also includes: a first source / drain doped region located in the active region exposed on the first surface of the substrate, wherein the capacitor structure is electrically connected to the first source / drain doped region.

[0051] Optionally, the bit line structure is electrically connected to the second source / drain doped region located in the first and second portions.

[0052] Optionally, the active region includes a channel region distributed along a direction perpendicular to the substrate surface, and the word line gate structure is adjacent to the channel region; the first portion and the second portion are connected to the channel region.

[0053] Optionally, the trench area includes a plurality of separate trench columns located in the first area.

[0054] Optionally, the word line grid structure includes: a first word line grid and a second word line grid, the first word line grid and the second word line grid are respectively located on the two side walls of the channel post along the first direction, the first word line grid and the second word line grid are parallel to the second direction, the first word line grid and the second word line grid are located within the first isolation layer, and the first isolation layer electrically isolates the adjacent first word line grid and the second word line grid.

[0055] Optionally, the central axes of two adjacent trench columns do not coincide in the first direction.

[0056] Optionally, the word line grid structure includes: a plurality of word line grids surrounding the channel post, wherein the plurality of word line grids are connected along a second direction and are parallel to the second direction.

[0057] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0058] The semiconductor structure formation method of the present invention involves forming a plurality of first severing layers penetrating the initial first isolation layer along a second direction in a second region, and forming a plurality of second severing layers penetrating the initial first isolation layer along a second direction in a third region. The first and second severing layers form the active region into mutually separate first and second portions. A first connection structure electrically connected to a first bit line is formed on the second region, and a second connection structure electrically connected to a second bit line is formed on the third region. The first connection structure is arbitrarily connected to the first bit line on the second region, and the second connection structure is arbitrarily connected to the second bit line on the third region. The process window for forming the first and second connection structures is increased, and the first and second connection structures are easier to form. This facilitates the connection of the first bit line to an external circuit through the first connection structure and the connection of the second bit line to an external circuit through the second connection structure. It also facilitates the individual control of spaced-apart bit lines and avoids capacitive coupling when two adjacent bit lines are energized simultaneously.

[0059] Furthermore, the depth of the first cut-off layer is greater than the depth of the channel region; the depth of the second cut-off layer is greater than the depth of the channel region. That is, the depths of the first and second cut-off layers are greater than the depth of the channel post. Therefore, when the surfaces of the first and second cut-off layers are exposed, and the first and second cut-off layers form the active region into mutually separate first and second portions, the bottom of the channel post is not exposed, and the first and second portions are connected to the channel post.

[0060] Furthermore, the dimension of the first cutting layer in the second direction is greater than the sum of the widths of the initial first isolation layer, the first portion, and the second portion; the dimension of the second cutting layer in the second direction is also greater than the sum of the widths of the initial first isolation layer, the first portion, and the second portion. This ensures that the first cutting layer and the second cutting layer cut through the active region, forming mutually independent first cutting layer and second cutting layer.

[0061] Furthermore, the first portion includes: a first vertical portion located in the first region and the second region, a first horizontal portion located in the second region, and a second vertical portion located in the second region. The projection of the first connection structure onto the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion in the second region. This increases the process window for forming the first connection structure.

[0062] Furthermore, the second portion includes: a third vertical portion located in the first region and the third region, a second horizontal portion located in the third region, and a fourth vertical portion located in the third region. The projection of the second connection structure onto the substrate coincides with a portion of at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion in the third region. This increases the process window for forming the second connection structure.

[0063] Furthermore, by etching back the first portion, a third opening is formed in the substrate; by etching back the second portion, a fourth opening is formed in the substrate; then, the first bit line is formed within the third opening, and the second bit line is formed within the fourth opening. This process enables self-alignment to form the bit line structure, allowing for a further reduction in the spacing between the bit line structures and saving on the use of a photomask.

[0064] The semiconductor structure of the present invention includes a plurality of first cutting layers cutting the spaced first isolation layers, a plurality of second cutting layers cutting the spaced first isolation layers, a first connection structure located on a second region and electrically connected to a first bit line, and a second connection structure located on a third region and electrically connected to a second bit line. The first connection structure is arbitrarily connected to the first bit line on the second region, and the second connection structure is arbitrarily connected to the second bit line on the third region. The process window for forming the first and second connection structures is increased, and the first and second connection structures are easy to form. This facilitates the connection of the first bit line to an external circuit through the first connection structure and the connection of the second bit line to an external circuit through the second connection structure. It also facilitates the individual control of spaced bit lines and avoids capacitive coupling when two adjacent bit lines are energized simultaneously. Attached Figure Description

[0065] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure in one embodiment;

[0066] Figures 3 to 35 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0067] As described in the background section, dynamic random access memory (DRAM) still has many problems that need to be solved. These will now be analyzed and explained in conjunction with specific embodiments.

[0068] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure in one embodiment.

[0069] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a storage cell in a dynamic random access memory (DRAM). Figure 2 The diagram shows the bit line distribution on the substrate surface. The memory cell of the dynamic random access memory includes: a channel post 101, which is parallel to a first direction; a word line gate structure 102 located on the sidewall surface of the channel post 101, which is parallel to a second direction and perpendicular to the first and second directions; a bit line structure 104 and a capacitor structure 103 electrically connected to both ends of the channel post 101, respectively, with the bit line structure 104 parallel to the first direction.

[0070] The dynamic random access memory (DRAM) includes several parallel bit line structures 104, each connected to an external circuit via a connection structure 105. As semiconductor devices become increasingly smaller, the spacing between adjacent bit line structures 104 also decreases. When multiple bit line structures 104 are simultaneously powered, capacitive coupling can easily occur between adjacent structures, generating parasitic capacitance and causing performance degradation in the DRAM.

[0071] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming such a semiconductor structure. A plurality of first severing layers are formed in a second region, penetrating the initial first isolation layer along a second direction. A plurality of second severing layers are formed in a third region, penetrating the initial first isolation layer along a second direction. These first and second severing layers divide the active region into mutually separate first and second portions. A first connection structure electrically connected to a first bit line is formed in the second region, and a second connection structure electrically connected to a second bit line is formed in the third region. The first connection structure is arbitrarily connected to the first bit line in the second region, and the second connection structure is arbitrarily connected to the second bit line in the third region. The process window for forming the first and second connection structures is increased, making them easier to form. This facilitates connection of the first bit line to an external circuit via the first connection structure and the second bit line to an external circuit via the second connection structure. It also facilitates individual control of spaced-apart bit lines, avoiding capacitive coupling when two adjacent bit lines are simultaneously energized.

[0072] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0073] Figures 3 to 35 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0074] A substrate is provided, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of active regions arranged parallel to each other along a second direction parallel to the substrate surface, the first direction being perpendicular to the second direction; and an initial first isolation layer located between adjacent active regions, the first surface of the substrate exposing the surface of the initial first isolation layer. The formation process of the substrate is described in reference [reference needed]. Figure 3 and Figure 4 .

[0075] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 Top view of the first surface of the initial substrate. Figure 4 for Figure 3 A schematic diagram along the section line AA1 shows an initial substrate. The initial substrate includes a first region I, a second region II, and a third region III distributed along a first direction Y parallel to the surface of the initial substrate. The initial substrate includes a substrate 200, a plurality of active regions 201 located on the substrate 200, the plurality of active regions 201 being arranged in parallel along a second direction X parallel to the surface of the initial substrate, the first direction Y being perpendicular to the second direction X, and an initial first isolation layer 202 located between adjacent active regions 201. The first surface of the initial substrate exposes the surface of the initial first isolation layer 202.

[0076] In this embodiment, the material of the substrate 200 is the same as the material of the active region 201. In other embodiments, the material of the substrate and the material of the active region may be different.

[0077] In this embodiment, the substrate 200 and the active region 201 are made of silicon.

[0078] In other embodiments, the substrate and the active region 201 are made of materials including silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0079] The material of the initial first isolation layer 202 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0080] In this embodiment, the material of the initial first isolation layer 202 includes silicon oxide.

[0081] The method for forming the initial substrate includes: providing a substrate material; forming a patterned mask layer on the substrate material; etching the substrate material using the patterned mask layer as a mask to form a plurality of grooves parallel to the first direction Y in the substrate material layer, forming a substrate 200 and a plurality of active regions 201 located on the substrate 200; forming an initial first isolation layer 202 in the grooves to form the initial substrate.

[0082] In this embodiment, the widths of the active regions 201 in the second direction X are the same; the widths of the grooves in the second direction X are the same.

[0083] The active region 201 includes a channel region distributed along a direction perpendicular to the substrate surface. The channel region is used to subsequently form a word line gate structure on the surface of the channel region. The channel region is close to the first surface of the initial substrate and does not contact the substrate 200. That is, the depth of the channel region is less than the depth of the initial first isolation layer 202.

[0084] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 Top view of the first surface of the initial substrate. Figure 6 for Figure 5 A schematic diagram along the cross-section line AA1 shows that the initial first isolation layer 202 is cut at intervals in the second region II, forming a plurality of first cut layers 203 penetrating the initial first isolation layer 202 along the second direction X in the second region II, with the first surface of the substrate exposing the surface of the first cut layer 203; the initial first isolation layer 202 is cut at intervals in the third region III, forming a plurality of second cut layers 204 penetrating the initial first isolation layer 202 along the second direction X in the third region III, with the first cut layer 203 and the second cut layer 204 penetrating two adjacent initial first isolation layers 202 respectively, and the first surface of the substrate exposing the surface of the second cut layer 204.

[0085] The first cutting layer 203 has a dimension in the second direction X that is greater than the width of the initial first isolation layer 202, and the first cutting layer 203 is also located in the active regions 201 on both sides adjacent to the initial first isolation layer 202.

[0086] The second cutting layer 204 has a dimension in the second direction X that is greater than the width of the initial first isolation layer 202, and the second cutting layer 204 is also located in the active regions 201 on both sides adjacent to the initial first isolation layer 202.

[0087] In this embodiment, the first cutting layer 203 and the second cutting layer 204 are formed simultaneously.

[0088] The formation process of the first cutting layer 203 and the second cutting layer 204 includes: forming a mask structure (not shown) on a first surface of an initial substrate, the mask structure having a plurality of first openings, the first openings exposing a portion of the initial first isolation layer 202 and a portion of the surface of the active region 201 on both sides of the initial first isolation layer 202; etching the exposed initial first isolation layer 202 and the active region 201 using the mask structure as a mask, forming a first groove (not shown) and a second groove (not shown) in the initial substrate, the first groove being located in a second region II and the second groove being located in a third region III; forming a cutting material layer in the first groove, the second groove and the first surface of the substrate; planarizing the cutting material layer until the surface of the active region 201 is exposed, forming a first cutting layer 203 in the first groove and a second cutting layer 204 in the second groove.

[0089] In this embodiment, the depth of the first cutting layer 203 is less than the depth of the initial first isolation layer 202; the depth of the second cutting layer 204 is less than the depth of the initial first isolation layer 202.

[0090] In this embodiment, the depth of the first cutting layer 203 is greater than the depth of the channel region; the depth of the second cutting layer 204 is greater than the depth of the channel region.

[0091] In this embodiment, the size of the first cutting layer 203 in the first direction Y is smaller than the size of the second region II; the size of the second cutting layer 204 in the first direction Y is smaller than the size of the third region III.

[0092] In this embodiment, the first cutting layer 203 and the second cutting layer 204 are made of the same material.

[0093] The materials of the first cutting layer 203 and the second cutting layer 204 include dielectric materials, which include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0094] In this embodiment, the materials of the first cutting layer 203 and the second cutting layer 204 include silicon oxide.

[0095] Please refer to Figures 7 to 9 , Figure 7 for Figure 8 and Figure 9 Top view, Figure 8 for Figure 7 A schematic diagram of the structure along section line BB1. Figure 9 for Figure 7A schematic diagram along the cross-sectional line CC1 shows that the channel region of the active region 201 is etched to form a plurality of discrete channel pillars 205 located in the first region I.

[0096] In this embodiment, the central axes of two adjacent channel posts 205 do not coincide in the first direction Y; in the second direction X, several of the channel posts 205 are located on the same straight line.

[0097] In this embodiment, the depth of the channel post 205 is less than the depth of the initial first isolation layer 202. That is, the channel post 205 is located on the active region 201 outside the channel region.

[0098] In this embodiment, one of the channel posts 205, another adjacent channel post 205 in the first direction Y, and another adjacent channel post 205 in the second direction X form a triangle. This allows the positions of the capacitor structures, which are electrically connected to the channel posts 205 respectively, to be staggered when forming a plurality of capacitor structures on the first surface, thereby increasing the process window.

[0099] The cross-sectional shape of the channel post 205 includes: a polygon with a side length greater than or equal to 5, a rectangle, a circle, or an ellipse. In this embodiment, the cross-sectional shape of the channel post 205 includes a rectangle.

[0100] In this embodiment, after forming the channel column 205, the method further includes filling the opening where the active region 201 has been removed with a filling layer 206.

[0101] Please refer to Figure 10 and Figure 11 , Figure 10 for Figure 11 Top view, Figure 11 for Figure 10 A schematic diagram of the structure along the cross-sectional line BB1 ​​shows a word line gate structure located in the first region I, the word line gate structure being parallel to the second direction X.

[0102] The active region 201 includes a channel region distributed along a direction perpendicular to the substrate surface, and the word line gate structure is adjacent to the channel region.

[0103] The word line grid structure includes: a first word line grid 207 and a second word line grid 208. The first word line grid 207 and the second word line grid 208 are respectively located on the two side walls of the channel post 205 along the first direction Y. The first word line grid 207 and the second word line grid 208 are parallel to the second direction X. The first word line grid 207 and the second word line grid 208 are located within the initial first isolation layer 202 and the filling layer 206. The first word line grid 207 and the second word line grid 208 are electrically isolated from each other within the initial first isolation layer 202 and the filling layer 206.

[0104] The first word line gate 207 includes a first gate dielectric layer located on the surface of the channel pillar 205, and a first gate layer located on the surface of the first gate dielectric layer. The second word line gate 208 includes a second gate dielectric layer located on the surface of the channel pillar 205, and a second gate layer located on the surface of the second gate dielectric layer.

[0105] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include silicon oxide or low-K (K less than 3.9) materials; the materials of the first gate layer and the second gate layer include polysilicon.

[0106] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include a high dielectric constant material, the high dielectric constant material having a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the materials of the first gate layer and the second gate layer include metals, the metal including tungsten.

[0107] The top surface of the word line grid structure is lower than or flush with the first surface of the substrate. The figure schematically illustrates that the top surface of the word line grid structure is flush with the first surface of the substrate.

[0108] In another embodiment, the word grid structure includes: a plurality of word grids surrounding the channel post, wherein the plurality of word grids are connected along a second direction and are parallel to the second direction.

[0109] In another embodiment, the cross-section of the channel column includes a circle or an ellipse.

[0110] Please refer to Figure 12 and Figure 13 , Figure 12 for Figure 13 Top view, Figure 13 for Figure 12 A schematic diagram of the structure along the cross-section line BB1 ​​shows that several capacitor structures 209 are formed on the first surface of the substrate, and one of the capacitor structures 209 is electrically connected to one of the channel pillars 205.

[0111] Before forming several capacitor structures, the method further includes: performing a first ion implantation on the channel pillar 205 exposed on the first surface of the substrate to form a first source / drain doped region, and the capacitor structure is electrically connected to the first source / drain doped region.

[0112] Next, a portion of the active region exposed on the second surface of the substrate is removed, exposing the surfaces of the first and second severing layers. The first and second severing layers form the active region into mutually separate first and second portions. The formation process of the first and second portions is described in [reference needed]. Figures 14 to 30 .

[0113] Please refer to Figures 14 to 16 , Figure 14 for Figure 15 and Figure 16 Top view, Figure 15 for Figure 14 A schematic diagram of the structure along section line BB1. Figure 16 for Figure 14 A schematic diagram of the structure along the cross-sectional line CC1 shows the substrate 200 being removed, exposing the surface of the initial first isolation layer 202 and the surface of the active region 201, thus forming the substrate.

[0114] It should be noted that since the depth of the channel region is less than the depth of the initial first isolation layer 202, after removing the substrate 200, the second surface of the substrate will not expose the channel pillar 205, but the active region 201 at the bottom of the channel pillar 205 will be exposed on the second surface of the substrate.

[0115] In this embodiment, the process for removing the substrate 200 includes a chemical mechanical polishing process.

[0116] Please refer to Figures 17 to 20 , Figure 17 for Figure 18 , Figure 19 and Figure 20 Top view, Figure 18 for Figure 17 A schematic diagram of the structure along section line AA1. Figure 19 for Figure 17 A schematic diagram of the structure along section line BB1. Figure 20 for Figure 17 A schematic diagram of the structure along the cross-section line CC1 shows the active region 201 exposed on the second surface of the substrate being etched back, and a third groove 210 being formed in the initial first isolation layer 202, the third groove 210 extending from the second surface of the substrate to the first surface.

[0117] The depth of the third groove 210 is less than the distance between the channel post 205 and the second surface of the substrate, that is, the third groove 210 will not expose the bottom surface of the channel post 205.

[0118] Please refer to Figures 21 to 24 , Figure 21 for Figure 22 , Figure 23 and Figure 24 Top view, Figure 22 for Figure 21 A schematic diagram of the structure along section line AA1. Figure 23 for Figure 21 A schematic diagram of the structure along section line BB1. Figure 24 for Figure 21A schematic diagram of the structure along the cross section line CC1 shows that a sidewall 211 is formed on the sidewall surface of the third groove 210, and the sidewall 211 exposes part of the surface of the active region 201.

[0119] The method for forming the sidewall 211 includes: forming a sidewall material layer on the sidewall surface and bottom surface of the third groove 210 and on the second surface of the substrate; etching back the sidewall material layer until the surface of the active region 201 is exposed, thereby forming the sidewall 211 on the sidewall of the third groove 210.

[0120] The sidewall 211 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0121] In this embodiment, the material of the sidewall 211 includes silicon nitride.

[0122] Please refer to Figure 25 and Figure 26 , Figure 25 In order to be in Figure 22 A basic diagram. Figure 26 In order to be in Figure 24 Based on the schematic diagram, the exposed active region 201 is removed using the sidewall 211 as a mask, and a fourth groove 212 is formed in the active region.

[0123] In this embodiment, the fourth groove 212 exposes the surface of the channel post 205.

[0124] The process of forming the fourth groove 212 includes: removing the exposed active region 201 using the sidewall 211 as a mask until the surface of the channel post 205 is exposed, and forming the fourth groove 212 in the active region 201.

[0125] In this embodiment, the projections of both ends of the first cutting layer 203 onto the substrate are located within the range of the fourth groove 212; the projections of both ends of the second cutting layer 204 onto the substrate are also located within the range of the fourth groove 212. This ensures that the first cutting layer 203 and the second cutting layer 204 can cut the active region 201 of the sidewall of the fourth groove 212.

[0126] Please refer to Figures 27 to 30 , Figure 27 for Figure 28 , Figure 29 and Figure 30 Top view, Figure 28 for Figure 27 A schematic diagram of the structure along section line AA1. Figure 29 for Figure 27A schematic diagram of the structure along section line BB1. Figure 30 for Figure 27 A schematic diagram along the cross-sectional line CC1 shows the following: the sidewall 211 is removed, and a second isolation layer 213 is formed in the fourth groove 212. The second isolation layer 213 is in contact with the first cut-off layer 203 and the second cut-off layer 204. The active region 201 exposed on the second surface of the substrate is removed until the surfaces of the first cut-off layer 203 and the second cut-off layer 204 are exposed, so that the active region 201 exposed on the second surface of the substrate is formed into a first portion 214 and a second portion 215 that are mutually independent.

[0127] In one embodiment, the process of forming the second isolation layer 213, the first portion 214, and the second portion 215 includes: after removing the sidewall 211, forming an isolation material layer (not shown) in the third groove 210, the fourth groove 212, and the second surface of the substrate; planarizing the isolation material layer, the active region 201, and the initial first isolation layer 202 until the surfaces of the first cut-off layer 203 and the second cut-off layer 204 are exposed; forming the second isolation layer 213 in the fourth groove 212; forming the active region 201 into mutually separate first portions 214 and second portions 215; and forming the initial first isolation layer 202 into a first isolation layer 230.

[0128] In another embodiment, the process of forming the second isolation layer 213, the first portion 214, and the second portion 215 includes: after removing the sidewall 211, removing a portion of the active region 201 exposed on the second surface of the substrate until the surface of the remaining active region 201 is lower than or flush with the surfaces of the first cut-off layer 203 and the second cut-off layer 204; forming an isolation material layer in the third groove 210, the fourth groove 212, and on the second surface of the substrate; planarizing the isolation material layer and the initial first isolation layer 202 until the surface of the active region 201 is exposed; forming the second isolation layer 213 in the fourth groove 212, so that the active region 201 is formed into mutually separate first portions 214 and second portions 215, and so that the initial first isolation layer 202 is formed into a first isolation layer 230.

[0129] In this embodiment, the active region 201 includes a channel region distributed along a direction perpendicular to the substrate surface. The first portion 214 and the second portion 215 are connected to the channel region, that is, the first portion 214 and the second portion 215 are connected to the channel post 205.

[0130] In this embodiment, the depth of the first cut-off layer 203 is greater than the depth of the channel region; the depth of the second cut-off layer 204 is greater than the depth of the channel region. That is, the depths of the first cut-off layer 203 and the second cut-off layer 204 are greater than the depth of the channel post 205. Therefore, when the surfaces of the first cut-off layer 203 and the second cut-off layer 204 are exposed, and the first cut-off layer 203 and the second cut-off layer 204 form the active region 201 into mutually separate first portions 214 and second portions 215, the bottom of the channel post 205 is not exposed, and the first portions 214 and the second portions 215 are connected to the channel post 205.

[0131] The first cutting layer 203 and the second cutting layer 204 are located in the active regions 201 on both sides of the initial first isolation layer 202. The projections of the two ends of the first cutting layer 203 on the substrate in the second direction X are located between the first portion 214 and the second portion 215. The projections of the two ends of the second cutting layer 204 on the substrate in the second direction X are located between the first portion 214 and the second portion 215.

[0132] The first cutting layer 203 has a dimension in the second direction X that is greater than the sum of the widths of the initial first isolation layer 202, the first portion 214, and the second portion 215; the second cutting layer 204 has a dimension in the second direction X that is greater than the sum of the widths of the initial first isolation layer 202, the first portion 214, and the second portion 215. This ensures that the first cutting layer 203 and the second cutting layer 204 cut through the active region 201, forming mutually independent first cutting layer 203 and second cutting layer 204.

[0133] In this embodiment, the first portion 214 is located at least in the first region I and the second region II; the second portion 215 is located at least in the first region I and the third region III.

[0134] In this embodiment, a portion of the first portion 214 is also located in the third region III; a portion of the second portion 215 is also located in the second region II.

[0135] In this embodiment, the first portion 214 includes: a first vertical portion located in the first region I and the second region II, a first horizontal portion located in the second region II, and a second vertical portion located in the second region II. The first vertical portion and the second vertical portion are parallel to the first direction Y, the first horizontal portion is parallel to the second direction X, and the first horizontal portion connects the first vertical portion and the second vertical portion.

[0136] In this embodiment, the second portion 215 includes: a third longitudinal portion located in the first region I and the third region III, a second transverse portion located in the third region III, and a fourth longitudinal portion located in the third region III. The third longitudinal portion and the fourth longitudinal portion are parallel to the first direction Y, the second transverse portion is parallel to the second direction X, and the second transverse portion connects the third longitudinal portion and the fourth longitudinal portion.

[0137] The material of the second insulating layer 213 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0138] In this embodiment, the material of the second isolation layer 213 includes silicon oxide.

[0139] Please refer to Figures 31 to 34 , Figure 31 for Figure 32 , Figure 33 and Figure 34 Top view, Figure 32 for Figure 31 A schematic diagram of the structure along section line AA1. Figure 33 for Figure 31 A schematic diagram of the structure along section line BB1. Figure 34 for Figure 31 A schematic diagram of the structure along the cross-section line CC1 shows that a bit line structure is formed on the second surface of the substrate. The bit line structure includes a first bit line 216 electrically connected to the first portion 214 and a second bit line 217 electrically connected to the second portion 215.

[0140] The projected area of ​​the first bit line 216 on the substrate is less than or equal to the projected area of ​​the first portion 214 on the substrate; the projected area of ​​the second bit line 217 on the substrate is less than or equal to the projected area of ​​the second portion 215 on the substrate.

[0141] In this embodiment, the projected area of ​​the first bit line 216 on the substrate is equal to the projected area of ​​the first portion 214 on the substrate; the projected area of ​​the second bit line 217 on the substrate is equal to the projected area of ​​the second portion 215 on the substrate.

[0142] The process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion 214 to form a third opening (not shown) in the substrate; etching back the second portion 215 to form a fourth opening (not shown) in the substrate; forming a bit line material layer (not shown) in the third opening, the fourth opening and on the first isolation layer 230; planarizing the bit line material layer until the surface of the first isolation layer 230 is exposed, forming the first bit line 216 in the third opening and the second bit line 217 in the fourth opening.

[0143] By etching back the first portion 214, a third opening is formed in the substrate; by etching back the second portion 215, a fourth opening is formed in the substrate; then, the first bit line 216 is formed in the third opening, and the second bit line 217 is formed in the fourth opening. This process enables self-alignment to form the bit line structure, further reducing the spacing between the bit line structures and saving on the use of a photomask.

[0144] Before forming bit line structures in the third and fourth openings, the method further includes: performing a second ion implantation on the first portion 214 and the second portion 215 to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0145] In this embodiment, there is a first spacing between the first bit line 216 and the second bit line 217, and the active region 201 has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:4.

[0146] In this embodiment, the range of the first spacing is 5 nanometers to 50 nanometers; the range of the first width is 10 nanometers to 100 nanometers.

[0147] In this embodiment, the ratio of the width of the first isolation layer 230 in the second direction X to the width of the active region is in the range of 1:2 to 1:4.

[0148] In this embodiment, the width of the first isolation layer 230 ranges from 5 nanometers to 50 nanometers.

[0149] The material of the bitline structure includes metal silicides, which include nickel silicon or titanium silicon.

[0150] Please refer to Figure 35 A first connection structure 218 is formed on the second region II, and the first connection structure 218 is electrically connected to the first bit line 216; a second connection structure 219 is formed on the third region III, and the second connection structure 219 is electrically connected to the second bit line 217.

[0151] In this embodiment, the first portion 214 includes: a first vertical portion located in the first region I and the second region II, a first horizontal portion located in the second region II, and a second vertical portion located in the second region II. The first vertical portion and the second vertical portion are parallel to the first direction Y, the first horizontal portion is parallel to the second direction X, and the first horizontal portion connects the first vertical portion and the second vertical portion.

[0152] The first line 216 on the second region II of the first connection structure 218 is electrically connected, including: the projection of the first connection structure 218 on the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion on the second region II. This increases the process window for the formation of the first connection structure 218.

[0153] In this embodiment, the second portion 215 includes: a third longitudinal portion located in the first region I and the third region III, a second transverse portion located in the third region III, and a fourth longitudinal portion located in the third region III. The third longitudinal portion and the fourth longitudinal portion are parallel to the first direction Y, the second transverse portion is parallel to the second direction X, and the second transverse portion connects the third longitudinal portion and the fourth longitudinal portion.

[0154] The second connection structure 219 is electrically connected to the second bit line 217 on the third region III, including: the projection of the second connection structure 219 on the substrate coincides with a portion of at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion on the third region III. This increases the process window for the formation of the second connection structure 219.

[0155] The projections of two adjacent first connecting structures 218 in the second direction X are at least partially overlapping or not overlapping; the projections of two adjacent second connecting structures 219 in the second direction X are at least partially overlapping or not overlapping.

[0156] In this embodiment, the projections of two adjacent first connecting structures 218 in the second direction X do not overlap, and the projections of two adjacent second connecting structures 219 in the second direction X do not overlap, so that the first connecting structures 218 and the second connecting structures 219 can have a large process window during the formation process.

[0157] In this embodiment, the first connection structure 218 and the second connection structure 219 are formed simultaneously.

[0158] The formation process of the first connection structure 218 and the second connection structure 219 includes: forming a dielectric structure (not shown) on the second surface of the substrate; forming a fifth opening and a sixth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the surface of the first bit line 216 on the second region II, and the sixth opening exposes at least a portion of the surface of the second bit line 217 on the third region III; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall surface and bottom surface of the fifth opening, the sidewall surface and bottom surface of the sixth opening, and the surface of the dielectric structure; planarizing the conductive material layer and the barrier material layer until the surface of the dielectric structure is exposed; forming the first connection structure 218 within the fifth opening and the second connection structure 219 within the sixth opening.

[0159] The barrier material layer is made of a metal nitride, including titanium nitride or tantalum nitride; the conductive material layer is made of a metal, including tungsten.

[0160] The semiconductor structure formed by the method has a smaller spacing between adjacent bit lines 216 and 217, and the process window for forming the first connection structure 218 and the second connection structure 219 is increased. The first connection structure 218 and the second connection structure 219 are easier to form, making it easier for the first bit line 216 to be connected to an external circuit through the first connection structure 218, and for the second bit line 217 to be connected to an external circuit through the second connection structure 219. This makes it easier to achieve individual control of the spaced bit lines and avoids capacitive coupling when two adjacent bit lines are energized at the same time.

[0161] Individual control is applied to the spaced-apart bit lines. Specifically, for the plurality of first bit lines 216 and the plurality of second bit lines 217 arranged along the second direction X, the first bit lines 216 and the second bit lines 217 in the odd number of positions are energized, or the first bit lines 216 and the second bit lines 217 in the even number of positions are energized. In this way, there is a bit line without working voltage between each pair of adjacent bit lines that are energized. The bit line without working voltage acts as a metal shield, which avoids the situation where capacitive coupling easily occurs when two adjacent bit lines are energized at the same time.

[0162] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 31 to 35 ,include:

[0163] A substrate comprising a first region I, a second region II, and a third region III distributed along a first direction Y parallel to the substrate surface, the first region I being located between the second region II and the third region III, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising: a plurality of active regions 201, the plurality of active regions 201 being arranged in parallel along a second direction X parallel to the substrate surface, the first direction Y being perpendicular to the second direction X being perpendicular to each other, the active regions 201 exposed on the second surface of the substrate comprising a first portion 214 and a second portion 215 being mutually separate; and a first isolation layer 230 located between adjacent active regions 201, the first surface and the second surface of the substrate exposing the surface of the first isolation layer 230.

[0164] A plurality of first cutting layers 203 located in the second region II cut the spaced first isolation layers 230. The first cutting layers 203 penetrate the first isolation layers 230 along the second direction X. The first surface of the substrate exposes the surface of the first cutting layers 203.

[0165] A plurality of second cutting layers 204 located in the third region III cut the first isolation layer 230 at intervals, the second cutting layers 204 penetrate the first isolation layer 230 along the second direction X, and the first surface of the substrate exposes the surface of the second cutting layers 204.

[0166] The word line gate structure is located in the first region I, and the word line gate structure is parallel to the second direction X;

[0167] A bit line structure located on the second surface of the substrate, the bit line structure including: a first bit line 216 electrically connected to the first portion 214, and a second bit line 217 electrically connected to the second portion 215;

[0168] A first connection structure 218 is located on the second region II, and the first connection structure 218 is electrically connected to the first bit line 216.

[0169] The second connection structure 219 is located on the third region III and is electrically connected to the second bit line 217.

[0170] In the semiconductor structure described, the spacing between adjacent bit lines 216 and 217 is small, the process window for forming the first connection structure 218 and the second connection structure 219 is increased, and the first connection structure 218 and the second connection structure 219 are easy to form. This makes it easier for the first bit line 216 to be connected to an external circuit through the first connection structure 218, and for the second bit line 217 to be connected to an external circuit through the second connection structure 219. It also makes it easy to achieve individual control of the spaced-apart bit lines and avoids the situation where capacitive coupling easily occurs when two adjacent bit lines are energized at the same time.

[0171] In this embodiment, the first cutting layer 203 has a larger dimension in the second direction X than the width of the first isolation layer 230, and the first cutting layer 203 is also located within the active regions 201 on both sides of the first isolation layer 230; the second cutting layer 204 has a larger dimension in the second direction X than the width of the first isolation layer 230, and the second cutting layer 204 is also located within the active regions 201 on both sides of the first isolation layer 230.

[0172] In this embodiment, the dimension of the first cutting layer 203 in the second direction X is greater than the sum of the widths of the first isolation layer 230, the first portion 214, and the second portion 215; the dimension of the second cutting layer 204 in the second direction X is greater than the sum of the widths of the first isolation layer 230, the first portion 214, and the second portion 215.

[0173] In this embodiment, the first cutting layer 203 and the second cutting layer 204 are located in the active regions 201 on both sides of the first isolation layer 230. The projections of the two ends of the first cutting layer 203 on the substrate in the second direction X are located between the first portion 214 and the second portion 215. The projections of the two ends of the second cutting layer 204 on the substrate in the second direction X are located between the first portion 214 and the second portion 215.

[0174] In this embodiment, the size of the first cutting layer 203 in the first direction Y is smaller than the size of the second region II; the size of the second cutting layer 204 in the first direction Y is smaller than the size of the third region III.

[0175] In this embodiment, the first portion 214 is located at least in the first region I and the second region II; the second portion 215 is located at least in the first region I and the third region III.

[0176] In this embodiment, a portion of the first portion 214 is also located in the third region III; a portion of the second portion 215 is also located in the second region II.

[0177] In this embodiment, the first portion 214 includes: a first vertical portion located in the first region I and the second region II, a first horizontal portion located in the second region II, and a second vertical portion located in the second region II. The first vertical portion and the second vertical portion are parallel to the first direction Y, and the first horizontal portion is parallel to the second direction X. The first horizontal portion connects the first vertical portion and the second vertical portion. The first connecting structure 218 is electrically connected to the first line 216 on the second region II, including: the projection of the first connecting structure 218 on the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion on the second region II.

[0178] In this embodiment, the second portion 215 includes: a third vertical portion located in the first region I and the third region III, a second horizontal portion located in the third region III, and a fourth vertical portion located in the third region III. The third vertical portion and the fourth vertical portion are parallel to the first direction Y, and the second horizontal portion is parallel to the second direction X. The second horizontal portion connects the third vertical portion and the fourth vertical portion. The second connection structure 219 is electrically connected to the second bit line 217 on the third region III, including: the projection of the second connection structure 219 on the substrate coincides with a partial area of ​​at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion on the third region III.

[0179] In this embodiment, a second isolation layer 213 is also included, located between the first portion 214 and the second portion 215.

[0180] In this embodiment, the projected area of ​​the first bit line 216 on the substrate is less than or equal to the projected area of ​​the first portion 214 on the substrate; the projected area of ​​the second bit line 217 on the substrate is less than or equal to the projected area of ​​the second portion 215 on the substrate.

[0181] In this embodiment, there is a first spacing between the first bit line 216 and the second bit line 217, and the active region 201 has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:4.

[0182] In this embodiment, the range of the first spacing is 5 nanometers to 50 nanometers; the range of the first width is 10 nanometers to 100 nanometers.

[0183] In this embodiment, it also includes: a plurality of capacitor structures 209 located on the first surface of the substrate, wherein one of the capacitor structures 209 is electrically connected to one of the active regions 201.

[0184] In this embodiment, it further includes a first source / drain doped region located within the active region 201 exposed on the first surface of the substrate, and the capacitor structure 209 is electrically connected to the first source / drain doped region.

[0185] In this embodiment, the bit line structure is electrically connected to the second source / drain doped region located in the first section 214 and the second section 215.

[0186] In this embodiment, the active region includes a channel region distributed along a direction perpendicular to the substrate surface, and the word line gate structure is adjacent to the channel region; the first portion 214 and the second portion 215 are connected to the channel region.

[0187] In this embodiment, the channel area includes a plurality of discrete channel columns 205 located in the first area I.

[0188] In this embodiment, the word line grid structure includes: a first word line grid 207 and a second word line grid 208. The first word line grid 207 and the second word line grid 208 are respectively located on the two side walls of the channel post 205 along the first direction Y. The first word line grid 207 and the second word line grid 208 are parallel to the second direction X. The first word line grid 207 and the second word line grid 208 are located within the first isolation layer 230. The first isolation layer 230 electrically isolates adjacent first word line grids 207 and second word line grids 208.

[0189] In this embodiment, the central axes of two adjacent channel posts 205 do not coincide in the first direction Y.

[0190] In another embodiment, the word grid structure includes: a plurality of word grids surrounding the channel post, wherein the plurality of word grids are connected along a second direction and are parallel to the second direction.

[0191] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of active regions arranged in parallel along a second direction parallel to the substrate surface, the first direction being perpendicular to the second direction; and an initial first isolation layer located between adjacent active regions, the first surface of the substrate exposing the surface of the initial first isolation layer; In the second region, the initial first isolation layer is cut at intervals to form a plurality of first cut layers penetrating the initial first isolation layer along a second direction in the second region, and the first surface of the substrate exposes the surface of the first cut layers. In the third region, the initial first isolation layer is cut at intervals, and a plurality of second cut layers are formed in the third region that penetrate the initial first isolation layer along a second direction. The first cut layer and the second cut layer respectively penetrate two adjacent initial first isolation layers, and the first surface of the substrate exposes the surface of the second cut layer. A word line gate structure is formed in the first region, the word line gate structure being parallel to the second direction; The active region exposed on the second surface of the substrate is removed, exposing the surfaces of the first cut-off layer and the second cut-off layer, wherein the first cut-off layer and the second cut-off layer form the active region into a first portion and a second portion that are mutually independent; A bit line structure is formed on the second surface of the substrate, the bit line structure comprising: a first bit line electrically connected to a first portion, and a second bit line electrically connected to a second portion; A first connection structure is formed on the second region, and the first connection structure is electrically connected to the first bit line; a second connection structure is formed on the third region, and the second connection structure is electrically connected to the second bit line.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first cutting layer has a dimension larger than the width of the initial first isolation layer in the second direction, and the first cutting layer is also located in the active regions on both sides adjacent to the initial first isolation layer; the second cutting layer has a dimension larger than the width of the initial first isolation layer in the second direction, and the second cutting layer is also located in the active regions on both sides adjacent to the initial first isolation layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The dimension of the first cutting layer in the second direction is greater than the sum of the widths of the initial first isolation layer, the first portion, and the second portion; the dimension of the second cutting layer in the second direction is greater than the sum of the widths of the initial first isolation layer, the first portion, and the second portion.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first cutting layer and the second cutting layer are located in the active regions on both sides of the initial first isolation layer. The projections of the two ends of the first cutting layer in the second direction onto the substrate are located between the first portion and the second portion. The projections of the two ends of the second cutting layer in the second direction onto the substrate are located between the first portion and the second portion.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first and second cutting layers are formed simultaneously. The formation process of the first and second cutting layers includes: forming a mask structure on a first surface of a substrate, the mask structure having a plurality of first openings, the first openings exposing a portion of the initial first isolation layer and a portion of the active region surface on both sides of the initial first isolation layer; etching the exposed initial first isolation layer and active region using the mask structure as a mask to form a first groove and a second groove in the substrate, the first groove being located in a second region and the second groove being located in a third region; forming a cutting material layer in the first groove, the second groove, and the first surface of the substrate; planarizing the cutting material layer until the active region surface is exposed, forming a first cutting layer in the first groove, and forming a second cutting layer in the second groove.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the first cutting layer is less than the depth of the initial first isolation layer; the depth of the second cutting layer is less than the depth of the initial first isolation layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first cutting layer has a smaller dimension in the first direction than the second region; the second cutting layer has a smaller dimension in the first direction than the third region.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first division is located at least in the first area and the second area; the second division is located at least in the first area and the third area.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, A portion of the first division is also located in the third region; a portion of the second division is also located in the second region.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first portion includes: a first vertical portion located in the first region and the second region, a first horizontal portion located in the second region, and a second vertical portion located in the second region. The first vertical portion and the second vertical portion are parallel to a first direction, and the first horizontal portion is parallel to a second direction. The first horizontal portion connects the first vertical portion and the second vertical portion. The first connecting structure is electrically connected to the first line on the second region, including: the projection of the first connecting structure on the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion on the second region.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The second portion includes: a third vertical portion located in the first region and the third region, a second horizontal portion located in the third region, and a fourth vertical portion located in the third region. The third vertical portion and the fourth vertical portion are parallel to a first direction, and the second horizontal portion is parallel to a second direction. The second horizontal portion connects the third vertical portion and the fourth vertical portion. The second connection structure is electrically connected to a second bit line on the third region, including: the projection of the second connection structure on the substrate coincides with a portion of at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion on the third region.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The active region includes a channel region distributed along a direction perpendicular to the substrate surface, and the word line gate structure is adjacent to the channel region; the first portion and the second portion are connected to the channel region.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, Removing a portion of the active region exposed on the second surface of the substrate to expose the surfaces of the first and second cut-off layers, wherein the first and second cut-off layers form the active region into mutually separate first and second portions, includes: etching back the active region exposed on the second surface of the substrate to form a third groove within an initial first isolation layer; forming a sidewall on the sidewall surface of the third groove, the sidewall exposing a portion of the surface of the active region; removing the exposed active region using the sidewall as a mask to form a fourth groove within the active region; removing the sidewall to form a second isolation layer within the fourth groove, the second isolation layer being in contact with the first and second cut-off layers; and removing the active region exposed on the second surface of the substrate until the surfaces of the first and second cut-off layers are exposed, thereby forming the active region into mutually separate first and second portions.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, Forming a sidewall on the surface of the third groove sidewall includes: forming a sidewall material layer on the surface and bottom surface of the third groove sidewall and on the second surface of the substrate; and etching back the sidewall material layer until the surface of the active region is exposed, thereby forming a sidewall on the third groove sidewall.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process of forming the fourth groove includes: removing the exposed active region using the sidewall as a mask until the surface of the channel region is exposed, and forming the fourth groove in the active region; the projections of the two ends of the first cutting layer on the substrate are located within the range of the fourth groove; the projections of the two ends of the second cutting layer on the substrate are located within the range of the fourth groove.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process of forming the second isolation layer, the first portion, and the second portion includes: after removing the sidewall, forming an isolation material layer in the third groove, the fourth groove, and the second surface of the substrate; planarizing the isolation material layer, the active region, and the initial first isolation layer until the surfaces of the first cut-off layer and the second cut-off layer are exposed; forming the second isolation layer in the fourth groove; forming the active region into a first portion and a second portion that are mutually independent; and forming the initial first isolation layer into the first isolation layer.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process of forming the second isolation layer, the first portion, and the second portion includes: after removing the sidewall, removing a portion of the active region exposed on the second surface of the substrate until the surface of the remaining active region is lower than or flush with the surfaces of the first cut-off layer and the second cut-off layer; forming an isolation material layer in the third groove, the fourth groove, and on the second surface of the substrate; planarizing the isolation material layer and the initial first isolation layer until the surface of the active region is exposed; forming the second isolation layer in the fourth groove, so that the active region is formed into a first portion and a second portion that are mutually independent, and forming the initial first isolation layer into the first isolation layer.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The process of forming a bit line structure on the second side of the substrate includes: etching back the first portion to form a third opening in the substrate; etching back the second portion to form a fourth opening in the substrate; forming a bit line material layer in the third opening, the fourth opening, and on the initial first isolation layer; planarizing the bit line material layer until the surface of the initial first isolation layer is exposed, forming the first bit line in the third opening, and forming the second bit line in the fourth opening.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, There is a first spacing between the first bit line and the second bit line, and the active region has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:

4.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

22. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first connection structure and the second connection structure are formed simultaneously. The formation process of the first connection structure and the second connection structure includes: forming a dielectric structure on a second surface of a substrate; forming a fifth opening and a sixth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the first bit line surface on the second region, and the sixth opening exposes at least a portion of the second bit line surface on the third region; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall surface and bottom surface of the fifth opening, the sidewall surface and bottom surface of the sixth opening, and the surface of the dielectric structure; planarizing the conductive material layer and the barrier material layer until the surface of the dielectric structure is exposed; forming a first connection structure within the fifth opening; and forming a second connection structure within the sixth opening.

23. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate formation process includes: providing an initial substrate, the initial substrate including a first region, a second region, and a third region distributed along a first direction parallel to the surface of the initial substrate, the initial substrate including: a substrate, a plurality of active regions located on the substrate, the plurality of active regions being arranged in parallel along a second direction parallel to the surface of the initial substrate, the first direction being perpendicular to the second direction, an initial first isolation layer located between adjacent active regions, the first surface of the initial substrate exposing the surface of the initial first isolation layer; after forming a word line gate structure located in the first region, the process further includes: removing the substrate to expose the surface of the initial first isolation layer and the surface of the active regions, thereby forming the substrate.

24. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the word line gate structure in the first region, the method further includes: forming a plurality of capacitor structures on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the active regions.

25. The method for forming a semiconductor structure as described in claim 24, characterized in that, Before forming several capacitor structures, the method further includes: performing a first ion implantation on the active region exposed on the first surface of the substrate to form a first source-drain doped region, wherein the capacitor structure is electrically connected to the first source-drain doped region.

26. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first portion and the second portion to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

27. The method for forming a semiconductor structure as described in claim 2, characterized in that, Before forming the word line grid structure located in the first region, the method further includes: etching the channel region of the active region to form the channel region into a plurality of discrete channel pillars located in the first region.

28. The method for forming a semiconductor structure as described in claim 27, characterized in that, The word line grid structure includes: a first word line grid and a second word line grid, the first word line grid and the second word line grid are respectively located on the two side walls of the channel post along the first direction, the first word line grid and the second word line grid are parallel to the second direction, the first word line grid and the second word line grid are located within the initial first isolation layer, and the initial first isolation layer electrically isolates adjacent first word line grids and second word line grids.

29. The method for forming a semiconductor structure as described in claim 28, characterized in that, The central axes of two adjacent trench columns do not coincide in the first direction.

30. The method for forming a semiconductor structure as described in claim 27, characterized in that, The word line grid structure includes: a plurality of word line grids surrounding the channel post, and the plurality of word line grids being connected along a second direction and parallel to the second direction.

31. A semiconductor structure, characterized in that, include: A substrate comprising a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising: a plurality of active regions arranged in parallel along a second direction parallel to the substrate surface, the first direction being perpendicular to the second direction, the active regions exposed on the second surface of the substrate comprising mutually separate first portions and second portions; and a first isolation layer located between adjacent active regions, the first surface and the second surface of the substrate exposing the surface of the first isolation layer; A plurality of first cutting layers located in the second region, the plurality of first cutting layers cutting through the spaced first isolation layers, the first cutting layers penetrating the first isolation layers along a second direction, the first surface of the substrate exposing the surface of the first cutting layers; A plurality of second cutting layers located in the third region, the plurality of second cutting layers cutting the spaced first isolation layer, the second cutting layers penetrating the first isolation layer along a second direction, the first surface of the substrate exposing the surface of the second cutting layers; A word line gate structure located in the first region, wherein the word line gate structure is parallel to the second direction; A bit line structure located on the second surface of a substrate, the bit line structure comprising: a first bit line electrically connected to a first portion, and a second bit line electrically connected to a second portion; A first connection structure located in the second region, the first connection structure being electrically connected to the first bit line; a second connection structure located in the third region, the second connection structure being electrically connected to the second bit line.

32. The semiconductor structure as described in claim 31, characterized in that, The first cutting layer has a dimension larger than the width of the first isolation layer in the second direction, and the first cutting layer is also located in the active regions on both sides adjacent to the first isolation layer; the second cutting layer has a dimension larger than the width of the first isolation layer in the second direction, and the second cutting layer is also located in the active regions on both sides adjacent to the first isolation layer.

33. The semiconductor structure as described in claim 32, characterized in that, The dimension of the first cutting layer in the second direction is greater than the sum of the widths of the first isolation layer, the first portion, and the second portion; the dimension of the second cutting layer in the second direction is greater than the sum of the widths of the first isolation layer, the first portion, and the second portion.

34. The semiconductor structure as described in claim 32, characterized in that, The first cutting layer and the second cutting layer are located in the active regions on both sides of the first isolation layer. The projections of the two ends of the first cutting layer in the second direction onto the substrate are located between the first portion and the second portion. The projections of the two ends of the second cutting layer in the second direction onto the substrate are located between the first portion and the second portion.

35. The semiconductor structure as described in claim 31, characterized in that, The first cutting layer has a smaller dimension in the first direction than the second region; the second cutting layer has a smaller dimension in the first direction than the third region.

36. The semiconductor structure as claimed in claim 31, characterized in that, The first division is located at least in the first area and the second area; the second division is located at least in the first area and the third area.

37. The semiconductor structure as described in claim 36, characterized in that, A portion of the first division is also located in the third region; a portion of the second division is also located in the second region.

38. The semiconductor structure as described in claim 36, characterized in that, The first portion includes: a first vertical portion located in the first region and the second region, a first horizontal portion located in the second region, and a second vertical portion located in the second region. The first vertical portion and the second vertical portion are parallel to a first direction, and the first horizontal portion is parallel to a second direction. The first horizontal portion connects the first vertical portion and the second vertical portion. The first connecting structure is electrically connected to the first line on the second region, including: the projection of the first connecting structure on the substrate coincides with a portion of at least one of the first vertical portion, the first horizontal portion, and the second vertical portion on the second region.

39. The semiconductor structure as described in claim 36, characterized in that, The second portion includes: a third vertical portion located in the first region and the third region, a second horizontal portion located in the third region, and a fourth vertical portion located in the third region. The third vertical portion and the fourth vertical portion are parallel to a first direction, and the second horizontal portion is parallel to a second direction. The second horizontal portion connects the third vertical portion and the fourth vertical portion. The second connection structure is electrically connected to a second bit line on the third region, including: the projection of the second connection structure on the substrate coincides with a portion of at least one of the third vertical portion, the second horizontal portion, and the fourth vertical portion on the third region.

40. The semiconductor structure as claimed in claim 31, characterized in that, Also includes: The second isolation layer is located between the first and second divisions.

41. The semiconductor structure as described in claim 31, characterized in that, The projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate.

42. The semiconductor structure as described in claim 31, characterized in that, There is a first spacing between the first bit line and the second bit line, and the active region has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:

4.

43. The semiconductor structure as described in claim 42, characterized in that, The first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

44. The semiconductor structure as claimed in claim 31, characterized in that, Also includes: A plurality of capacitor structures located on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the active regions.

45. The semiconductor structure as described in claim 44, characterized in that, Also includes: The first source / drain doped region is located within the active region exposed on the first surface of the substrate, and the capacitor structure is electrically connected to the first source / drain doped region.

46. ​​The semiconductor structure as claimed in claim 31, characterized in that, The second source / drain doped region is located within the first and second divisions, and the bit line structure is electrically connected to the second source / drain doped region.

47. The semiconductor structure as claimed in claim 31, characterized in that, The active region includes a channel region distributed along a direction perpendicular to the substrate surface, and the word line gate structure is adjacent to the channel region; the first portion and the second portion are connected to the channel region.

48. The semiconductor structure as claimed in claim 47, characterized in that, The trench area includes several separate trench columns located in the first area.

49. The semiconductor structure as described in claim 48, characterized in that, The word line grid structure includes: a first word line grid and a second word line grid, the first word line grid and the second word line grid are respectively located on the two side walls of the channel post along the first direction, the first word line grid and the second word line grid are parallel to the second direction, the first word line grid and the second word line grid are located within the first isolation layer, and the first isolation layer electrically isolates the adjacent first word line grid and the second word line grid.

50. The semiconductor structure as claimed in claim 49, characterized in that, The central axes of two adjacent trench columns do not coincide in the first direction.

51. The semiconductor structure as described in claim 48, characterized in that, The word line grid structure includes: a plurality of word line grids surrounding the channel post, and the plurality of word line grids being connected along a second direction and parallel to the second direction.

Images