Memory device, manufacturing method and control method

Abstract

The embodiment of the invention discloses a memory device, a manufacturing method and a control method, and the memory device comprises a row which comprises a plurality of first semiconductor columns arranged along a first direction; a column including a plurality of first semiconductor pillars arranged in a second direction; any two adjacent first semiconductor columns on the row are arranged at an interval of one column, and any two adjacent first semiconductor columns on the column are arranged at an interval of one row; the first semiconductor column comprises a first end and a second end which are oppositely arranged along a third direction; a conductive structure extending in a first direction between two adjacent rows; a gate layer extending along a first direction; the conductive structure and the gate layer are located on the two opposite sides of the first semiconductor column in the second direction, and the gate layer covers the side wall of the first semiconductor column in the second direction; the bit line extends in the second direction and is located on the side, close to the first end, of the first semiconductor column, and the bit line is coupled with the first end of the first semiconductor column.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device, a method for manufacturing the same, and a method for controlling the same. Background Technology

[0002] Some memory devices, such as Dynamic Random Access Memory (DRAM), may include a memory array and peripheral circuitry. The peripheral circuitry controls the memory array, performing read, write, or refresh operations. The memory array comprises multiple memory cells arranged in rows and columns. Each memory cell may include coupled transistors and capacitors. Turning on the transistors selects and accesses the capacitors. There is considerable room for improvement in both memory devices and their fabrication methods to enhance performance. Summary of the Invention

[0003] According to some aspects of embodiments of the present disclosure, a memory device is provided, comprising: rows including a plurality of first semiconductor pillars arranged along a first direction, with odd-numbered rows and even-numbered rows alternately arranged along a second direction;

[0004] The column includes a plurality of first semiconductor pillars arranged along the second direction, with odd-numbered columns and even-numbered columns alternately arranged along the first direction;

[0005] Any two adjacent first semiconductor pillars in the row are arranged with a column spaced apart, and any two adjacent first semiconductor pillars in the column are arranged with a row spaced apart.

[0006] The first semiconductor pillar extends along a third direction, and the first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction;

[0007] A conductive structure, extending along the first direction, is located between two adjacent rows;

[0008] A gate layer extends along the first direction and corresponds to the row; the conductive structure and the gate layer are located on opposite sides of the first semiconductor pillar along the second direction, and the gate layer covers the sidewall of the first semiconductor pillar along the second direction.

[0009] Bit lines extend along the second direction and are located on the side of the first semiconductor pillar near the first end; the bit lines correspond to the column and are coupled to the first end of the first semiconductor pillar.

[0010] In some embodiments, the first gate layer in the gate layer is configured to apply a first operating voltage to select the first row;

[0011] The odd-numbered bit lines corresponding to the first row are configured to apply a second operating voltage to select the odd-numbered columns in the first row, and the even-numbered bit lines corresponding to the first row are configured to apply a first preset voltage; or,

[0012] The even-numbered bit lines corresponding to the first row are configured to apply the second operating voltage to select the even-numbered column on the first row, and the odd-numbered bit lines corresponding to the first row are configured to apply the first preset voltage.

[0013] In some embodiments, the conductive structure is configured to apply a second preset voltage.

[0014] According to some aspects of embodiments of this disclosure, a method for manufacturing a memory device is provided, comprising:

[0015] The semiconductor layer is etched to form a plurality of first trenches arranged along a first direction, and the first trenches extend along a second direction; the first trenches divide the semiconductor layer into column structures.

[0016] The column structure is etched to form first semiconductor pillars arranged along the second direction; the first semiconductor pillar includes a first end and a second end disposed opposite each other along a third direction, and the first semiconductor pillars on two adjacent columns are offset from each other along the second direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction;

[0017] A gate dielectric layer and a gate layer are formed on one side of the first semiconductor pillar along the second direction; the gate layer extends along the first direction and covers the sidewall of the first semiconductor pillar along the second direction.

[0018] A conductive structure extending in the second direction is formed on one side of the first semiconductor pillar along the second direction, and the conductive structure and the gate layer are located on opposite sides of the first semiconductor pillar along the second direction.

[0019] A bit line is formed on the side of the first semiconductor pillar near the first end, the bit line extending along the second direction and coupled to the first end of the first semiconductor pillar.

[0020] According to some aspects of embodiments of this disclosure, a control method for a memory device is provided, applied to any of the memory devices described in any one of the present disclosures, wherein the gate layer of the memory device is configured as a word line, and the control method includes:

[0021] A first operating voltage is applied to the first word line in the word lines to select the first row;

[0022] Apply a second operating voltage or float to the odd-numbered bit lines corresponding to the first row, and apply a first preset voltage to the even-numbered bit lines corresponding to the first row to select the odd-numbered column in the first row; or,

[0023] Apply the second operating voltage or float to the even-numbered bit lines corresponding to the first row, and apply the first preset voltage to the odd-numbered bit lines corresponding to the first row to select the even-numbered column in the first row.

[0024] In some embodiments, the control method further includes:

[0025] A second preset voltage is applied to the conductive structure in the memory device.

[0026] This disclosure provides a memory device comprising a semiconductor pillar array consisting of a plurality of spaced-apart first semiconductor pillars, a row consisting of a plurality of first semiconductor pillars arranged along a first direction, and a column consisting of first semiconductor pillars arranged along a second direction; any two adjacent first semiconductor pillars in a row are arranged with a column gap, and any two adjacent first semiconductor pillars in a column are arranged with a row gap, i.e., the first semiconductor pillars in any two adjacent columns are offset from each other along the second direction; a conductive structure extending along the first direction is located between two adjacent rows; a gate layer corresponding to the row covers the sidewalls of the first semiconductor pillars along the second direction, and the conductive structure and the gate layer are located on opposite sides of the first semiconductor pillars along the second direction. The bit lines corresponding to the columns extend along the second direction and are located on the side of the first semiconductor pillar near the first end. The bit lines are coupled to the first end of the first semiconductor pillar, which can be coupled to a capacitor structure. The first semiconductor pillars of adjacent columns are staggered to reduce mutual interference between the first semiconductor pillars. One of the odd-numbered bit lines and the even-numbered bit lines can be selected for operation by applying an operating voltage or floating. Other bit lines are subjected to other voltages to reduce crosstalk, that is, any two bit lines that are operating are separated by a non-operating bit line to reduce crosstalk. The conductive structure can apply the transistor's turn-off voltage or ground to reduce crosstalk between adjacent first semiconductor pillars and improve the stability of the memory device. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an exemplary storage array according to an exemplary embodiment;

[0028] Figure 2 This is a schematic diagram of a semiconductor pillar distribution according to an exemplary embodiment;

[0029] Figures 3 to 10 This is a schematic diagram of an exemplary memory device shown according to embodiments of the present disclosure;

[0030] Figure 11 This is a flowchart illustrating the fabrication process of an exemplary memory device according to embodiments of the present disclosure;

[0031] Figures 12 to 22 This is a schematic diagram illustrating a method for fabricating a memory device according to an embodiment of the present disclosure;

[0032] Figure 23 This is a schematic diagram of a memory device control method according to an embodiment of the present disclosure. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., are used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "below" or "under" or "below" other elements or features would be oriented "on" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations) and the spatial description used herein shall be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0038] The memory device in the embodiments of this disclosure may be DRAM, or at least a portion of DRAM, or the memory device may include DRAM, which includes the memory device of this disclosure. It is applicable to Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) using DDR4 memory specifications, DDR5 memory specifications, and Low Power Double Data Rate DRAM using LPDDR5 memory specifications. It should be noted that the embodiments of this disclosure are not limited to DRAM, but for clarity, DRAM will be used as an example in the following description.

[0039] In DRAM, memory arrays can be arranged in rows and columns, allowing memory cells to be addressed by specifying their rows and columns. A memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting the memory cell at the intersection of the selected word line and bit line selects it for read, write, or refresh operations. Figure 1As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. Memory cells within the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. The word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have an additional voltage (such as Vcc / 2) applied to it. Figure 1 As shown, the memory cell array is arranged in an x-row, y-column configuration. The rows and columns can be perpendicular or non-perpendicular. The x-direction can be the first direction mentioned in the embodiments of this disclosure, and the y-direction can be the second direction mentioned in the embodiments of this disclosure. The extension direction of the word line or row can be parallel to the x-direction or at an angle to the x-direction. The extension direction of the bit line or column can be parallel to the y-direction or at an angle to the y-direction. The orthogonal projection of the word line on the xoy plane is perpendicular to the orthogonal projection of the bit line on the xoy plane, or it is not perpendicular but at a certain angle. This disclosure does not limit this. The z-direction in the examples shown below can be a third direction. The z-direction can be perpendicular to the xoy plane, or it can intersect the xoy plane but not perpendicular to it. The z-direction can be a vertical direction, and the z-direction can be the wafer thickness direction or the device thickness direction.

[0040] The memory array of this disclosure embodiment has memory cells arranged in rows and columns. A row of the memory array may include transistors arranged along the x-direction and capacitors coupled to the transistors. A row may also be called a sub-memory array. A column of the memory array may include transistors arranged along the y-direction and capacitors coupled to the transistors. A column may also be called a sub-memory array.

[0041] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0042] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0043] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1 Peripheral circuitry coupled to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to: a sensing amplifier circuit, a row decoding circuit, a column decoding circuit, and a voltage generation circuit. The sensing amplifier circuit is coupled to bit lines and can be configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sensing amplifier circuit may include a latch to latch the reconstructed capacitor voltage value, thereby transferring the information stored in the memory cell from the capacitor to the amplifier circuit. The sensing amplifier circuit may include a differential sensing amplifier circuit coupled to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuit is configured to address the memory array and apply an operating voltage to the word lines. The column decoding circuit is configured to column address the memory array, apply a bit line voltage, or receive a bit line voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0044] According to some aspects of embodiments of this disclosure, Figure 2 An exemplary transistor layout is provided, wherein the transistor includes a semiconductor pillar 101 or an active pillar, the semiconductor pillar 101 extending along the z-direction, and a gate 102 surrounding the sidewalls of the semiconductor pillar 101 extending along the z-direction. The gate 102 and the semiconductor pillar 101 are separated by a gate dielectric layer. The gate 102 serves as the control terminal of the transistor to control the transistor's on and off states by applying a voltage. The opposite ends of the semiconductor pillar 101 along the z-direction are doped to form active regions, which respectively serve as the source or drain of the transistor. The region between the source and drain forms the transistor channel, and the positions of the source and drain are interchangeable. The gate 102 can serve as a word line of a memory device, extending along the x-direction, and can be coupled to or correspond to multiple semiconductor pillars 101 arranged in the x-direction. The semiconductor pillars 101 penetrate the gate 102 along the z-direction and have both ends exposed. A bit line 103 is coupled to one end of the semiconductor pillar 101 (such as one of the source or drain). The bit line 103 extends along the y-direction and can be coupled to or correspond to multiple semiconductor pillars 101 arranged in the y-direction. Figure 2 As shown, semiconductor pillars 101 on any two adjacent columns are aligned with each other, and semiconductor pillars 101 on any two adjacent rows are aligned with each other. When the integration density of transistors increases, when adjacent columns are selected or accessed to perform operations, the small spacing between semiconductor pillars 101 may cause crosstalk. The small spacing between bit lines 103 may also cause crosstalk and lead to a reduction in the sensing window of bit line 103, thereby reducing the operating accuracy and stability of memory devices.

[0045] In view of this, an exemplary memory device 200 is provided according to some aspects of embodiments of the present disclosure, such as... Figure 3 This is a cross-sectional schematic diagram of the memory device 200 in the xoy plane, or a planar distribution schematic diagram. Different locations of the same structure may have different cross-sectional morphologies or structures. Figure 4 , Figure 5 as well as Figure 6 yes Figure 3 Schematic diagrams of cross-sections at AA' (parallel to the y-direction), BB' (parallel to the y-direction), and CC' (parallel to the x-direction) in the structure; combined with Figures 3 to 6 As shown, the memory device 200 includes:

[0046] The row includes a plurality of first semiconductor pillars 201 arranged along a first direction (x direction), with odd-numbered rows and even-numbered rows arranged alternately along a second direction (y direction);

[0047] The column includes a plurality of first semiconductor pillars 201 arranged along the y direction, with odd columns and even columns alternately arranged along the x direction;

[0048] Any two adjacent first semiconductor pillars 201 in the row are arranged with a column spaced apart, and any two adjacent first semiconductor pillars 201 in the column are arranged with a row spaced apart.

[0049] The first semiconductor pillar 201 extends along a third direction (z direction), and the first semiconductor pillar 201 includes a first end and a second end disposed opposite to each other along the z direction; wherein the x direction intersects the y direction, and the plane formed by the x direction and the y direction intersects the z direction;

[0050] Conductive structure 202 extends along the x-direction and is located between two adjacent rows;

[0051] Gate layer 203 extends along the x direction and corresponds to the row; conductive structure 202 and gate layer 203 are located on opposite sides of the first semiconductor pillar 201 along the y direction, and gate layer 203 covers the sidewall of the first semiconductor pillar 201 along the y direction.

[0052] Bit line 204 extends along the y direction and is located on the side of the first semiconductor pillar 201 near the first end; bit line 204 corresponds to the column and is coupled to the first end of the first semiconductor pillar 201.

[0053] In some embodiments, the memory device 200 further includes a gate dielectric layer 205 located between the gate layer 203 and the first semiconductor pillar 201.

[0054] In some embodiments, the memory device 200 further includes a capacitor structure 206 located on the side of the first semiconductor pillar 201 away from the capacitor structure 206, and the capacitor structure 206 is coupled to a second end of the first semiconductor pillar 201. The capacitor structure 206 may be as follows: Figure 7 As exemplified, capacitor structure 206 may include a first electrode, a second electrode, and an insulating layer located between the first electrode and the second electrode. This disclosure does not limit the capacitor structure 206. For example, capacitor structure 206 may include a first electrode extending along the z-direction, the first electrode being columnar, an insulating layer surrounding the first electrode, and a second electrode surrounding the insulating layer. The second electrode is located close to the first semiconductor column 201 relative to the first electrode, and is coupled to a second end of the first semiconductor column 201 or through other connecting portions, which may include, but are not limited to, metal, metal silicide, or combinations thereof. The first electrode is grounded or connected to another common voltage, and multiple capacitor structures 206 may share the first electrode.

[0055] Reference Figure 4 As shown, the memory device 200 may include multiple rows extending along the x-direction. Each row may include first semiconductor pillars 201 spaced apart relative to the columns in the x-direction, and each row may include a capacitor structure 206 coupled to the second end of the first semiconductor pillars 201. Columns extend along the y-direction and intersect the rows. Each column may include first semiconductor pillars 201 spaced apart relative to the rows in the y-direction, and capacitor structures 206 coupled to the second end of the first semiconductor pillars 201. For any row, the first semiconductor pillars 201 may be provided in odd-numbered columns, and not in even-numbered columns; or the first semiconductor pillars 201 may be provided in even-numbered columns, and not in odd-numbered columns. For any column, the first semiconductor pillars 201 may be provided in odd-numbered rows, and not in even-numbered rows; or the first semiconductor pillars 201 may be provided in even-numbered rows, and not in odd-numbered rows. The first semiconductor pillars 201 are arranged at intervals in rows, with a one-column gap between any two columns corresponding to any two first semiconductor pillars 201, and that column having no first semiconductor pillars 201; the first semiconductor pillars 201 are also arranged at intervals in columns, with a one-row gap between any two rows corresponding to any two first semiconductor pillars 201, and that row having no first semiconductor pillars 201. Odd-numbered columns in odd-numbered rows have first semiconductor pillars 201, and even-numbered columns in even-numbered rows have first semiconductor pillars 201, while the intersections of other rows and columns do not have first semiconductor pillars 201; or, even-numbered columns in odd-numbered rows have first semiconductor pillars 201, and odd-numbered columns in even-numbered rows have first semiconductor pillars 201, while the intersections of other rows and columns do not have first semiconductor pillars 201.

[0056] For example, refer to Figure 3As shown, the intersection of the first row and the first column may have a first semiconductor pillar 201, the intersection of the second row and the second column may have a first semiconductor pillar 201, and the intersections of other rows and columns may not have a first semiconductor pillar 201. For example, the intersection of the first row and the second column may have a first semiconductor pillar 201, the intersection of the second row and the first column may have a first semiconductor pillar 201, and the intersections of other rows and columns may not have a first semiconductor pillar 201.

[0057] For a structural diagram of adjacent columns, please refer to Figure 4 and Figure 5 The example row structure diagram can be found by referring to... Figure 6 As illustrated in the embodiments of this disclosure, the number of rows and columns is not limited, nor is the number of first semiconductor pillars 201 limited. A transistor may include a first semiconductor pillar 201, a gate layer portion corresponding to the first semiconductor pillar 201, and a gate dielectric layer 205 portion. The first semiconductor pillar 201 extends along the z-direction. A first end of the first semiconductor pillar 201 may be the bottom in the negative z-direction, and a second end may be the top in the positive z-direction. Both the first and second ends may be homo-doped source or drain electrodes. The middle portion between the first and second ends forms the transistor channel, which is inversely doped compared to the first end. The gate layer 203, serving as the control gate of the transistor, may be located on the sidewall of the middle portion of the transistor. The gate layer 203 covers the sidewall of the middle portion along the y-direction, and is spaced from the first semiconductor pillar 201 by the gate dielectric layer 205. The first end of the first semiconductor pillar 201 is coupled to a bit line 204 at the bottom of the first semiconductor pillar 201, and the second end is coupled to a capacitor structure 206 at the top of the first semiconductor pillar 201. The gate layer 203 serves as the word line of the memory device 200 and corresponds to the first semiconductor pillar 201 on the row. The gate dielectric layer 205 is located at least on the middle sidewall of the first semiconductor pillar 201 or surrounds the sidewall of the first semiconductor pillar 201. The gate dielectric layer 205 may cover other sidewall areas of the first semiconductor pillar 201 but exposes the top surface of the second end to facilitate coupling of the capacitor structure 206.

[0058] Reference Figure 4 and Figure 5 As shown in the example, the first semiconductor pillar 201 is used to construct a transistor array, to be coupled with the capacitor structure 206 to form a DRAM memory cell, or to be coupled with other device structures to form logic circuits such as gate circuits. The staggered arrangement of the first semiconductor pillars 201 reduces crosstalk between two adjacent first semiconductor pillars 201 in a row and reduces crosstalk between two adjacent first semiconductor pillars 201 in a column.

[0059] In some embodiments, for two adjacent first semiconductor pillars 201 in the y-direction, or for two adjacent rows, one row corresponds to one gate layer 203. Two gate layers 203 are arranged face-to-face between the two rows, separated by a dielectric material, an air gap, or a dielectric material with an air gap. The conductive structure 202 and the gate layer 203 are arranged opposite to the first semiconductor pillars 201 in the y-direction, separated by a dielectric material. The explanation is illustrated using six consecutive rows as examples. Figure 4 The first semiconductor pillar 201 corresponding to three consecutive odd-numbered rows and the gate layer 203 corresponding to six consecutive rows are shown; Figure 5 This shows the first semiconductor pillar 201 corresponding to three consecutive even-numbered rows and the gate layer 203 corresponding to six consecutive rows; the gate layer 203 is located at... Figure 4 On the right side of the odd-numbered rows, gate layer 203 is located Figure 5 On the left side of even-numbered rows, conductive structure 202 is located between two adjacent rows and on the side without gate layer 203. Conductive structure 202 can be connected to negative voltage, ground, or a preset voltage such as Vcc / 2 to reduce crosstalk between adjacent transistors and improve device stability.

[0060] In some embodiments, the two protruding ends of the bit line 204 in the y-direction can be used to couple with a connection structure. The connection structure may include conductive plugs, conductive channels, or other structures for powering the bit line 204 or sensing signals from the bit line 204. The connection structure may be disposed on the side of the bit line 204 closer to the first semiconductor pillar 201 in the z-direction, or the connection structure may be disposed on the side of the bit line 204 farther from the first semiconductor pillar 201 in the z-direction.

[0061] For example, the materials constituting the gate layer 203 and the connection structure may include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum. The materials constituting the semiconductor pillars may include, but are not limited to, elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. The bit line 204 may include a metallic conductive material, or it may include a semiconductor metallization material, such as titanium silicide, nickel silicide, or other metal silicides. The bit line 204 may also be formed by heavily doping semiconductor materials to create conductive lines.

[0062] In some embodiments, combined with Figure 3 As shown, the memory device 200 includes:

[0063] Two adjacent first conductive structures 202a and second conductive structures 202b, two adjacent first rows 21a and second rows 21b, and two adjacent first gate layers 203a and second gate layers 203b; wherein the first conductive structures 202a, first rows 21a, first gate layers 203a, second gate layers 203b, second rows 21b, and second conductive structures 202b are arranged sequentially along the y-direction. This disclosure embodiment can be referred to. Figure 3 The arrangement pattern shown involves arranging more rows, gate layer 203, and conductive structure 202.

[0064] In some embodiments, refer to Figure 4 and Figure 5 The schematic diagram of the column cross section shown shows that the bottoms of multiple first semiconductor pillars 201 in the y direction can be connected to each other through semiconductor materials, or the first semiconductor pillars 201 and the semiconductor materials connected to the bottoms can be an integral structure, with no physical boundary or an indistinct physical boundary between them. The first semiconductor pillars 201 are formed by etching semiconductor layers 2001 or semiconductor materials, and the semiconductor materials connected to the bottoms are the remaining structure after etching. The first semiconductor pillars 201 can be doped to form the active region and channel of a transistor.

[0065] In some embodiments, refer to Figure 4 and Figure 5 As shown, the column also includes:

[0066] A semiconductor strip 2011 extends along the y-direction and is located on the side of the first semiconductor pillar 201 near the first end; the semiconductor strip 2011 is connected to the first semiconductor pillar 201.

[0067] In some embodiments, refer to Figure 4 and Figure 5 As shown, bit line 204 is located on the side of semiconductor strip 2011 away from the first semiconductor pillar 201;

[0068] Semiconductor strip 2011 includes silicon, and bit line 204 includes metal silicide.

[0069] In some embodiments, refer to Figure 4 The schematic cross-sectional view of the column shown includes a bit line 204, which corresponds to a column; adjacent first semiconductor pillars 201 can be interrupted or connected via semiconductor material. Different regions of this embodiment can be electrically isolated by dielectric material. The gate dielectric layer 205 and the dielectric material may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Dielectric materials of the same composition and film layers such as the gate dielectric layer 205 may not have obvious physical boundaries after contact.

[0070] Semiconductor strip 2011 and first semiconductor pillar 201 are made of the same material, such as silicon. Semiconductor strip 2011 is the leftover material from etching semiconductor material to form first semiconductor pillar 201 and second semiconductor pillar 207, used to reduce the etching depth. Semiconductor strip 2011 can be used to form bit line 204 or to carry bit line 204. There may be no clear physical boundary between semiconductor strip 2011 and first semiconductor pillar 201.

[0071] Bit lines 204 can be formed based on semiconductor strip 2011. For example, the semiconductor strip 2011 can be metallized to form a metal compound to constitute bit lines 204; or metal material can be deposited on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction to form bit lines 204; or the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction can be heavily doped to form conductive lines. For example, semiconductor strip 2011 may include silicon. Metal material can be deposited on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction and heat-treated. A portion of the silicon in semiconductor strip 2011 reacts with the metal material to form a metal silicide layer to form bit lines 204. The metal silicide may include, but is not limited to, titanium silicide, nickel silicide, etc. For example, conductive materials such as tungsten, aluminum, and titanium can be deposited on the metal silicide to form bit lines 204 with a composite material layer, improving the electrical connection performance between bit lines 204 and the first semiconductor pillar 201 and reducing contact resistance.

[0072] In some embodiments, refer to Figure 6 The schematic cross-sectional view shown illustrates multiple bit lines 204. Semiconductor material between adjacent first semiconductor pillars 201 in the x-direction is removed to form a spaced arrangement, isolated by a dielectric material. Remaining semiconductor material between the first semiconductor pillars 201 can be used to form or support bit lines 204. A bit line 204 corresponds to the bottom of a first semiconductor pillar 201. A bit line 204 exists in the region between two adjacent first semiconductor pillars 201. Adjacent bit lines 204 are isolated by a dielectric material.

[0073] In some embodiments, Figure 8 This diagram shows a cross-sectional view, or a planar distribution view, of the memory device 200 including the second semiconductor pillar 207 in the xoy plane. Figure 8 The second semiconductor pillar 207 is set in Figure 3At the intersections of rows and columns where no first semiconductor structure is provided, that is, between any two first semiconductor pillars 201 in each row, there is a second semiconductor pillar 207, and between any two first semiconductor pillars 201 in each column, there is a second semiconductor pillar 207. The second semiconductor pillar 207 is not used for electrical connection of the circuit structure. The second semiconductor pillar 207 is used to provide physical support for the device structure and to space between two adjacent first semiconductor pillars 201, so as to realize the staggered arrangement of the first semiconductor pillars 201, reduce crosstalk between two adjacent first semiconductor pillars 201 in a row, and reduce crosstalk between two adjacent first semiconductor pillars 201 in a column.

[0074] Figure 9 , Figure 10 yes Figure 8 Cross-sectional schematic diagrams of the middle structure at DD' and EE' respectively; refer to Figures 8 to 10 As shown, the row further includes: a second semiconductor pillar 207, which is arranged alternately with the first semiconductor pillar 201 along the x-direction;

[0075] The column also includes: a second semiconductor pillar 207, which is arranged alternately with the first semiconductor pillar 201 along the y direction;

[0076] The second semiconductor pillar 207 extends along the z-direction. The dimension of the second semiconductor pillar 207 in the z-direction is smaller than that of the first semiconductor pillar 201 in the z-direction. The height of the top surface of the second end of the first semiconductor pillar 201 is greater than the height of the top surface of the end of the second semiconductor pillar 207 furthest from the bit line 204. The second end of the first semiconductor pillar 201 is higher than the upper end of the second semiconductor pillar 207, facilitating coupling between the upper end of the first semiconductor pillar 201 and devices such as the capacitor structure 206, reducing the electrical connection distance in the z-direction, and improving the integration density of the memory device 200 in the z-direction. The bottom of the first semiconductor pillar 201 and the bottom of the second semiconductor pillar 207 can be connected by a semiconductor material, forming a continuous integral structure. The bottoms of the first semiconductor pillar 201 and the second semiconductor pillar 207 can be at the same film layer height or at different film layer heights.

[0077] In some embodiments, refer to Figure 8 As shown, the intersection of the first row and the first column can be a first semiconductor pillar 201, the intersection of the first row and the second column can be a second semiconductor pillar 207, the intersection of the second row and the first column can be a second semiconductor pillar 207, and the intersection of the second row and the second column can be a first semiconductor pillar 201. In some other specific embodiments, the intersection of the first row and the first column can be a second semiconductor pillar 207, the intersection of the first row and the second column can be a first semiconductor pillar 201, the intersection of the second row and the first column can be a first semiconductor pillar 201, and the intersection of the second row and the second column can be a second semiconductor pillar 207.

[0078] This disclosure does not limit the cross-sectional shape of the first semiconductor pillar 201 in the xoy plane. The square shape is just an example. It may be any shape, such as a rectangle, circle, rhombus, trapezoid, ellipse, or an irregular shape.

[0079] In some embodiments, refer to Figure 9 The schematic cross-sectional view of the column shown illustrates that the column includes a semiconductor strip 2011 extending along the y-direction, located on the side of the first semiconductor pillar 201 near its first end; the semiconductor strip 2011 connects the first semiconductor pillar 201 and the second semiconductor pillar 207. The semiconductor strip 2011, the first semiconductor pillar 201, and the second semiconductor pillar 207 are made of the same material, such as silicon. The semiconductor strip 2011 is leftover material from the etching process of the semiconductor material to form the first semiconductor pillar 201 and the second semiconductor pillar 207, used to reduce the etching depth. The semiconductor strip 2011 can be used to form bit lines 204 or to support bit lines 204. There may be no clear physical boundary between the semiconductor strip 2011, the first semiconductor pillar 201, and the second semiconductor pillar 207. Figure 9 In this configuration, for any given column, the gate layer 203 is located between the first semiconductor pillar 201 and the second semiconductor pillar 207, and the conductive structure 202 is located between the first semiconductor pillars 201.

[0080] In some embodiments, refer to Figure 10 The schematic cross-sectional view shown illustrates multiple bit lines 204. The first semiconductor pillar 201 and the second semiconductor pillar 207 in the x-direction are interrupted and isolated by a dielectric material. Each bit line 204 corresponds to a bottom of the first semiconductor pillar 201 and a bottom of the second semiconductor pillar 207. Adjacent bit lines 204 are isolated by a dielectric material. (Refer to...) Figure 9 The schematic cross-sectional view of the column shown includes a bit line 204 corresponding to a column; the first semiconductor pillar 201 and the second semiconductor pillar 207 can be broken or connected via semiconductor material. The gate dielectric layer 205 can cover the sidewalls and top surface of the second semiconductor pillar 207. The gate dielectric layer 205 has the same composition as other dielectric materials and may not have physical boundaries.

[0081] In some embodiments, Figures 3 to 10 The illustrated memory device 200 can be used as a memory device, or as part of a memory device, wherein a first gate layer 203 of a plurality of gate layers 203 is configured to apply a first operating voltage to select a first row; the first gate layer 203 is any one of the plurality of gate layers 203, the odd-numbered bit lines 204 corresponding to the first row are configured to apply a second operating voltage or float to select odd-numbered columns on the first row, and the even-numbered bit lines 204 corresponding to the first row are configured to apply a first preset voltage; or,

[0082] The even-numbered bit line 204 corresponding to the first row is configured to apply a second operating voltage or float to select the even-numbered column on the first row, and the odd-numbered bit line 204 corresponding to the first row is configured to apply a first preset voltage.

[0083] A first operating voltage is applied to the selected word line to be operated on. The first operating voltage is greater than or equal to the threshold voltage of the transistor (or the first semiconductor pillar 201) to turn on the transistor. Other voltages are applied to the unselected word lines that do not require operation to turn off the transistors and reduce inter-line crosstalk. When a memory cell performs a write operation, a second operating voltage, such as Vcc or 0, is applied to the selected bit line to be operated on; a first preset voltage, such as Vcc / 2 or other fixed voltage, is applied to the other unselected bit lines. When a read operation is performed, the selected bit line to be operated on is floated, and the first preset voltage Vcc / 2 is applied to the other unselected bit lines.

[0084] Different read, write, and refresh operations on the memory device 200 require different operating voltages and timings. The first and second operating voltages can be applied with different values ​​depending on the timing. These voltages can be generated and applied within their respective voltage fluctuation ranges, specifically generated by a voltage generator in the peripheral circuit and applied to the gate layer 203 (word line) and bit line 204 at the corresponding address. The first preset voltage is a fixed or static voltage, a calibration value used for testing the memory device, such as Vcc / 2 or another voltage. It is applied to the unselected bit line 204, preventing the transistor and capacitor structure 206 corresponding to the unselected bit line 204 from being accessed for operation.

[0085] In some embodiments, taking any one of multiple rows as an example of the target behavior, the first semiconductor pillar 201 is located on the odd-numbered columns of the first row. A first operating voltage is applied to the gate layer 203 corresponding to the first row, and all transistors in the first row are turned on and selected. A cutoff voltage is applied to the gate layer 203 corresponding to other rows to turn off the transistors. If all or some odd-numbered bit lines 204 in the first row need to be selected to perform an operation, a second operating voltage is applied to some selected odd-numbered bit lines 204 or they are floated, and a first preset voltage, which can be 1 / 2Vcc, that is, the average potential value between the high potential 1 and the low potential of the bit line 204, is applied to some or all even-numbered bit lines 204 to prevent crosstalk between adjacent transistors in the first row and improve device stability. Adapted to the arrangement of the first semiconductor pillar 201 and / or the second semiconductor pillar 207 in the first row, the first semiconductor pillar 201 on the selected odd-numbered columns can be separated by the even-numbered bit lines 204 or the second semiconductor pillar 207 to reduce crosstalk between the first semiconductor pillars 201 and between transistors.

[0086] In other embodiments, the arrangement of the first semiconductor pillar 201 and / or the second semiconductor pillar 207 on the first row is adapted to the even-numbered columns of the first row. If all or some even-numbered bit lines 204 on the first row need to be selected for operation, a second operating voltage is applied to or the even-numbered bit lines 204 are floated, and a first preset voltage is applied to some or the odd-numbered bit lines 204 to prevent crosstalk between adjacent transistors in the first row. The first semiconductor pillar 201 on the selected even-numbered column can be separated by the odd-numbered bit lines 204 or the second semiconductor pillar 207 to reduce crosstalk between the first semiconductor pillars 201.

[0087] In some embodiments, the conductive structure 202 is configured to apply a second preset voltage to reduce crosstalk between adjacent transistors and improve device stability. The conductive structure 202 applies a second preset voltage, which is a fixed voltage or a static voltage, and may be the turn-off voltage of the corresponding transistor to reduce crosstalk between transistors. For example, a negative voltage may be applied for an NMOS transistor, and a positive voltage may be applied for a PMOS transistor. In other embodiments, the second preset voltage may be a ground voltage.

[0088] According to some aspects of embodiments of this disclosure, Figure 11 A method for manufacturing a memory device 200 is provided, comprising:

[0089] The semiconductor layer is etched to form a plurality of first trenches arranged along a first direction, and the first trenches extend along a second direction; the first trenches divide the semiconductor layer into column structures.

[0090] The column structure is etched to form first semiconductor pillars arranged along the second direction; the first semiconductor pillar includes a first end and a second end disposed opposite each other along a third direction, and the first semiconductor pillars on two adjacent columns are offset from each other along the second direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction;

[0091] A gate dielectric layer and a gate layer are formed on one side of the first semiconductor pillar along the second direction; the gate layer extends along the first direction and covers the sidewall of the first semiconductor pillar along the second direction.

[0092] A conductive structure extending in the second direction is formed on one side of the first semiconductor pillar along the second direction, and the conductive structure and the gate layer are located on opposite sides of the first semiconductor pillar along the second direction.

[0093] A bit line is formed on the side of the first semiconductor pillar near the first end, the bit line extending along the second direction and coupled to the first end of the first semiconductor pillar.

[0094] Reference Figure 12 As shown, etching the semiconductor layer 2001 forms a first trench 211 extending along the y-direction. Multiple first trenches 211 are arranged along the x-direction. The first trenches 211 may penetrate the semiconductor layer 2001 or may not completely penetrate it, such as... Figure 12 The bottom of the first trench 211 is located in the semiconductor layer 2001 but does not completely penetrate it. The semiconductor layer 2001 can be a semiconductor substrate or a wafer, or a semiconductor layer 2001 deposited on a substrate, and the semiconductor layer 2001 can be thinned on the back side. Figure 12 Part a is a cross-sectional view of the first trench 211 in the xoy plane, and part b is a cross-sectional view of the first trench 211 at FF' in the xoz plane, wherein the first trench 211 is filled with dielectric material. Figure 12 Part b includes multiple column structures arranged along the x-direction.

[0095] Reference Figure 13 As shown, the column structure is etched to form multiple spaced openings, forming a fence structure, and forming the first semiconductor pillars 201 arranged along the y-direction. Figure 13 A cross-sectional view of a column in the yoz plane is shown. The column includes a plurality of first semiconductor pillars 201 arranged along the y-direction. The portions between adjacent first semiconductor pillars 201 are etched away. The first semiconductor pillars 201 in adjacent columns are staggered relative to each other in the y-direction. Figure 13 as well as Figure 14 The diagram shows the distribution of the first semiconductor pillars 201 on two adjacent columns.

[0096] Reference Figure 14 As shown, a gate dielectric layer 205 is formed on the sidewall of the first semiconductor pillar 201; Refer to Figure 15 and Figure 16 As shown, the gaps between the first semiconductor pillars 201 are filled with dielectric material, and the dielectric material and the composition of the gate dielectric layer 205 can be the same without physical boundary. Figure 15 This is a cross-sectional diagram of a column. Figure 16 The diagram shows a cross-sectional view of a row. Each first semiconductor pillar 201 corresponds to a column, and the semiconductor layer 2001 portion between two adjacent first semiconductor pillars 201 corresponds to a column, which is used to carry or form bit lines 204.

[0097] Reference Figure 17 As shown, a gate layer 203 is formed between two adjacent rows, that is, between two adjacent first semiconductor pillars 201. One row corresponds to one gate layer 203. Adjacent gate layers 203 can be arranged face-to-face. The gate layer 203 covers the middle region of the sidewall of the first semiconductor pillar 201 along the y-direction. (Refer to...) Figure 18As shown, a conductive structure 202 is provided on the side of the first semiconductor pillar 201 where the gate layer 203 is not provided. The conductive structure 202 and the gate layer 203 are disposed opposite to the first semiconductor pillar 201 in the y-direction. A bit line 204 is formed at the bottom of the first semiconductor pillar 201, and the bit line 204 corresponds to a column.

[0098] In some embodiments, refer to Figure 18 As shown, a plurality of first semiconductor pillars 201 arranged at column intervals along the x-direction constitute a row; two adjacent first rows 21a and second rows 21b, two adjacent first conductive structures 202a and second conductive structures 202b, and two adjacent first gate layers 203a and second gate layers 203b; wherein, the first conductive structures 202a, first rows 21a, first gate layers 203a, second gate layers 203b, second rows 21b, and second conductive structures 202b are arranged sequentially along the y-direction. This disclosure embodiment can be referred to. Figure 18 The arrangement pattern shown involves arranging more rows, gate layer 203, and conductive structure 202.

[0099] In some embodiments, Figure 12 The bottom of the first trench 211 is located in the semiconductor layer 2001. Figure 13 The etching depth of the column structure is less than the etching depth of the first trench 211; the fabrication method further includes:

[0100] Reference Figure 12 , Figure 15 as well as Figure 16 As shown, the first trench 211 is filled at least with dielectric material 221; the dielectric materials used for multiple fillings in this embodiment may be the same or different, and the dielectric materials may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or spin-coated insulating dielectric; the gate layer 203 may be formed before the dielectric material 221 is filled, or the dielectric material 221 may be filled again after the gate layer 203 is formed, and the dielectric materials in different filling steps may be the same and have no physical boundary;

[0101] Reference Figure 20 As shown, for Figure 19 The semiconductor layer 2001 shown is thinned on the side away from the first semiconductor pillar 201 until the dielectric material 221 in the first trench 211 is exposed;

[0102] Reference Figure 21As shown, the dielectric material 221 extending along the y-direction divides the thinned semiconductor layer 2001 into multiple columns arranged along the x-direction; each column includes: semiconductor strips 2011 extending along the y-direction, and first semiconductor pillars 201 alternately arranged along the y-direction on the semiconductor strips 2011, with the semiconductor strips 2011 connected to the first ends of the first semiconductor pillars 201. During back-side thinning of the semiconductor layer 2001, Figure 20 Dielectric material 221 extending along the y-direction is exposed first, and some semiconductor layers 2001 are retained to form bit lines 204. The semiconductor layers 2001 are divided into columns along the y-direction.

[0103] In some embodiments, refer to Figure 20 and Figure 21 As shown, the manufacturing method includes:

[0104] The bit line 204 is formed based on the semiconductor strip 2011; the semiconductor strip 2011 includes silicon, and the bit line 204 includes metal silicide.

[0105] For example, the semiconductor strip 2011 may include silicon. A metal material is deposited on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction and then heat-treated. A portion of the silicon in the semiconductor strip 2011 reacts with the metal material to form a metal silicide layer to form the bit line 204. The metal silicide may include, but is not limited to, titanium silicide, nickel silicide, etc. For example, conductive materials such as tungsten, aluminum, and titanium may be deposited on the metal silicide to form the bit line 204 with a composite material layer, thereby improving the electrical connection performance between the bit line 204 and the first semiconductor pillar 201 and reducing the contact resistance.

[0106] In some embodiments, refer to Figure 7 As shown, the manufacturing method further includes:

[0107] A capacitor structure 206 is formed on the side of the first semiconductor pillar 201 away from the bit line 204, and the capacitor structure 206 is coupled to the second end of the first semiconductor pillar 201.

[0108] In some embodiments, refer to Figure 22 As shown, the manufacturing method further includes:

[0109] Figure 13 During the etching of the column structure, a portion of the semiconductor layer 2001 is retained between adjacent first semiconductor pillars 201 to form a second semiconductor pillar 207; the top surface height of the second semiconductor pillar 207 is less than the top surface height of the second end of the first semiconductor pillar 201. (Refer to...) Figure 9As shown, a gate layer 203 is formed face-to-face between the first semiconductor pillar 201 and the second semiconductor pillar 207, forming a conductive structure 202 and a bit line 204. A second semiconductor pillar 207 is located between any two first semiconductor pillars 201 in each column. The second semiconductor pillar 207 is not used for electrical connection in the circuit structure; instead, it provides physical support for the device structure and spacees adjacent first semiconductor pillars 201, achieving a staggered arrangement of the first semiconductor pillars 201, reducing crosstalk between adjacent first semiconductor pillars 201 in a row and column.

[0110] According to some aspects of embodiments of this disclosure, Figure 23 A control method for a memory device 200 is provided, the memory device 200 may include Figures 3 to 10 The illustrated device structure; the gate layer 203 of the memory device 200 is configured as a word line, and the control method includes:

[0111] A first operating voltage is applied to the first word line in the word lines to select the first row;

[0112] Apply a second operating voltage or float to the odd-numbered bit lines corresponding to the first row, and apply a first preset voltage to the even-numbered bit lines corresponding to the first row to select the odd-numbered column in the first row; or,

[0113] Apply the second operating voltage or float to the even-numbered bit lines corresponding to the first row, and apply the first preset voltage to the odd-numbered bit lines corresponding to the first row to select the even-numbered column in the first row.

[0114] In some embodiments, the control method further includes:

[0115] A second preset voltage is applied to the conductive structure 202 in the memory device 200.

[0116] The first line can be any of multiple lines. The first operating voltage is greater than or equal to the threshold voltage of the transistor (or the first semiconductor pillar 201), causing the transistor to turn on. Other word lines are given a turn-off voltage to turn off the transistor. The selected bit line is given a second operating voltage, which can be Vcc, 0, or floating. The first preset voltage is a fixed voltage or a static voltage, which is a calibration value for testing a memory device, such as Vcc / 2. The second preset voltage is a fixed voltage or a static voltage, which can be the transistor's turn-off voltage or ground voltage.

[0117] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: The row includes a plurality of first semiconductor pillars arranged along a first direction, with odd-numbered rows and even-numbered rows alternately arranged along a second direction; The column includes a plurality of first semiconductor pillars arranged along the second direction, with odd-numbered columns and even-numbered columns alternately arranged along the first direction; Any two adjacent first semiconductor pillars in the row are arranged with a column spaced apart, and any two adjacent first semiconductor pillars in the column are arranged with a row spaced apart. The first semiconductor pillar extends along a third direction, and the first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction; A conductive structure, extending along the first direction, is located between two adjacent rows; A gate layer extends along the first direction and corresponds to the row; the conductive structure and the gate layer are located on opposite sides of the first semiconductor pillar along the second direction, and the gate layer covers the sidewall of the first semiconductor pillar along the second direction. Bit lines extend along the second direction and are located on the side of the first semiconductor pillar near the first end; the bit lines correspond to the column and are coupled to the first end of the first semiconductor pillar.

2. The memory device according to claim 1, characterized in that, The row further includes: a second semiconductor pillar, which is arranged alternately with the first semiconductor pillar along the first direction; The column further includes: a second semiconductor pillar, which is arranged alternately with the first semiconductor pillar along the second direction; The second semiconductor pillar extends along the third direction; the size of the second semiconductor pillar in the third direction is smaller than the size of the first semiconductor pillar in the third direction, and the height of the top surface of the second end of the first semiconductor pillar is greater than the height of the top surface of the second semiconductor pillar at the end away from the bit line.

3. The memory device according to claim 1, characterized in that, The memory device includes: Two adjacent first conductive structures and second conductive structures, two adjacent first rows and second rows, and two adjacent first gate layers and second gate layers; wherein the first conductive structure, the first row, the first gate layer, the second gate layer, the second row, and the second conductive structure are arranged sequentially along the second direction.

4. The memory device according to claim 1, characterized in that, The column also includes: A semiconductor strip extending along the second direction, the semiconductor strip being located on the side of the first semiconductor pillar near the first end; the semiconductor strip being connected to the first semiconductor pillar.

5. The memory device according to claim 4, characterized in that, The bit line is located on the side of the semiconductor strip away from the first semiconductor pillar; The semiconductor strip comprises silicon, and the bit line comprises metal silicide.

6. The memory device according to claim 1, characterized in that, The memory device further includes: A gate dielectric layer is located between the gate layer and the first semiconductor pillar.

7. The memory device according to claim 1, characterized in that, The memory device further includes: A capacitor structure is located on the side of the first semiconductor pillar away from the capacitor structure, and the capacitor structure is coupled to the second end of the first semiconductor pillar.

8. The memory device according to claim 1, characterized in that, The first gate layer in the gate layer is configured to apply a first operating voltage to select the first row; The odd-numbered bit lines corresponding to the first row are configured to apply a second operating voltage or float to select the odd-numbered column on the first row, and the even-numbered bit lines corresponding to the first row are configured to apply a first preset voltage. or, The even-numbered bit lines corresponding to the first row are configured to apply the second operating voltage or float to select the even-numbered column on the first row, and the odd-numbered bit lines corresponding to the first row are configured to apply the first preset voltage.

9. The memory device according to claim 8, characterized in that, The conductive structure is configured to apply a second preset voltage.

10. A method for manufacturing a memory device, characterized in that, include: The semiconductor layer is etched to form a plurality of first trenches arranged along a first direction, and the first trenches extend along a second direction; The first trench divides the semiconductor layer into a column structure; The column structure is etched to form first semiconductor pillars arranged along the second direction; the first semiconductor pillar includes a first end and a second end disposed opposite each other along a third direction, and the first semiconductor pillars on two adjacent columns are offset from each other along the second direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction; A gate dielectric layer and a gate layer are formed on one side of the first semiconductor pillar along the second direction; the gate layer extends along the first direction and covers the sidewall of the first semiconductor pillar along the second direction. A conductive structure extending in the second direction is formed on one side of the first semiconductor pillar along the second direction, and the conductive structure and the gate layer are located on opposite sides of the first semiconductor pillar along the second direction. A bit line is formed on the side of the first semiconductor pillar near the first end, the bit line extending along the second direction and coupled to the first end of the first semiconductor pillar.

11. The manufacturing method according to claim 10, characterized in that, The manufacturing method further includes: When etching the column structure, a portion of the semiconductor layer is retained between adjacent first semiconductor pillars to form a second semiconductor pillar; the top surface height of the second semiconductor pillar is less than the top surface height of the second end of the first semiconductor pillar.

12. The manufacturing method according to claim 10, characterized in that, A plurality of first semiconductor pillars arranged at column intervals along the first direction constitute a row; two adjacent first rows and second rows, two adjacent first conductive structures and second conductive structures, and two adjacent first gate layers and second gate layers; wherein the first conductive structures, the first rows, the first gate layers, the second gate layers, the second rows, and the second conductive structures are arranged sequentially along the second direction.

13. The manufacturing method according to claim 10, characterized in that, The bottom of the first trench is located in the semiconductor layer, and the etching depth of the column structure is less than the etching depth of the first trench. The manufacturing method further includes: The first trench is filled with at least one dielectric material; The semiconductor layer is thinned on the side away from the first semiconductor pillar until the dielectric material in the first trench is exposed; The dielectric material extending along the second direction divides the thinned semiconductor layer into multiple columns arranged along the first direction; each column includes: a semiconductor strip extending along the second direction, and first semiconductor pillars alternately arranged along the second direction on the semiconductor strip, the semiconductor strip being connected to a first end of the first semiconductor pillar.

14. The manufacturing method according to claim 13, characterized in that, The manufacturing method includes: The bit line is formed based on the semiconductor strip; the semiconductor strip comprises silicon, and the bit line comprises metal silicide.

15. The manufacturing method according to claim 10, characterized in that, The manufacturing method further includes: A capacitor structure is formed on the side of the first semiconductor pillar away from the bit line, and the capacitor structure is coupled to the second end of the first semiconductor pillar.

16. A control method for a memory device, characterized in that, Applied to the memory device as described in any one of claims 1 to 9; The gate layer of the memory device is configured as a word line, and the control method includes: A first operating voltage is applied to the first word line in the word lines to select the first row; Apply a second operating voltage or float to the odd-numbered bit lines corresponding to the first row, and apply a first preset voltage to the even-numbered bit lines corresponding to the first row to select the odd-numbered column in the first row; or, Apply the second operating voltage or float to the even-numbered bit lines corresponding to the first row, and apply the first preset voltage to the odd-numbered bit lines corresponding to the first row to select the even-numbered column in the first row.

17. The control method according to claim 16, characterized in that, The control method further includes: A second preset voltage is applied to the conductive structure in the memory device.

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