Semiconductor structure, forming method thereof and memory array

Abstract

The invention discloses a semiconductor structure, a forming method thereof and a memory array. The method comprises the following steps: providing a substrate; forming a first photoresist layer on the first surface; exposing and developing the first photoresist layer to form the first photoresist layer with a vertical transistor pattern; etching a part of the active region and a part of the isolation region along the first surface by taking the first photoresist layer with the vertical transistor pattern as a mask to form vertical transistors and bit lines located at the bottoms of the vertical transistors, and forming first grooves between the adjacent vertical transistors; filling a first interlayer dielectric layer in the first groove; etching and removing the vertical transistor and the isolation region on the surface of the side wall of the vertical transistor by adopting a dry etching process with a selective etching ratio to form a second groove; and filling the second trench with a first vertical transistor. The vertical transistor and the isolation region located on the side wall of the vertical transistor are removed through etching to form the groove, and the first vertical transistor is formed in the groove, so that the width of the first vertical transistor is increased, the supporting performance of the first vertical transistor is improved, and the stability of the structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its formation method, and a memory array. Background Technology

[0002] Memory is a storage device used in modern information technology to store information. As storage device technology continues to iterate, the demand for storage cell density is increasing, requiring the size parameters of various parts of the device to be continuously reduced, such as SN-SN distance (distance between storage nodes) and BLC-BLC distance (distance between bit line contacts).

[0003] However, current storage units have low storage efficiency. Summary of the Invention

[0004] The technical problem solved by this invention is how to improve the storage efficiency of storage units.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate having a bit line direction and a word line direction arranged perpendicularly and intersectingly, the substrate including a plurality of active regions arranged parallel to each other along the bit line direction and isolation regions located between the active regions, and the substrate including a first surface; forming a first photoresist layer on the first surface; exposing and developing the first photoresist layer to form a first photoresist layer having a vertical transistor pattern, the first photoresist layer having the vertical transistor pattern being staggered along the bit line direction and the word line direction on the first surface of the active regions; using the first photoresist layer having the vertical transistor pattern as a mask, etching a portion of the active regions and a portion of the isolation regions along the first surface to form a vertical transistor and a bit line located at the bottom of the vertical transistor, and a first trench between adjacent vertical transistors; filling the first trench with a first interlayer dielectric layer; using a dry etching process with a selective etching ratio to etch away the vertical transistor and the isolation region located on the sidewall surface of the vertical transistor to form a second trench; and filling the second trench with a first vertical transistor.

[0006] Optionally, the substrate further includes adjacent first and second regions arranged along the bit line direction; the first vertical transistor on the same active region and the bit line located at the bottom of the first vertical transistor are located on the first region or the second region; the first vertical transistor on the same first region and the bit line located at the bottom of the first vertical transistor are located on one of the adjacent active regions; the first vertical transistor on the same second region and the bit line located at the bottom of the first vertical transistor are located on one of the adjacent active regions.

[0007] Optionally, the etching process for removing the active region and the isolation region can be a dry etching process or a wet etching process.

[0008] Optionally, the first vertical transistor on the same active region and the bit line located at the bottom of the first vertical transistor are located on the first region or the second region; the first vertical transistor on the same first region and the bit line located at the bottom of the first vertical transistor are located on one of the adjacent active regions; the first vertical transistor on the same second region and the bit line located at the bottom of the first vertical transistor are located on one of the adjacent active regions.

[0009] Optionally, the width of the vertical transistor ranges from 5 nanometers to 50 nanometers, and the width of the first vertical transistor ranges from 15 nanometers to 100 nanometers.

[0010] Optionally, after the step of filling the second trench with the first vertical transistor, the method includes: etching the first interlayer dielectric layer to form a third trench located on the first interlayer dielectric layer; forming a first annular word line gate oxide layer on the sidewall surface of the third trench, the first annular word line gate oxide layer surrounding the first vertical transistor; using an atomic layer deposition process, forming a first annular word line gate layer and a fourth trench on the bottom surface of the third trench and the sidewall surface of the first annular word line gate oxide layer, the first annular word line gate layer surrounding the first annular word line gate oxide layer; filling the fourth trench with an insulating layer, the first annular word line gate layer, the first annular word line gate oxide layer and the insulating layer constituting a first annular word line; and etching the top of the first annular word line gate layer and the insulating layer to form a first annular word line.

[0011] Optionally, the thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, the material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, and the first annular word line gate oxide layer and the first annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular or polygonal annular.

[0012] Optionally, after filling the second trench with the first vertical transistor, the method further includes: etching the first interlayer dielectric layer to form a third trench on the first interlayer dielectric layer; forming a second annular word line gate oxide layer on the sidewall surface of the third trench, the second annular word line gate oxide layer surrounding the first vertical transistor; filling the third trench with the second annular word line gate layer using atomic layer deposition, PVD, or CVD processes, the second annular word line gate layer surrounding the second annular word line gate oxide layer, the second annular word line gate layer and the second annular word line gate oxide layer constituting a second annular word line; etching the top of the second annular word line gate oxide layer and the second annular word line gate layer to form a second annular word line.

[0013] Optionally, the thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular, or polygonal annular.

[0014] Optionally, the substrate includes a second surface, wherein the first surface and the second surface are two opposite surfaces of the substrate; after the step of forming the first annular word line and the step of forming the second annular word line, the method further includes: forming a second interlayer dielectric layer on top of the first annular word line and the second annular word line, the second interlayer dielectric layer being flush with the top of the first vertical transistor; forming a hard mask layer on the substrate, the hard mask layer extending along the word line direction and covering the entire first vertical transistor along the word line direction, the hard mask layers being discretely arranged along the bit line direction, and adjacent hard mask layers in the bit line direction exposing a portion of the bit line. The top surface of the second interlayer dielectric layer is described; using the hard mask layer as a mask, the second interlayer dielectric layer, the first ring word line, and the second ring word line are etched sequentially until the first interlayer dielectric layer is exposed, forming a plurality of discrete first ring word lines, second ring word lines, and a fifth trench, wherein the plurality of discrete first ring word lines and second ring word lines are arranged along the bit line direction; a third interlayer dielectric layer is filled into the fifth trench, the third interlayer dielectric layer being flush with the top of the first vertical transistor; the second surface of the substrate is thinned, and a portion of the substrate and a portion of the bit lines are etched away to form a plurality of discrete bit lines.

[0015] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate having a bit line direction and a word line direction arranged in a perpendicular cross configuration, the substrate including a plurality of active regions arranged in parallel along the bit line direction and an isolation region located between the active regions, and the substrate including a first surface; a first vertical transistor formed on the first surface of the active regions that are staggered in the bit line direction and the word line direction, and a first trench being formed between adjacent first vertical transistors; a bit line located at the bottom of the first vertical transistor; and a first interlayer dielectric layer located within the first trench.

[0016] Optionally, the substrate further includes adjacent first and second regions arranged along the bit line direction; the first vertical transistor on the same active region and the bit line located at the bottom of the first vertical transistor are located on the first region or the second region; the first vertical transistor on the same first region and the bit line located at the bottom of the first vertical transistor are located on one of the adjacent active regions; the first vertical transistor on the same second region and the bit line located at the bottom of the first vertical transistor are located on one of the adjacent active regions.

[0017] Optionally, it further includes: a first annular word line, the first annular word line including: a first annular word line gate oxide layer, a first annular word line gate layer and an insulating layer, the first annular word line gate oxide layer surrounding the first vertical transistor and the first annular word line gate oxide layer located on the sidewall surface of the first vertical transistor, the first annular word line gate layer surrounding the first annular word line gate oxide layer, and the insulating layer located in a fourth trench between adjacent first annular word line gate layers.

[0018] Optionally, it further includes: a second interlayer dielectric layer and a third interlayer dielectric layer, wherein the first ring word lines are located within a first trench between adjacent first vertical transistors, the first interlayer dielectric layer is located at the bottom of the first ring word lines, the second interlayer dielectric layer is located at the top of the first ring word lines, and the third interlayer dielectric layer is located within the first ring word lines and the second interlayer dielectric layer.

[0019] Optionally, the thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers, the material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, and the first annular word line gate oxide layer and the first annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular or polygonal annular.

[0020] Optionally, it further includes: a second ring word line, the second ring word line being discretely arranged along the bit line direction, the second ring word line including: a second ring word line gate oxide layer and a second ring word line gate layer, the second ring word line gate oxide layer surrounding the first vertical transistor, and the second ring word line gate oxide layer being located on the sidewall surface of the first vertical transistor, the second ring word line gate layer surrounding the second ring word line gate oxide layer, and the second ring word line gate layer filling in a third trench between adjacent second ring word line gate oxide layers.

[0021] Optionally, it further includes: a second interlayer dielectric layer and a third interlayer dielectric layer, wherein the second ring word line is located within a first trench between adjacent first vertical transistors, the first interlayer dielectric layer is located at the bottom of the second ring word line, the second interlayer dielectric layer is located at the top of the second ring word line, and the third interlayer dielectric layer is located within the second ring word line and the second interlayer dielectric layer.

[0022] Optionally, the thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular, wherein the annular is a circular annular, elliptical annular, square annular, or polygonal annular.

[0023] Optionally, the width of the first vertical transistor ranges from 15 nanometers to 100 nanometers.

[0024] Accordingly, the present invention also provides a memory array, comprising: a plurality of bit lines arranged along word line direction; a plurality of word lines arranged along bit line direction, wherein the plurality of bit lines intersect with the plurality of word lines in a grid-like arrangement; a plurality of gate ring transistors, wherein the plurality of gate ring transistors are arranged in an array at intervals in the grid formed by the intersection of the plurality of bit lines and the plurality of word lines, wherein in a row of grids formed by the intersection of any word line and the plurality of bit lines, the gate ring transistor is located in one of two adjacent grids, and in a column of grids formed by the intersection of any bit line and the plurality of word lines, the gate ring transistor is located in one of two adjacent grids, wherein the source / drain of the gate ring transistor is connected to the bit line, and the gate of the gate ring transistor is connected to the word line; and a plurality of memory capacitors, wherein the first end of the memory capacitor is connected to the source / drain of the gate ring transistor, and the second end of the memory capacitor is grounded.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0026] In this invention, a second photoresist layer with a first vertical transistor pattern is formed on the first surface. This allows only one active region from adjacent active regions to be retained after subsequent etching, forming several discrete first vertical transistors. This spacing effectively reduces coupling between adjacent bit lines and improves the storage efficiency of the memory cell. Furthermore, the photoresist layer is staggered along the bit line direction, ensuring that the first vertical transistors are also staggered along the bit line direction after subsequent etching, increasing the arrangement density compared to the rectangular arrangement in the prior art. In addition, this invention forms trenches by etching away the vertical transistors and the isolation regions located on the sidewalls of the vertical transistors, and forms the first vertical transistors within these trenches. This increases the width of the first vertical transistors, enhancing their support performance and structural stability.

[0027] Furthermore, the present invention achieves process diversity of word lines by forming a first annular word line and a second annular word line in the trench between adjacent first vertical transistors, wherein the first annular word line is located on the surface of the trench between adjacent first vertical transistors and the second annular word line fills the trench between adjacent first vertical transistors.

[0028] Furthermore, the present invention forms a first interlayer dielectric layer at the bottom of the trench between adjacent first vertical transistors, forms a first annular word line on the first interlayer dielectric layer, and etches the top of the first annular word line, so that the depth of the subsequently formed first annular word line or second annular word line can be precisely defined, thereby ensuring the performance of the formed annular gate transistor. Attached Figure Description

[0029] Figure 1 A schematic diagram of a storage array structure;

[0030] Figures 2 to 33 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention;

[0031] Figures 34 to 47 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention;

[0032] Figure 48 This is a schematic diagram of the structure of a storage array in one embodiment of the present invention. Detailed Implementation

[0033] As the demand for memory cell density increases, the size parameters of various parts of the device are constantly shrinking, such as SN-SN distance (distance between memory nodes) and BLC-BLC distance (distance between bit line contacts).

[0034] The current memory array structure is shown in Figure 1. The memory array includes several bit lines BL, which are arranged along the word line direction X; several word lines WL, which are arranged along the bit line direction Y, and the bit lines BL and word lines WL intersect to form a grid; several gate ring transistors 101, which are arrayed in the grid formed by the intersection of the bit lines BL and word lines WL, with the source / drain of the gate ring transistors 101 connected to the bit lines BL and the gate of the gate ring transistors 101 connected to the word lines WL; and several memory capacitors 102, with the first end of the memory capacitors 102 connected to the source / drain of the gate ring transistors 101 and the second end of the memory capacitors 102 grounded.

[0035] As can be seen, the ring gate transistors 101 in the above scheme are arranged in an array. The density of the ring gate transistors 101 is relatively large, which leads to increased coupling between adjacent bit lines BL when the ring gate transistors 101 are working, thereby affecting the storage performance.

[0036] To address the aforementioned technical problems, the present invention provides a semiconductor structure and its formation method, as well as a memory array. By forming a plurality of discrete first vertical transistors on the first surface, and thereby achieving a spacing distribution between the plurality of first vertical transistors, the coupling effect between adjacent bit lines can be effectively reduced, the storage efficiency of the memory cell can be improved, and the arrangement density can be increased compared to the rectangular arrangement of the prior art. In addition, by etching away the bit lines and the isolation region located on the sidewall of the bit lines to form a trench, and forming the first vertical transistor in the trench, the width of the first vertical transistor is increased, the support performance of the first vertical transistor is increased, and the stability of the structure is increased.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] The following example uses the formation of the first circular character line, combined with... Figures 2 to 33 The formation process of semiconductor structures is explained in detail.

[0039] Please refer to Figure 2 and Figure 3 , Figure 2 It is a top view. Figure 3 yes Figure 2 A cross-sectional view along the AA1 direction is provided, and a substrate 200 is provided. The substrate 200 has a bit line direction Y and a word line direction X arranged perpendicularly. The substrate 200 includes a plurality of active regions 201 arranged in parallel along the bit line direction Y and an isolation region located between the active regions 201. The substrate 200 includes a first surface a.

[0040] In this embodiment, the substrate 200 is made of silicon.

[0041] In other embodiments, the substrate 200 may be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate 200 may be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0042] In some embodiments of the present invention, the method of forming the isolation region includes: etching away the substrate 200 between adjacent active regions 201 to form a shallow trench 202.

[0043] Please refer to Figure 4 and Figure 5 , Figure 4 It is a top view. Figure 5 yes Figure 4 A cross-sectional view along the AA1 direction shows that a bit line gate oxide layer 2022 is formed on the surface of the shallow trench 202; an insulating material is filled into the shallow trench 202 to form an isolation layer 2021.

[0044] In this embodiment, the material of the isolation layer 2021 is silicon nitride.

[0045] In this embodiment, the bit line gate oxide layer 2022 is made of silicon dioxide.

[0046] Please refer to Figure 6 and Figure 7 , Figure 6 It is a top view. Figure 7 yes Figure 6 A cross-sectional view along the AA1 direction shows that a first photoresist layer 203 is formed on the first surface a; the first photoresist layer 203 is exposed and developed to form a first photoresist layer 203 with a vertical transistor pattern, wherein the first photoresist layer 203 with the vertical transistor pattern is staggered along the bit line direction Y and the word line direction X on the first surface a of the active region 201.

[0047] In this embodiment, the substrate 200 further includes adjacent first region I and second region II arranged along the bit line direction YY.

[0048] The staggered arrangement of the first photoresist layer 203 with the vertical transistor pattern is characterized as follows: the vertical transistors 204 on the same active region 201 and the bit line 2042 located at the bottom of the first vertical transistor 204 are located on the first region I or the second region II; the vertical transistors 204 on the same first region I and the bit line 2042 located at the bottom of the vertical transistor 204 are located on one of the adjacent active regions 201; and the vertical transistors 204 on the same second region II and the bit line 2042 located at the bottom of the vertical transistor 204 are located on one of the adjacent active regions 201.

[0049] In a specific embodiment, Figure 6 The seven first photoresist layers 203 with vertical transistor patterns are arranged in a hexagonal pattern on the substrate 200, and Figure 6 The two first photoresist layers 203 with vertical transistor patterns on the second region II and the first photoresist layer 203 with vertical transistor patterns on the first region are arranged in an equilateral triangle.

[0050] The number of the first photoresist layer 203 with the vertical transistor pattern is the same as the number of the bit lines 2042.

[0051] The present invention does not limit the number of the first photoresist layer 203 with vertical transistor pattern. Other numbers of first photoresist layers 203 with vertical transistor pattern are all within the protection scope of the present invention, and the first photoresist layer 203 with vertical transistor pattern is arranged in a honeycomb pattern on the substrate 200.

[0052] In this embodiment, the vertical transistor 204 is made of silicon.

[0053] Since the first photoresist layer 203 with the vertical transistor pattern defines the shape of the vertical transistor 204 on the substrate 200, the shape and arrangement of the subsequently formed vertical transistor 204 are the same as those of the first photoresist layer 203 with the vertical transistor pattern. Therefore, the first photoresist layer 203 with the vertical transistor pattern is arranged in an alternating pattern on the first surface a of the substrate 200, so that the arrangement of the subsequently formed vertical transistor 204 is also alternating, thereby reducing the coupling effect between adjacent bit lines. Furthermore, the arrangement of the first photoresist layer 203 with the vertical transistor pattern determines the arrangement of the capacitor, increasing the density of the capacitor arrangement and the capacitance.

[0054] Please refer to Figure 8 , Figure 9 and Figure 10 , Figure 8 It is a top view. Figure 9 yes Figure 8 Cross-sectional view along the AA1 direction. Figure 10 yes Figure 8 A cross-sectional view along the BB1 ​​direction shows that, using the first photoresist layer 203 (not shown in the figure) with the vertical transistor pattern as a mask, a portion of the active region 201 and a portion of the isolation region are etched along the first surface a to form a vertical transistor 204, and a first trench 2041 is formed between adjacent vertical transistors 204.

[0055] In some embodiments of the present invention, the etching process for removing the active region 201 and the isolation region is a dry etching process or a wet etching process.

[0056] In this embodiment, the etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

[0057] In this embodiment, a first trench 2041 is provided between adjacent vertical transistors 204.

[0058] The first groove 2041 is used to accommodate the subsequently formed first annular letter line 207.

[0059] In some embodiments of the present invention, the width of the vertical transistor 204 along the word line direction XX ranges from 5 nanometers to 50 nanometers.

[0060] In the above solution, the present invention forms a first photoresist layer 203 with a vertical transistor pattern on the first surface a. The first photoresist layer 203 is staggered along the bit line direction Y and the word line direction X on the first surface a of the active region 201. This allows only one of the adjacent active regions 201 to be retained after the subsequent etching process, forming several discrete vertical transistors. This achieves a spacing distribution between the several vertical transistors 204, effectively reducing the coupling effect between adjacent bit lines and improving the storage efficiency of the memory cell. Furthermore, the staggered distribution of the first photoresist layer 203 along the bit line direction Y ensures that the vertical transistors 204 are also staggered along the bit line direction Y after the subsequent etching process, increasing the arrangement density compared to the rectangular arrangement of the prior art.

[0061] Please refer to Figure 11 and Figure 12 , Figure 11 View direction and Figure 9 same, Figure 12 View direction and Figure 10 Similarly, the first interlayer dielectric layer 205 is filled into the first trench 2041.

[0062] In this embodiment, the method further includes: planarizing the first interlayer dielectric layer 205 until the top surface of the vertical transistor 204 is exposed.

[0063] In this embodiment, the material of the first interlayer dielectric layer 205 is silicon dioxide.

[0064] In this embodiment, the planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical mechanical polishing, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nanoscale.

[0065] Please refer to Figure 13 and Figure 14 , Figure 13 View direction and Figure 11 same, Figure 14 View direction and Figure 12 Similarly, a dry etching process with a selective etching ratio is used to etch away the vertical transistor 204 and the isolation region located on the sidewall surface of the vertical transistor 204 to form a second trench 2061.

[0066] The second trench 2061 is used to accommodate the subsequently formed first vertical transistor 206.

[0067] The etching process for the vertical transistor 204 and the active region 201 located on both sides of the vertical transistor 204 is either dry etching or wet etching.

[0068] In this embodiment, the etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

[0069] Please refer to Figure 15 , Figure 16 and Figure 17 , Figure 15 It is a top view. Figure 16 yes Figure 15 Cross-sectional view along the AA1 direction. Figure 17 yes Figure 15 A cross-sectional view along the BB1 ​​direction shows that the second trench 2061 is filled with the first vertical transistor 206.

[0070] The width of the first vertical transistor 206 along the word line direction XX ranges from 15 nanometers to 100 nanometers.

[0071] The present invention removes part of the vertical transistor 204 and the isolation regions on both sides of the vertical transistor 204 by etching, and forms the first vertical transistor 206 in the trench formed by etching, thereby increasing the width of the first vertical transistor 206, increasing the support performance of the first vertical transistor 206, and increasing the stability of the structure.

[0072] Please refer to Figure 18 and Figure 19 , Figure 18 View direction and Figure 16 same, Figure 19 View direction and Figure 17 Similarly, the first interlayer dielectric layer 205 is etched to form a third trench 2071 located on the first interlayer dielectric layer 205.

[0073] The third groove 2071 is used to accommodate the subsequently formed first annular letter line 207.

[0074] The present invention etches the first interlayer dielectric layer 205 and retains the bottom portion of the first interlayer dielectric layer 205, so that the depth of the subsequently formed first ring word line 207 can be precisely defined, thereby ensuring the performance of the formed ring gate transistor.

[0075] Please refer to Figure 20 and Figure 21 , Figure 20 View direction and Figure 18 same, Figure 21 View direction and Figure 19 Similarly, a first annular word line gate oxide layer 2072 is formed on the sidewall surface of the third trench 2071, and the first annular word line gate oxide layer 2072 surrounds the first vertical transistor 206; using an atomic layer deposition process, a first annular word line gate layer 2073 and a fourth trench 2074 are formed on the bottom surface of the third trench 2071 and the sidewall surface of the first annular word line gate oxide layer 2072.

[0076] The first annular word line gate layer 2073 surrounds the first annular word line gate oxide layer 2072.

[0077] The material of the first annular word line gate layer 2073 is one of TIN, a combination of TIN and W, or Mo.

[0078] The material of the first annular word line gate oxide layer 2072 is one of silicon dioxide, nitrogen-doped silicon dioxide, or HK.

[0079] The first annular word line gate oxide layer 2072 and the first annular word line gate layer 2073 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring or a polygonal annular ring.

[0080] Please refer to Figure 22 , Figure 23 and Figure 24 , Figure 22 It is a top view. Figure 23 yes Figure 22 Cross-sectional view along the AA1 direction. Figure 24 yes Figure 22 A cross-sectional view along the BB1 ​​direction shows that the fourth trench 2074 is filled with an insulating layer 2075.

[0081] The first annular word line gate layer 2073, the first annular word line gate oxide layer 2072 and the insulating layer 2075 constitute the first annular word line 207;

[0082] Please refer to Figure 25 and Figure 26 , Figure 25 View direction and Figure 23 same, Figure 26 View direction and Figure 24 Similarly, the top of the first annular word line gate layer 2073 and the insulating layer 2075 are etched to form the first annular word line 207.

[0083] The thickness of the first annular word line gate layer 2073 along the word line direction X ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer 2073 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers.

[0084] In this embodiment, since the first annular word line gate oxide layer 2072 surrounds a portion of the first vertical transistor 206, based on the positional relationship between the first annular word line 207 and the first vertical transistor 206, the device formed on the substrate 200 is determined to be a gate ring transistor (GAA). The gate of the gate ring transistor (GAA) is shared with the first annular word line 207, and the source / drain of the gate ring transistor (GAA) is shared with the bit line 2042.

[0085] The present invention etches the top of the first annular word line 207, so that the depth of the subsequently formed first annular word line 207 can be precisely defined, thereby ensuring the performance of the formed gate ring transistor (GAA).

[0086] Please refer to Figure 27 and Figure 28 , Figure 27 View direction and Figure 25 same, Figure 28 View direction and Figure 26 Similarly, a second interlayer dielectric layer 208 is formed on top of the first annular word line 207.

[0087] The second interlayer dielectric layer 208 is flush with the top of the first vertical transistor 206.

[0088] The material of the second interlayer dielectric layer 208 is silicon dioxide.

[0089] Please refer to Figure 29 and Figure 30 , Figure 29 It is a top view. Figure 30 yes Figure 22 A cross-sectional view along the BB1 ​​direction shows that a hard mask layer 209 is formed on the substrate 200; using the hard mask layer 209 as a mask, the second interlayer dielectric layer 208 and the first annular word line 207 are etched sequentially until the first interlayer dielectric layer 205 is exposed, forming a plurality of discrete first annular word lines 207 and a fifth trench 2091, and the plurality of discrete first annular word lines 207 are arranged along the bit line direction Y.

[0090] The hard mask layer 209 extends along the word line direction X and covers all the first vertical transistors 206 along the word line direction X. The hard mask layers 209 are arranged discretely along the bit line direction Y, and the top surface of the second interlayer dielectric layer 208 is exposed between adjacent hard mask layers 209 in the bit line direction Y.

[0091] The present invention forms a hard mask layer 209 and uses the hard mask layer 209 as a mask to etch the second interlayer dielectric layer 208 and the first annular word line 207 in sequence, so that the first annular word line 207 is etched apart in the bit line direction Y, thereby making the first annular word line 207 arranged sequentially in the bit line direction Y. Any first annular word line 207 can control the opening or closing of a row of memory cells, and adjacent first annular word lines 207 do not interfere with each other and work independently.

[0092] Please refer to Figure 31 , Figure 31 View direction and Figure 30 Similarly, a third interlayer dielectric layer 210 is filled into the fifth trench 2091, and the third interlayer dielectric layer 210 is flush with the top of the first vertical transistor 206.

[0093] The material of the third interlayer dielectric layer 210 is silicon dioxide.

[0094] In other embodiments, after forming the third interlayer dielectric layer 210, processes such as storage node contact SNC and storage node SN are also performed.

[0095] Please refer to Figure 32 and Figure 33 , Figure 32 View direction and Figure 28 same, Figure 33 View direction and Figure 31 Similarly, the second surface b of the substrate 200 is thinned, and a portion of the substrate 200 and a portion of the bit line 2042 are etched away to form a plurality of discrete bit lines 2042.

[0096] The substrate 200 includes a second surface b, and the first surface a and the second surface b are two opposite surfaces of the substrate 200.

[0097] This invention thins the second surface b, allowing the thinner wafer to conduct heat away more quickly, preventing chip overheating, improving the wafer's heat dissipation performance, and thus enhancing the reliability and performance of the device.

[0098] The following example uses the formation of the second circular character line, combined with... Figures 34 to 45 The formation process of semiconductor structures is explained in detail.

[0099] Please Figure 18 , Figure 19 Based on, refer to Figure 34 , Figure 35 and Figure 36 , Figure 34 It is a top view. Figure 35 yes Figure 34 Cross-sectional view along the AA1 direction. Figure 36 yes Figure 35 A cross-sectional view along the BB1 ​​direction shows that a second annular word line gate oxide layer 3071 is formed on the sidewall surface of the third trench 2071, and the second annular word line gate oxide layer 3071 surrounds the first vertical transistor 206; using an atomic layer deposition process, a second annular word line gate layer 3072 is filled into the third trench 2071, and the second annular word line gate layer 3072 surrounds the second annular word line gate oxide layer 3071, and the second annular word line gate layer 3072 and the second annular word line gate oxide layer 3071 constitute a second annular word line 307.

[0100] Please refer to Figure 37 and Figure 38 , Figure 37 View direction and Figure 35 same, Figure 38 View direction and Figure 36Similarly, the top of the second annular word line gate oxide layer 3071 and the second annular word line gate layer 3072 are etched to form the second annular word line 307.

[0101] The second annular word line gate layer 3072 has a thickness ranging from 5 nanometers to 50 nanometers along the word line direction X, and a depth ranging from 30 nanometers to 300 nanometers along the direction perpendicular to the substrate 200.

[0102] The material of the second annular word line gate layer 3072 is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si, or a combination of Mo and Si.

[0103] In this embodiment, the material of the second annular word line gate layer 3062 formed by atomic layer deposition process is one of TIN, a combination of TIN and W, or Mo.

[0104] The second annular word line gate oxide layer 3071 and the second annular word line gate layer 3072 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring or a polygonal annular ring.

[0105] In one embodiment of the present invention, when the material of the second annular word line gate layer 3072 is TIN, that is, along the word line direction X, the third trench 2071 is filled with the second annular word line gate layer 3072 of TIN material. At this time, along the bit line direction Y, the second annular word line gate layer 3072 in the third trench 2071 has two filling situations: one is that along the bit line direction Y, the third trench 2071 is filled with the second annular word line gate layer 3072 of TIN material, and the other is that along the bit line direction Y, a layer of the second annular word line gate layer 3072 of TIN material is deposited on the surface of the third trench 2071.

[0106] In this embodiment, since the second annular word line gate oxide layer 3071 surrounds a portion of the first vertical transistor 206, based on the positional relationship between the second annular word line 307 and the first vertical transistor 206, the device formed on the substrate 200 is determined to be a gate ring transistor (GAA). The gate of the gate ring transistor (GAA) is shared with the second annular word line, and the source / drain of the gate ring transistor (GAA) is shared with the bit line 2042.

[0107] The present invention etches the top of the second ring word line 307, so that the depth of the subsequently formed second ring word line 307 can be precisely defined, thereby ensuring the performance of the formed gate ring transistor (GAA).

[0108] The present invention achieves process diversity of word lines by forming a second annular word line 307 in the trench between adjacent first vertical transistors 206. The second annular word line 307 is located on the surface of the trench between adjacent first vertical transistors 206 and fills the trench between adjacent first vertical transistors 206.

[0109] Please refer to Figure 39 and Figure 40 , Figure 39 View direction and Figure 36 same, Figure 40 View direction and Figure 38 Similarly, a second interlayer dielectric layer 308 is formed on top of the second annular letter line 307.

[0110] The second interlayer dielectric layer 308 is flush with the top of the first vertical transistor 206.

[0111] The material of the second interlayer dielectric layer 308 is silicon dioxide.

[0112] In another embodiment, please refer to Figure 41 and Figure 42 , Figure 41 The direction of the diagram and Figure 39 Consistent, Figure 42 The direction of the diagram and Figure 40 Consistent, when the material of the second annular word line gate layer is TIN and Si, that is, the second annular word line gate layer includes a silicon layer 3112 and titanium nitride layers 3111 located on the upper and lower surfaces of the silicon layer 3112, the second word line 311 is a composite structure, and the structure of the second word line 311 is a sandwich structure.

[0113] In this embodiment, the material of the second annular word line gate layer formed by PVD or CVD process is one of the following: a combination of TIN and Si, or a combination of Mo and Si.

[0114] In this embodiment, the method for forming the second annular word line gate layer includes: using PVD or CVD process, sequentially depositing a titanium nitride layer 3111, a silicon layer 3112, and a titanium nitride layer 3111 along a direction perpendicular to the substrate.

[0115] In this embodiment, a second interlayer dielectric layer 308 is also included on the titanium nitride layer 3111.

[0116] In specific embodiments, the subsequent process steps are the same whether the material of the second annular word line gate layer is TIN material or the second annular word line gate layer is a composite structure. The following scheme is described with the material of the second annular word line gate layer being TIN material as an example. The process steps of the second annular word line gate layer being a composite structure will not be repeated here.

[0117] Please refer to Figure 43 and Figure 44 , Figure 43 It is a top view. Figure 44 yes Figure 43 A cross-sectional view along the BB1 ​​direction shows that a hard mask layer 309 is formed on the substrate 200; using the hard mask layer 309 as a mask, the second interlayer dielectric layer 308 and the second annular word line 307 are etched sequentially until the first interlayer dielectric layer 205 is exposed, forming a plurality of discrete second annular word lines 307 and a fourth trench 3091, and the plurality of discrete second annular word lines 307 are arranged along the bit line direction Y.

[0118] The hard mask layer 309 extends along the word line direction X and covers the entire first vertical transistor 206 along the word line direction X. The hard mask layers 309 are discretely arranged along the bit line direction Y, and the top surface of the second interlayer dielectric layer 308 is partially exposed between adjacent hard mask layers 309 in the bit line direction Y.

[0119] The present invention forms a hard mask layer 309 and uses the hard mask layer 309 as a mask to etch the second interlayer dielectric layer 308 and the second annular word line 307 in sequence, so that the second annular word line 307 is etched apart in the bit line direction Y, thereby making the second annular word line 307 arranged sequentially in the bit line direction Y. Any second annular word line 307 can control the opening or closing of a row of memory cells, and adjacent second annular word lines 307 do not interfere with each other and work independently.

[0120] Please refer to Figure 45 , Figure 45 View direction and Figure 44 Similarly, a third interlayer dielectric layer 310 is filled into the fourth trench 2074, and the third interlayer dielectric layer 310 is flush with the top of the first vertical transistor 206.

[0121] The material of the third interlayer dielectric layer 310 is silicon dioxide.

[0122] In other embodiments, after forming the third interlayer dielectric layer, processes such as storage node contact (SNC) and storage node (SN) are also performed.

[0123] Please refer to Figure 46 and Figure 47 , Figure 46 View direction and Figure 41 same, Figure 47 View direction and Figure 45Similarly, the second surface b of the substrate 200 is thinned, and a portion of the substrate 200 and a portion of the bit line 2042 are etched away to form a plurality of discrete bit lines 2042.

[0124] The substrate 200 includes a second surface b, and the first surface a and the second surface b are two opposite surfaces of the substrate 200.

[0125] This invention thins the second surface b, allowing the thinner wafer to conduct heat away more quickly, preventing chip overheating, improving the wafer's heat dissipation performance, and thus enhancing the reliability and performance of the device.

[0126] In summary, this invention forms a second photoresist layer with a pattern of first vertical transistors 206 on the first surface a, so that after subsequent etching, only one active region 201 of adjacent active regions 201 is retained, forming a plurality of discrete first vertical transistors 206. This achieves a spacing distribution between the plurality of first vertical transistors 206, effectively reducing the coupling effect between adjacent bit lines and improving the storage efficiency of the memory cell. Furthermore, the photoresist layer is staggered along the bit line direction Y, so that after subsequent etching, the structure of the first vertical transistors 206 is also staggered along the bit line direction Y, increasing the arrangement density compared to the rectangular arrangement of the prior art. In addition, this invention forms trenches by etching away the vertical transistors 204 and the isolation regions located on the sidewalls of the vertical transistors 204, and forms the first vertical transistors 206 in the trenches, thereby increasing the width of the first vertical transistors 206, increasing the support performance of the first vertical transistors 206, and increasing the stability of the structure.

[0127] Accordingly, please refer to Figure 15 The present invention also provides a semiconductor structure, comprising: a substrate 200 having a bit line direction Y and a word line direction X arranged perpendicularly and intersectingly, the substrate 200 including a plurality of active regions 201 arranged parallel to each other along the bit line direction Y and an isolation region located between the active regions 201, and the substrate 200 including a first surface a; a first vertical transistor 206 formed on the first surface a of the active regions 201 that are staggered in the bit line direction Y and the word line direction X, and a first trench between adjacent first vertical transistors 206; a bit line 2042 located at the bottom of the first vertical transistor 206; and a first interlayer dielectric layer 205 located in the first trench.

[0128] In this embodiment, the substrate 200 further includes adjacent first regions I and second regions II arranged along the bit line direction Y; the first vertical transistor 206 on the same active region 201 is located on the first region I or the second region II, the first vertical transistor 206 on the same first region I is located on one of the adjacent active regions 201, and the first vertical transistor 206 on the same second region II is located on one of the adjacent active regions 201.

[0129] In this embodiment, the semiconductor structure further includes a first annular word line 207, which includes a first annular word line gate oxide layer 2072, a first annular word line gate layer 2073, and an insulating layer 2075. The first annular word line gate oxide layer 2072 surrounds the first vertical transistor 206 and is located on the sidewall surface of the first vertical transistor 206. The first annular word line gate layer 2073 surrounds the first annular word line gate oxide layer 2072. The insulating layer 2075 is located in a fourth trench 2074 between adjacent first annular word line gate layers 2073.

[0130] In this embodiment, the semiconductor structure further includes: a second interlayer dielectric layer 208 and a third interlayer dielectric layer 210, wherein the first annular word lines are located in a first trench between adjacent first vertical transistor 206 structures, the first interlayer dielectric layer 205 is located at the bottom of the first annular word lines 207, the second interlayer dielectric layer 208 is located at the top of the first annular word lines 207, and the third interlayer dielectric layer 210 is located within the first annular word lines 207 and the second interlayer dielectric layer 208.

[0131] In this embodiment, the thickness of the first annular word line gate layer 2073 along the word line direction X ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer 2073 along the direction perpendicular to the substrate 200 ranges from 30 nanometers to 300 nanometers. The material of the first annular word line gate layer 2073 is one of TIN, a combination of TIN and W, or Mo. The first annular word line gate oxide layer 2072 and the first annular word line gate layer 2073 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

[0132] In this embodiment, the semiconductor structure further includes: a second annular word line 307, the second annular word line 307 being discretely arranged along the bit line direction Y, the second annular word line including: a second annular word line gate oxide layer 3071 and a second annular word line gate layer 3072, the second annular word line gate oxide layer 3071 surrounding the first vertical transistor 206, and the second annular word line gate oxide layer 3071 being located on the sidewall surface of the first vertical transistor 206, the second annular word line gate layer 3072 surrounding the second annular word line gate oxide layer 3071, and the second annular word line gate layer 3072 filling the third trench between adjacent second annular word line gate oxide layers 3071.

[0133] In this embodiment, the semiconductor structure further includes: a second interlayer dielectric layer 308 and a third interlayer dielectric layer 310, the second annular word lines 307 being located within a first trench between adjacent first vertical transistors 206, the first interlayer dielectric layer 205 being located at the bottom of the second annular word lines 307, the second interlayer dielectric layer 308 being located at the top of the second annular word lines 307, and the third interlayer dielectric layer 310 being located within the second annular word lines 307 and the second interlayer dielectric layer 308.

[0134] In this embodiment, the thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer 3072 is one of TIN, a combination of TIN and W, or Mo, or the material of the second annular word line gate layer is one of a combination of TIN and Si, or a combination of Mo and Si. The second annular word line gate oxide layer 3071 and the second annular word line gate layer 3072 are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

[0135] In this embodiment, the width of the first vertical transistor 206 ranges from 15 nanometers to 100 nanometers.

[0136] In summary, the first vertical transistors in the technical solution of the present invention are staggered along the bit line direction and word line direction on the first surface of the active region, realizing the spacing distribution between a number of first vertical transistors, which can effectively reduce the coupling effect between adjacent bit lines, improve the storage efficiency of the memory cell, and increase the arrangement density compared with the rectangular arrangement of the prior art.

[0137] Accordingly, please refer to Figure 48The present invention also provides a memory array, comprising: a plurality of bit lines arranged along the word line direction X; a plurality of word lines arranged along the bit line direction Y, wherein the bit lines intersect with the word lines in a grid-like arrangement; a plurality of gate ring transistors 601, wherein the gate ring transistors 601 are arranged in an array at intervals in the grid formed by the intersection of the bit lines and the word lines, wherein in any row of grids formed by the intersection of a word line and the bit lines, the gate ring transistor 601 is located in one of two adjacent grids, and in any column of grids formed by the intersection of a bit line and the word lines, the gate ring transistor 601 is located in one of two adjacent grids, wherein the source / drain of the gate ring transistor 601 is connected to the bit line, and the gate of the gate ring transistor 601 is connected to the word line; and a plurality of memory capacitors 602, wherein the first end of the memory capacitor 602 is connected to the source / drain of the gate ring transistor 601, and the second end of the memory capacitor 602 is grounded.

[0138] In a specific embodiment, the memory array consists of a first word line WL0, a second word line WL1, a third word line WL2, a fourth word line WL3, a fifth word line WL4, a first bit line BL0, a second bit line BL1, a third bit line BL2, a fourth bit line BL3, a fifth bit line BL4, and a plurality of ring gate transistors 601 and memory capacitors 602.

[0139] Depend on Figure 48 It can be seen that in the first row of the memory array, the plurality of gate ring transistors 601 are connected to the first bit line BL0 and the third bit line BL2; in the second row of the memory array, the plurality of gate ring transistors 601 are connected to the second bit line BL1 and the fourth bit line BL3; in the third row of the memory array, the plurality of gate ring transistors 601 are connected to the first bit line BL0 and the third bit line BL2; and in the fourth row of the memory array, the plurality of gate ring transistors 601 are connected to the second bit line BL1 and the fourth bit line BL3.

[0140] In the first column of the memory array, the plurality of gate ring transistors 601 are connected to the first word line WL0 and the third word line WL2. In the second column of the memory array, the plurality of gate ring transistors 601 are connected to the second word line WL1 and the fourth word line WL3. In the third column of the memory array, the plurality of gate ring transistors 601 are connected to the first word line WL0 and the third word line WL2. In the fourth column of the memory array, the plurality of gate ring transistors 601 are connected to the second word line WL1 and the fourth word line WL3.

[0141] The working principle of the above-mentioned memory array is as follows: an enable voltage is applied to any of the word lines, so that the gate ring transistor on the word line is selected, and then an operating voltage is applied to the bit line connected to the gate ring transistor 601, and a default voltage (e.g., VCC / 2) is applied to the bit lines not connected to the gate ring transistor 601, so that the adjacent bit lines play a shielding role and greatly reduce the coupling between adjacent bit lines.

[0142] In a specific embodiment, an enable voltage is applied to the first word line WL0, and an operating voltage is applied to the first bit line BL0 and the third bit line BL2 to perform storage or read operations on the ring gate transistor 601.

[0143] In a specific embodiment, an enable voltage is applied to the second word line WL1, and an operating voltage is applied to the second bit line BL1 and the fourth bit line BL3 to perform storage or read operations on the ring gate transistor 601.

[0144] In a specific embodiment, an enable voltage is applied to the third word line WL2, and an operating voltage is applied to the first bit line BL0 and the third bit line BL2 to perform storage or read operations on the ring gate transistor 601.

[0145] In a specific embodiment, an enable voltage is applied to the fourth word line WL3, and an operating voltage is applied to the second bit line BL1 and the fourth bit line BL3 to perform storage or read operations on the ring gate transistor 601.

[0146] As can be seen, in the above-mentioned storage array, the bit lines are arranged in an alternating pattern, which achieves a shielding effect between adjacent bit lines and greatly reduces the coupling between adjacent bit lines.

[0147] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a bit line direction and a word line direction arranged in a perpendicular cross configuration, the substrate including a plurality of active regions arranged in parallel along the bit line direction and an isolation region located between the active regions, and the substrate including a first surface. A first photoresist layer is formed on the first surface; The first photoresist layer is exposed and developed to form a first photoresist layer with a vertical transistor pattern, wherein the first photoresist layer with the vertical transistor pattern is staggered along the bit line direction and word line direction on the first surface of the active region. Using the first photoresist layer with the vertical transistor pattern as a mask, a portion of the active region and a portion of the isolation region are etched along the first surface to form a vertical transistor and a bit line located at the bottom of the vertical transistor, and a first trench is formed between adjacent vertical transistors. Fill the first trench with a first interlayer dielectric layer; A dry etching process with a selective etching ratio is used to etch away the vertical transistor and the isolation region located on the sidewall surface of the vertical transistor to form a second trench. The first vertical transistor is filled into the second trench.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes adjacent first and second regions arranged along the bit line direction; The first vertical transistor on the same active region and the bit line at the bottom of the first vertical transistor are located on the first region or the second region. The first vertical transistor on the same first region and the bit line at the bottom of the first vertical transistor are located on one of the adjacent active regions. The first vertical transistor on the same second region and the bit line at the bottom of the first vertical transistor are located on one of the adjacent active regions.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for removing the active region and the isolation region is either a dry etching process or a wet etching process.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The etching depth of the dry etching process or the wet etching process along the direction perpendicular to the substrate ranges from 100 nanometers to 500 nanometers, the etching width of the dry etching process or the wet etching process along the word line direction ranges from 5 nanometers to 50 nanometers, and the etching width of the dry etching process or the wet etching process along the bit line direction ranges from 10 nanometers to 100 nanometers.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The width of the vertical transistor ranges from 5 nanometers to 50 nanometers, and the width of the first vertical transistor ranges from 15 nanometers to 100 nanometers.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the step of filling the second trench with the first vertical transistor, the following steps are included: The first interlayer dielectric layer is etched to form a third trench located on the first interlayer dielectric layer; A first annular word line gate oxide layer is formed on the sidewall surface of the third trench, and the first annular word line gate oxide layer surrounds the first vertical transistor; Using an atomic layer deposition process, a first annular word line gate layer and a fourth trench are formed on the bottom surface of the third trench and the sidewall surface of the first annular word line gate oxide layer, wherein the first annular word line gate layer surrounds the first annular word line gate oxide layer. An insulating layer is filled into the fourth trench, and the first annular word line gate layer, the first annular word line gate oxide layer and the insulating layer constitute the first annular word line; The top of the first annular word line gate layer and the insulating layer are etched to form the first annular word line.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo. The first annular word line gate oxide layer and the first annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the step of filling the second trench with the first vertical transistor, the method further includes: The first interlayer dielectric layer is etched to form a third trench located on the first interlayer dielectric layer; A second annular word line gate oxide layer is formed on the sidewall surface of the third trench, and the second annular word line gate oxide layer surrounds the first vertical transistor; A second annular word line gate layer is filled into the third trench using atomic layer deposition, PVD, or CVD processes. The second annular word line gate layer surrounds the second annular word line gate oxide layer, and the second annular word line gate layer and the second annular word line gate oxide layer constitute the second annular word line. The top of the second annular word line gate oxide layer and the second annular word line gate layer are etched to form the second annular word line.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or a combination of TIN and Si, or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

10. The method for forming a semiconductor structure as described in claim 6 or 8, characterized in that, The substrate includes a second surface, and the first surface and the second surface are two opposite surfaces of the substrate; After the step of forming the first circular character line and after the step of forming the second circular character line, the following is also included: A second interlayer dielectric layer is formed on top of the first ring word line and the second ring word line, and the second interlayer dielectric layer is flush with the top of the first vertical transistor; A hard mask layer is formed on the substrate, the hard mask layer extends along the word line direction and covers all the first vertical transistors along the word line direction, the hard mask layers are discretely arranged along the bit line direction, and a portion of the top surface of the second interlayer dielectric layer is exposed between adjacent hard mask layers in the bit line direction. Using the hard mask layer as a mask, the second interlayer dielectric layer and the first and second ring word lines are etched sequentially until the first interlayer dielectric layer is exposed, forming a plurality of discrete first ring word lines, second ring word lines and a fifth trench, and the plurality of discrete first and second ring word lines are arranged along the bit line direction. A third interlayer dielectric layer is filled into the fifth trench, and the third interlayer dielectric layer is flush with the top of the first vertical transistor; The second surface of the substrate is thinned, and a portion of the substrate and a portion of the bit lines are etched away to form a plurality of discrete bit lines.

11. A semiconductor structure, characterized in that, include: A substrate having a bit line direction and a word line direction arranged in a perpendicular cross configuration, the substrate including a plurality of active regions arranged in parallel along the bit line direction and an isolation region located between the active regions, and the substrate including a first surface. A first vertical transistor is formed on a first surface of an active region that is alternately spaced in the bit line direction and word line direction, and a first trench is formed between adjacent first vertical transistors. 、 Bit lines are located at the bottom of the first vertical transistor; The first interlayer dielectric layer is located within the first trench.

12. The semiconductor structure as claimed in claim 11, characterized in that, The substrate further includes adjacent first and second regions arranged along the bit line direction; The first vertical transistor on the same active region and the bit line at the bottom of the first vertical transistor are located on the first region or the second region. The first vertical transistor on the same first region and the bit line at the bottom of the first vertical transistor are located on one of the adjacent active regions. The first vertical transistor on the same second region and the bit line at the bottom of the first vertical transistor are located on one of the adjacent active regions.

13. The semiconductor structure as described in claim 11, characterized in that, Also includes: The first annular word line includes: a first annular word line gate oxide layer, a first annular word line gate layer, and an insulating layer. The first annular word line gate oxide layer surrounds the first vertical transistor and is located on the sidewall surface of the first vertical transistor. The first annular word line gate layer surrounds the first annular word line gate oxide layer. The insulating layer is located in a fourth trench between adjacent first annular word line gate layers.

14. The semiconductor structure as described in claim 13, characterized in that, Also includes: The second interlayer dielectric layer and the third interlayer dielectric layer are located in the first trench between adjacent first vertical transistors between the first ring word lines. The first interlayer dielectric layer is located at the bottom of the first ring word line, the second interlayer dielectric layer is located at the top of the first ring word line, and the third interlayer dielectric layer is located within the first ring word line and the second interlayer dielectric layer.

15. The semiconductor structure as described in claim 14, characterized in that, The thickness of the first annular word line gate layer along the word line direction ranges from 1 nanometer to 10 nanometers, and the depth of the first annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the first annular word line gate layer is one of TIN, a combination of TIN and W, or Mo. The first annular word line gate oxide layer and the first annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

16. The semiconductor structure as claimed in claim 11, characterized in that, Also includes: The second annular word line is discretely arranged along the bit line direction. The second annular word line includes a second annular word line gate oxide layer and a second annular word line gate layer. The second annular word line gate oxide layer surrounds the first vertical transistor and is located on the sidewall surface of the first vertical transistor. The second annular word line gate layer surrounds the second annular word line gate oxide layer and fills the third trench between adjacent second annular word line gate oxide layers.

17. The semiconductor structure as claimed in claim 16, characterized in that, Also includes: The second interlayer dielectric layer and the third interlayer dielectric layer are located in the first trench between adjacent first vertical transistors, the second ring word line is located at the bottom of the second ring word line, the second interlayer dielectric layer is located at the top of the second ring word line, and the third interlayer dielectric layer is located within the second ring word line and the second interlayer dielectric layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, The thickness of the second annular word line gate layer along the word line direction ranges from 5 nanometers to 50 nanometers, and the depth of the second annular word line gate layer along the direction perpendicular to the substrate ranges from 30 nanometers to 300 nanometers. The material of the second annular word line gate layer is one of TIN, a combination of TIN and W, or Mo, or a combination of TIN and Si, or a combination of Mo and Si. The second annular word line gate oxide layer and the second annular word line gate layer are closed annular rings, wherein the annular ring is a circular annular ring, an elliptical annular ring, a square annular ring, or a polygonal annular ring.

19. The semiconductor structure as claimed in claim 11, characterized in that, The width of the first vertical transistor ranges from 15 nanometers to 100 nanometers.

20. A storage array, characterized in that, include: Several bit lines, the several bit lines are arranged along the word line direction; A plurality of word lines are arranged along the bit line direction, and the plurality of bit lines intersect with the plurality of word lines in a grid pattern. A plurality of gate ring transistors are arranged in an array at intervals in a grid formed by the intersection of a plurality of bit lines and a plurality of word lines. In a row of grids formed by the intersection of any word line and a plurality of bit lines, the gate ring transistor is located in one of two adjacent grids. In a column of grids formed by the intersection of any bit line and a plurality of word lines, the gate ring transistor is located in one of two adjacent grids. The source / drain of the gate ring transistor is connected to the bit line, and the gate of the gate ring transistor is connected to the word line. A plurality of storage capacitors, wherein the first end of the storage capacitors is connected to the source / drain of the ring gate transistor, and the second end of the storage capacitors is grounded.

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