Memory device, manufacturing method and control method

Abstract

The embodiment of the invention discloses a memory device, a manufacturing method and a control method, and the memory device comprises rows which comprise first semiconductor columns and second semiconductor columns which are alternately arranged along a first direction, and odd-numbered rows and even-numbered rows are alternately arranged along a second direction; the columns comprise first semiconductor columns and second semiconductor columns which are alternately arranged in the second direction, and the odd-numbered columns and the even-numbered columns are alternately arranged in the first direction; the size of the first semiconductor column in the third direction is larger than that of the second semiconductor column in the third direction; the first semiconductor column comprises a first end and a second end which are oppositely arranged along a third direction, and an area between the first end and the second end is a middle part; a gate structure extending in a first direction; gate structures surround the middle parts of the first semiconductor columns on the rows; the bit line extends along the second direction and is positioned on one side, close to the first end, of the first semiconductor column; a bit line is coupled to a first end of the first semiconductor pillar on the column.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device, a method for manufacturing the same, and a method for controlling the same. Background Technology

[0002] Some memory devices, such as Dynamic Random Access Memory (DRAM), may include a memory array and peripheral circuitry. The peripheral circuitry controls the memory array, performing read, write, or refresh operations. The memory array comprises multiple memory cells arranged in rows and columns. Each memory cell may include coupled transistors and capacitors. Turning on the transistors selects and accesses the capacitors. There is considerable room for improvement in both memory devices and their fabrication methods to enhance performance. Summary of the Invention

[0003] According to some aspects of embodiments of the present disclosure, a memory device is provided, comprising: rows including first semiconductor pillars and second semiconductor pillars alternately disposed along a first direction, wherein odd-numbered rows and even-numbered rows are alternately arranged along a second direction;

[0004] The column includes first semiconductor pillars and second semiconductor pillars alternately arranged along the second direction, and odd-numbered columns and even-numbered columns are alternately arranged along the first direction; there is a second semiconductor pillar between any two adjacent first semiconductor pillars in the row, and there is a second semiconductor pillar between any two adjacent first semiconductor pillars in the column;

[0005] The first semiconductor pillar and the second semiconductor pillar extend along a third direction, and the dimension of the first semiconductor pillar in the third direction is greater than the dimension of the second semiconductor pillar in the third direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction;

[0006] The first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction, and the region between the first end and the second end is a middle portion;

[0007] A gate structure extending along the first direction; the gate structure corresponds to the row and surrounds the middle portion of the first semiconductor pillar on the row;

[0008] Bit lines extend along the second direction and are located on the side of the first semiconductor pillar near the first end; the bit lines correspond to the column and are coupled to the first end of the first semiconductor pillar on the column.

[0009] In some embodiments, the first gate structure in the gate structure is configured to apply a first operating voltage to select the first row;

[0010] The odd-numbered bit lines corresponding to the first row are configured to apply a second operating voltage to select the odd-numbered columns in the first row, and the even-numbered bit lines corresponding to the first row are configured to apply a preset voltage; or,

[0011] The even-numbered bit lines corresponding to the first row are configured to apply the second operating voltage to select the even-numbered column on the first row, and the odd-numbered bit lines corresponding to the first row are configured to apply the preset voltage.

[0012] According to some aspects of embodiments of this disclosure, a method for manufacturing a memory device is provided, comprising:

[0013] Etching a semiconductor layer forms a first trench and a second trench, the first trench and the second trench dividing the semiconductor layer into a plurality of semiconductor pillars; the second trench extends along a first direction, and the first trench extends along a second direction; wherein the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects with a third direction;

[0014] The semiconductor pillar is etched along the third direction to form a third trench extending along the second direction; the third trench penetrates the semiconductor pillar and divides one semiconductor pillar into two first semiconductor pillars spaced apart along the first direction.

[0015] Etching is performed on any two adjacent first semiconductor pillars in the first direction along the third direction to form a second semiconductor pillar; etching is performed on any two adjacent first semiconductor pillars in the second direction along the third direction to form a second semiconductor pillar.

[0016] A gate dielectric layer is formed around the sidewall of the first semiconductor pillar, and a gate structure is formed around the middle portion of the first semiconductor pillar, the gate structure extending along the first direction; the first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction, and the region between the first end and the second end is the middle portion;

[0017] A bit line is formed on the side of the first semiconductor pillar near the first end, the bit line extending along the second direction and coupled to the first end of the first semiconductor pillar.

[0018] According to some aspects of embodiments of this disclosure, a control method for a memory device is provided, applied to any of the memory devices described in the present disclosure, wherein the gate structure of the memory device is configured as word lines, and the control method includes:

[0019] A first operating voltage is applied to the first word line in the word lines to select the first row;

[0020] Apply a second operating voltage or float to the odd-numbered bit lines corresponding to the first row, and apply a preset voltage to the even-numbered bit lines corresponding to the first row to select the odd-numbered column in the first row; or,

[0021] The second operating voltage or floating is applied to the even-numbered bit lines corresponding to the first row, and the preset voltage is applied to the odd-numbered bit lines corresponding to the first row to select the even-numbered column in the first row.

[0022] This disclosure provides a memory device comprising an array of alternating first and second semiconductor pillars, the alternating first and second semiconductor pillars along a first direction forming a row, and the alternating first and second semiconductor pillars along a second direction forming a column, with the rows and columns intersecting. The first and second semiconductor pillars extend along a third direction, with the dimension of the first semiconductor pillar in the third direction being larger than the dimension of the second semiconductor pillar in the third direction. Each first semiconductor pillar includes a first end and a second end disposed opposite each other along the third direction, with the region between the first end and the second end being a middle portion. A gate structure extending along the first direction corresponds to the row and surrounds the first semiconductor pillar on the row. The memory device comprises: a bit line extending along a second direction and located on the side of the first semiconductor pillar near its first end; a bit line corresponding to a column and coupled to the first end of the first semiconductor pillar in the column; the first semiconductor pillar can be connected to a capacitor structure, and the second semiconductor pillar is not used to connect to a capacitor structure but can be used to form continuous bit lines; the first semiconductor pillars in adjacent columns are staggered to reduce mutual interference between the first semiconductor pillars; one of the odd-numbered bit lines and the even-numbered bit lines can be selected for operation by applying an operating voltage or floating, and the other bit lines are subjected to other voltages to reduce crosstalk, that is, any two operating bit lines are separated by a non-operating bit line with other fixed voltages applied to reduce crosstalk, thereby improving the stability of the memory device. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an exemplary storage array according to an exemplary embodiment;

[0024] Figure 2 This is a schematic diagram of a semiconductor pillar distribution according to an exemplary embodiment;

[0025] Figures 3 to 5 This is a schematic diagram of an exemplary memory device shown according to embodiments of the present disclosure;

[0026] Figure 6 This is a flowchart illustrating the fabrication process of an exemplary memory device according to embodiments of the present disclosure;

[0027] Figures 7 to 22 This is a schematic diagram illustrating a method for fabricating a memory device according to an embodiment of the present disclosure;

[0028] Figure 23 This is a schematic diagram of a memory device control method according to an embodiment of the present disclosure.

[0029] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0030] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0031] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0036] The memory device in the embodiments of this disclosure may be DRAM, or at least a portion of DRAM, or the memory device may include DRAM, which includes the memory device of this disclosure. It is applicable to Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) using DDR4 memory specifications, DDR5 memory specifications, and Low Power Double Data Rate DRAM using LPDDR5 memory specifications. It should be noted that the embodiments of this disclosure are not limited to DRAM, but for clarity, DRAM will be used as an example in the following description.

[0037] In DRAM, memory arrays can be arranged in rows and columns, allowing memory cells to be addressed by specifying their rows and columns. A memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting the memory cell at the intersection of the selected word line and bit line selects it for read, write, or refresh operations. Figure 1 As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. Memory cells within the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. The word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have an additional voltage (such as Vcc / 2) applied to it. Figure 1 As shown, the memory cell array is arranged in an x-row, y-column configuration. The rows and columns can be perpendicular or non-perpendicular. The x-direction can be the first direction mentioned in the embodiments of this disclosure, and the y-direction can be the second direction mentioned in the embodiments of this disclosure. The extension direction of the word line or row can be parallel to the x-direction or at an angle to the x-direction. The extension direction of the bit line or column can be parallel to the y-direction or at an angle to the y-direction. The orthogonal projection of the word line on the xoy plane is perpendicular to the orthogonal projection of the bit line on the xoy plane, or it is not perpendicular but at a certain angle. This disclosure does not limit this. The z-direction in the examples shown below can be a third direction. The z-direction can be perpendicular to the xoy plane, or it can intersect the xoy plane but not perpendicular to it. The z-direction can be a vertical direction, and the z-direction can be the wafer thickness direction or the device thickness direction.

[0038] The memory array of this disclosure embodiment has memory cells arranged in rows and columns. A row of the memory array may include transistors arranged along the x-direction and capacitors coupled to the transistors. A row may also be called a sub-memory array. A column of the memory array may include transistors arranged along the y-direction and capacitors coupled to the transistors. A column may also be called a sub-memory array.

[0039] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0040] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0041] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1 Peripheral circuitry coupled to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to: a sensing amplifier circuit, a row decoding circuit, a column decoding circuit, and a voltage generation circuit. The sensing amplifier circuit is coupled to bit lines and can be configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sensing amplifier circuit may include a latch to latch the reconstructed capacitor voltage value, thereby transferring the information stored in the memory cell from the capacitor to the amplifier circuit. The sensing amplifier circuit may include a differential sensing amplifier circuit coupled to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuit is configured to address the memory array and apply an operating voltage to the word lines. The column decoding circuit is configured to column address the memory array, apply a bit line voltage, or receive a bit line voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0042] According to some aspects of embodiments of this disclosure, Figure 2 An exemplary planar distribution of a transistor is provided. The transistor includes a semiconductor pillar 101 or an active pillar, the semiconductor pillar 101 extending along the z-direction, and a gate 102 (or word line) surrounding the sidewalls of the semiconductor pillar 101 extending along the z-direction. The gate 102 and the semiconductor pillar 101 are separated by a gate dielectric layer. The gate 102 serves as the control terminal of the transistor to control the transistor's on and off states by applying a voltage. The opposite ends of the semiconductor pillar 101 along the z-direction are doped to form active regions, which respectively serve as the source or drain of the transistor. The region between the source and drain forms the transistor channel, and the positions of the source and drain are interchangeable. The gate 102 can serve as a word line of a memory device, extending along the x-direction, and can be coupled to or correspond to multiple semiconductor pillars 101 arranged in the x-direction. The semiconductor pillars 101 penetrate the gate 102 along the z-direction and expose both ends. A bit line 103 is coupled to one end of the semiconductor pillar 101 (such as one of the source or drain). The bit line 103 extends along the y-direction and can be coupled to or correspond to multiple semiconductor pillars 101 arranged in the y-direction. Figure 2As shown, semiconductor pillars 101 on any two adjacent columns are aligned with each other, and semiconductor pillars 101 on any two adjacent rows are aligned with each other. When the integration density of transistors increases, when adjacent columns are selected or accessed to perform operations, the small spacing between semiconductor pillars 101 may cause crosstalk. The small spacing between bit lines 103 may also cause crosstalk and lead to a reduction in the sensing window of bit line 103, thereby reducing the operating accuracy and stability of memory devices.

[0043] In view of this, an exemplary memory device 200 is provided according to some aspects of embodiments of the present disclosure, such as... Figure 3 This is a cross-sectional schematic diagram of the memory device 200 in the xoy plane, or a planar distribution schematic diagram. Different cross-sectional positions of the same structure have different cross-sectional morphologies or structures. Figure 4 and Figure 5 yes Figure 3 Schematic diagrams of cross-sections at AA' (parallel to the y-direction) and BB' (parallel to the x-direction) in the structure; refer to Figure 3 , Figure 4 as well as Figure 5 As shown, the memory device 200 includes:

[0044] The rows include first semiconductor pillars 201 and second semiconductor pillars 202 alternately arranged along a first direction (x direction), and odd-numbered rows and even-numbered rows alternately arranged along a second direction (y direction);

[0045] The column includes first semiconductor pillars 201 and second semiconductor pillars 202 alternately arranged along the y direction, and odd columns and even columns are arranged alternately along the x direction; there is a second semiconductor pillar 202 between any two adjacent first semiconductor pillars 201 in the row, and there is a second semiconductor pillar 202 between any two adjacent first semiconductor pillars 201 in the column.

[0046] The first semiconductor pillar 201 and the second semiconductor pillar 202 extend along the z-direction, and the dimension of the first semiconductor pillar 201 in the z-direction is larger than the dimension of the second semiconductor pillar 202 in the z-direction; wherein, the x-direction intersects the y-direction, and the plane formed by the x-direction and the y-direction intersects the z-direction;

[0047] The first semiconductor pillar 201 includes a first end and a second end disposed opposite to each other along the z-direction, and the region between the first end and the second end is the middle part;

[0048] A gate structure 203 extends along the x-direction; the gate structure 203 corresponds to the row and surrounds the middle portion of the first semiconductor pillar 201 on the row;

[0049] Bit line 204 extends along the y direction and is located on the side of the first semiconductor pillar 201 near the first end; bit line 204 corresponds to the column and is coupled to the first end of the first semiconductor pillar 201 on the column.

[0050] In some embodiments, the memory device 200 further includes:

[0051] A gate dielectric layer 205 is located between the gate structure 203 and the first semiconductor pillar 201; the gate dielectric layer 205 surrounds the sidewall of the first semiconductor pillar 201;

[0052] Capacitor structure 206 is located on the side of the first semiconductor pillar 201 away from the bit line 204, and capacitor structure 206 is coupled to the second end of the first semiconductor pillar 201. Capacitor structure 206 can be described as follows. Figure 22 As exemplified, capacitor structure 206 may include a first electrode, a second electrode, and an insulating layer located between the first electrode and the second electrode. This disclosure does not limit the capacitor structure 206. For example, capacitor structure 206 may include a first electrode extending along the z-direction, which may be columnar; an insulating layer surrounding the first electrode; and a second electrode surrounding the insulating layer. The second electrode is located close to the first semiconductor column 201 relative to the first electrode. The second electrode is coupled to a second end of the first semiconductor column 201 or coupled through other connecting portions, which may include, but are not limited to, metal, metal silicide, or combinations thereof. The first electrode is grounded or connected to another common voltage. Multiple capacitor structures 206 may share the first electrode.

[0053] Reference Figure 3 As shown, the memory device 200 may include multiple rows extending along the x-direction. Each row may include alternating first semiconductor pillars 201 and second semiconductor pillars 202 arranged in the x-direction, and may also include a capacitor structure 206 coupled to the second end of the first semiconductor pillar 201. A column extends along the y-direction and intersects with the rows. Each column may include alternating first semiconductor pillars 201 and second semiconductor pillars 202 arranged in the y-direction, and may also include a capacitor structure 206 coupled to the second end of the first semiconductor pillar 201. A schematic diagram of the column structure is shown below. Figure 4 The example provided illustrates the structure of a row as follows: Figure 5 As illustrated in the embodiments of this disclosure, there is no limitation on the number of rows and columns, nor on the number of the first semiconductor pillar 201 and the second semiconductor pillar 202. The transistor may include the first semiconductor pillar 201, a gate structure 203 portion corresponding to the first semiconductor pillar 201, and a gate dielectric layer 205 portion. The first semiconductor pillar 201 extends along the z-direction. The first end of the first semiconductor pillar 201 may be the bottom in the negative z-direction, and the second end may be the top in the positive z-direction. The first and second ends may be homo-doped source or drain electrodes. The middle portion between the first and second ends forms the transistor channel, which is inversely doped compared to the first end.

[0054] The gate structure 203, serving as the control gate of the transistor, surrounds the middle sidewall of the first semiconductor pillar 201. The gate structure 203 and the first semiconductor pillar 201 are separated by a gate dielectric layer 205. The first semiconductor pillar 201 extends through the gate structure 203 along the z-direction, with its first and second ends exposed within the gate structure 203. The first end is coupled to the bit line 204 at the bottom of the first semiconductor pillar 201, and the second end is coupled to the capacitor structure 206 at the top of the first semiconductor pillar 201. The gate structure 203 serves as the word line of the memory device 200, corresponding to the first semiconductor pillar 201 on the row. Figure 3 The gate structure 203 covers the second semiconductor pillar 202, and the position of the second semiconductor pillar 202 is indicated by a dashed box. The gate dielectric layer 205 surrounds at least the middle sidewall of the first semiconductor pillar 201. The gate dielectric layer 205 may cover other sidewall areas of the first semiconductor pillar 201 but exposes the top surface of the second end for easy coupling of the capacitor structure 206. Other parts of the gate dielectric layer 205 may be located in any area of ​​the second semiconductor pillar 202, such as covering the sidewalls and top surface of the second semiconductor pillar 202.

[0055] Reference Figure 4 and Figure 5 As shown, the dimension of the first semiconductor pillar 201 in the z-direction is larger than that of the second semiconductor pillar 202 in the z-direction. The first semiconductor pillar 201 is used to construct a transistor array, to couple with the capacitor structure 206 to form a DRAM memory cell, or to couple with other device structures to form logic circuits such as gate circuits. The second semiconductor pillar 202 is not used for electrical connection of the circuit structure. The second semiconductor pillar 202 is used to provide physical support for the device structure and to space between two adjacent first semiconductor pillars 201, so as to realize the staggered arrangement of the first semiconductor pillars 201, reduce crosstalk between two adjacent first semiconductor pillars 201 in a row, and reduce crosstalk between two adjacent first semiconductor pillars 201 in a column.

[0056] Reference Figure 4 The illustrated column cross-sectional diagram includes a bit line 204 corresponding to a column; the first semiconductor pillar 201 and the second semiconductor pillar 202 can be broken or connected via semiconductor material. (Refer to...) Figure 5The schematic cross-sectional view shown illustrates multiple bit lines 204. The first semiconductor pillar 201 and the second semiconductor pillar 202 in the x-direction are interrupted and isolated by a dielectric material. Each bit line 204 corresponds to the bottom of the first semiconductor pillar 201 and the bottom of the second semiconductor pillar 202. Adjacent bit lines 204 are isolated by a dielectric material. Different regions of this embodiment can be electrically isolated using dielectric materials. The gate dielectric layer 205 and the dielectric material can include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Dielectric materials of the same composition and film layers such as the gate dielectric layer 205 may not have a clear physical boundary after contact.

[0057] Reference Figure 4 The example illustrates multiple electrically isolated gate structures 203. The gate structure 203 surrounding the sidewalls of the first semiconductor pillar 201 forms a word line corresponding to one row, while the gate structure 203 covering the second semiconductor pillar 202 forms a word line corresponding to another row. (Refer to...) Figure 5 The example includes a gate structure 203 that surrounds the sidewall of the first semiconductor pillar 201 and covers the second semiconductor pillar 202.

[0058] In some embodiments, the height of the top surface of the second end of the first semiconductor pillar 201 is greater than the height of the top surface of the end of the second semiconductor pillar 202 furthest from the bit line 204. The second end of the first semiconductor pillar 201 is higher than the upper end of the second semiconductor pillar 202, facilitating coupling between the upper end of the first semiconductor pillar 201 and devices such as the capacitor structure 206, reducing the electrical connection distance in the z-direction, and improving the integration density of the memory device 200 in the z-direction. The bottom of the first semiconductor pillar 201 and the bottom of the second semiconductor pillar 202 can be connected by a semiconductor material, forming a continuous integral structure; the bottoms of the first semiconductor pillar 201 and the bottom of the second semiconductor pillar 202 can be at the same film layer height or at different film layer heights.

[0059] Reference Figures 3 to 5 As shown, the second semiconductor pillar 202 is covered by the gate structure 203 and does not protrude from the gate structure 203. The second semiconductor pillar 202 and the first semiconductor pillar 201 are arranged alternately in the x and y directions, such that the first semiconductor pillars 201 between any two adjacent columns are misaligned and offset along the y direction, and the first semiconductor pillars 201 between any two adjacent rows are misaligned and offset along the x direction; for example Figure 3 The first semiconductor pillar 201a and the first semiconductor pillar 202b are not aligned along the y-direction. This disclosure does not limit the cross-sectional shape of the first semiconductor pillar 201 in the xoy plane; the square shape is merely an example, and it may be any shape, such as a rectangle, circle, rhombus, trapezoid, ellipse, or an irregular shape.

[0060] In some specific embodiments, each odd-numbered column in any odd-numbered row is a first semiconductor pillar 201, and each even-numbered column in any even-numbered row is a first semiconductor pillar 201; each even-numbered column in any odd-numbered row is a second semiconductor pillar 202, and each odd-numbered column in any even-numbered row is a second semiconductor pillar 202. Alternatively, each odd-numbered column in any odd-numbered row is a second semiconductor pillar 202, and each even-numbered column in any even-numbered row is a second semiconductor pillar 202; each even-numbered column in any odd-numbered row is a first semiconductor pillar 201, and each odd-numbered column in any even-numbered row is a first semiconductor pillar 201. (Refer to...) Figure 3 As shown, the intersection of the first row and the first column can be a first semiconductor pillar 201, the intersection of the first row and the second column can be a second semiconductor pillar 202, the intersection of the second row and the first column can be a second semiconductor pillar 202, and the intersection of the second row and the second column can be a first semiconductor pillar 201. In some other specific embodiments, the intersection of the first row and the first column can be a second semiconductor pillar 202, the intersection of the first row and the second column can be a first semiconductor pillar 201, the intersection of the second row and the first column can be a first semiconductor pillar 201, and the intersection of the second row and the second column can be a second semiconductor pillar 202.

[0061] In some embodiments, refer to Figure 3 As shown, the bit line 204 has two protruding ends relative to the gate structure 203 in the y-direction. Either end or both ends of the bit line 204 in the y-direction can be used to couple with a connection structure. The connection structure may include conductive plugs, conductive channels, or other structures for powering the bit line 204 or sensing signals from the bit line 204. The connection structure may be located on the side of the bit line 204 closer to the first semiconductor pillar 201 in the z-direction, or it may be located on the side of the bit line 204 farther from the first semiconductor pillar 201 in the z-direction.

[0062] For example, the materials constituting the gate structure 203 and the connection structure may include, but are not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum. The materials constituting the semiconductor pillars may include, but are not limited to, elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. The bit line 204 may include a metallic conductive material, or it may include a semiconductor metallization material, such as titanium silicide, nickel silicide, or other metal silicides. The bit line 204 may also be formed by heavily doping semiconductor materials to create conductive lines.

[0063] In some embodiments, refer to Figure 4In the example of the column cross-sectional schematic diagram, the bottom of the first semiconductor pillar 201 and the bottom of the second semiconductor pillar 202 in the y direction can be connected to each other through semiconductor materials, or the first semiconductor pillar 201, the second semiconductor pillar 202 and the semiconductor material connected to the bottom are an integral structure, and there may be no physical boundary or the physical boundary may be indistinct. The first semiconductor pillar 201 and the second semiconductor pillar 202 are formed by etching the same semiconductor layer 2001 or semiconductor material. The first semiconductor pillar 201 may be doped to form the active region and channel of the transistor, and the second semiconductor pillar 202 may be doped or not.

[0064] In some embodiments, refer to Figure 4 As exemplified, the columns include:

[0065] A semiconductor strip 2011 extends along the y-direction and is located on the side of the first semiconductor pillar 201 near its first end. The semiconductor strip 2011 connects the first semiconductor pillar 201 and the second semiconductor pillar 202. The semiconductor strip 2011, the first semiconductor pillar 201, and the second semiconductor pillar 202 are made of the same material, such as silicon. The semiconductor strip 2011 is leftover material from the etching process of the semiconductor material to form the first semiconductor pillar 201 and the second semiconductor pillar 202, used to reduce the etching depth. The semiconductor strip 2011 can be used to form bit lines 204 or to carry bit lines 204. There may be no clear physical boundary between the semiconductor strip 2011, the first semiconductor pillar 201, and the second semiconductor pillar 202.

[0066] In some embodiments, the bit line 204 is located on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201; the semiconductor strip 2011 includes silicon, and the bit line 204 includes a metal silicide. The bit line 204 can be formed based on the semiconductor strip 2011, such as by metallizing the semiconductor strip 2011 to form a metal compound to constitute the bit line 204, or by depositing a metal material on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction to form the bit line 204, or by heavily doping the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction to form a conductive line. For example, the semiconductor strip 2011 may include silicon, and a metal material is deposited on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction and subjected to heat treatment. A portion of the silicon in the semiconductor strip 2011 reacts with the metal material to form a metal silicide layer to form the bit line 204. The metal silicide may include, but is not limited to, titanium silicide, nickel silicide, etc. For example, conductive materials such as tungsten, aluminum, and titanium can be deposited on metal silicides to form bit lines 204 with composite material layers, thereby improving the electrical connection performance between bit lines 204 and the first semiconductor pillar 201 and reducing contact resistance.

[0067] In some embodiments, refer to Figure 4 and Figure 5 As shown, the gate structure 203 surrounds the sidewall of the second semiconductor pillar 202 extending in the z-direction and covers the end of the second semiconductor pillar 202 away from the bit line 204. The first semiconductor pillar 201 extends through the gate structure 203 in the z-direction, with its top end exposed from the gate structure 203. A dielectric material is located at the first end of the first semiconductor pillar 201, situated between the gate structure 203 and the semiconductor strip 2011. The dielectric material surrounds the first end of the first semiconductor pillar 201 to reduce leakage current and to adjust the doping height at the first end. The gate structure 203 covers the portion of the second semiconductor pillar 202 exposed from the dielectric material, surrounding the portion of the first semiconductor pillar 201 exposed from the dielectric material and exposing the second end. In other embodiments, the gate structure 203 may surround the sidewall of the second semiconductor pillar 202, exposing the end of the second semiconductor pillar 202 away from the bit line 204 in the z-direction.

[0068] In some embodiments, Figure 5 As shown, taking a gate structure 203 corresponding to a row as an example, the gate structure 203 may include:

[0069] A first portion surrounds the first semiconductor pillar 201, and a second portion covers the second semiconductor pillar 202; wherein the top surface height of the first portion is greater than the top surface height of the second portion. A gate structure 203 extends along the x-direction, and the top surface of the gate structure 203 is away from the bit line 204 in the z-direction, i.e., the top surface in the positive z-direction has a different film height. The first portion surrounds the middle part of the first semiconductor pillar 201 as the transistor control gate, and the second portion covers the second semiconductor pillar 202; with the bit line 204 as a horizontal reference, the top surface film height of the first portion is greater than the top surface film height of the second portion.

[0070] In some embodiments, refer to Figure 5 As shown, the first plane intersects the y-direction and is parallel to the z-direction. The first plane can be... Figure 5 The xoz plane is perpendicular to or intersects the y-direction; the cross-sectional structure of the gate structure 203 along the xoz plane includes:

[0071] The I-beam 2031, also known as an I-shaped component, is located between two adjacent first semiconductor pillars 201 in the x-direction. The I-beam 2031 includes two side surfaces extending in the z-direction and a top surface located between and connecting the two side surfaces. The side surfaces of the I-beam 2031 are located between adjacent first semiconductor pillars 201 and second semiconductor pillars 202. The side surfaces of the I-beam 2031 cover the sidewalls of the first semiconductor pillars 201 in the x-direction and are spaced apart from the first semiconductor pillars 201 by a gate dielectric layer 205. The top surface of the I-beam 2031 covers the second semiconductor pillars 202 in the z-direction.

[0072] Figure 5 for Figure 3 The example of the cross-sectional structure at BB' is provided for the purposes of explaining the gate structure 203 of this disclosure, and is not intended to impose any other limitations on the gate structure 203. Figure 5 The gate structure 203 shown is an example corresponding to a certain row. The gate structure 203 is in Figure 5 The cross-sectional structure of the gate structure 203 can be composed of multiple H-shaped sections 2031. The H-shaped structure can be located above the second semiconductor pillar 202 and between two adjacent first semiconductor pillars 201. Two opposing sides of the H-shaped section 2031 along the x-direction are located between the first semiconductor pillar 201 and the second semiconductor pillar 202. The top surface of the H-shaped section 2031 along the z-direction covers the second semiconductor pillar 202, and the film height is lower than the film height of the sides. The sides of two adjacent H-shaped sections 2031 surround the sidewall of a first semiconductor pillar 201, and one H-shaped section 2031 covers a second semiconductor pillar 202. The top surface heights of the various sides of the H-shaped section 2031 extending along the z-direction may not be equal in the z-direction, but the top surface height of any side is greater than the surface height of its top surface extending along the x-direction between the sides. In other embodiments, the cross-sectional structure of the gate structure 203 along the xoz plane may include a Z-shape or a U-shape. For example, in a Z-shape... Figure 5 In the example of the H-beam 2031, the top surfaces of the two sides extending along the z-direction are flush with the top surface extending along the x-direction; as in the case of a U-shape, Figure 5 The bottom surfaces of the two sides of the H-shaped part 2031 extending along the z-direction are flush with the top surface extending along the x-direction.

[0073] In some embodiments, Figures 3 to 5 The illustrated memory device 200 can be used as a memory device, or as part of a memory device, wherein a first gate structure of a plurality of gate structures 203 is configured to apply a first operating voltage to select a first row; the first gate structure is any one of the plurality of gate structures 203; the odd-numbered bit lines 204 corresponding to the first row are configured to apply a second operating voltage or float to select odd-numbered columns on the first row, and the even-numbered bit lines 204 corresponding to the first row are configured to apply a preset voltage; or,

[0074] The even bit line 204 corresponding to the first row is configured to apply a second operating voltage or float to select the even column on the first row, and the odd bit line 204 corresponding to the first row is configured to apply a preset voltage.

[0075] A first operating voltage is applied to the selected word line to be operated on. This first operating voltage is greater than or equal to the threshold voltage of the transistor (or the first semiconductor pillar 201), turning on the transistor on the corresponding row. Other voltages are applied to unselected word lines that do not require operation to turn off the transistors and reduce inter-row crosstalk. When a write operation is performed on the memory cell, a second operating voltage, such as Vcc or 0, is applied to the selected bit line to be operated on; other unselected bit lines are applied with a preset voltage, such as Vcc / 2 or another fixed voltage. When a read operation is performed, the selected bit line to be operated on is floated, and the other unselected bit lines are applied with the preset voltage Vcc / 2.

[0076] Different read, write, and refresh operations on the memory device 200 require different operating voltages and timing sequences. The first and second operating voltages can be applied with different values ​​depending on the timing sequence. These voltages can be generated and applied within their respective voltage fluctuation ranges, specifically generated by a voltage generator in the peripheral circuit and applied to the gate structure 203 (word line) and bit line 204 corresponding to the address. The preset voltage is a fixed or static voltage, a calibration value used for testing the memory device, such as Vcc / 2 or other voltages. It is applied to the unselected bit line 204, preventing the access of the transistor and capacitor structure 206 corresponding to the unselected bit line 204 from performing operations.

[0077] In some embodiments, taking any one of multiple rows as an example of the target behavior, the first semiconductor pillar 201 is located on an odd-numbered column of the first row. A first operating voltage is applied to the gate structure 203 corresponding to the first row, turning on all transistors in the first row and selecting them. A cutoff voltage is applied to the gate structures 203 corresponding to other rows to turn off the transistors. If all or some odd-numbered bit lines 204 in the first row need to be selected for operation, a second operating voltage is applied to or the selected odd-numbered bit lines 204 are floated, and a preset voltage, which can be 1 / 2Vcc, i.e., the average potential value between the high potential 1 and the low potential of the bit line 204, is applied to some or all even-numbered bit lines 204 to prevent crosstalk between adjacent transistors in the first row and improve device stability. Adapted to the arrangement of the first semiconductor pillar 201 and the second semiconductor pillar 202 on the first row, the first semiconductor pillar 201 on the selected odd-numbered column can be separated by the second semiconductor pillar 202 on the even-numbered column, reducing crosstalk between the first semiconductor pillars 201 and between transistors.

[0078] In other embodiments, adapted to the arrangement of the first semiconductor pillar 201 and the second semiconductor pillar 202 in the first row, the first semiconductor pillar 201 is located in the even-numbered columns of the first row. If all or some even-numbered bit lines 204 in the first row need to be selected for operation, a second operating voltage is applied to or the even-numbered bit lines 204 are floated, and a preset voltage is applied to some or the odd-numbered bit lines 204 to prevent crosstalk between adjacent transistors in the first row. The first semiconductor pillar 201 in the selected even-numbered column can be separated by the second semiconductor pillar 202 in the odd-numbered column, reducing crosstalk between the first semiconductor pillars 201.

[0079] According to some aspects of embodiments of this disclosure, Figure 6 A method for manufacturing a memory device 200 is provided, comprising:

[0080] Etching a semiconductor layer forms a first trench and a second trench, the first trench and the second trench dividing the semiconductor layer into a plurality of semiconductor pillars; the second trench extends along a first direction, and the first trench extends along a second direction; wherein the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects with a third direction;

[0081] The semiconductor pillar is etched along the third direction to form a third trench extending along the second direction; the third trench penetrates the semiconductor pillar and divides one semiconductor pillar into two first semiconductor pillars spaced apart along the first direction.

[0082] Etching is performed on any two adjacent first semiconductor pillars in the first direction along the third direction to form a second semiconductor pillar; etching is performed on any two adjacent first semiconductor pillars in the second direction along the third direction to form a second semiconductor pillar.

[0083] A gate dielectric layer is formed around the sidewall of the first semiconductor pillar, and a gate structure is formed around the middle portion of the first semiconductor pillar, the gate structure extending along the first direction; the first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction, and the region between the first end and the second end is the middle portion;

[0084] A bit line is formed on the side of the first semiconductor pillar near the first end, the bit line extending along the second direction and coupled to the first end of the first semiconductor pillar.

[0085] Reference Figure 7 As shown, etching the semiconductor layer 2001 forms a first trench 211 extending along the y-direction. The first trench 211 may penetrate the semiconductor layer 2001 or may not completely penetrate the semiconductor layer 2001, such as... Figure 7The bottom of the first trench 211 is located in the semiconductor layer 2001 but does not completely penetrate it. The semiconductor layer 2001 can be a semiconductor substrate or a wafer, or a semiconductor layer 2001 deposited on a substrate, and the semiconductor layer 2001 can be thinned on the back side. Figure 7 Part a is a cross-sectional schematic diagram of the first trench 211 in the xoy plane, and part b is a cross-sectional schematic diagram of the first trench 211 at CC' in the xoz plane, wherein the first trench 211 is filled with dielectric material.

[0086] Reference Figure 8 As shown, etching the semiconductor layer 2001 forms a second trench 212 extending along the x-direction. The depth of the second trench 212 in the z-direction may be less than or equal to the depth of the first trench 211 in the z-direction. (Refer to...) Figure 9 The second trench 212 is shown to be filled with a dielectric material, which may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or spin-coated insulating media. The first trench 211 and the second trench 212 may be filled with the same dielectric material or different dielectric materials. Figure 9 In the process, the first trench 211 and the second trench 212 intersect to divide the semiconductor layer 2001 into multiple semiconductor pillars 2012. The semiconductor pillars 2012 can be etched along the z-direction to form a third trench 213 extending along the y-direction. The third trench 213 penetrates the semiconductor pillar 2012, dividing one semiconductor pillar 2012 into two first semiconductor pillars 201, as shown below. Figure 12 As exemplified, etching a wider semiconductor pillar 2012 to form a narrower first semiconductor pillar 201 reduces photolithography difficulty, increases the photolithography process window, and allows for the fabrication of smaller critical dimensions using high-resolution photolithography processes.

[0087] Reference Figure 13 As illustrated, the first semiconductor pillars 201 are arranged in rows along the x-direction and in columns along the y-direction; see reference. Figure 14 As shown, the first semiconductor pillar 201 is etched diagonally. For any three consecutive first semiconductor pillars 201 in any row along the x-direction, the height of the middle first semiconductor pillar 201 is reduced to form a second semiconductor pillar 202. Similarly, for any three consecutive first semiconductor pillars 201 in any column along the y-direction, the height of the middle first semiconductor pillar 201 is reduced to form a second semiconductor pillar 202. The first semiconductor pillar 201 is doped to form source and drain electrodes at its top and bottom ends, as well as a middle portion between the source and drain electrodes. A gate dielectric layer 205 and a gate structure 203 are formed around the middle portion. A bit line 204 is formed and coupled at the bottom of the first semiconductor pillar 201, and a capacitor structure 206 is formed and coupled at the top of the first semiconductor pillar 201.

[0088] For example, etching processes may include, but are not limited to, dry etching, wet etching, or combinations thereof. Deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0089] In some embodiments, the method of forming the first semiconductor pillar 201 includes:

[0090] Reference Figure 9 As shown, a filling structure 221 is formed by filling the first trench 211 and the second trench 212 with dielectric material. The top surface of the filling structure 221 is flush with the top surface of the semiconductor pillar 2012. The first trench 211 and the second trench 212 can be filled sequentially or integrally formed by filling the second trench 212 to form the filling structure 221.

[0091] Reference Figure 10 As shown, semiconductor pillars 2012 are etched along the z-direction to form a fourth trench 214 extending along the y-direction; the sidewalls of the fourth trench 214 are provided by a filling structure 221, and the bottom of the fourth trench 214 is provided by the remaining semiconductor pillars 2012; the depth of the fourth trench 214 may be less than or equal to the depth of the first trench 211.

[0092] Reference Figure 11 As shown, a mask layer 223 is formed on the semiconductor pillar 2012 and on the sidewall of the fourth trench 214 to form a fifth trench 215, the fifth trench 215 being fitted into the fourth trench 214; the bottom of the fifth trench 215 is supported on the semiconductor pillar 2012 and exposes the upper part of the semiconductor pillar 2012, and the top surface of the mask layer 223 can be flush with the top surface of the filling structure 221;

[0093] Reference Figure 12 As shown, using mask layer 223 as an etching mask, the semiconductor pillar 2012 exposed by the fifth trench 215 is etched to form the third trench 213. The third trench 213 divides a semiconductor pillar 2012 into a first semiconductor pillar 201 with a smaller size in the x-direction. (Refer to...) Figure 13 As shown, the mask layer 223 and dielectric material on the top of the first semiconductor pillar 201 are removed by a combination of etching and chemical mechanical polishing processes to form rows and columns of the first semiconductor pillar 201. (Refer to...) Figure 14As shown, the height of the first semiconductor pillar 201 is reduced by etching along an inclined diagonal to form the second semiconductor pillar 202; there is a second semiconductor pillar 202 between any two first semiconductor pillars 201 in any row, and a first semiconductor pillar 201 between any two second semiconductor pillars 202; there is a second semiconductor pillar 202 between any two first semiconductor pillars 201 in any column, and a first semiconductor pillar 201 between any two second semiconductor pillars 202.

[0094] In some embodiments, the manufacturing method further includes:

[0095] Reference Figure 14 As shown, the gap between the first semiconductor pillar 201 and the second semiconductor pillar 202 is filled with dielectric material 222; Refer to Figure 15 As shown, dielectric material 222 is etched to expose the second end and the middle portion of the first semiconductor pillar 201; the remaining dielectric material 222 surrounds the first end of the first semiconductor pillar 201; a gate dielectric layer 205 is formed on the exposed sidewall of the first semiconductor pillar 201.

[0096] Reference Figure 15 As shown, a portion of the dielectric material 222 is etched to expose the top and part of the sidewalls of the first semiconductor pillar 201. The remaining dielectric material 222 surrounds the bottom of the first semiconductor pillar 201, defining the first end height of the first semiconductor pillar 201. The first semiconductor pillar 201 has a first doping, and the first and second ends of the first semiconductor pillar 201 are doped to form the source and drain electrodes, respectively. The middle portion serves as a transistor channel. A gate dielectric layer 205 is deposited on the exposed sidewalls and top surface of the first semiconductor pillar 201 and the second semiconductor pillar 202, or the exposed semiconductor pillar 2012 is directly oxidized to form a silicon oxide layer as the gate dielectric layer 205. The gate dielectric layer 205 on the top surface of the top (second end) of the first semiconductor pillar 201 is removed to couple the capacitor structure 206.

[0097] In some embodiments, the method of forming the gate structure 203 further includes:

[0098] Reference Figure 16 As shown, the gap between the first semiconductor pillar 201 and the second semiconductor pillar 202 is filled with conductive material 2032. The conductive material 2032 covers at least the sidewalls of the first semiconductor pillar 201 and the sidewalls of the second semiconductor pillar 202, and covers the top surface of the second semiconductor pillar 202. The conductive material 2032 and the first semiconductor pillar 201 are separated by a gate dielectric layer 205.

[0099] Reference Figure 17As shown, conductive material 2032 is etched along the z-direction to expose the second end (top) of the first semiconductor pillar 201; the remaining conductive material 2032 surrounds the middle part of the first semiconductor pillar 201, and the height of the top surface of the conductive material 2032 surrounding the first semiconductor pillar 201 is less than the height of the top surface of the first semiconductor pillar 201.

[0100] Reference Figure 18 As shown, a sixth trench 216 extending along the x-direction is formed. The sixth trench 216 penetrates a conductive material 2032 extending along the y-direction between adjacent first semiconductor pillars 201 and second semiconductor pillars 202 in the y-direction to form a gate structure 203. The sidewalls of the sixth trench 216 are provided by the conductive material 2032 on the sidewalls of the first semiconductor pillar 201 and the second semiconductor pillar 202. (Refer to...) Figure 19 The schematic diagram of the cross-section shown shows that the top surface of the portion of the gate structure 203 surrounding the first semiconductor pillar 201 is higher, while the top surface of the portion of the gate structure 203 covering the second semiconductor pillar 202 is lower.

[0101] In some embodiments, refer to Figure 7 and Figure 8 As shown, the bottom of the first trench 211 and the bottom of the second trench 212 are located in the semiconductor layer 2001. The dimension of the second trench 212 in the z-direction is smaller than the dimension of the first trench 211 in the z-direction. The fabrication method further includes:

[0102] Reference Figure 19 As shown, an isolation structure 224 is formed by filling the gap between the first semiconductor pillar 201 and the second semiconductor pillar 202 with dielectric material; the isolation structure 224 can be formed after the gate structure 203 is formed or before the gate structure 203 is formed; the isolation structure 224 can be obtained by filling dielectric material in multiple steps, and the filling material in each step is the same and has no physical boundary;

[0103] The dimension of the portion of the isolation structure 224 extending along the x-direction in the z-direction is smaller than the dimension of the portion of the isolation structure 224 extending along the y-direction in the z-direction. The film height at the bottom of the dielectric material (isolation structure 224) extending along the x-direction in the second trench 212 is higher than the film height at the bottom of the dielectric material extending along the y-direction in the first trench 211. When the semiconductor layer 2001 is thinned on the back side, the dielectric material extending along the y-direction is exposed first, and some of the semiconductor layer 2001 is retained to form the bit line 204. The semiconductor layer 2001 is divided into columns along the y-direction.

[0104] In some embodiments, the manufacturing method further includes:

[0105] Reference Figure 20As shown, the semiconductor layer 2001 is thinned in the z-direction away from the first semiconductor pillar 201 and the second semiconductor pillar 202 until the portion of the isolation structure 224 extending in the y-direction is exposed; the portion of the isolation structure 224 extending in the y-direction divides the thinned semiconductor layer 2001 into multiple columns, which are arranged in the x-direction; Refer to Figure 21 As shown, the column includes: a semiconductor strip 2011 extending along the y direction, and a first semiconductor pillar 201 and a second semiconductor pillar 202 alternately arranged along the y direction on the semiconductor strip 2011, wherein the semiconductor strip 2011 connects the first semiconductor pillar 201 and the second semiconductor pillar 202.

[0106] In some embodiments, refer to Figure 4 and Figure 5 As shown, the manufacturing method includes:

[0107] Bit line 204 is formed based on semiconductor strip 2011; semiconductor strip 2011 includes silicon, and bit line 204 includes metal silicide.

[0108] For example, the semiconductor strip 2011 may include silicon. A metal material is deposited on the side of the semiconductor strip 2011 away from the first semiconductor pillar 201 in the z-direction and then heat-treated. A portion of the silicon in the semiconductor strip 2011 reacts with the metal material to form a metal silicide layer to form the bit line 204. The metal silicide may include, but is not limited to, titanium silicide, nickel silicide, etc. For example, conductive materials such as tungsten, aluminum, and titanium may be deposited on the metal silicide to form the bit line 204 with a composite material layer, thereby improving the electrical connection performance between the bit line 204 and the first semiconductor pillar 201 and reducing the contact resistance.

[0109] In some embodiments, refer to Figure 22 As shown, the manufacturing method further includes:

[0110] A capacitor structure 206 is formed on the side of the first semiconductor pillar 201 away from the bit line 204, and the capacitor structure 206 is coupled to the second end of the first semiconductor pillar 201.

[0111] According to some aspects of embodiments of this disclosure, Figure 23 A control method for a memory device 200 is provided.

[0112] Memory device 200 may include Figures 3 to 5 as well as Figure 22 The illustrated device structure; the gate structure 203 of the memory device 200 is configured as a word line, and the control method includes:

[0113] A first operating voltage is applied to the first word line in the word lines to select the first row;

[0114] Apply a second operating voltage or float to the odd-numbered bit lines corresponding to the first row, and apply a preset voltage to the even-numbered bit lines corresponding to the first row to select the odd-numbered column in the first row; or,

[0115] The second operating voltage or floating is applied to the even-numbered bit lines corresponding to the first row, and the preset voltage is applied to the odd-numbered bit lines corresponding to the first row to select the even-numbered column in the first row.

[0116] The first line can be any of multiple lines. The first operating voltage is greater than or equal to the threshold voltage of the transistor (or the first semiconductor pillar 201), turning the transistor on. Other word lines are given a turn-off voltage to turn off the transistor. The selected bit line is given a second operating voltage, which can be Vcc, 0, or floating. The preset voltage is a fixed voltage or a static voltage, which is a calibration value for testing a memory device, such as Vcc / 2.

[0117] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: The row includes a first semiconductor pillar and a second semiconductor pillar that are alternately arranged along a first direction, and odd-numbered rows and even-numbered rows are alternately arranged along a second direction; The column includes first semiconductor pillars and second semiconductor pillars alternately arranged along the second direction, and odd-numbered columns and even-numbered columns are alternately arranged along the first direction; there is a second semiconductor pillar between any two adjacent first semiconductor pillars in the row, and there is a second semiconductor pillar between any two adjacent first semiconductor pillars in the column; The first semiconductor pillar and the second semiconductor pillar extend along a third direction, and the dimension of the first semiconductor pillar in the third direction is greater than the dimension of the second semiconductor pillar in the third direction; wherein, the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects the third direction; The first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction, and the region between the first end and the second end is a middle portion; A gate structure extending along the first direction; the gate structure corresponds to the row and surrounds the middle portion of the first semiconductor pillar on the row; Bit lines extend along the second direction and are located on the side of the first semiconductor pillar near the first end; the bit lines correspond to the column and are coupled to the first end of the first semiconductor pillar on the column.

2. The memory device according to claim 1, characterized in that, The height of the top surface of the second end of the first semiconductor pillar is greater than the height of the top surface of the second semiconductor pillar at the end furthest from the bit line.

3. The memory device according to claim 1, characterized in that, The column includes: A semiconductor strip extending along the second direction, the semiconductor strip being located on the side of the first semiconductor pillar near the first end; the semiconductor strip connecting the first semiconductor pillar and the second semiconductor pillar.

4. The memory device according to claim 3, characterized in that, The bit line is located on the side of the semiconductor strip away from the first semiconductor pillar; The semiconductor strip comprises silicon, and the bit line comprises metal silicide.

5. The memory device according to claim 1, characterized in that, The gate structure surrounds the sidewall of the second semiconductor pillar extending in the third direction and covers the end of the second semiconductor pillar away from the bit line.

6. The memory device according to claim 5, characterized in that, The gate structure includes: A first portion surrounding the first semiconductor pillar and a second portion covering the second semiconductor pillar; wherein the top surface height of the first portion is greater than the top surface height of the second portion.

7. The memory device according to claim 6, characterized in that, The first plane intersects the second direction, and the first plane is parallel to the third direction; the cross-sectional structure of the gate structure along the first plane includes: An H-shaped portion is located between two adjacent first semiconductor pillars in the first direction; the H-shaped portion includes two side surfaces extending along the third direction, and a top surface located between the two side surfaces and connecting the two side surfaces; wherein, the side surfaces of the H-shaped portion are located between adjacent first semiconductor pillars and second semiconductor pillars, the side surfaces of the H-shaped portion cover the sidewalls of the first semiconductor pillars along the first direction, and are spaced from the first semiconductor pillars by a gate dielectric layer; the top surface of the H-shaped portion covers the second semiconductor pillars along the third direction.

8. The memory device according to claim 1, characterized in that, The memory device further includes: A gate dielectric layer is located between the gate structure and the first semiconductor pillar; the gate dielectric layer surrounds the sidewall of the first semiconductor pillar; A capacitor structure is located on the side of the first semiconductor pillar away from the bit line, and the capacitor structure is coupled to the second end of the first semiconductor pillar.

9. The memory device according to claim 1, characterized in that, The first gate structure in the gate structure is configured to apply a first operating voltage to select the first row; The odd-numbered bit lines corresponding to the first row are configured to apply a second operating voltage or float to select the odd-numbered column on the first row, and the even-numbered bit lines corresponding to the first row are configured to apply a preset voltage. or, The even-numbered bit lines corresponding to the first row are configured to apply the second operating voltage or float to select the even-numbered column on the first row, and the odd-numbered bit lines corresponding to the first row are configured to apply the preset voltage.

10. A method for manufacturing a memory device, characterized in that, include: Etching the semiconductor layer forms a first trench and a second trench, the first trench and the second trench dividing the semiconductor layer into a plurality of semiconductor pillars; The second groove extends along a first direction, and the first groove extends along a second direction; wherein the first direction intersects the second direction, and the plane formed by the first direction and the second direction intersects with a third direction; The semiconductor pillar is etched along the third direction to form a third trench extending along the second direction; the third trench penetrates the semiconductor pillar and divides one semiconductor pillar into two first semiconductor pillars spaced apart along the first direction. Etching is performed on any two adjacent first semiconductor pillars in the first direction along the third direction to form a second semiconductor pillar; etching is performed on any two adjacent first semiconductor pillars in the second direction along the third direction to form a second semiconductor pillar. A gate dielectric layer is formed around the sidewall of the first semiconductor pillar, and a gate structure is formed around the middle portion of the first semiconductor pillar, the gate structure extending along the first direction; the first semiconductor pillar includes a first end and a second end disposed opposite to each other along the third direction, and the region between the first end and the second end is the middle portion; A bit line is formed on the side of the first semiconductor pillar near the first end, the bit line extending along the second direction and coupled to the first end of the first semiconductor pillar.

11. The manufacturing method according to claim 10, characterized in that, The method for forming the first semiconductor pillar includes: A filling structure is formed by filling the first trench and the second trench with a dielectric material, wherein the top surface of the filling structure is flush with the top surface of the semiconductor pillar. The semiconductor pillars are etched along the third direction to form a fourth trench extending along the second direction; the sidewalls of the fourth trench are provided by the filling structure, and the bottom of the fourth trench is provided by the remaining semiconductor pillars; A mask layer is formed on the sidewall of the fourth trench to form a fifth trench, and the fifth trench is fitted into the fourth trench; The semiconductor pillars exposed by the fifth trench are etched to form the third trench.

12. The manufacturing method according to claim 11, characterized in that, The manufacturing method further includes: The gap between the first semiconductor pillar and the second semiconductor pillar is filled with dielectric material, and the dielectric material is etched to expose the second end and the middle portion of the first semiconductor pillar; the remaining dielectric material surrounds the first end of the first semiconductor pillar. The gate dielectric layer is formed on the exposed sidewall of the first semiconductor pillar.

13. The manufacturing method according to claim 10, characterized in that, The method for forming the gate structure further includes: The gap between the first semiconductor pillar and the second semiconductor pillar is filled with a conductive material, the conductive material at least covering the sidewalls of the first semiconductor pillar and the sidewalls of the second semiconductor pillar, and covering the top surface of the second semiconductor pillar; the conductive material and the first semiconductor pillar are separated by the gate dielectric layer; The conductive material is etched along the third direction to expose the second end of the first semiconductor pillar; the remaining conductive material surrounds the middle portion of the first semiconductor pillar, and the height of the top surface of the conductive material surrounding the first semiconductor pillar is less than the height of the top surface of the first semiconductor pillar. A sixth trench extending along the first direction is formed, the sixth trench penetrating a conductive material extending along the second direction between the first semiconductor pillar and the second semiconductor pillar adjacent in the second direction to form the gate structure; the sidewalls of the sixth trench are provided by conductive material on the sidewalls of the first semiconductor pillar and conductive material on the sidewalls of the second semiconductor pillar.

14. The manufacturing method according to claim 10, characterized in that, The bottom of the first trench and the bottom of the second trench are located in the semiconductor layer, and the dimension of the second trench in a third direction is smaller than the dimension of the first trench. The fabrication method further includes: An isolation structure is formed by filling the gap between the first semiconductor pillar and the second semiconductor pillar with dielectric material. The dimension of the portion of the isolation structure extending along the first direction in the third direction is smaller than the dimension of the portion of the isolation structure extending along the second direction in the third direction.

15. The manufacturing method according to claim 14, characterized in that, The manufacturing method further includes: The semiconductor layer is thinned on the side away from the semiconductor pillar in the third direction until the portion of the isolation structure extending along the second direction is exposed; the portion of the isolation structure extending along the second direction divides the thinned semiconductor layer into multiple columns, the columns being arranged along the first direction; each column includes: a semiconductor strip extending along the second direction, and first semiconductor pillars and second semiconductor pillars alternately arranged along the second direction on the semiconductor strip, the semiconductor strip connecting the first semiconductor pillars and the second semiconductor pillars.

16. The manufacturing method according to claim 15, characterized in that, The manufacturing method includes: The bit line is formed based on the semiconductor strip; the semiconductor strip comprises silicon, and the bit line comprises metal silicide.

17. The manufacturing method according to claim 10, characterized in that, The manufacturing method further includes: A capacitor structure is formed on the side of the first semiconductor pillar away from the bit line, and the capacitor structure is coupled to the second end of the first semiconductor pillar.

18. A control method for a memory device, characterized in that, Applied to the memory device as described in any one of claims 1 to 9; The gate structure of the memory device is configured as a word line, and the control method includes: A first operating voltage is applied to the first word line in the word lines to select the first row; Apply a second operating voltage or float to the odd-numbered bit lines corresponding to the first row, and apply a preset voltage to the even-numbered bit lines corresponding to the first row to select the odd-numbered column in the first row; or, The second operating voltage or floating is applied to the even-numbered bit lines corresponding to the first row, and the preset voltage is applied to the odd-numbered bit lines corresponding to the first row to select the even-numbered column in the first row.

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