Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method thereof, the structure comprises a substrate, the substrate comprises a first region, a second region and a third region, the substrate comprises a plurality of first active regions and a plurality of second active regions, the first active regions and the second active regions are alternately arranged, the first active region on the second surface of the substrate comprises a first branch part and a second branch part which are separated from each other, and the second active region on the second surface of the substrate comprises a second branch part and a third branch part; the second active region of the second surface of the substrate comprises a third branch part and a fourth branch part which are separated from each other; the word line gate structure is positioned in the first region; the first bit line is located on the second surface of the substrate and is electrically connected with the first branch, the second bit line is electrically connected with the second branch, the third bit line is electrically connected with the third branch, and the fourth bit line is electrically connected with the fourth branch; the first connecting structure and the second connecting structure are located on the third area and do not coincide in projection in the second direction; the third connecting structure and the fourth connecting structure are located on the second area and do not coincide in projection in the second direction. The structure is easy to realize independent control of the spaced bit lines.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] A basic memory cell in Dynamic Random Access Memory (DRAM) consists of a transistor and a storage capacitor, while a memory array consists of multiple memory cells. As semiconductor devices become smaller, to reduce the area of ​​a single memory cell, the bit line structures of the capacitor and control transistor are typically placed on opposite sides of the semiconductor substrate to save planar area.

[0004] However, as the size of semiconductor devices continues to shrink, dynamic random access memory still faces many challenges that need to be addressed. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to continuously improve the performance of dynamic random access memory.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first and third regions, the second active regions being located in the first and second regions, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other; forming a word line gate structure located in the first region, the word line gate structure being parallel to the second direction; removing a portion of the first active region exposed on the second surface of the substrate, so that the first active region is formed into a first portion and a second portion that are mutually discrete, the first portion and the second portion being parallel to the first direction; A portion of the second active region exposed on the second surface of the substrate is removed, forming the second active region into mutually discrete third and fourth portions, which are parallel to a first direction. A bit line structure is formed on the second surface of the substrate, comprising: a first bit line electrically connected to the first portion, a second bit line electrically connected to the second portion, a third bit line electrically connected to the third portion, and a fourth bit line electrically connected to the fourth portion, which are parallel to the first direction. A first connection structure and a second connection structure are formed on the third region, wherein the first connection structure is electrically connected to the first bit line, and the second connection structure is electrically connected to the second bit line, and their projections in the second direction do not coincide. A third connection structure and a fourth connection structure are formed on the second region, wherein the third connection structure is electrically connected to the third bit line, and the fourth connection structure is electrically connected to the fourth bit line, and their projections in the second direction do not coincide.

[0007] Optionally, the first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface, the word line gate structure is adjacent to the first channel region and the second channel region; the first portion and the second portion are connected to the first channel region, and the third portion and the fourth portion are connected to the second channel region.

[0008] Optionally, the first, second, third, and fourth portions are formed simultaneously; the formation process of the first, second, third, and fourth portions includes: etching back the first active region to form a first groove in the substrate, the first groove extending from the second surface of the substrate to the first surface; etching back the second active region to form a second groove in the substrate, the second groove extending from the second surface of the substrate to the first surface; forming sidewalls on the sidewalls of the first and second grooves, the sidewalls on the sidewalls of the first and second grooves exposing a portion of the surface of the first active region, and the sidewalls on the sidewalls of the second grooves exposing a portion of the surface of the second active region; using the sidewalls... To mask and remove the exposed first active region, a third groove is formed within the first active region; using the sidewall as a mask, to remove the exposed second active region, a fourth groove is formed within the second active region; a second isolation layer is formed within the third and fourth grooves; a first cutting layer is formed within the substrate, penetrating the first active region, so that the first active region is formed into a first portion and a second portion that are mutually independent, the first cutting layer being parallel to a first direction; a second cutting layer is formed within the substrate, penetrating the second active region, so that the second active region is formed into a third portion and a fourth portion that are mutually independent, the second cutting layer being parallel to the first direction.

[0009] Optionally, forming sidewalls on the first and second groove sidewalls includes: forming a sidewall material layer on the surface and bottom surface of the first groove sidewall, the surface and bottom surface of the second groove sidewall, and the first surface of the substrate; and etching back the sidewall material layer until the surfaces of the first and second active regions are exposed, thereby forming sidewalls on the first and second groove sidewalls.

[0010] Optionally, the third and fourth grooves are formed simultaneously. The formation process of the third and fourth grooves includes: removing the exposed first active area using the sidewall as a mask until the surface of the first channel area is exposed, forming a third groove in the first active area; and removing the exposed second active area using the sidewall as a mask until the surface of the second channel area is exposed, forming a fourth groove in the second active area.

[0011] Optionally, forming a second isolation layer in the third and fourth grooves includes: removing the sidewalls; after removing the sidewalls, forming an isolation material layer in the third and fourth grooves and on the second surface of the substrate; planarizing the isolation material layer and the second surface of the substrate until the surfaces of the first and second active regions are exposed, thereby forming a second isolation layer in the third and fourth grooves.

[0012] Optionally, the first cutting layer and the second cutting layer are formed simultaneously; the formation process of the first cutting layer and the second cutting layer includes: forming a fifth groove penetrating the first active region and a sixth groove penetrating the second active region in the substrate; forming the first cutting layer in the fifth groove and forming the second cutting layer in the sixth groove.

[0013] Optionally, the projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; the projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the third portion on the substrate; and the projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate.

[0014] Optionally, the process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion to form a first opening in the substrate; etching back the second portion to form a second opening in the substrate; etching back the third portion to form a third opening in the substrate; etching back the fourth portion to form a fourth opening in the substrate; forming a bit line material layer in the first opening, the second opening, the third opening, the fourth opening, and on the first isolation layer; planarizing the bit line material layer until the surface of the second surface of the substrate is exposed; forming the first bit line in the first opening; forming the second bit line in the second opening; forming the third bit line in the third opening; and forming the fourth bit line in the fourth opening.

[0015] Optionally, there is a first spacing between the first bit line and the second bit line, and the first active region has a first width, wherein the ratio of the first spacing to the first width is in the range of 1:2 to 1:4.

[0016] Optionally, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0017] Optionally, there is a second spacing between the third bit line and the fourth bit line, and the second active region has a second width, wherein the ratio of the second spacing to the second width is in the range of 1:2 to 1:4.

[0018] Optionally, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0019] Optionally, the first, second, third, and fourth connection structures are formed simultaneously. The formation process of the first, second, third, and fourth connection structures includes: forming a dielectric structure on a second surface of a substrate; forming a fifth, sixth, seventh, and eighth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the first bit line surface on the third region, the sixth opening exposes at least a portion of the second bit line surface on the third region, the seventh opening exposes at least a portion of the third bit line surface on the second region, and the eighth opening exposes at least a portion of the fourth bit line surface on the second region; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall and bottom surfaces of the fifth opening, the sixth opening, the seventh opening, the eighth opening, and the dielectric structure surface; planarizing the conductive material layer and the barrier material layer until the dielectric structure surface is exposed; forming a first connection structure within the fifth opening, a second connection structure within the sixth opening, a third connection structure within the seventh opening, and a fourth connection structure within the eighth opening.

[0020] Optionally, the substrate further includes: a first isolation layer located between adjacent first active regions and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; the substrate formation process includes: providing an initial substrate, the initial substrate including a first region, a second region and a third region distributed along a first direction parallel to the surface of the initial substrate, the first region being located between the second region and the third region, the initial substrate including: a substrate, a plurality of initial first active regions and a plurality of initial second active regions located on the substrate, and a first isolation layer located between adjacent initial first active regions and initial second active regions, the plurality of initial first active regions and the plurality of initial second active regions along a first direction parallel to the surface of the initial substrate. The initial first active region and the initial second active region are arranged in parallel directions parallel to the surface of the initial substrate, and are arranged alternately. The first surface of the initial substrate exposes the surface of the first isolation layer. The initial first active region of the second region is removed to form a first active region located in the first region and the third region, and a seventh groove is formed in the initial substrate, the seventh groove extending from the first surface of the initial substrate to the second surface. The initial second active region of the third region is removed to form a second active region located in the first region and the second region, and an eighth groove is formed in the initial substrate, the eighth groove extending from the first surface of the initial substrate to the second surface. A third isolation layer is formed in the seventh groove and the eighth groove.

[0021] Optionally, the substrate formation process further includes: before removing a portion of the first active region and the second active region exposed on the second surface of the substrate, removing the substrate to expose the surface of the first isolation layer, the surface of the first active region, and the surface of the second active region to form the substrate.

[0022] Optionally, after forming the word line gate structure in the first region, the method further includes: forming a plurality of capacitor structures on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the first active regions or the second active region.

[0023] Optionally, before forming several capacitor structures, the method further includes: performing a first ion implantation on a first active region and a second active region exposed on the first surface of the substrate to form a first source-drain doped region, wherein the capacitor structure is electrically connected to the first source-drain doped region.

[0024] Optionally, before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first, second, third, and fourth portions to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0025] Optionally, before forming the word line grid structure located in the first region, the method further includes: etching the first channel region of the first active region to form a plurality of discrete first channel pillars located in the first region; and etching the second channel region of the second active region to form a plurality of discrete second channel pillars located in the first region.

[0026] Optionally, the word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction, the first word line gate and the second word line gate being parallel to the second direction, the first word line gate and the second word line gate being located within the substrate, and adjacent first word line gates and second word line gates being electrically isolated from each other.

[0027] Optionally, the central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

[0028] Optionally, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0029] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second region and the third region, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region and the third region, the second active regions being located in the first region and the second region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other, the first active regions exposed on the second surface of the substrate including mutually separate first portions and second portions, the first portions and the second portions being parallel to the first direction, the second active regions exposed on the second surface of the substrate including mutually separate third portions and fourth portions, the first active regions including a first portion and a fourth portion, the first active regions including a first portion and a third portion, the second active regions exposed on the second surface of the substrate including a third portion and a fourth portion, the first active regions including a first portion and a third portion, the second active regions including a first portion and a third portion, the third ... The third and fourth portions are parallel to the first direction; a word line gate structure is located in the first region, the word line gate structure being parallel to the second direction; a bit line structure is located on the second surface of the substrate, the bit line structure including: a first bit line electrically connected to the first portion, a second bit line electrically connected to the second portion, a third bit line electrically connected to the third portion, and a fourth bit line electrically connected to the fourth portion, the bit line structure being parallel to the first direction; a first connection structure and a second connection structure are located on the third region, the first connection structure being electrically connected to the first bit line, the second connection structure being electrically connected to the second bit line, the projections of the first connection structure and the second connection structure in the second direction not coinciding; a third connection structure and a fourth connection structure are located on the second region, the third connection structure being electrically connected to the third bit line, the fourth connection structure being electrically connected to the fourth bit line, the projections of the third connection structure and the fourth connection structure in the second direction not coinciding.

[0030] Optionally, the first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface, the word line gate structure is adjacent to the first channel region and the second channel region; the first portion and the second portion are connected to the first channel region, and the third portion and the fourth portion are connected to the second channel region.

[0031] Optionally, the substrate further includes: a first isolation layer located between adjacent first and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; and a third isolation layer located in the second and third regions, the third isolation layer in the second region being in contact with the first active region and the first isolation layer, and the third isolation layer in the third region being in contact with the second active region and the first isolation layer.

[0032] Optionally, it further includes: a second isolation layer and a first cutting layer located between the first segment and the second segment, wherein the second isolation layer is parallel to the first direction and the first cutting layer is parallel to the first direction; and a second isolation layer and a second cutting layer located between the third segment and the fourth segment, wherein the second isolation layer is parallel to the first direction and the second cutting layer is parallel to the first direction.

[0033] Optionally, the projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; the projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the third portion on the substrate; and the projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate.

[0034] Optionally, there is a first spacing between the first bit line and the second bit line, and the first active region has a first width, wherein the ratio of the first spacing to the first width is in the range of 1:2 to 1:4.

[0035] Optionally, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0036] Optionally, there is a second spacing between the third bit line and the fourth bit line, and the second active region has a second width, wherein the ratio of the second spacing to the second width is in the range of 1:2 to 1:4.

[0037] Optionally, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0038] Optionally, it may also include: a plurality of capacitor structures located on the first surface of the substrate, one of the capacitor structures being electrically connected to a first active region or a second active region.

[0039] Optionally, it further includes: a first source / drain doped region located within a first active region and a second active region exposed on the first surface of the substrate, wherein the capacitor structure is electrically connected to the first source / drain doped region.

[0040] Optionally, it also includes: a second source / drain doped region located in the first, second, third, and fourth portions, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0041] Optionally, the first channel area includes a plurality of separate first channel columns located in the first area; the second channel area includes a plurality of separate second channel columns located in the first area.

[0042] Optionally, the word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction, the first word line gate and the second word line gate being parallel to the second direction, the first word line gate and the second word line gate being located within the substrate, and adjacent first word line gates and second word line gates being electrically isolated from each other.

[0043] Optionally, the central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

[0044] Optionally, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0045] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0046] The method of forming the present invention involves forming a first active region into two mutually separate parts, the first active region being located in a first region and a third region, forming a second active region into two mutually separate parts, the second active region being located in the first region and the second region, forming a first connecting structure and a second connecting structure on the third region, wherein the projections of the first connecting structure and the second connecting structure in a second direction do not coincide, and forming a third connecting structure and a fourth connecting structure on the second region, wherein the projections of the third connecting structure and the fourth connecting structure in a second direction do not coincide. The process window for forming the first, second, third, and fourth connection structures is increased, making it easier to form these structures. This facilitates the connection of the first bit line to an external circuit via the first connection structure, the second bit line to an external circuit via the second connection structure, the third bit line to an external circuit via the third connection structure, and the fourth bit line to an external circuit via the fourth connection structure. It also makes it easier to achieve individual control of the phase-spaced bit lines and avoids capacitive coupling when two adjacent bit lines are energized simultaneously.

[0047] Furthermore, a first severing layer is formed within the substrate, penetrating the first active region, thus forming the first active region into a first and a second mutually independent portion. A second severing layer is formed within the substrate, penetrating the second active region, thus forming the second active region into a third and a fourth mutually independent portion. The depths of the first and second severing layers are equal to the distance between the first and second channel pillars and the second surface of the substrate. This ensures that the channel pillars can electrically connect to the bitline structure and capacitor structure on the first and second surfaces of the substrate.

[0048] Furthermore, by etching back the first portion, a first opening is formed in the substrate; by etching back the second portion, a second opening is formed in the substrate; by etching back the third portion, a third opening is formed in the substrate; by etching back the fourth portion, a fourth opening is formed in the substrate. Then, the first bit line is formed within the first opening, the second bit line is formed within the second opening, the third bit line is formed within the third opening, and the fourth bit line is formed within the fourth opening. This process enables self-alignment to form the bit line structure, further reducing the spacing between the bit line structures and saving on the use of a photomask.

[0049] The semiconductor structure of the present invention includes a first active region exposed on the second surface of the substrate comprising a first portion and a second portion, and a second active region exposed on the second surface of the substrate comprising a third portion and a fourth portion, and a first connection structure and a second connection structure located on the third region, wherein the projections of the first connection structure and the second connection structure in a second direction do not coincide. A third connection structure and a fourth connection structure located on the second region, wherein the projections of the third connection structure and the fourth connection structure in a second direction do not coincide. The process window for forming the first, second, third, and fourth connection structures is increased, making it easier to form these structures. This facilitates the connection of the first bit line to an external circuit via the first connection structure, the second bit line to an external circuit via the second connection structure, the third bit line to an external circuit via the third connection structure, and the fourth bit line to an external circuit via the fourth connection structure. It also facilitates individual control of spaced-apart bit lines, avoiding capacitive coupling when two adjacent bit lines are simultaneously energized. Attached Figure Description

[0050] Figure 1 and Figure 2 This is a schematic diagram of the semiconductor structure in one embodiment;

[0051] Figures 3 to 34 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0052] As described in the background section, dynamic random access memory (DRAM) still has many problems that need to be solved. These will now be analyzed and explained in conjunction with specific embodiments.

[0053] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure in one embodiment.

[0054] Please refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a storage cell in a dynamic random access memory (DRAM). Figure 2 The diagram shows the bit line distribution on the substrate surface. The memory cell of the dynamic random access memory includes: a channel post 101, which is parallel to a first direction; a word line gate structure 102 located on the sidewall surface of the channel post 101, which is parallel to a second direction and perpendicular to the first and second directions; a bit line structure 104 and a capacitor structure 103 electrically connected to both ends of the channel post 101, respectively, with the bit line structure 104 parallel to the first direction.

[0055] The dynamic random access memory (DRAM) includes several parallel bit line structures 104, each connected to an external circuit via a connection structure 105. As semiconductor devices become increasingly smaller, the spacing between adjacent bit line structures 104 also decreases. When multiple bit line structures 104 are simultaneously powered, capacitive coupling can easily occur between adjacent structures, generating parasitic capacitance and causing performance degradation in the DRAM.

[0056] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. The first active region is formed into two mutually separate first and second portions, located in a first and a third region. The second active region is formed into two mutually separate third and fourth portions, located in the first and second regions. A first and second connection structures are then formed on the third region, where the projections of the first and second connection structures in a second direction do not coincide. A third and fourth connection structures are then formed on the second region, where the projections of the third and fourth connection structures in a second direction do not coincide. The process window for forming the first, second, third, and fourth connection structures is increased, making it easier to form these structures. This facilitates the connection of the first bit line to an external circuit via the first connection structure, the second bit line to an external circuit via the second connection structure, the third bit line to an external circuit via the third connection structure, and the fourth bit line to an external circuit via the fourth connection structure. It also makes it easier to achieve individual control of the phase-spaced bit lines and avoids capacitive coupling when two adjacent bit lines are energized simultaneously.

[0057] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0058] Figures 3 to 34 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0059] A substrate is provided, the substrate including a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first and third regions, the second active regions being located in the first and second regions, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other; a first isolation layer located between adjacent first active regions and second active regions, the first surface of the substrate exposing the surface of the first isolation layer. The formation process of the substrate is described in reference [reference needed]. Figures 3 to 10 .

[0060] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 Top view of the first surface of the initial substrate. Figure 4 for Figure 3 A schematic diagram along the cross-section line AA1 shows an initial substrate. The initial substrate includes a first region I, a second region II, and a third region III distributed along a first direction Y parallel to the surface of the initial substrate. The first region I is located between the second region II and the third region III. The initial substrate includes a substrate 200, a plurality of initial first active regions 201 and a plurality of initial second active regions 202 located on the substrate 200, and a first isolation layer 203 located between adjacent initial first active regions 201 and initial second active regions 202. The plurality of initial first active regions 201 and the plurality of initial second active regions 202 are arranged in parallel along a second direction X parallel to the surface of the initial substrate. The initial first active regions 201 and the initial second active regions 202 are arranged alternately. The first surface of the initial substrate exposes the surface of the first isolation layer 203.

[0061] In this embodiment, the material of the substrate 200 is the same as the material of the initial first active region 201 and the initial second active region 202. In other embodiments, the material of the substrate may be different from the material of the initial first active region and the initial second active region.

[0062] In this embodiment, the substrate 200, the initial first active region 201, and the initial second active region 202 are made of silicon.

[0063] In other embodiments, the materials of the substrate, the initial first active region, and the initial second active region include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0064] The material of the first isolation layer 203 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0065] In this embodiment, the material of the first isolation layer 203 includes silicon oxide.

[0066] The method for forming the initial substrate includes: providing a substrate material; forming a patterned mask layer on the substrate material; etching the substrate material using the patterned mask layer as a mask to form a plurality of grooves parallel to the first direction Y in the substrate material layer, forming a substrate 200 and an initial first active region 201 and an initial second active region 202 located on the substrate 200; forming a first isolation layer 203 in the grooves to form the initial substrate.

[0067] In this embodiment, the initial first active region 201 and the initial second active region 202 have the same width in the second direction X; the grooves have the same width in the second direction X.

[0068] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 Top view of the first surface of the initial substrate. Figure 6 for Figure 5 A schematic diagram along the section line AA1 shows a mask structure 204 formed on the first surface of the initial substrate, which exposes the surface of the initial first active region 201 on the second region II and the surface of the initial second active region 202 on the third region III.

[0069] In this embodiment, the material of the mask structure 204 includes photoresist.

[0070] In other embodiments, the mask structure includes a pad layer, an anti-reflective layer on the pad layer, and a photoresist layer on the anti-reflective layer.

[0071] The material of the padding layer includes an amorphous material, which includes amorphous silicon or amorphous carbon; the antireflective layer includes a thin silicon antireflective layer (Si-ARC), an organic material bottom antireflective layer (organic BARC), a dielectric antireflective layer (DARC), or a combination of an organic bottom antireflective layer and a dielectric antireflective layer.

[0072] Please refer to Figure 7 and Figure 8 , Figure 7 for Figure 8 Top view of the first surface of the initial substrate. Figure 8 for Figure 7 A schematic diagram along the cross-sectional line AA1 shows that, using the mask structure 204 as a mask, the initial first active region 201 of the second region II is removed to form the first active region 207 located in the first region I and the third region III, and a seventh groove 205 is formed in the initial substrate, the seventh groove 205 extending from the first surface of the initial substrate to the second surface; the initial second active region 202 of the third region III is removed to form the second active region 208 located in the first region I and the second region II, and an eighth groove (not shown) is formed in the initial substrate, the eighth groove extending from the first surface of the initial substrate to the second surface.

[0073] The seventh groove 205 exposes the surface of the substrate 200, and the eighth groove exposes the surface of the substrate 200.

[0074] The first active region 207 includes a first channel region distributed along a direction perpendicular to the substrate surface, and the second active region 208 includes a second channel region distributed along a direction perpendicular to the substrate surface. The first and second channel regions are used to subsequently form word line gate structures on the surfaces of the first and second channel regions. The first and second channel regions are close to the first surface of the initial substrate and do not contact the substrate 200, that is, the depth of the first and second channel regions is less than the depth of the first isolation layer 203.

[0075] Please refer to Figure 9 and Figure 10 , Figure 9 for Figure 10 Top view of the first surface of the initial substrate. Figure 10 for Figure 9 A structural schematic diagram along the section line AA1 shows that a third isolation layer 206 is formed in the seventh groove 205 and the eighth groove.

[0076] The method for forming the third isolation layer 206 includes: forming an isolation material layer in the seventh groove 205, the eighth groove and the first surface of the initial substrate; planarizing the isolation material layer, exposing the surfaces of the first active region 207 and the second active region 208, and forming the third isolation layer 206 in the seventh groove 205 and the eighth groove.

[0077] The material of the third isolation layer 206 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0078] In this embodiment, the material of the third isolation layer 206 includes silicon oxide.

[0079] Please refer to Figures 11 to 13 , Figure 11 for Figure 12 and Figure 13 Top view, Figure 12 for Figure 11 A schematic diagram of the structure along section line BB1. Figure 13 for Figure 11 The structural schematic diagram along the cross-sectional line CC1 shows that the first channel region of the first active region 207 is etched to form a plurality of discrete first channel pillars 209 located in the first region I; the second channel region of the second active region 208 is etched to form a plurality of discrete second channel pillars 210 located in the first region I.

[0080] In this embodiment, the central axes of two adjacent first channel posts 209 do not coincide in the first direction Y; the central axes of two adjacent second channel posts 210 do not coincide in the first direction Y. In the second direction X, a plurality of first channel posts 209 and second channel posts 210 are located on the same straight line.

[0081] In this embodiment, the depth of the first channel post 209 is less than the depth of the first isolation layer 203; the depth of the second channel post 210 is less than the depth of the first isolation layer 203. That is, the first channel post 209 is located on the first active region 207 other than the first channel region, and the second channel post 210 is located on the second active region 208 other than the second channel region.

[0082] In this embodiment, one first channel post 209, another first channel post 209 adjacent in the first direction Y, and a second channel post 210 adjacent in the second direction X form a triangle; one second channel post 210, another second channel post 210 adjacent in the first direction Y, and a first channel post 209 adjacent in the second direction X form a triangle. This allows the positions of the capacitor structures to be staggered when a plurality of capacitor structures electrically connected to the first channel post 209 or the second channel post 210 are subsequently formed on the first surface, thus increasing the process window.

[0083] The cross-sectional shapes of the first channel post 209 and the second channel post 210 include polygons, rectangles, circles, or ellipses with a side length greater than or equal to 5. In this embodiment, the cross-sectional shapes of the first channel post 209 and the second channel post 210 include rectangles.

[0084] In this embodiment, after forming the first channel post 209 and the second channel post 210, the method further includes filling the openings of the first active region 207 and the second active region 208 with a filling layer.

[0085] In this embodiment, the first channel post 209 and the second channel post 210 are formed simultaneously.

[0086] Please refer to Figure 14 and Figure 15 , Figure 14 for Figure 15 Top view, Figure 15 for Figure 14 A schematic diagram of the structure along the cross-sectional line BB1 ​​shows a word line gate structure located in the first region I, the word line gate structure being parallel to the second direction X.

[0087] The word line grid structure is adjacent to the first channel region and the second channel region.

[0088] The word line grid structure includes: a first word line grid 211 and a second word line grid 212. The first word line grid 211 and the second word line grid 212 are respectively located on the two side walls of the first channel post 209 along the first direction Y, and respectively located on the two side walls of the second channel post 210 along the first direction Y. The first word line grid 211 and the second word line grid 212 are parallel to the second direction X. The first word line grid 211 and the second word line grid 212 are located within the first isolation layer 203 and the filling layer. The first isolation layer and the filling layer electrically isolate the adjacent first word line grid 211 and the second word line grid 212.

[0089] The first word line gate 211 includes: a first gate dielectric layer located on the surface of the first channel pillar 209 and the surface of the second channel pillar 210, and a first gate layer located on the surface of the first gate dielectric layer. The second word line gate 212 includes: a second gate dielectric layer located on the surface of the first channel pillar 209 and the surface of the second channel pillar 210, and a second gate layer located on the surface of the second gate dielectric layer.

[0090] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include silicon oxide or low-K (K less than 3.9) materials; the materials of the first gate layer and the second gate layer include polysilicon.

[0091] In one embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include a high dielectric constant material, the high dielectric constant material having a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the materials of the first gate layer and the second gate layer include metals, the metal including tungsten.

[0092] The top surface of the word line grid structure is lower than or flush with the first surface of the substrate. The figure schematically illustrates that the top surface of the word line grid structure is flush with the first surface of the substrate.

[0093] In another embodiment, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0094] In another embodiment, the cross-section of the first channel post includes a circular or elliptical shape; the cross-section of the second channel post includes a circular or elliptical shape.

[0095] Please refer to Figure 16 and Figure 17 , Figure 16 for Figure 17 Top view, Figure 17 for Figure 16A schematic diagram of the structure along the cross-sectional line BB1 ​​shows that several capacitor structures are formed on the first surface of the substrate, and one of the capacitor structures is electrically connected to a first channel pillar 209 or a second channel pillar 210.

[0096] Before forming several capacitor structures, the method further includes: performing a first ion implantation on the first channel pillar 209 and the second channel pillar 210 exposed on the first surface of the substrate to form a first source-drain doped region, and the capacitor structure is electrically connected to the first source-drain doped region.

[0097] Next, a portion of the first active region exposed on the second surface of the substrate is removed, forming the first active region into a first portion and a second portion that are mutually independent, with the first and second portions parallel to the first direction. A portion of the second active region exposed on the second surface of the substrate is then removed, forming the second active region into a third portion and a fourth portion that are mutually independent, with the third and fourth portions parallel to the first direction. The formation process of the first, second, third, and fourth portions is described in [reference needed]. Figures 18 to 30 .

[0098] Please refer to Figures 18 to 20 , Figure 18 for Figure 19 and Figure 20 Top view, Figure 19 for Figure 18 A schematic diagram of the structure along section line BB1. Figure 20 for Figure 18 A schematic diagram along the cross-sectional line CC1 shows the substrate 200 being removed, exposing the surfaces of the first isolation layer 203, the first active region 207, and the second active region 208, thus forming the substrate.

[0099] It should be noted that since the depth of the first channel region and the depth of the second channel region are less than the depth of the first isolation layer 203, after removing the substrate 200, the second surface of the substrate will not expose the first channel pillar 209 and the second channel pillar 210, but will expose the first active region 207 at the bottom of the first channel pillar 209 and the second active region 208 at the bottom of the second channel pillar 210.

[0100] In this embodiment, the process for removing the substrate 200 includes a chemical mechanical polishing process.

[0101] Please refer to Figure 21 and Figure 22 , Figure 21 In order to be in Figure 19 A basic diagram. Figure 22 In order to be in Figure 20Based on the schematic diagram, the first active region 207 exposed by etching back the second surface of the substrate forms a first groove 244 in the substrate, which extends from the second surface of the substrate to the first surface; the second active region 208 exposed by etching back the second surface of the substrate forms a second groove 214 in the substrate, which extends from the second surface of the substrate to the first surface.

[0102] In this embodiment, the first groove 244 and the second groove 214 are formed simultaneously. The depth of the first groove 244 and the second groove 214 is less than the distance between the first channel post 209 and the second channel post 210 and the second surface of the substrate, that is, the first groove 244 and the second groove 214 will not expose the bottom surface of the first channel post 209 and the second channel post 210.

[0103] Please refer to Figures 23 to 25 , Figure 23 for Figure 24 and Figure 25 Top view, Figure 24 for Figure 23 A schematic diagram of the structure along section line BB1. Figure 25 for Figure 23 The structural schematic diagram along the cross section line CC1 shows that sidewalls 215 are formed on the sidewalls of the first groove 244 and the second groove 214. The sidewall 215 on the sidewall of the first groove 244 exposes part of the surface of the first active region 207, and the sidewall on the sidewall of the second groove 214 exposes part of the surface of the second active region 208.

[0104] The method for forming the sidewall 215 includes: forming a sidewall material layer on the sidewall surface and bottom surface of the first groove 244, the sidewall surface and bottom surface of the second groove 214, and the second surface of the substrate; etching back the sidewall material layer until the surface of the first active region 207 and the surface of the second active region 208 are exposed, and forming the sidewall 215 on the sidewall of the first groove and the sidewall of the second groove 214.

[0105] The sidewall 215 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0106] In this embodiment, the material of the sidewall 215 includes silicon nitride.

[0107] Please refer to Figure 26 , Figure 26 In order to be in Figure 25Based on the schematic diagram, the first active region 207 exposed by the sidewall 215 is removed, and a third groove 245 is formed in the first active region 207; the second active region exposed by the sidewall is removed, and a fourth groove 216 is formed in the second active region 208.

[0108] The third groove 245 exposes the surface of the first channel post 209, and the fourth groove 216 exposes the surface of the second channel post 210.

[0109] In this embodiment, the third groove 245 and the fourth groove 216 are formed simultaneously. In other embodiments, the third groove and the fourth groove may be formed asynchronously.

[0110] Please refer to Figures 27 to 29 , Figure 27 for Figure 28 and Figure 29 Top view, Figure 28 for Figure 27 A schematic diagram of the structure along section line BB1. Figure 29 for Figure 27 A structural schematic diagram along the cross-sectional line CC1 shows that a second isolation layer 217 is formed in the third groove 245 and the fourth groove 216.

[0111] The method of forming the second isolation layer 217 includes: removing the sidewall 215; after removing the sidewall 215, forming an isolation material layer in the third groove 245, the fourth groove 216 and the second surface of the substrate; planarizing the isolation material layer and the first isolation layer 203 until the surface of the first active region 207 and the surface of the second active region 208 are exposed, and forming the second isolation layer 217 in the third groove 245 and the fourth groove 216.

[0112] The material of the second isolation layer 217 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0113] In this embodiment, the material of the second isolation layer 217 includes silicon oxide.

[0114] Please refer to Figure 30 , Figure 30 In order to be in Figure 27Based on the schematic diagram, a first cutting layer 218 is formed within the first isolation layer 203 and the second isolation layer 217, penetrating the first active region 207, so that the first active region 207 is formed into a first part 222 and a second part 223 that are mutually separate, and the first cutting layer 218 is parallel to the first direction Y; a second cutting layer 220 is formed within the first isolation layer 203 and the second isolation layer 217, penetrating the second active region 208, so that the second active region 208 is formed into a third part 224 and a fourth part 225 that are mutually separate, and the second cutting layer 220 is parallel to the first direction Y.

[0115] There are two first cutting layers 218, located at opposite ends of the first active region 207 along the first direction Y. The first cutting layer 218 penetrates the first active region 207 along the first direction Y. The first cutting layer 218 penetrates the first active region 207 at the bottom of the first channel post 209.

[0116] There are two second cutting layers 220, located at opposite ends of the second active region 208 along the first direction Y. The second cutting layer 220 penetrates the second active region 208 along the first direction Y. The second cutting layer 220 penetrates the second active region 208 at the bottom of the second channel post 210.

[0117] In this embodiment, the depth of the first cut-off layer 218 is equal to the distance between the first channel pillar 209 and the second channel pillar 210 and the second surface of the substrate. The depth of the second cut-off layer 220 is also equal to the distance between the first channel pillar 209 and the second channel pillar 210 and the second surface of the substrate. This ensures that the channel pillars can electrically connect to the bit line structure and capacitor structure on the first and second surfaces of the substrate.

[0118] In this embodiment, the first cutting layer 218 and the second cutting layer 22 are formed simultaneously.

[0119] A fifth groove penetrating the first active region 207 and a sixth groove penetrating the second active region 208 are formed within the first isolation layer 203 and the second isolation layer 217, respectively. The depths of the fifth and sixth grooves are equal to the distances from the first channel pillars 209 and 210 to the second surface of the substrate. A cutting material layer is formed within the first fifth groove, the sixth groove, and the second surface of the substrate. The cutting material layer is planarized until the surfaces of the first active region 207 and the second active region 208 are exposed. A first cutting layer 218 is formed within the fifth groove, and a second cutting layer 220 is formed within the sixth groove.

[0120] The materials of the first isolation layer 203 and the second isolation layer 217 are the same. The materials of the first cutting layer 218 and the second cutting layer 220 are the same, but the materials of the first cutting layer 218 and the second cutting layer 220 are different from the materials of the first isolation layer 203 and the second isolation layer 217.

[0121] The materials of the first cutting layer 218 and the second cutting layer 220 include dielectric materials, which include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0122] In this embodiment, the materials of the first cutting layer 218 and the second cutting layer 220 include silicon nitride.

[0123] The first portion 222 and the second portion 223 are connected to the first channel area, that is, the first portion 222 and the second portion 223 are connected to the first channel post 209. The third portion 224 and the fourth portion 225 are connected to the second channel area, that is, the third portion 224 and the fourth portion 225 are connected to the second channel post 210.

[0124] In this embodiment, the first portion 222, the second portion 223, the third portion 224, and the fourth portion 225 are formed simultaneously.

[0125] In this embodiment, the first portion 222 and the second portion 223 are located in the first region I and the third region III. The third portion 224 and the fourth portion 225 are located in the first region I and the second region II.

[0126] Please refer to Figures 31 to 33 , Figure 31 for Figure 32 and Figure 33 Top view, Figure 32 for Figure 31 A schematic diagram of the structure along section line BB1. Figure 33 for Figure 31 A schematic diagram of the structure along the cross-sectional line CC1 shows a bit line structure formed on the second surface of the substrate. The bit line structure includes: a first bit line 226 electrically connected to the first portion 222, a second bit line 227 electrically connected to the second portion 223, a third bit line 228 electrically connected to the third portion 224, and a fourth bit line 229 electrically connected to the fourth portion 225. The bit line structure is parallel to the first direction Y.

[0127] In this embodiment, before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first portion 222, the second portion 223, the third portion 224 and the fourth portion 225 to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0128] The projected area of ​​the first bit line 226 on the substrate is less than or equal to the projected area of ​​the first portion 222 on the substrate; the projected area of ​​the second bit line 227 on the substrate is less than or equal to the projected area of ​​the second portion 223 on the substrate; the projected area of ​​the third bit line 228 on the substrate is less than or equal to the projected area of ​​the third portion 224 on the substrate; and the projected area of ​​the fourth bit line 229 on the substrate is less than or equal to the projected area of ​​the fourth portion 225 on the substrate.

[0129] In this embodiment, the projected area of ​​the first bit line 226 on the substrate is equal to the projected area of ​​the first portion 222 on the substrate; the projected area of ​​the second bit line 227 on the substrate is equal to the projected area of ​​the second portion 223 on the substrate; the projected area of ​​the third bit line 228 on the substrate is equal to the projected area of ​​the third portion 224 on the substrate; and the projected area of ​​the fourth bit line 229 on the substrate is equal to the projected area of ​​the fourth portion 225 on the substrate.

[0130] The process of forming a bitline structure on the second surface of the substrate includes: etching back the first portion 222 to form a first opening in the substrate; etching back the second portion 223 to form a second opening in the substrate; etching back the third portion 224 to form a third opening in the substrate; etching back the fourth portion 225 to form a fourth opening in the substrate; forming a bitline material layer in the first opening, the second opening, the third opening, the fourth opening, and on the first isolation layer 203; planarizing the bitline material layer until the surface of the first isolation layer 203 is exposed; forming the first bitline 226 in the first opening, the second bitline 227 in the second opening, the third bitline 228 in the third opening, and the fourth bitline 229 in the fourth opening. This process enables self-alignment of the bitline structure, further reducing the spacing between the bitline structures and saving on the use of a photomask.

[0131] In this embodiment, there is a first spacing between the first bit line 226 and the second bit line 227, and the first active region 207 has a first width in the second direction X. The ratio of the first spacing to the first width is between 1:2 and 1:4.

[0132] In this embodiment, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0133] In this embodiment, there is a second spacing between the third bit line 228 and the fourth bit line 229, and the second active region has a second width in the second direction X. The ratio of the second spacing to the second width is between 1:2 and 1:4.

[0134] In this embodiment, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0135] In this embodiment, the ratio of the width of the first isolation layer 203 in the second direction X to the width of the active region is in the range of 1:2 to 1:4.

[0136] In this embodiment, the width of the first isolation layer 203 ranges from 5 nanometers to 50 nanometers.

[0137] The material of the bitline structure includes metal silicides, which include nickel silicon or titanium silicon.

[0138] Please refer to Figure 34 , Figure 34 In order to be in Figure 31 Based on the schematic diagram, a first connection structure 230 and a second connection structure 231 are formed in the third region III. The first connection structure 230 is electrically connected to the first bit line 226, and the second connection structure 231 is electrically connected to the second bit line 227. The projections of the first connection structure 230 and the second connection structure 231 in the second direction X do not coincide. A third connection structure 232 and a fourth connection structure 233 are formed in the second region II. The third connection structure 232 is electrically connected to the third bit line 228, and the fourth connection structure 233 is electrically connected to the fourth bit line 229. The projections of the third connection structure 232 and the fourth connection structure 233 in the second direction X do not coincide.

[0139] In this embodiment, the first connection structure 230, the second connection structure 231, the third connection structure 232 and the fourth connection structure 233 are formed simultaneously.

[0140] The formation process of the first connection structure 230, the second connection structure 231, the third connection structure 232, and the fourth connection structure 233 includes: forming a dielectric structure (not shown) on the second surface of the substrate; forming a fifth opening, a sixth opening, a seventh opening, and an eighth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the surface of the first bit line 226 on the third region III, the sixth opening exposes at least a portion of the surface of the second bit line 227 on the third region III, the seventh opening exposes at least a portion of the surface of the third bit line 228 on the second region II, and the eighth opening exposes at least a portion of the surface of the second region I. The fourth bit line 229 on I; a barrier material layer and a conductive material layer on the barrier material layer are formed on the sidewall and bottom surfaces of the fifth opening, the sidewall and bottom surfaces of the sixth opening, the sidewall and bottom surfaces of the seventh opening, the sidewall and bottom surfaces of the eighth opening, and the dielectric structure surface; the conductive material layer and the barrier material layer are planarized until the dielectric structure surface is exposed; a first connection structure 230 is formed in the fifth opening, a second connection structure 231 is formed in the sixth opening, a third connection structure 232 is formed in the seventh opening, and a fourth connection structure 233 is formed in the eighth opening.

[0141] The barrier material layer is made of a metal nitride, including titanium nitride or tantalum nitride; the conductive material layer is made of a metal, including tungsten.

[0142] The semiconductor structure formed by the method has a smaller spacing between adjacent bit line structures, and the process window for forming the first connection structure 230, the second connection structure 231, the third connection structure 232, and the fourth connection structure 233 is increased. The first connection structure 230, the second connection structure 231, the third connection structure 232, and the fourth connection structure 233 are easier to form. This makes it easier for the first bit line 226 to be connected to an external circuit through the first connection structure 230, for the second bit line 227 to be connected to an external circuit through the second connection structure 231, for the third bit line 228 to be connected to an external circuit through the third connection structure 232, and for the fourth bit line 229 to be connected to an external circuit through the fourth connection structure 233. It also makes it easier to control the spaced bit lines individually and avoids capacitive coupling when two adjacent bit lines are energized at the same time.

[0143] Individual control is applied to the spaced-apart bit lines. Specifically, for the first bit lines 226, second bit lines 227, third bit lines 228, and fourth bit lines 229 arranged along the second direction X, the first bit lines 226, second bit lines 227, third bit lines 228, and fourth bit lines 229 in the odd-numbered sequence are energized, or the first bit lines 226, second bit lines 227, third bit lines 228, and fourth bit lines 229 in the even-numbered sequence are energized. In this way, there is a bit line without working voltage between each pair of adjacent bit lines that are energized. The bit line without working voltage acts as a metal shield, avoiding the situation where capacitive coupling easily occurs when two adjacent bit lines are energized at the same time.

[0144] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figures 31 to 34 ,include:

[0145] The substrate includes a first region I, a second region II, and a third region III distributed along a first direction Y parallel to the substrate surface. The first region I is located between the second region II and the third region III. The substrate includes opposing first and second surfaces. The substrate includes a plurality of first active regions 207 and a plurality of second active regions 208. The first active regions 207 are located in the first region I and the third region III, and the second active regions 208 are located in the first region I and the second region II. The plurality of first active regions 207 and the plurality of second active regions 208 are distributed along a first direction Y parallel to the substrate surface. The first active region 207 and the second active region 208 are arranged in parallel along the second direction X. The first direction Y is perpendicular to the second direction X. The first active region 207 exposed on the second surface of the substrate includes a first portion 222 and a second portion 223 that are mutually separate. The first portion 222 and the second portion 223 are parallel to the first direction Y. The second active region 208 exposed on the second surface of the substrate includes a third portion 224 and a fourth portion 225 that are mutually separate. The third portion 224 and the fourth portion 225 are parallel to the first direction Y.

[0146] A word line gate structure located in the first region I, wherein the word line gate structure is parallel to the second direction X;

[0147] The bit line structure located on the second surface of the substrate includes: a first bit line 226 electrically connected to the first portion 222, a second bit line 227 electrically connected to the second portion 223, a third bit line 228 electrically connected to the third portion 224, and a fourth bit line 229 electrically connected to the fourth portion 225. The bit line structure is parallel to the first direction Y.

[0148] The first connection structure 230 and the second connection structure 231 are located in the third region III. The first connection structure 230 is electrically connected to the first bit line 226, and the second connection structure 231 is electrically connected to the second bit line 227. The projections of the first connection structure 230 and the second connection structure 231 in the second direction X do not coincide.

[0149] The third connection structure 232 and the fourth connection structure 233 are located in the second region II. The third connection structure 232 is electrically connected to the third bit line 228, and the fourth connection structure 233 is electrically connected to the fourth bit line 229. The projections of the third connection structure 232 and the fourth connection structure 233 in the second direction X do not coincide.

[0150] The semiconductor structure allows for a larger process window for forming the first connection structure 230, the second connection structure 231, the third connection structure 232, and the fourth connection structure 233. This facilitates the formation of these structures, making it easier to connect the first bit line 226 to an external circuit via the first connection structure 230, the second bit line 227 to an external circuit via the second connection structure 231, the third bit line 228 to an external circuit via the third connection structure 232, and the fourth bit line 229 to an external circuit via the fourth connection structure 233. This also makes it easier to individually control the spaced-apart bit lines and avoids capacitive coupling when two adjacent bit lines are energized simultaneously.

[0151] In this embodiment, the first active region 207 includes a first channel region distributed along a direction perpendicular to the substrate surface, the second active region 208 includes a second channel region distributed along a vertical direction, the word line gate structure is adjacent to the first channel region and the second channel region; the first portion 222 and the second portion 223 are connected to the first channel region, and the third portion 224 and the fourth portion 225 are connected to the second channel region.

[0152] In this embodiment, the substrate further includes: a first isolation layer 203 located between adjacent first active regions 207 and second active regions 208, with the surface of the first isolation layer 203 exposed on a first surface of the substrate; and a third isolation layer 206 located in second region II and third region III, wherein the third isolation layer 206 located in second region II is in contact with the first active region 207 and the first isolation layer 203, and the third isolation layer 206 located in third region III is in contact with the second active region and the first isolation layer 203.

[0153] In this embodiment, it further includes: a second isolation layer 217 and a first cutting layer 218 located between the first portion 222 and the second portion 223, wherein the second isolation layer 217 is parallel to the first direction and the first cutting layer 218 is parallel to the first direction; and a second isolation layer 217 and a second cutting layer 220 located between the third portion 224 and the fourth portion 225, wherein the second isolation layer 217 is parallel to the first direction and the second cutting layer 220 is parallel to the first direction Y.

[0154] In this embodiment, the projected area of ​​the first bit line 226 on the substrate is less than or equal to the projected area of ​​the first portion 222 on the substrate; the projected area of ​​the second bit line 227 on the substrate is less than or equal to the projected area of ​​the second portion 223 on the substrate; the projected area of ​​the third bit line 228 on the substrate is less than or equal to the projected area of ​​the third portion 224 on the substrate; and the projected area of ​​the fourth bit line 229 on the substrate is less than or equal to the projected area of ​​the fourth portion 225 on the substrate.

[0155] In this embodiment, there is a first spacing between the first bit line 226 and the second bit line 227, and the first active region 207 has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:4.

[0156] In this embodiment, the first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

[0157] In this embodiment, there is a second spacing between the third bit line 228 and the fourth bit line 229, and the second active region 208 has a second width. The ratio of the second spacing to the second width is between 1:2 and 1:4.

[0158] In this embodiment, the second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

[0159] In this embodiment, it also includes: a plurality of capacitor structures 213 located on the first surface of the substrate, wherein one of the capacitor structures 213 is electrically connected to a first active region 207 or a second active region 208.

[0160] In this embodiment, it further includes: a first source / drain doped region located within the first active region 207 and the second active region 208 exposed on the first surface of the substrate, and the capacitor structure 213 is electrically connected to the first source / drain doped region.

[0161] In this embodiment, it further includes a second source / drain doped region located in the first portion 222, the second portion 223, the third portion 224 and the fourth portion 225, wherein the bit line structure is electrically connected to the second source / drain doped region.

[0162] In this embodiment, the first channel region includes a plurality of discrete first channel columns 209 located in the first region I; the second channel region includes a plurality of discrete second channel columns 210 located in the first region I.

[0163] In this embodiment, the word line gate structure includes: a first word line gate 211 and a second word line gate 212. The first word line gate 211 and the second word line gate 212 are respectively located on the two sidewalls of the first channel post 209 along the first direction Y, and respectively located on the two sidewalls of the second channel post 210 along the first direction Y. The first word line gate 211 and the second word line gate 212 are parallel to the second direction X. The first word line gate 211 and the second word line gate 212 are located in the substrate, and adjacent first word line gates 211 and second word line gates 212 are electrically isolated from each other.

[0164] In this embodiment, the central axes of two adjacent first channel posts 209 do not coincide in the first direction Y; the central axes of two adjacent second channel posts 210 do not coincide in the first direction Y.

[0165] In another embodiment, the word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

[0166] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region, a second region and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second region and the third region, the substrate including a first surface and a second surface opposite to each other, the substrate including: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first region and the third region, the second active regions being located in the first region and the second region, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other; A word line gate structure is formed within the first region, the word line gate structure being parallel to the second direction; The first active region exposed on the second surface of the substrate is removed, so that the first active region is formed into a first portion and a second portion that are mutually independent, and the first portion and the second portion are parallel to the first direction; The second active region exposed on the second surface of the substrate is removed, so that the second active region is formed into a third portion and a fourth portion that are mutually independent, the third portion and the fourth portion being parallel to the first direction; A bit line structure is formed on the second surface of the substrate. The bit line structure includes: a first bit line electrically connected to a first portion, a second bit line electrically connected to a second portion, a third bit line electrically connected to a third portion, and a fourth bit line electrically connected to a fourth portion. The bit line structure is parallel to the first direction. A first connection structure and a second connection structure are formed on the third region. The first connection structure is electrically connected to the first bit line, and the second connection structure is electrically connected to the second bit line. The projections of the first connection structure and the second connection structure in the second direction do not coincide. A third connection structure and a fourth connection structure are formed on the second region. The third connection structure is electrically connected to the third bit line, and the fourth connection structure is electrically connected to the fourth bit line. The projections of the third connection structure and the fourth connection structure in the second direction do not coincide.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, and the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface. The word line gate structure is adjacent to the first channel region and the second channel region. The first portion and the second portion are connected to the first channel region, and the third portion and the fourth portion are connected to the second channel region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first, second, third, and fourth portions are formed simultaneously. The formation process of the first, second, third, and fourth portions includes: etching back the first active region to form a first groove within the substrate, the first groove extending from the second surface of the substrate to the first surface; etching back the second active region to form a second groove within the substrate, the second groove extending from the second surface of the substrate to the first surface; forming sidewalls on the sidewalls of the first and second grooves, the sidewall on the sidewall of the first groove exposing a portion of the surface of the first active region, and the sidewall on the sidewall of the second groove exposing a portion of the surface of the second active region; using the sidewalls as a mask... The membrane removes the exposed first active region, forming a third groove within the first active region; the sidewall is used as a mask to remove the exposed second active region, forming a fourth groove within the second active region; a second isolation layer is formed within the third and fourth grooves; a first cutting layer is formed within the substrate, penetrating the first active region, such that the first active region is formed into a first and a second mutually independent portion, the first cutting layer being parallel to a first direction; a second cutting layer is formed within the substrate, penetrating the second active region, such that the second active region is formed into a third and a fourth mutually independent portion, the second cutting layer being parallel to the first direction.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, Forming sidewalls on the first and second groove sidewalls includes: forming a sidewall material layer on the surface and bottom surface of the first groove sidewall, the surface and bottom surface of the second groove sidewall, and the first surface of the substrate; and etching back the sidewall material layer until the surfaces of the first and second active regions are exposed, thereby forming sidewalls on the first and second groove sidewalls.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The third and fourth grooves are formed simultaneously. The formation process of the third and fourth grooves includes: removing the exposed first active area using the sidewall as a mask until the surface of the first channel area is exposed, and forming a third groove in the first active area; removing the exposed second active area using the sidewall as a mask until the surface of the second channel area is exposed, and forming a fourth groove in the second active area.

6. The method for forming a semiconductor structure as described in claim 3, characterized in that, Forming a second isolation layer in the third and fourth grooves includes: removing the sidewalls; after removing the sidewalls, forming an isolation material layer in the third and fourth grooves and on the second surface of the substrate; planarizing the isolation material layer and the second surface of the substrate until the surfaces of the first and second active regions are exposed, and forming a second isolation layer in the third and fourth grooves.

7. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first cutting layer and the second cutting layer are formed simultaneously; the formation process of the first cutting layer and the second cutting layer includes: forming a fifth groove penetrating the first active region and a sixth groove penetrating the second active region in the substrate; forming the first cutting layer in the fifth groove and forming the second cutting layer in the sixth groove.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; The projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the third portion on the substrate; The projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process of forming a bit line structure on the second surface of the substrate includes: etching back the first portion to form a first opening in the substrate; etching back the second portion to form a second opening in the substrate; etching back the third portion to form a third opening in the substrate; etching back the fourth portion to form a fourth opening in the substrate; forming a bit line material layer in the first opening, the second opening, the third opening, the fourth opening, and on the first isolation layer; planarizing the bit line material layer until the surface of the second surface of the substrate is exposed; forming the first bit line in the first opening; forming the second bit line in the second opening; forming the third bit line in the third opening; and forming the fourth bit line in the fourth opening.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, There is a first spacing between the first bit line and the second bit line, and the first active region has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:

4.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The third bit line and the fourth bit line have a second spacing, the second active region has a second width, and the ratio of the second spacing to the second width is in the range of 1:2 to 1:

4.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first connection structure, the second connection structure, the third connection structure, and the fourth connection structure are formed simultaneously; The formation process of the first connection structure, the second connection structure, the third connection structure, and the fourth connection structure includes: forming a dielectric structure on a second surface of a substrate; forming a fifth opening, a sixth opening, a seventh opening, and an eighth opening within the dielectric structure, wherein the fifth opening exposes at least a portion of the first bit line surface on a third region, the sixth opening exposes at least a portion of the second bit line surface on a third region, the seventh opening exposes at least a portion of the third bit line surface on a second region, and the eighth opening exposes at least a portion of the fourth bit line surface on a second region; forming a barrier material layer and a conductive material layer on the barrier material layer on the sidewall and bottom surfaces of the fifth opening, the sixth opening, the seventh opening, the eighth opening, and the dielectric structure surface; planarizing the conductive material layer and the barrier material layer until the dielectric structure surface is exposed; forming a first connection structure within the fifth opening, a second connection structure within the sixth opening, a third connection structure within the seventh opening, and a fourth connection structure within the eighth opening.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a first isolation layer located between adjacent first active regions and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; the substrate formation process includes: providing an initial substrate, the initial substrate including a first region, a second region and a third region distributed along a first direction parallel to the surface of the initial substrate, the first region being located between the second region and the third region, the initial substrate including: a substrate, a plurality of initial first active regions and a plurality of initial second active regions located on the substrate, and a first isolation layer located between adjacent initial first active regions and initial second active regions, the plurality of initial first active regions and the plurality of initial second active regions being distributed along a first direction parallel to the surface of the initial substrate, the initial substrate including: a substrate, a plurality of initial first active regions and a plurality of initial second active regions located on the substrate, and a first isolation layer located between adjacent initial first active regions and initial second active regions, the plurality of initial first active regions and the plurality of initial second active regions being distributed along a first direction parallel to the surface of the initial substrate, the first region being located between the second region and the third region, the first surface of the initial substrate exposing the surface of the first isolation layer and the third active ... The initial first active region and the initial second active region are arranged parallel to each other in a second direction on the surface of the initial substrate, and are arranged alternately. The first surface of the initial substrate exposes the surface of the first isolation layer. The initial first active region in the second region is removed to form a first active region located in the first region and the third region, and a seventh groove is formed in the initial substrate, the seventh groove extending from the first surface of the initial substrate to the second surface. The initial second active region in the third region is removed to form a second active region located in the first region and the second region, and an eighth groove is formed in the initial substrate, the eighth groove extending from the first surface of the initial substrate to the second surface. A third isolation layer is formed in the seventh groove and the eighth groove.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The substrate formation process further includes: before removing a portion of the first active region and the second active region exposed on the second surface of the substrate, the process further includes: removing the substrate to expose the surface of the first isolation layer, the surface of the first active region, and the surface of the second active region, thereby forming the substrate.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the word line gate structure in the first region, the method further includes: forming a plurality of capacitor structures on the first surface of the substrate, wherein one of the capacitor structures is electrically connected to one of the first active regions or the second active region.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Before forming several capacitor structures, the method further includes: performing a first ion implantation on a first active region and a second active region exposed on the first surface of the substrate to form a first source-drain doped region, wherein the capacitor structure is electrically connected to the first source-drain doped region.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the bit line structure on the second surface of the substrate, the method further includes: performing a second ion implantation on the first, second, third, and fourth portions to form a second source / drain doped region, wherein the bit line structure is electrically connected to the second source / drain doped region.

20. The method for forming a semiconductor structure as described in claim 2, characterized in that, Before forming the word line grid structure located in the first region, the method further includes: etching the first channel region of the first active region to form a plurality of discrete first channel pillars located in the first region; and etching the second channel region of the second active region to form a plurality of discrete second channel pillars located in the first region.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction. The first word line gate and the second word line gate are parallel to the second direction. The first word line gate and the second word line gate are located within the substrate, and adjacent first word line gates and second word line gates are electrically isolated from each other.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

23. The method for forming a semiconductor structure as described in claim 20, characterized in that, The word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

24. A semiconductor structure, characterized in that, include: A substrate comprising a first region, a second region, and a third region distributed along a first direction parallel to the substrate surface, the first region being located between the second and third regions, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising: a plurality of first active regions and a plurality of second active regions, the first active regions being located in the first and third regions, the second active regions being located in the first and second regions, the plurality of first active regions and the plurality of second active regions being arranged in parallel along a second direction parallel to the substrate surface, the first active regions and the second active regions being arranged alternately, the first direction and the second direction being perpendicular to each other, the first active regions exposed on the second surface of the substrate comprising mutually separate first portions and second portions, the first portions and the second portions being parallel to the first direction, the second active regions exposed on the second surface of the substrate comprising mutually separate third portions and fourth portions, the third portions and the fourth portions being parallel to the first direction; A word line gate structure located in the first region, the word line gate structure being parallel to the second direction; A bit line structure located on the second surface of a substrate, the bit line structure comprising: a first bit line electrically connected to a first portion, a second bit line electrically connected to a second portion, a third bit line electrically connected to a third portion, and a fourth bit line electrically connected to a fourth portion, the bit line structure being parallel to a first direction; A first connection structure and a second connection structure are located in the third region. The first connection structure is electrically connected to the first bit line, and the second connection structure is electrically connected to the second bit line. The projections of the first connection structure and the second connection structure in the second direction do not coincide. The third and fourth connection structures are located in the second region. The third connection structure is electrically connected to the third bit line, and the fourth connection structure is electrically connected to the fourth bit line. The projections of the third and fourth connection structures in the second direction do not coincide.

25. The semiconductor structure as described in claim 24, characterized in that, The first active region includes a first channel region distributed along a direction perpendicular to the substrate surface, and the second active region includes a second channel region distributed along a direction perpendicular to the substrate surface. The word line gate structure is adjacent to the first channel region and the second channel region. The first portion and the second portion are connected to the first channel region, and the third portion and the fourth portion are connected to the second channel region.

26. The semiconductor structure as claimed in claim 24, characterized in that, The substrate further includes: a first isolation layer located between adjacent first and second active regions, the first surface of the substrate exposing the surface of the first isolation layer; and a third isolation layer located in the second and third regions, the third isolation layer in the second region being in contact with the first active region and the first isolation layer, and the third isolation layer in the third region being in contact with the second active region and the first isolation layer.

27. The semiconductor structure as claimed in claim 24, characterized in that, Also includes: A second isolation layer and a first cutting layer are located between the first section and the second section, wherein the second isolation layer is parallel to the first direction and the first cutting layer is parallel to the first direction; A second isolation layer and a second cutting layer are located between the third and fourth sections, the second isolation layer being parallel to the first direction and the second cutting layer being parallel to the first direction.

28. The semiconductor structure as claimed in claim 24, characterized in that, The projected area of ​​the first bit line on the substrate is less than or equal to the projected area of ​​the first portion on the substrate; the projected area of ​​the second bit line on the substrate is less than or equal to the projected area of ​​the second portion on the substrate; The projected area of ​​the third bit line on the substrate is less than or equal to the projected area of ​​the third portion on the substrate; The projected area of ​​the fourth bit line on the substrate is less than or equal to the projected area of ​​the fourth portion on the substrate.

29. The semiconductor structure as claimed in claim 24, characterized in that, There is a first spacing between the first bit line and the second bit line, and the first active region has a first width. The ratio of the first spacing to the first width is between 1:2 and 1:

4.

30. The semiconductor structure as claimed in claim 29, characterized in that, The first spacing ranges from 5 nanometers to 50 nanometers; the first width ranges from 10 nanometers to 100 nanometers.

31. The semiconductor structure as described in claim 24, characterized in that, The third bit line and the fourth bit line have a second spacing, the second active region has a second width, and the ratio of the second spacing to the second width is in the range of 1:2 to 1:

4.

32. The semiconductor structure as described in claim 31, characterized in that, The second spacing ranges from 5 nanometers to 50 nanometers; the second width ranges from 10 nanometers to 100 nanometers.

33. The semiconductor structure as described in claim 24, characterized in that, Also includes: A plurality of capacitor structures located on a first surface of a substrate, wherein one of the capacitor structures is electrically connected to a first active region or a second active region.

34. The semiconductor structure as described in claim 33, characterized in that, Also includes: The capacitor structure is electrically connected to the first source / drain doped region located within the first and second active regions exposed on the first surface of the substrate.

35. The semiconductor structure as described in claim 24, characterized in that, Also includes: The second source / drain doped region is located in the first, second, third, and fourth sections, and the bit line structure is electrically connected to the second source / drain doped region.

36. The semiconductor structure as described in claim 25, characterized in that, The first trench area includes a plurality of separate first trench columns located in the first area; the second trench area includes a plurality of separate second trench columns located in the first area.

37. The semiconductor structure as described in claim 36, characterized in that, The word line gate structure includes: a first word line gate and a second word line gate, the first word line gate and the second word line gate being located on the two sidewalls of the first channel post along the first direction, and respectively on the two sidewalls of the second channel post along the first direction. The first word line gate and the second word line gate are parallel to the second direction. The first word line gate and the second word line gate are located within the substrate, and adjacent first word line gates and second word line gates are electrically isolated from each other.

38. The semiconductor structure as described in claim 37, characterized in that, The central axes of two adjacent first trench columns do not coincide in the first direction; the central axes of two adjacent second trench columns do not coincide in the first direction.

39. The semiconductor structure as described in claim 36, characterized in that, The word grid structure includes: a plurality of first word grids surrounding the first channel post, a plurality of second word grids surrounding the second channel post, and a plurality of first word grids and a plurality of second word grids connected along a second direction and parallel to the second direction.

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