Semiconductor memory device and semiconductor device

Abstract

The embodiment provides a semiconductor memory device and a semiconductor device capable of manufacturing a high-quality semiconductor device. According to one embodiment, a semiconductor memory device includes: an oxide semiconductor extending in a vertical direction; a first electrode including a first conductor including a first oxide conductive material and connected to an upper end of the oxide semiconductor; a gate electrode facing the oxide semiconductor with a gate insulating film interposed therebetween; a second electrode provided below the oxide semiconductor and extending in the vertical direction; a dielectric layer provided on the outer peripheral surface of the second electrode; and a third electrode provided on the outer peripheral surface of the dielectric layer, the second electrode including a second conductor that includes a second oxide conductive material, is connected to the lower end of the oxide semiconductor, and has an opposing surface that opposes the inner peripheral surface of the third electrode with the dielectric layer interposed therebetween.

Description

[0001] Related applications:

[0002] This application enjoys priority by virtue of Japanese Patent Application No. 2024-158967 (filed on September 13, 2024). This application is incorporated herein by reference to the entire contents of that earlier application. Technical Field

[0003] This embodiment relates to a semiconductor memory device and a semiconductor device. Background Technology

[0004] In some semiconductor devices, metal oxides containing indium and tin are used as electrodes. Summary of the Invention

[0005] In the manufacturing process of semiconductor devices that use metal oxides as electrodes, there is a need for technologies that produce high-quality semiconductor devices.

[0006] The problem to be solved by the present invention is to provide a semiconductor memory device and a semiconductor device capable of manufacturing high-quality semiconductor devices.

[0007] The semiconductor memory device according to the embodiments includes: an oxide semiconductor extending in a vertical direction; a first electrode including a first conductor comprising a first oxide conductive material and connected to the upper end of the oxide semiconductor; a gate electrode facing the oxide semiconductor through a gate insulating film; a second electrode disposed below the oxide semiconductor and extending in the vertical direction; a dielectric layer disposed on the outer peripheral surface of the second electrode; and a third electrode disposed on the outer peripheral surface of the dielectric layer, the second electrode including a second conductor comprising a second oxide conductive material, connected to the lower end of the oxide semiconductor, and having a facing surface facing the inner peripheral surface of the third electrode through the dielectric layer.

[0008] The semiconductor device according to the embodiments includes: an oxide semiconductor extending in a vertical direction; a first electrode including a first conductor comprising a first oxide conductive material and connected to the upper end of the oxide semiconductor; a gate electrode facing the oxide semiconductor through a gate insulating film; and a second electrode connected to the lower end of the oxide semiconductor and comprising a second oxide conductive material, wherein a first contact portion between the oxide semiconductor and the second electrode does not contact a seam included in the second electrode.

[0009] The semiconductor memory device according to the embodiments includes: the semiconductor device; a first capacitor electrode connected to the second electrode; a second capacitor electrode opposite to the first capacitor electrode; and a dielectric film disposed between the first capacitor electrode and the second capacitor electrode. Attached Figure Description

[0010] Figure 1 This is a circuit diagram used to illustrate an example of the circuit structure of the memory cell array according to the first embodiment.

[0011] Figure 2 This is a cross-sectional schematic diagram used to illustrate a construction example of the semiconductor memory device according to the first embodiment, showing a cross-sectional view parallel to the ZX plane.

[0012] Figure 3 This is a detailed cross-sectional view of the semiconductor memory device 101 as viewed through a section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70.

[0013] Figure 4 This is a detailed cross-sectional view of the semiconductor memory device 101 as viewed through a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0014] Figure 5 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0015] Figure 6 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0016] Figure 7 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0017] Figure 8 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0018] Figure 9 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0019] Figure 10 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0020] Figure 11 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0021] Figure 12 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0022] Figure 13 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0023] Figure 14 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0024] Figure 15 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0025] Figure 16 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0026] Figure 17 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0027] Figure 18 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0028] Figure 19 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0029] Figure 20 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0030] Figure 21 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0031] Figure 22 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0032] Figure 23 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0033] Figure 24 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor memory device according to the first embodiment.

[0034] Figure 25 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the capacitor according to the first embodiment.

[0035] Figure 26 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the capacitor according to the first embodiment.

[0036] Figure 27 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the capacitor according to the first embodiment.

[0037] Figure 28 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the capacitor according to the first embodiment.

[0038] Figure 29 This is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the capacitor according to the first embodiment.

[0039] Figure 30 A detailed cross-sectional view of a modified example of a semiconductor memory device 101 as viewed through a section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70.

[0040] Figure 31 A detailed cross-sectional view showing a modified example of the semiconductor memory device 101 as viewed through a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0041] Figure 32 This is a cross-sectional view of the semiconductor memory device 102 as viewed through a section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70.

[0042] Figure 33 This is a plan view of capacitor 120 viewed from above.

[0043] Figure 34 This is a schematic diagram used to illustrate joint 301.

[0044] Figure 35 This is a plan view of the metal oxide layer 50a viewed from below.

[0045] Figure 36 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device of the comparative example.

[0046] Figure 37 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device of the comparative example.

[0047] Figure 38 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device of the comparative example.

[0048] Figure 39 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device of the comparative example.

[0049] Figure 40 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device of the comparative example.

[0050] Figure 41 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor memory device according to the second embodiment.

[0051] Figure 42 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor memory device according to the second embodiment.

[0052] Figure 43 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor memory device according to the second embodiment.

[0053] Figure 44 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor memory device according to the second embodiment.

[0054] Figure 45 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor memory device according to the second embodiment.

[0055] Figure 46 This is a diagram used to illustrate joint 302, which is a variation of joint 301.

[0056] Figure 47 This is a diagram used to illustrate joint 303, which is a variation of joint 301.

[0057] Figure 48 This is a diagram used to illustrate joint 304, which is a variation of joint 301.

[0058] Figure 49 This is a diagram used to illustrate joint 305, which is a variation of joint 301.

[0059] Explanation of reference numerals in the attached figures:

[0060] 10…Semiconductor substrate, 11…Circuit, 20, 20a, 120…Capacitor, 21…Conductive film, 22…Dielectric layer, 22o…Outer peripheral surface, 22i…Inner peripheral surface, 22a, 22b…Insulating film, 23…Conductor, 24…Electrode, 24o…Outer peripheral surface, 25…Electrode, 25i…Inner peripheral surface, 30, 30B…Semiconductor device, 32…Metal oxide layer, 32d…Central axis, 32a…Opposite surface, 33…Conductor, 34…Insulating layer, 35…Insulating layer, 36…Hard mask layer, 36a…Opening, 37…Resist layer, 37a…Opening, 40…Field effect transistor, 42…Conductive layer, 43…Gate insulating film, 45…Insulating layer, 45a, 45b…Insulating layer Film, 50…electrode, 50a…metal oxide layer, 50b…barrier metal layer, 50c…metal film, 63…insulating layer, 70…oxide semiconductor layer, 70a…upper end, 70b…lower end, 70d…central axis, 101, 102…semiconductor memory device, 124…electrode, 132…metal oxide layer, 132L…lateral orientation portion, 132V…vertical orientation portion, 224…barrier metal layer, 224a…recess, 201, 202…contact portion, 211, 212…surface, 211cg, 212cg…center of gravity, 211c…central portion, 211o…outer periphery, 301, 302, 303, 304, 305…seam, CH…capacitor hole, TH…transistor hole. Detailed Implementation

[0061] Hereinafter, this embodiment will be described with reference to the accompanying drawings. In order to make the description easy to understand, the same reference numerals will be used for the same constituent elements as much as possible in each drawing, and repeated descriptions will be omitted.

[0062] [First Implementation]

[0063] The configuration of the semiconductor memory device according to the first embodiment will be explained. In the various figures, the X-axis, Y-axis, and Z-axis are sometimes indicated. The X-axis, Y-axis, and Z-axis form a three-dimensional orthogonal coordinate system in a right-handed system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the direction opposite to the arrow is sometimes referred to as the X-axis- direction, and the same applies to the other axes. In addition, the Z-axis+ direction and the Z-axis- direction are sometimes referred to as "above" and "below," respectively. Furthermore, the plane orthogonal to the X-axis, Y-axis, or Z-axis is sometimes referred to as the YZ plane, ZX plane, or XY plane, respectively. In addition, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms indicating relative positional relationships within the figures, and are not terms determining the orientation based on the vertical direction.

[0064] In addition, except where specifically described, the dimensions of the constituent elements shown in the figures are sometimes different from the actual dimensions in order to make the explanation easier to understand.

[0065] In this specification, "connection" includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0066] In this specification, "formed above" includes not only the case of forming above and grounding, but also the case of forming above with other objects in between, unless otherwise specified. The same applies to cases such as "formed below".

[0067] The semiconductor memory device 101 according to the first embodiment is an OS-RAM (Oxide Semiconductor-Random Access Memory) and has a memory cell array.

[0068] like Figure 1 As shown, the memory cell array includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

[0069] exist Figure 1 In the example of multiple word lines WL, it represents word line WL. n 、Word line WL n+1 WL (with character line) n+2 (Here, n is a positive integer). Additionally, in Figure 1 In the example, BL represents the bit line BL. m Bitline BL m+1 and position line BL m+2 (Here, m is a positive integer). Furthermore, the number of memory cells MC is not limited to... Figure 1 The number shown.

[0070] Multiple memory cells MC are arranged, for example, in a matrix, to form a memory cell array. A memory cell MC includes a storage transistor MTR, which is a field-effect transistor (FET), and a storage capacitor MCP.

[0071] A series of memory cells MC arranged along the row direction are connected to the word line WL (e.g., word line WL) corresponding to their respective row (e.g., the nth row). n A series of memory cells MC arranged along the column direction are connected to the bit line BL corresponding to their respective column (e.g., the (m+2)th column). m+2 ).

[0072] In detail, the gate of the storage transistor MTR included in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs. The source or drain of the storage transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0073] One electrode of the storage capacitor MCP included in the memory cell MC is connected to the other electrode of the storage transistor MTR included in the memory cell MC, either the source or the drain. The other electrode of the memory cell MC is connected to a power supply line (not shown) that provides a specific potential.

[0074] The memory cell MC is configured such that the storage transistor MTR switches based on the potential of the corresponding word line WL, and the current flowing in the corresponding bit line BL stores charge in the storage capacitor MCP, thereby storing data.

[0075] like Figure 2 As shown, the semiconductor memory device 101 includes a semiconductor substrate 10, a circuit 11 (an example of a “semiconductor circuit”), a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35 and 63.

[0076] The capacitor 20 includes a dielectric layer 22 (an example of a “dielectric film”), a conductor 23, an electrode 24 (a “second electrode”), and an electrode 25 (an example of a “third electrode” and a “second capacitor electrode”).

[0077] The semiconductor device 30 includes a field-effect transistor 40 (an example of a “semiconductor element”), an electrode 50 disposed above the field-effect transistor 40 (an example of a “first electrode”), and an electrode 24 disposed below the field-effect transistor 40 (an example of a “second electrode”).

[0078] The field-effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of a "gate electrode"), and an insulating layer 45. The field-effect transistor 40 corresponds to the memory transistor MTR of a memory cell MC (see reference). Figure 1 ).

[0079] An oxide semiconductor layer 70 is formed within an insulating layer 45, having an upper end 70a and a lower end 70b. The oxide semiconductor layer 70 is a columnar body extending in the vertical direction. The oxide semiconductor layer 70 has a central axis 70d (an example of a "second central axis") that is substantially parallel to the Z-axis. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure.

[0080] The oxide semiconductor layer 70 is a semiconductor in which oxygen defects serve as donors. The oxide semiconductor layer 70 includes at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), iridium (Ir), ruthenium (Ru), and titanium (Ti), as well as oxygen.

[0081] In this embodiment, the oxide semiconductor layer 70 contains indium, zinc, and gallium as metal elements. Specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, namely IGZO (InGaZnO). Alternatively, the oxide semiconductor layer 70 may be other types of oxide semiconductors.

[0082] The field-effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) that is substantially perpendicular to the surface of the semiconductor substrate 10.

[0083] The conductive layer 42 is positioned opposite the oxide semiconductor layer 70, separated by a gate insulating film 43. Specifically, the conductive layer 42 functions as the gate electrode of the field-effect transistor 40, and surrounds the oxide semiconductor layer 70 between its upper end 70a and lower end 70b, separated by the gate insulating film 43. The conductive layer 42 may contain, for example, tungsten (W).

[0084] The conductive layer 42 consists of multiple electrodes extending approximately parallel to the Y-axis and repeatedly arranged in the X-axis direction. These electrodes correspond to the word line WL (see reference). Figure 1 ).

[0085] The gate insulating film 43 comprises, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen. The gate insulating film 43 is formed to cover the sides of the oxide semiconductor layer 70 throughout the entire perimeter.

[0086] Electrode 50 is formed above oxide semiconductor layer 70 and connected to the upper end 70a of oxide semiconductor layer 70. Electrode 50 includes metal oxide layer 50a (an example of "first conductor"), barrier metal layer 50b and metal film 50c.

[0087] The metal oxide layer 50a is connected to the upper end 70a of the oxide semiconductor layer 70. In this embodiment, the metal oxide layer 50a is in contact with the upper end 70a of the oxide semiconductor layer 70. The metal oxide layer 50a contains a first oxide conductive material. Specifically, the first oxide conductive material is an oxide conductive material containing indium and tin as metal elements. More specifically, the first oxide conductive material is indium-tin oxide (ITO).

[0088] A metal film 50c is disposed above the metal oxide layer 50a and contains tungsten. A barrier metal layer 50b is formed between the metal oxide layer 50a and the metal film 50c. The barrier metal layer 50b contains, for example, titanium and nitrogen. In this embodiment, the barrier metal layer 50b is formed of titanium nitride (TiN).

[0089] Circuit 11 constitutes a decoder for selecting a specific memory cell MC from among the plurality of memory cells MC of the semiconductor memory device 101, namely capacitors 20 and field-effect transistors 40, a sense amplifier connected to bit line BL, a register composed of SRAM, and other peripheral circuits. Circuit 11 may also include CMOS circuitry having P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs) formed by CMOS technology.

[0090] For example, a field-effect transistor (FET) for forming a circuit 11 can be formed using a semiconductor substrate 10 such as a single-crystal silicon substrate. P-FETs and N-FETs are so-called lateral field-effect transistors, wherein the semiconductor substrate 10 has a channel region, a source region, and a drain region, and a channel for allowing charge carriers to flow in the X-axis or Y-axis direction, which is substantially parallel to the surface of the semiconductor substrate 10, is present in a region close to the surface of the semiconductor substrate 10. Furthermore, the semiconductor substrate 10 may also have P-type or N-type conductivity. Figure 2 For convenience, an example of a field-effect transistor in circuit 11 is shown.

[0091] Capacitor 20 is the storage capacitor MCP included in the memory cell MC (refer to...). Figure 1 ). Figure 2 The diagram shows four capacitors 20, but the number of capacitors 20 is not limited to four.

[0092] Figure 3 This is a detailed cross-sectional view of the semiconductor memory device 101 as viewed through a section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70. Figure 4 This is a detailed cross-sectional view of the semiconductor memory device 101 as viewed through a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0093] like Figure 3 and Figure 4 As shown, capacitor 20 is disposed below oxide semiconductor layer 70 and above semiconductor substrate 10. Electrode 24 in capacitor 20 is disposed below oxide semiconductor layer 70 and has a columnar shape extending in the vertical direction. The upper end of electrode 24 is connected to the lower end 70b of oxide semiconductor layer 70.

[0094] A dielectric layer 22 is disposed on the outer peripheral surface 24o of the electrode 24. An electrode 25 is disposed on the outer peripheral surface 22o of the dielectric layer 22.

[0095] In detail, electrode 24 includes a conductive film 21 (an example of a "third conductor") and a metal oxide layer 32 (an example of a "second conductor").

[0096] The metal oxide layer 32 includes a second oxide conductive material. The second oxide conductive material includes at least one of indium (In), zinc (Zn), tin (Sn), iridium (Ir), ruthenium (Ru), titanium (Ti) and tungsten (W), and oxygen.

[0097] In this embodiment, the second oxide conductive material comprises indium, tin, and oxygen. Specifically, the second oxide conductive material is the same indium-tin oxide (ITO) as the metal oxide layer 50a.

[0098] The upper end of the metal oxide layer 32 contacts the lower end 70b of the oxide semiconductor layer 70. The metal oxide layer 32 has a columnar shape extending in the vertical direction. The metal oxide layer 32 has a central axis 32d (an example of a "first central axis") that is substantially parallel to the Z-axis. The central axis 32d is aligned with the central axis 70d.

[0099] The lower part of the outer peripheral surface of the metal oxide layer 32 is the opposing surface 32a, which is opposite to the inner peripheral surface 25i of the electrode 25, separated by the dielectric layer 22.

[0100] A conductive film 21 in electrode 24 is disposed between the metal oxide layer 32 and the dielectric layer 22. Specifically, the conductive film 21 is disposed on the outer peripheral surface of the metal oxide layer 32. The conductive film 21 has a cup shape with an opening at the top, and the metal oxide layer 32 is contained within the cup.

[0101] The conductive film 21 comprises, for example, titanium and nitrogen. In this embodiment, the conductive film 21 is formed of titanium nitride. The outer peripheral surface of the conductive film 21 becomes the outer peripheral surface 24o of the electrode 24.

[0102] The dielectric layer 22 includes insulating films 22a and 22b. The insulating film 22a is disposed on the outer peripheral surface 24o of the electrode 24. The insulating film 22a has a cup shape with an opening at the top, and the electrode 24 is housed within the cup.

[0103] An insulating film 22b is disposed on the outer peripheral surface of the insulating film 22a. The insulating film 22b has a cup shape with an opening at the top, and the insulating film 22a is stored in the cup.

[0104] The upper end of the metal oxide layer 32, the opening above the conductive film 21, the opening above the insulating film 22a, and the opening above the insulating film 22b are aligned in the Z direction.

[0105] Insulating films 22a and 22b are formed of materials with high dielectric constants. Specifically, insulating film 22a may also contain materials such as ZrO containing zirconium and oxygen. Insulating film 22b may also contain materials such as ZrAlO containing zirconium, aluminum, and oxygen. The outer peripheral surface of insulating film 22b becomes the outer peripheral surface 22o of dielectric layer 22.

[0106] Electrode 25 is disposed on a portion below the outer peripheral surface 22o of dielectric layer 22. Electrode 25 has a cup shape with an opening at the top, and a portion below dielectric layer 22 is housed within the cup. In addition, electrode 25 has a lower end that abuts against the upper surface of conductor 23.

[0107] Electrode 25 comprises, for example, titanium and nitrogen. In this embodiment, electrode 25 is formed of titanium nitride. The upper opening of electrode 25 is located below the upper end of metal oxide layer 32. The inner peripheral surface 25i of electrode 25 faces a portion below the outer peripheral surface 24o of electrode 24, separated by dielectric layer 22.

[0108] The conductor 23 is in contact with the lower ends of the plurality of electrodes 25 included in each of the plurality of capacitors 20. The conductor 23 functions, for example, as a grounding electrode for grounding. The conductor 23 may also contain materials such as tungsten or titanium nitride.

[0109] like Figure 2 As shown, conductor 33 includes wiring that electrically connects circuit 11 to semiconductor device 30. Conductor 33 may also include via wiring, such as via wiring that extends in the Z-axis direction and connects word line WL to circuit 11 disposed on semiconductor substrate 10. Conductor 33 may contain copper, for example.

[0110] An insulating layer 34 is disposed between multiple capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0111] An insulating layer 35 is disposed above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen. The upper surface of the insulating layer 35 is aligned in the Z direction with the upper end of the electrode 24 and the upper end of the dielectric layer 22.

[0112] [Manufacturing Method of Semiconductor Memory Devices]

[0113] Hereinafter, as an example of the manufacturing method of the semiconductor memory device according to the first embodiment, the manufacturing method of the semiconductor memory device 101 will be described.

[0114] First, such as Figure 5 As shown, an insulating layer 34 and an insulating layer 35 are sequentially formed above the conductor 23. The conductor 23, the insulating layer 34, and the insulating layer 35 each extend along a plane that is approximately parallel to the XY plane.

[0115] Next, as Figure 6As shown, a hard mask layer 36 and a photoresist layer 37 are sequentially formed above the insulating layer 35. The hard mask layer 36 and the photoresist layer 37 each extend along a plane that is approximately parallel to the XY plane. Then, the photoresist layer 37 is exposed, developed, and stripped using photolithography to form multiple openings 37a in the photoresist layer 37.

[0116] Next, as Figure 7 As shown, the hard mask layer 36 exposed through the opening 37a of the resist layer 37 is removed by reactive ion etching. Thus, an opening 36a, continuous with the opening 37a, is formed in the hard mask layer 36.

[0117] Next, as Figure 8 As shown, a portion of the insulating layer 35 and a portion of the insulating layer 34 are removed through openings 37a and 36a by reactive ion etching. This forms a capacitor hole CH whose bottom reaches the conductor 23.

[0118] Next, as Figure 9 As shown, electrode 25 forms a film on the inner surface of capacitor hole CH and on the surface above insulating layer 35.

[0119] Next, as Figure 10 As shown, an insulating layer 134 is formed above electrode 25. The insulating layer 134 is, for example, a silicon oxide film containing silicon and oxygen. Then, a portion of the insulating layer 134 above is removed by reactive ion etching. Thus, an insulating layer 134 is formed that fills a portion below the capacitor hole CH.

[0120] Next, as Figure 11 As shown, the electrode 25, which was exposed above the end of the insulating layer 134, is removed by etching. Thus, the electrode 25 is formed on the inner surface of the capacitor hole CH. Furthermore, the upper end of the electrode 25 is located below the surface above the insulating layer 35.

[0121] Next, as Figure 12 As shown, the insulating layer 134 inside the capacitor hole CH is removed by etching.

[0122] Next, as Figure 13 As shown, insulating film 22b, insulating film 22a and conductive film 21 are sequentially deposited on the inner surface of capacitor hole CH and on the surface above insulating layer 35.

[0123] Next, as Figure 14As shown, a metal oxide layer 32 is deposited on the surface above the conductive film 21. The metal oxide layer 32 is deposited, for example, inside the capacitor aperture CH by ALD (atomic layer deposition).

[0124] Next, as Figure 15 As shown, a portion of the upper part of each of the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b is removed by chemical mechanical polishing, exposing the insulating layer 35. This forms a metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b separated according to each capacitor hole CH. Furthermore, the upper ends of each of the metal oxide layer 32, conductive film 21, insulating film 22a, and insulating film 22b are aligned in the Z-direction.

[0125] Next, as Figure 16 As shown, an insulating film 45b, a conductive layer 42, and an insulating film 45a are sequentially disposed above the insulating layer 35. The insulating film 45b, the conductive layer 42, and the insulating film 45a each extend along a plane that is approximately parallel to the XY plane.

[0126] Next, as Figure 17 As shown, for example, after forming a mask above the insulating film 45a by photolithography, a transistor hole TH is formed by reactive ion etching. The transistor hole TH extends approximately parallel to the Z-axis, penetrating the insulating film 45a, the conductive layer 42, and the insulating film 45b. At the bottom of the transistor hole TH, the surface above the metal oxide layer 32 is exposed. The transistor hole TH has a tapered shape with a smaller cross-section towards the bottom.

[0127] Next, as Figure 18 As shown, the gate insulating film 43 is formed in such a way that it covers the surface above the insulating film 45a and the inner surface of the transistor hole TH.

[0128] Next, as Figure 19 As shown, a portion of the gate insulating film 43 is etched using reactive ion etching. This exposes the surface above the metal oxide layer 32 at the bottom of the transistor hole TH.

[0129] Next, as Figure 20 As shown, an oxide semiconductor layer 70 is formed on the surface above the insulating film 45a and in the transistor hole TH. The lower end 70b of the oxide semiconductor layer 70 contacts the surface above the metal oxide layer 32 exposed at the bottom of the transistor hole TH. Thus, the transistor hole TH is filled by the oxide semiconductor layer 70.

[0130] Next, as Figure 21As shown, a portion of the oxide semiconductor layer 70 is removed, exposing the surface above the insulating film 45a. At this time, the surface of the upper end 70a of the oxide semiconductor layer 70 is aligned in the Z direction with the upper end of the gate insulating film 43 and the surface above the insulating film 45a.

[0131] Next, as Figure 22 As shown, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are sequentially formed above the oxide semiconductor layer 70 and the insulating film 45a. The metal oxide layer 50a, the barrier metal layer 50b, and the metal film 50c each extend along a plane that is substantially parallel to the XY plane.

[0132] Next, as Figure 23 As shown, an electrode 50 is formed on each oxide semiconductor layer 70 by etching a portion of each of the metal film 50c, the barrier metal layer 50b, and the metal oxide layer 50a. The electrode 50 functions as a pad.

[0133] Next, as Figure 24 As shown, an insulating layer 63 is formed to cover the electrode 50. The insulating layer 63 contains, for example, silicon oxide. Then, a portion of the insulating layer 63 is chemically mechanically polished, thereby exposing the surface above the electrode 50.

[0134] [Manufacturing method of capacitor 120]

[0135] The following describes a method for manufacturing a capacitor 120 having a structure different from that of capacitor 20.

[0136] First, such as Figure 25 As shown, the manufacturing method of capacitor 120 is similar to... Figure 15 Compared to the manufacturing method of the capacitor 20 shown, an electrode 124 is deposited on the surface above the conductive film 21 to replace the metal oxide layer 32. The electrode 124 may contain, for example, SiGe containing silicon and germanium. The electrode 124 is deposited inside the capacitor aperture CH, for example, by CVD (Chemical Vapor Deposition).

[0137] Next, as Figure 26 As shown, through chemical mechanical polishing, a portion of the upper part of each of the electrode 124, conductive film 21, insulating film 22a, and insulating film 22b is removed, exposing the insulating layer 35. This forms an electrode 124, conductive film 21, insulating film 22a, and insulating film 22b separated according to each capacitor hole CH. Furthermore, the upper ends of each of the electrode 124, conductive film 21, insulating film 22a, and insulating film 22b are aligned in the Z-direction.

[0138] Next, as Figure 27As shown, a portion above electrode 124 is removed by etching. This forms electrode 124 (an example of "first capacitor electrode") that fills a portion below capacitor hole CH.

[0139] Next, as Figure 28 As shown, a barrier metal layer 224 and a metal oxide layer 132 are sequentially deposited above the capacitor aperture CH. The barrier metal layer 224, for example, comprises titanium nitride containing nitrogen and titanium. The metal oxide layer 132, for example, comprises ITO.

[0140] Next, as Figure 29 As shown, by chemical mechanical polishing, a portion of the upper part of each of the metal oxide layer 132 and the barrier metal layer 224 is removed, exposing the insulating layer 35. Furthermore, the upper ends of the insulating layer 35, insulating film 22b, insulating film 22a, conductive film 21, barrier metal layer 224, and metal oxide layer 132 are aligned in the Z-direction.

[0141] (Effect)

[0142] like Figures 25-29 As shown, in the manufacturing method of capacitor 120, from the deposition of electrode 124 to the completion of capacitor 120, the process includes chemical mechanical polishing, forming a recess by removing a portion above electrode 124, depositing barrier metal layer 224 and metal oxide layer 132, and chemical mechanical polishing steps.

[0143] In contrast, in the manufacturing method of capacitor 20, such as Figure 14 and Figure 15 As shown, the capacitor 20 is completed by chemical mechanical polishing after depositing the metal oxide layer 32. That is, the capacitor 20 can be manufactured using a simple process.

[0144] In addition, in capacitor 120, the resistance value increases due to the contact resistance between metal oxide layer 132 and barrier metal layer 224 and between barrier metal layer 224 and electrode 124.

[0145] In contrast, in capacitor 20, by using a metal oxide layer 32 instead of the metal oxide layer 132, electrode 124 and barrier metal layer 224, the aforementioned contact resistance is not generated, thus reducing the resistance value.

[0146] Furthermore, the metal oxide layer 132 in capacitor 120 is smaller in volume compared to the metal oxide layer 32 in capacitor 20. Therefore, the metal oxide layer 132 is sometimes smaller due to the formation process of the gate insulating film 43 (see reference). Figure 18 ) and etching process (refer to) Figure 19 And then disappeared.

[0147] In contrast, in capacitor 20, by employing a larger configuration for the metal oxide layer 32, the formation process of the gate insulating film 43 can be suppressed (see reference). Figure 18 ) and etching process (refer to) Figure 19 The case where the metal oxide layer 132 disappears in the middle.

[0148] In addition, it is also considered to provide an electrode 124 (refer to) that replaces the metal oxide layer 32. Figure 26 The structure is formed by contacting the lower end 70b of the oxide semiconductor layer 70, but the work function of SiGe and IGZO is not well matched, so the resistance value becomes high.

[0149] In contrast, in the semiconductor memory device 101, by employing a configuration in which the lower end 70b of the metal oxide layer 32 (ITO) and the oxide semiconductor layer 70 (IGZO) are in contact, which allows for better matching of work functions, the resistance value can be reduced.

[0150] (Modification of semiconductor memory device 101)

[0151] Figure 30 A detailed cross-sectional view of a modified example of a semiconductor memory device 101 as viewed through a section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70. Figure 31 A detailed cross-sectional view showing a modified example of the semiconductor memory device 101 as viewed through a section 70YZ parallel to the YZ plane and contained within the oxide semiconductor layer 70.

[0152] like Figure 30 and Figure 31 As shown, a modified example of the semiconductor memory device 101 is similar to... Figure 3 and Figure 4 Compared to the semiconductor memory device 101 shown, a capacitor 20a is provided instead of a capacitor 20.

[0153] The electrode 24 in capacitor 20a, compared to the electrode 24 in capacitor 20, does not include the conductive film 21. That is, the outer peripheral surface of the metal oxide layer 32 becomes the outer peripheral surface 24o of the electrode 24.

[0154] By employing a configuration that does not include the conductive film 21, the process of depositing the conductive film 21 can be omitted. That is, the capacitor 20a can be manufactured using a simplified process.

[0155] [Second Implementation]

[0156] The semiconductor memory device 102 according to the second embodiment will be described. From the second embodiment onwards, descriptions of aspects common to the first embodiment will be omitted, and only the differences will be explained. In particular, the same effects achieved through the same configuration will not be described one by one according to each embodiment.

[0157] Figure 32 This is a cross-sectional view of the semiconductor memory device 102 as viewed through a section 70ZX parallel to the ZX plane and contained within the oxide semiconductor layer 70.

[0158] like Figure 32 As shown, the semiconductor memory device 102 according to the second embodiment and Figure 3 and Figure 4 Compared to the semiconductor memory device 101 shown, a semiconductor device 30B and a capacitor 120 are provided instead of semiconductor device 30 and capacitor 20.

[0159] Compared to capacitor 20, capacitor 120 includes an electrode 124, a metal oxide layer 132, and a barrier metal layer 224 instead of metal oxide layer 32.

[0160] Figure 33 This is a plan view of capacitor 120 viewed from above. (See diagram below.) Figure 32 and Figure 33 As shown, in the semiconductor device 30B, the barrier metal layer 224 forms a downwardly recessed recess 224a.

[0161] In detail, the barrier metal layer 224 has an upwardly opening cup shape. The lower surface of the barrier metal layer 224 is in contact with the upper surface of the electrode 124. The side surface of the barrier metal layer 224 is in contact with the upper inner peripheral surface of the conductive film 21.

[0162] The metal oxide layer 132 (an example of the "second electrode") fills the recess 224a. The upper ends of the insulating layer 35, insulating film 22b, insulating film 22a, conductive film 21, barrier metal layer 224 and metal oxide layer 132 are aligned in the Z direction.

[0163] Furthermore, the metal oxide layer 132 is connected to the lower end 70b of the oxide semiconductor layer 70 and contains a second oxide conductive material. In this embodiment, the upper surface 211 of the metal oxide layer 132 is in contact with the lower end 70b of the oxide semiconductor layer 70.

[0164] The contact portion 201 (an example of the "first contact portion") between the metal oxide layer 132 and the oxide semiconductor layer 70 is generally circular. The metal oxide layer 132 is a cylinder having a central axis extending in the vertical direction.

[0165] Figure 34 This is a schematic diagram used to illustrate joint 301. For example... Figures 32-34 As shown, the metal oxide layer 132 includes a seam 301. When the metal oxide layer 132 is viewed along the vertical direction, the centroid 211cg of the upper surface 211 of the metal oxide layer 132 overlaps with the seam 301.

[0166] For example, when ITO is filled into the recess 224a by sputtering, sometimes ITO is filled in the outer peripheral portion 211o which is close to the side of the recess 224a, but the filling in the central portion 211c which is far away from the side and close to the center of gravity 211cg is insufficient.

[0167] The unfilled ITO voids are the seam 301. In this embodiment, the seam 301 has a spindle shape that is elongated in the vertical direction.

[0168] Furthermore, the metal oxide layer 132 filling the recess 224a includes a transversely oriented portion 132L and a longitudinally oriented portion 132V. The transversely oriented portion 132L is close to the side surface of the recess 224a, and the ITO is oriented along a plane parallel to the XY plane. The longitudinally oriented portion 132V is located closer to the centroid 211cg side than the transversely oriented portion 132L, and the ITO is oriented along an axis parallel to the Z-axis.

[0169] The contact portion 201 between the oxide semiconductor layer 70 and the metal oxide layer 32 does not contact the seam 301 included in the metal oxide layer 32.

[0170] When the metal oxide layer 132 is viewed in the vertical direction, the contact portion 201 separates from the center of gravity 211cg. Preferably, when the metal oxide layer 132 is viewed in the vertical direction, the contact portion 201 does not overlap with the seam 301.

[0171] Furthermore, the contact portion 201 is closer to the outer periphery of the metal oxide layer 132 than the center of gravity 211cg. In detail, when the metal oxide layer 132 is viewed along the vertical direction, the distance between the contact portion 201 and the outer periphery of the metal oxide layer 132 is shorter than the distance between the contact portion 201 and the center of gravity 211cg.

[0172] Figure 35 This is a plan view of the metal oxide layer 50a as seen from below. (See attached image.) Figure 32 and Figure 35 As shown, when the metal oxide layer 50a is viewed along the vertical direction, the contact portion 202 (an example of the "second contact portion") between the oxide semiconductor layer 70 and the metal oxide layer 50a overlaps with the center of gravity 212cg of the surface 212 below the metal oxide layer 50a.

[0173] Furthermore, the contact portion 202 may not overlap with the center of gravity 212cg. In this case, it is preferable that the contact portion 202 is closer to the center of gravity 212cg than the outer periphery of the metal oxide layer 50a. Specifically, when viewing the metal oxide layer 50a in the vertical direction, the distance between the contact portion 202 and the center of gravity 212cg is shorter than the distance between the contact portion 202 and the outer periphery of the metal oxide layer 50a.

[0174] (Topic)

[0175] Figures 36-40 This is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device of the comparative example.

[0176] First, such as Figure 36 As shown, a seam 301 is formed in the metal oxide layer 132. When the metal oxide layer 132 is viewed along the vertical direction, the seam 301 overlaps with the center of gravity 211cg.

[0177] Next, as Figure 37 As shown, the transistor hole TH is formed by reactive ion etching. However, when the transistor hole TH is formed with its bottom overlapping the center of gravity 211cg, the transistor hole TH sometimes penetrates the metal oxide layer 132 due to the presence of the seam 301. In this case, the metal oxide layer 132 is exposed on the sidewall of the transistor hole TH.

[0178] Next, as Figure 38 As shown, the gate insulating film 43 is formed in a manner that covers the inner surface of the transistor hole TH. However, due to the heat applied during the formation of the gate insulating film 43, the temperature of the metal oxide layer 132 rises, and sometimes the metal oxide layer 132 disappears.

[0179] Next, as Figure 39 As shown, the gate insulating film 43 at the bottom of the transistor hole TH is etched by reactive ion etching. However, since the transistor hole TH has a tapered shape, the area at the bottom of the transistor hole TH is small, making it difficult to etch the gate insulating film 43.

[0180] Next, as Figure 40 As shown, an oxide semiconductor layer 70 is formed in the transistor hole TH. However, since the transistor hole TH has a tapered shape, the contact area between the oxide semiconductor layer 70 at the lower end 70b and the conductive film 21 is reduced.

[0181] [Manufacturing method of semiconductor memory device 102]

[0182] Hereinafter, as an example of the manufacturing method of the semiconductor memory device according to the second embodiment, the manufacturing method of the semiconductor memory device 102 will be described.

[0183] First, such as Figure 41 As shown, a seam 301 is formed in the metal oxide layer 132. When the metal oxide layer 132 is viewed along the vertical direction, the seam 301 overlaps with the center of gravity 211cg.

[0184] Next, as Figure 42 As shown, the transistor hole TH is formed by reactive ion etching in a manner that separates the bottom of the transistor hole TH from the center of gravity 211cg. This prevents the transistor hole TH from being continuous with the seam 301 located directly below the center of gravity 211cg, thus preventing the transistor hole TH from penetrating the metal oxide layer 132.

[0185] Next, as Figure 43 As shown, a gate insulating film 43 is formed in a manner that covers the inner surface of the transistor aperture TH. At this time, with... Figure 38 In the case shown, the exposure of the metal oxide layer 132 is suppressed at the bottom of the transistor hole TH. Therefore, even if the temperature of the metal oxide layer 132 rises due to the heat applied during the formation of the gate insulating film 43, the disappearance of the metal oxide layer 132 can be suppressed.

[0186] Next, as Figure 44 As shown, the gate insulating film 43 at the bottom of the transistor hole TH is etched using reactive ion etching. (And...) Figure 39 The situation shown is different, allowing the bottom of the transistor hole TH to be located at a higher position, thus ensuring sufficient area at the bottom of the transistor hole TH for proper etching of the gate insulating film 43.

[0187] Next, as Figure 45 As shown, an oxide semiconductor layer 70 is formed in the transistor aperture TH. (And...) Figure 40 The situation is different in that the lower end 70b of the oxide semiconductor layer 70 can be located at a higher position, thus ensuring the area of ​​the contact portion 201 is sufficiently large.

[0188] (Examples of variations in the shape of seams)

[0189] The shape of seam 301 is not limited to spindle shape (see reference). Figure 32 Sometimes it also takes other shapes. For example, such as... Figure 46 As shown, the joint 302 can also be a columnar structure with a relatively long vertical direction, with its upper and lower ends exposed from the metal oxide layer 132. That is, the joint 302 penetrates the metal oxide layer 132.

[0190] In addition, such as Figure 47As shown, the joint 303 is not limited to a configuration that penetrates the metal oxide layer 132 like the joint 302, but can also be a columnar structure that is relatively long in the vertical direction and is embedded in the metal oxide layer 132. Alternatively, the upper or lower end of the joint 303 may be exposed from the metal oxide layer 132.

[0191] In addition, such as Figure 48 As shown, the seam 304 can also be a conical shape with its upper end exposed from the metal oxide layer 132 and tapering from top to bottom.

[0192] In addition, such as Figure 49 As shown, the joint 305 can also be configured such that the upper and lower ends are exposed from the metal oxide layer 132 and have a tapered shape that expands from top to bottom.

[0193] Furthermore, the shape of the seams 301 to 305 is roughly determined based on the shape of the metal oxide layer 132, i.e., the shape of the recess 224a. In most cases, the shapes of the metal oxide layers 132 in adjacent capacitors 120 are approximately the same. Therefore, in most cases, seams of approximately the same shape are formed in adjacent metal oxide layers 132.

[0194] Furthermore, in the semiconductor memory device 101, a configuration has been described in which the central axis 70d of the oxide semiconductor layer 70 is aligned with the central axis 32d of the metal oxide layer 32, but this is not a limitation. A configuration in which the central axis 70d and the central axis 32d are separated in a direction intersecting the vertical direction may also be used. Specifically, a configuration in which the semiconductor device 30B is disposed above the capacitor 20 may also be used.

[0195] Furthermore, in capacitor 120, the recess 224a is described as being formed by a barrier metal layer 224, but this is not a limitation. At least a portion of the recess 224a may also be formed by other electrodes or insulating films.

[0196] Furthermore, in the semiconductor memory device 102, a configuration including one of the seams 301 to 305 of the metal oxide layer 132 has been described, but it is not limited to this. The metal oxide layer 132 may also be configured without seams 301 to 305. Even when the metal oxide layer 132 includes one of the seams 301 to 305, the semiconductor memory device 102 exhibits excellent electrical characteristics. Therefore, even when the metal oxide layer 132 does not include seams 301 to 305, the semiconductor memory device 102 obviously exhibits excellent electrical characteristics.

[0197] (a) A semiconductor device

[0198] The semiconductor device further includes an insulating film or electrode having at least a portion of a recess formed thereon.

[0199] The second electrode is embedded in the recess.

[0200] When the second electrode is viewed along the vertical direction, the first contact portion does not overlap with the seam.

[0201] The embodiments described above have been illustrated with reference to specific examples. However, this disclosure is not limited to these specific examples. Methods obtained by those skilled in the art through appropriate design modifications to these specific examples, as long as they possess the features of this disclosure, are also included within the scope of this disclosure. The elements, their configurations, conditions, shapes, etc., of each of the above-described specific examples are not limited to the illustrated cases and can be appropriately modified. The combinations of the elements of each of the above-described specific examples can be appropriately changed as long as there is no technical contradiction.

Claims

1. A semiconductor memory device, wherein, have: Oxide semiconductor, extending along the vertical direction; The first electrode includes a first conductor, which comprises a first oxide conductive material and is connected to the upper end of the oxide semiconductor. The gate electrode is positioned opposite the oxide semiconductor, separated by a gate insulating film; The second electrode is disposed below the oxide semiconductor and extends in the vertical direction; A dielectric layer is disposed on the outer peripheral surface of the second electrode; as well as The third electrode is disposed on the outer peripheral surface of the dielectric layer. The second electrode includes a second conductor comprising a second oxide conductive material, connected to the lower end of the oxide semiconductor, and having a facing surface that faces the inner peripheral surface of the third electrode through the dielectric layer.

2. The semiconductor memory device as claimed in claim 1, wherein, The second electrode further includes a third conductor disposed between the second conductor and the dielectric layer, and comprising titanium and nitrogen.

3. The semiconductor memory device as claimed in claim 1, wherein, The second oxide conductive material includes at least one of indium, zinc, tin, iridium, ruthenium, titanium and tungsten, and oxygen.

4. The semiconductor memory device as claimed in claim 1, wherein, The second conductor is a column with a first central axis extending along the vertical direction. The oxide semiconductor is columnar with a second central axis extending along the vertical direction. The first central axis and the second central axis separate in a direction that intersects with the vertical direction.

5. A semiconductor device, wherein, have: Oxide semiconductor, extending along the vertical direction; The first electrode includes a first conductor, which comprises a first oxide conductive material and is connected to the upper end of the oxide semiconductor. The gate electrode is opposed to the oxide semiconductor through a gate insulating film; and The second electrode is connected to the lower end of the oxide semiconductor and comprises a second oxide conductive material. The first contact portion between the oxide semiconductor and the second electrode does not contact the seam included in the second electrode.

6. The semiconductor device of claim 5, wherein, The semiconductor device further includes an insulating film or electrode having at least a portion of a recess formed thereon. The second electrode is embedded in the recess.

7. The semiconductor device of claim 5, wherein, When the second electrode is viewed along the vertical direction, the center of gravity of the surface above the second electrode overlaps with the seam.

8. The semiconductor device of claim 5, wherein, The semiconductor device further includes an insulating film or electrode having at least a portion of a recess formed thereon. The second electrode is embedded in the recess. When the second electrode is viewed along the vertical direction, the first contact portion separates from the center of gravity of the surface above the second electrode.

9. The semiconductor device of claim 5, wherein, The oxide semiconductor comprises at least one of indium, gallium, zinc, tin, aluminum, iridium, ruthenium, and titanium, and oxygen.

10. The semiconductor device of claim 5, wherein, The second oxide conductive material comprises at least one of indium, zinc, tin, iridium, ruthenium, titanium and tungsten, and oxygen.

11. The semiconductor device of claim 5, wherein, The second contact portion of the oxide semiconductor with the first electrode overlaps with the center of gravity of the surface below the first electrode.

12. A semiconductor memory device, wherein, have: The semiconductor device as claimed in claim 5; The first capacitor electrode is connected to the second electrode; The second capacitor electrode is opposite to the first capacitor electrode; as well as A dielectric film is disposed between the first capacitor electrode and the second capacitor electrode.

13. A semiconductor memory device, wherein, have: The semiconductor device as claimed in claim 5; The second electrode is disposed below the oxide semiconductor and extends in the vertical direction; A dielectric layer is disposed on the outer peripheral surface of the second electrode; as well as The third electrode is disposed on the outer peripheral surface of the dielectric layer. The second electrode includes a second conductor comprising a second oxide conductive material, is connected to the lower end, and has a facing surface that is separated from the inner peripheral surface of the third electrode by the dielectric layer.

14. A semiconductor device, wherein, have: Oxide semiconductor, extending along the vertical direction; The first electrode includes a first conductor, which comprises a first oxide conductive material and is connected to the upper end of the oxide semiconductor. The gate electrode is opposed to the oxide semiconductor through a gate insulating film; and The second electrode is connected to the lower end of the oxide semiconductor and comprises a second oxide conductive material. The first contact portion between the oxide semiconductor and the second electrode is separated from the center of gravity of the surface above the second electrode.

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