Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. According to one embodiment, a semiconductor device includes a laminated film including a plurality of electrode layers and a plurality of first insulating films alternately provided in a first direction. The device further includes a columnar portion extending in the first direction within the laminated film and including a charge storage layer provided on a side surface of the laminated film via a second insulating film and a semiconductor layer provided on a side surface of the charge storage layer via a third insulating film. A first electrode layer among the plurality of electrode layers includes a first layer containing molybdenum, nitrogen, and a group 14 element, and a second layer containing molybdenum.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] In three-dimensional semiconductor memories, electrode material layers within electrode layers such as word lines are formed, for example, from a Mo (molybdenum) layer. In this case, the question arises as to what layer to use to form the barrier metal layer within the electrode layers. Summary of the Invention

[0003] According to one embodiment, a semiconductor device includes a laminated film comprising a plurality of electrode layers and a plurality of first insulating films alternately disposed in a first direction. The device further includes a columnar portion extending within the laminated film along the first direction, and comprising a charge storage layer disposed on a side of the laminated film separated by a second insulating film, and a semiconductor layer disposed on a side of the charge storage layer separated by a third insulating film. The first electrode layers among the plurality of electrode layers include a first layer containing molybdenum, nitrogen, and a Group 14 element, and a second layer containing molybdenum. Attached Figure Description

[0004] Figure 1 This is a perspective view showing the structure of the semiconductor device according to the first embodiment.

[0005] Figures 2-5 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0006] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment and the structure of the semiconductor device of the first embodiment.

[0007] Figure 7 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0008] Figure 8 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0009] Figure 9 and Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. Detailed Implementation

[0010] The embodiments will now be described with reference to the accompanying drawings. Figures 1-10 In this context, the same label is used for the same component, and repeated descriptions are omitted.

[0011] (First Embodiment)

[0012] Figure 1 This is a perspective view showing the structure of the semiconductor device according to the first embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0013] The semiconductor device of this embodiment includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a block insulating film 5, and an electrode layer 6. The block insulating film 5 includes an insulating film 5a and an insulating film 5b, and the electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The barrier metal layer 6a and the electrode material layer 6b are examples of the first and second layers, respectively. The channel semiconductor layer 2 is an example of a semiconductor layer. The insulating film 5a, the tunnel insulating film 3, and the insulating film 5b are examples of the second, third, and fourth insulating films, respectively.

[0014] exist Figure 1 In this process, multiple electrode layers and multiple insulating films are alternately stacked on the substrate, and storage holes MH are provided in these electrode layers and insulating films. Figure 1 One of these electrode layers, layer 6, is shown. Each of these electrode layers functions, for example, as a word line or select line of a three-dimensional semiconductor memory. Figure 1 The X and Y directions, parallel and perpendicular to the surface of the substrate, and the Z direction, perpendicular to the surface of the substrate, are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction as the downward direction. The -Z direction may or may not align with the direction of gravity. The Z direction is an example of the first direction, and the storage hole MH is an example of the first recess. Figure 1 In the image, the storage hole MH extends in the Z direction and has a circular shape when viewed from above.

[0015] A core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge accumulation layer 4, and an insulating film 5a are formed within a memory aperture MH, constituting a memory cell of a three-dimensional semiconductor memory. The insulating film 5a is formed on the side of the electrode layer and the insulating film within the memory aperture MH, and the charge accumulation layer 4 is formed on the side of the insulating film 5a. The charge accumulation layer 4 can accumulate the signal charge of the three-dimensional semiconductor memory. The tunnel insulating film 3 is formed on the side of the charge accumulation layer 4, and the channel semiconductor layer 2 is formed on the side of the tunnel insulating film 3. The channel semiconductor layer 2 functions as the channel of the three-dimensional semiconductor memory. The core insulating film 1 is formed on the side of the channel semiconductor layer 2.

[0016] The insulating film 5a is, for example, a SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, a SiO2 film. The channel semiconductor layer 2 is, for example, a polycrystalline silicon layer. The core insulating film 1 is, for example, a SiO2 film. Figure 1In this structure, a columnar portion CL comprising a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, and an insulating film 5a is formed within a storage via MH. Figure 1 In the middle, the columnar part CL extends in the Z direction and has a circular shape when viewed from above.

[0017] An insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are formed between two of the plurality of insulating films, sequentially on the upper surface of the lower insulating film, the lower surface of the upper insulating film, and the side surface of the insulating film 5a. Specifically, the barrier metal layer 6a is formed between the lower and upper insulating films, with the insulating film 5b in between, and is formed on the upper surface, lower surface, and side surface of the insulating film 5b. Similarly, the electrode material layer 6b is formed between the lower and upper insulating films, with the insulating film 5b and the barrier metal layer 6a in between, and is formed on the upper surface, lower surface, and side surface of the barrier metal layer 6a. The plurality of insulating films are examples of a first insulating film, the lower insulating film is an example of a lower insulating film, and the upper insulating film is an example of an upper insulating film. Furthermore, Figure 1 The electrode layer 6 shown is an example of the first electrode layer.

[0018] The insulating film 5b is, for example, an Al₂O₃ film (Al represents aluminum, O represents oxygen). The barrier metal layer 6a is, for example, a MoSiN film (Mo represents molybdenum, Si represents silicon, N represents nitrogen). The electrode material layer 6b is, for example, a Mo (molybdenum) layer.

[0019] Next, continue to refer to Figure 1 The barrier metal layer 6a and electrode material layer 6b of this embodiment will be described in further detail.

[0020] The barrier metal layer 6a comprises molybdenum, silicon, and nitrogen, and may also include one or more other elements. Examples of such elements are oxygen and hydrogen. The barrier metal layer 6a is, for example, a MoSiN film containing oxygen and / or hydrogen as impurity elements. However, in this embodiment, the barrier metal layer 6a preferably contains molybdenum as the main component element. For example, the barrier metal layer 6a contains elements E1, E2, ... E N When N is an integer greater than or equal to 2, the preferred atomic concentration of molybdenum within the barrier metal layer 6a is that of elements E1, E2, ..., E within the barrier metal layer 6a. N Atomic concentrations C1, C2, ... C N The maximum concentration in.

[0021] The atomic concentration of nitrogen within the barrier metal layer 6a is, for example, 20% or more of the total atomic concentration of molybdenum, silicon, and nitrogen within the barrier metal layer 6a. Furthermore, the atomic concentration of silicon within the barrier metal layer 6a is, for example, 5% or more of the total atomic concentration of molybdenum, silicon, and nitrogen within the barrier metal layer 6a. Additionally, if the barrier metal layer 6a contains hydrogen, the atomic concentration of hydrogen within the barrier metal layer 6a is, for example, 1.0 × 10⁻⁶. 20 atoms / cm 3 above.

[0022] The barrier metal layer 6a is, for example, an amorphous layer. The thickness of the barrier metal layer 6a is, for example, 3 nm or less. According to this embodiment, by making the barrier metal layer 6a thin, the electrode layer 6 can be made thin, for example. In this embodiment, because the barrier metal layer 6a is thin, the barrier metal layer 6a, being an amorphous layer, will not change into a polycrystalline layer due to annealing, and will remain an amorphous layer after annealing. However, the barrier metal layer 6a may also be a polycrystalline layer.

[0023] The barrier metal layer 6a may also contain a Group 14 element other than silicon to replace silicon. An example of such a Group 14 element is carbon. The foregoing and subsequent descriptions related to the barrier metal layer 6a also apply to the case where the barrier metal layer 6a contains a Group 14 element other than silicon to replace silicon.

[0024] Electrode material layer 6b contains molybdenum, and may also contain one or more other elements. An example of such an element is hydrogen. Electrode material layer 6b is, for example, a Mo layer containing hydrogen as an impurity element. However, in this embodiment, electrode material layer 6b preferably contains molybdenum as the main component element. For example, electrode material layer 6b contains elements e1, e2, ... e n When n is an integer greater than or equal to 2, the preferred atomic concentration of molybdenum within the electrode material layer 6b is that of elements e1, e2, ..., e within the electrode material layer 6b. n atomic concentrations c1, c2, ... c n The maximum concentration in.

[0025] The atomic concentration of hydrogen within the electrode material layer 6b is, for example, higher than the atomic concentration of hydrogen within the insulating film 5a. Further details of this relationship will be described later.

[0026] Both the barrier metal layer 6a and the electrode material layer 6b contain molybdenum. The barrier metal layer 6a and the electrode material layer 6b are formed, for example, using a source gas containing molybdenum and chlorine. In this case, the barrier metal layer 6a and the electrode material layer 6b may contain chlorine as an impurity element. Furthermore, hydrogen and oxygen in the barrier metal layer 6a may be introduced into the barrier metal layer 6a, for example, from the source gas used in forming the barrier metal layer 6a and other layers. Similarly, hydrogen in the electrode material layer 6b may be introduced into the electrode material layer 6b, for example, from the source gas used in forming the electrode material layer 6b and other layers. However, impurity elements in the barrier metal layer 6a and the electrode material layer 6b may also originate from sources other than the source gas, such as annealing gases.

[0027] As described above, the electrode material layer 6b in this embodiment is formed using molybdenum. This reduces the resistance of the electrode material layer 6b. For example, by using molybdenum to form the electrode material layer 6b, the resistance of the electrode material layer 6b can be reduced compared to using tungsten or aluminum.

[0028] Furthermore, the barrier metal layer 6a in this embodiment is formed using molybdenum, silicon, and nitrogen. This suppresses the diffusion of nitrogen (N) atoms from the barrier metal layer 6a to the electrode material layer 6b, thus suppressing the increase in resistance of the electrode material layer 6b caused by N atoms. Moreover, it suppresses the diffusion of oxygen (O), hydrogen (H), and chlorine (Cl) atoms through the barrier metal layer 6a to the barrier insulating film 5 and the charge accumulation layer 4, thus suppressing the decrease in data retention capability of the three-dimensional semiconductor memory caused by these atoms.

[0029] Furthermore, the oxygen and hydrogen within the barrier metal layer 6a may originate from O and H atoms that did not penetrate the barrier metal layer 6a and remain within it. The barrier metal layer 6a may sometimes contain 1.0 × 10⁻⁶ H atoms, for example. 20 atoms / cm 3 The above describes a high concentration of H atoms. Furthermore, the relationship that the hydrogen atom concentration within the electrode material layer 6b is higher than that within the insulating film 5a stems, for example, from a large number of H atoms remaining within the electrode material layer 6b instead of penetrating the barrier metal layer 6a. Further details regarding the diffusion of these atoms will be described later.

[0030] Figures 2-5 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0031] First, a laminated film 12 is formed on the substrate 11. Figure 2The laminated film 12 comprises a plurality of sacrificial layers 13 and a plurality of insulating films 14 alternately formed in the Z direction. The laminated film 12 is formed by alternately laminating these sacrificial layers 13 and insulating films 14 on a substrate 11. The laminated film 12 can be formed directly on the substrate 11 or formed on the substrate 11 with other layers in between. The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The sacrificial layer 13 is, for example, a SiN film. The insulating film 14 is, for example, a SiO2 film. The sacrificial layer 13 is an example of a third layer. The insulating film 14 is an example of a first insulating film.

[0032] Next, multiple storage vias MH are formed within the stacked film 12 using photolithography and RIE (Reactive Ion Etching). Figure 2 ). Figure 2 One of these storage holes MH is shown. In this embodiment, each storage hole MH extends in the Z direction, penetrating the laminated film 12. Each storage hole MH is an example of the first recess.

[0033] Next, an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed on the sides of the stacked films 12 within each memory hole MH. Figure 3 As a result, multiple columnar portions CL are formed within multiple storage holes MH. Figure 3 One of these columnar portions CL is shown. In this embodiment, each columnar portion CL extends in the Z direction and penetrates the laminated film 12. In each columnar portion CL, a charge storage layer 4 is formed on the side of the plurality of sacrificial layers 13 and the plurality of insulating films 14, separated by an insulating film 5a, and a channel semiconductor layer 2 is formed on the side of the charge storage layer 4, separated by a tunnel insulating film 3.

[0034] Next, multiple slits (not shown) are formed within the laminated film 12, and the sacrificial layer 13 is removed through these slits using a liquid chemical reagent such as an aqueous phosphoric acid solution. As a result, multiple voids RC ( ) are formed within the laminated film 12. Figure 4 ).

[0035] Next, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are sequentially formed on the surfaces of the insulating films 5a and 14 within each cavity RC. Figure 5 As a result, a barrier insulating film 5 including insulating films 5a and 5b is formed. Furthermore, an electrode layer 6 comprising a barrier metal layer 6a and an electrode material layer 6b is formed within each void RC. Additionally, a laminated film 12 alternately comprising multiple electrode layers 6 and multiple insulating films 14 is formed on the substrate 11. Thus, a replacement process is performed to replace the sacrificial layer 13 with an electrode layer 6.

[0036] Each void RC is formed between two adjacent insulating films 14 in the Z direction. Within each void RC, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are sequentially formed on the upper surface of the lower insulating film 14, the lower surface of the upper insulating film 14, and the side surface of the insulating film 5a. The lower insulating film 14 is an example of a lower insulating film, and the upper insulating film 14 is an example of an upper insulating film. Furthermore, Figure 5 The electrode layers 6 shown are examples of the first electrode layer.

[0037] The semiconductor device of this embodiment is manufactured in this way. Figure 5 ). Figure 1 Show Figure 5 A portion of the semiconductor device shown.

[0038] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device of the comparative example of the first embodiment and the structure of the semiconductor device of the first embodiment.

[0039] Figure 6 (a) shows the charge storage layer 4, the barrier insulating film 5, and the electrode layer 6 within the semiconductor device of the comparative example. The electrode layer 6 of the comparative example includes a barrier metal layer 6a' replacing the barrier metal layer 6a of the first embodiment, and similarly includes an electrode material layer 6b as in the first embodiment. The barrier metal layer 6a' of the comparative example is, for example, a MoN film. The electrode material layer 6b of the comparative example is, for example, a Mo layer.

[0040] When the barrier metal layer 6a' is a MoN film, such as Figure 6 As shown in (a), the N atoms contained in the barrier metal layer 6a' can easily diffuse into the electrode material layer 6b. As a result, the resistance of the electrode material layer 6b increases, which becomes a problem.

[0041] Furthermore, when the barrier metal layer 6a' is a MoN film, such as Figure 6 As shown in (a), O and H atoms readily diffuse through the barrier metal layer 6a to the barrier insulating film 5 and the charge accumulation layer 4. The same applies to Cl atoms, etc. Consequently, these atoms reduce the data retention capability of the three-dimensional semiconductor memory, which becomes a problem. For example, OH groups are generated within the barrier insulating film 5, and electrons (e... - The problem arises from the ability of the OH group to escape from charge accumulation layer 4.

[0042] Figure 6 (b) shows the charge storage layer 4, the barrier insulating film 5, and the electrode layer 6 within the semiconductor device of the first embodiment. As described above, the electrode layer 6 of this embodiment includes a barrier metal layer 6a and an electrode material layer 6b. The barrier metal layer 6a of this embodiment is, for example, a MoSiN film. The electrode material layer 6b of this embodiment is, for example, a Mo layer.

[0043] In this embodiment, the barrier metal layer 6a contains Si atoms in addition to N atoms. Therefore, as... Figure 6 As shown in (b), it is possible to suppress the diffusion of N atoms contained in the barrier metal layer 6a into the electrode material layer 6b, and to suppress the increase in resistance of the electrode material layer 6b caused by N atoms.

[0044] Furthermore, according to this embodiment, such as Figure 6 As shown in (b), H atoms and the like can be trapped by the barrier metal layer 6a containing Si atoms. This suppresses the diffusion of H atoms and the like through the barrier metal layer 6a to the barrier insulating film 5 and the charge accumulation layer 4, thus suppressing the decrease in data retention capability of the three-dimensional semiconductor memory caused by H atoms and the like. For example, it suppresses the generation of OH groups within the barrier insulating film 5, and suppresses the generation of electrons (e... - It escapes from charge accumulation layer 4 with the help of OH groups.

[0045] As described above, each electrode layer 6 in this embodiment includes a barrier metal layer 6a containing molybdenum, silicon, and nitrogen, and an electrode material layer 6b containing molybdenum. Therefore, according to this embodiment, a suitable electrode layer 6 can be formed that can suppress performance degradation of the semiconductor device caused by the barrier metal layer 6a.

[0046] Furthermore, when the semiconductor device of this embodiment is manufactured by bonding two or more substrates including substrate 11, the semiconductor device of this embodiment may not include substrate 11. An example of such a semiconductor device will be described in the second embodiment.

[0047] (Second Implementation)

[0048] Figure 7 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device in this embodiment is, for example, a three-dimensional semiconductor memory.

[0049] The semiconductor device of this embodiment includes an array chip 21 and a circuit chip 22 that are bonded together. As described below, the semiconductor device of this embodiment is manufactured by bonding an array wafer including the array chip 21 and a circuit wafer including the circuit chip 22.

[0050] The array chip 21 includes a memory cell array 31 comprising multiple memory cells, an insulating film 32 on the memory cell array 31, and an interlayer insulating film 33 beneath the memory cell array 31. The insulating film 32 is, for example, a SiO2 film. The interlayer insulating film 33 is, for example, a laminated film comprising a SiO2 film and other insulating films. A portion of the memory cell array 31 in this embodiment corresponds to the laminated film 12 in the first embodiment.

[0051] The circuit chip 22 is disposed below the array chip 21. The reference numeral S indicates the bonding surface between the array chip 21 and the circuit chip 22. The circuit chip 22 includes an interlayer insulating film 34 below the interlayer insulating film 33 and a substrate 35 below the interlayer insulating film 34. The interlayer insulating film 34 is, for example, a laminated film including a SiO2 film and other insulating films. The substrate 35 is, for example, a semiconductor substrate such as a Si substrate.

[0052] Figure 7 The X and Y directions, which are parallel to and perpendicular to each other, and the Z direction, which is perpendicular to the surface of the substrate 35, are shown. The X, Y, and Z directions intersect each other. In this embodiment, similar to the first embodiment, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not be aligned with the direction of gravity.

[0053] The array chip 21 has multiple word lines WL as multiple electrode layers within the memory cell array 31. Figure 7 The diagram shows a stepped structure 41 within the memory cell array 31 and multiple beams 42 disposed within the stepped structure 41. Each word line WL extends in the X direction and is electrically connected to the word wiring layer 44 via a contact plug 43. Each columnar portion CL passing through the multiple word lines WL is electrically connected to the bit line BL via a via plug 45 and is also electrically connected to the source line SL. The bit line BL extends in the Y direction and is disposed below the multiple word lines WL. The source line SL extends in the X direction and is disposed above the multiple word lines WL.

[0054] The circuit chip 22 includes a plurality of transistors 51. Each transistor 51 includes a gate insulating film 51a and a gate electrode 51b sequentially disposed on a substrate 35, and a source diffusion layer (not shown) and a drain diffusion layer disposed within the substrate 35. Furthermore, the circuit chip 22 includes a plurality of contact plugs 52 disposed on the gate electrode 51b, source diffusion layer, or drain diffusion layer of the plurality of transistors 51. Additionally, the circuit chip 22 includes a wiring layer 53, a wiring layer 54, and a wiring layer 55. The wiring layer 53 includes a plurality of wirings disposed on the plurality of contact plugs 52. The wiring layer 54 includes a plurality of wirings disposed on the wiring layer 53. The wiring layer 55 includes a plurality of wirings disposed on the wiring layer 54.

[0055] The circuit chip 22 also includes a plurality of via plugs 56 disposed on the wiring layer 55 and a plurality of metal pads 57 disposed on the plurality of via plugs 56. The metal pads 57 are, for example, metal layers including a Cu (copper) layer. The circuit chip 22 functions as a logic circuit that controls the operation of the array chip 21. This logic circuit is composed of transistors 51, etc., and is electrically connected to the metal pads 57.

[0056] The array chip 21 includes multiple metal pads 61 disposed on the aforementioned multiple metal pads 57, and multiple via plugs 62 disposed on the multiple metal pads 61. The metal pads 61 are, for example, metal layers including a Cu layer. Additionally, the array chip 21 includes a wiring layer 63 and a wiring layer 64. The wiring layer 63 includes multiple wirings disposed on the aforementioned multiple via plugs 62. The wiring layer 64 includes multiple wirings disposed on the wiring layer 63. The aforementioned bit lines BL are contained within the wiring layer 64. Furthermore, the aforementioned logic circuits are electrically connected to the memory cell array 31 via the metal pads 61, 57, etc., and control the operation of the memory cell array 31 via the metal pads 61, 57, etc.

[0057] The array chip 21 also includes a plurality of via plugs 65 disposed on the wiring layer 64, and metal pads 66 disposed on the plurality of via plugs 65 and on the insulating film 32. Additionally, the array chip 21 includes a passivation insulating film 67 disposed on the metal pads 66 and on the insulating film 32. The metal pads 66 are, for example, metal layers including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of this embodiment. The passivation insulating film 67 is, for example, a laminated film including a SiO2 film and a SiN film, and has an opening P exposing the upper surface of the metal pads 66. The metal pads 66 can be electrically connected to the mounting substrate and other devices via the opening P and through bonding wires, solder balls, metal bumps, etc.

[0058] Figure 8 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0059] Figure 8 Show Figure 7 The memory cell array 31 shown is a multilayer film 71 comprising a plurality of electrode layers 71a and a plurality of insulating films 71b alternately stacked in the Z direction. The plurality of electrode layers 71a function, for example, as the word lines WL described above. Each electrode layer 71a is, for example, a metal layer comprising a MoSiN film (barrier metal layer) and a Mo layer (electrode material layer). Each insulating film 71b is, for example, a SiO2 film. The multilayer film 71, electrode layers 71a, and insulating film 71b of this embodiment correspond to the multilayer film 12, electrode layer 6, and insulating film 14 of the first embodiment, respectively.

[0060] Figure 8 It also shows Figure 7One of the plurality of columnar portions CL shown. Each columnar portion CL includes a memory insulating film 72, a channel semiconductor layer 73, and a core insulating film 74 sequentially disposed on the side of the laminated film 71. The memory insulating film 72 includes a barrier insulating film 72a, a charge storage layer 72b, and a tunnel insulating film 72c sequentially disposed on the side of the laminated film 71. The barrier insulating film 72a is, for example, a SiO2 film. The charge storage layer 72b is, for example, an insulating film such as a SiN film. The charge storage layer 72b may also be a semiconductor layer such as a polysilicon layer. The charge storage layer 72b is capable of storing the signal charge of the three-dimensional semiconductor memory. The tunnel insulating film 72c is, for example, a SiO2 film. The channel semiconductor layer 73 is, for example, a polysilicon layer. The channel semiconductor layer 73 functions as the channel of the three-dimensional semiconductor memory. The core insulating film 74 is, for example, a SiO2 film. The columnar portion CL of this embodiment corresponds to the columnar portion CL of the first embodiment.

[0061] Furthermore, the semiconductor device of this embodiment may also include an insulating film corresponding to the insulating film 5b of the first embodiment.

[0062] Figure 9 and Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0063] Figure 9 An array wafer W1 comprising multiple array chips 21 and a circuit wafer W2 comprising multiple circuit chips 22 are shown. Figure 9 The orientation of the array chip W1 in the array is the same as that of the array chip W1 in ... Figure 7 The array chips 21 are oriented in opposite directions. In this embodiment, a semiconductor device is manufactured by bonding the array chip W1 to the circuit chip W2. Figure 9 This shows the array chip W1 facing upwards before being flipped for bonding. Figure 7 The image shows the array chip 21 after it has been flipped and diced for bonding.

[0064] exist Figure 9 In the diagram, S1 denotes the upper surface of the array wafer W1, and S2 denotes the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 36 disposed under the insulating film 32. The substrate 36 is, for example, a semiconductor substrate such as a Si substrate. The substrate 36 of this embodiment corresponds to the substrate 11 of the first embodiment.

[0065] In this embodiment, firstly, as Figure 9 As shown, a memory cell array 31, an insulating film 32, an interlayer insulating film 33, metal pads 61, and via plugs 65 are formed on the substrate 36 of the array chip W1, while an interlayer insulating film 34, transistors 51, and metal pads 57 are formed on the substrate 35 of the circuit chip W2. Next, as... Figure 10 As shown, array wafer W1 and circuit wafer W2 are bonded together using mechanical pressure with surfaces S1 and S2 facing each other. This bonds interlayer insulating film 33 and interlayer insulating film 34. Next, array wafer W1 and circuit wafer W2 are annealed. This bonds metal pad 61 and metal pad 57. In this way, substrate 36 and substrate 35 are bonded together via interlayer insulating films 33 and 34.

[0066] Next, substrate 36 is removed by CMP (Chemical Mechanical Polishing), and substrate 35 is thinned by CMP. Then, the array wafer W1 and circuit wafer W2 are diced into multiple chips. This is how it is manufactured. Figure 7 The semiconductor device shown. In addition, after removing the substrate 36 and thinning the substrate 35, metal pads 66 and passivation insulating film 67 are formed on the insulating film 32.

[0067] In addition, although Figure 7 The boundary surfaces of interlayer insulating films 33 and 34, and metal pads 61 and 57 are shown, but these boundary surfaces typically become obscured after the annealing process described above. However, the locations of these boundary surfaces can be estimated, for example, by detecting the tilt of the sides of metal pads 61 and / or 57, and the positional offset between the sides of metal pads 61 and 57.

[0068] According to this embodiment, the semiconductor device and its manufacturing method of the first embodiment can be applied to this embodiment.

[0069] While certain embodiments have been described, these embodiments are given by way of example only and are not intended to limit the scope of the invention. In fact, the new apparatuses and methods described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the apparatuses and methods described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the invention.

Claims

1. A semiconductor device comprising: A laminated film comprising a plurality of electrode layers and a plurality of first insulating films alternately disposed in a first direction; and The columnar portion extends along the first direction within the laminated film and includes a charge storage layer disposed on the side of the laminated film through a second insulating film, and a semiconductor layer disposed on the side of the charge storage layer through a third insulating film. The first electrode layer among the plurality of electrode layers includes: The first layer contains molybdenum, nitrogen, and Group 14 elements; and The second layer contains molybdenum.

2. The semiconductor device according to claim 1, The first layer also contains oxygen.

3. The semiconductor device according to claim 1, The first layer also contains hydrogen.

4. The semiconductor device according to claim 1, The first layer contains carbon or silicon as a Group 14 element.

5. The semiconductor device according to claim 1, The first layer is a MoSiN film, wherein, Mo represents molybdenum, Si represents silicon, and N represents nitrogen.

6. The semiconductor device according to claim 5, The first layer is a MoSiN film containing oxygen as an impurity element.

7. The semiconductor device according to claim 5, The first layer is a MoSiN film containing hydrogen as an impurity element.

8. The semiconductor device according to claim 1, The atomic concentration of nitrogen in the first layer is more than 20% of the atomic concentrations of molybdenum, nitrogen, and group 14 elements in the first layer.

9. The semiconductor device according to claim 1, The atomic concentration of Group 14 elements in the first layer is more than 5% of the atomic concentration of molybdenum, nitrogen, and other Group 14 elements in the first layer.

10. The semiconductor device according to claim 1, The hydrogen atom concentration in the first layer is 1.0 × 10⁻⁶. 20 atoms / cm 3 above.

11. The semiconductor device according to claim 1, The first layer contains molybdenum as its main component element.

12. The semiconductor device according to claim 1, The thickness of the first layer is less than 3 nm.

13. The semiconductor device according to claim 1, The first layer is an amorphous layer.

14. The semiconductor device according to claim 1, The second layer contains molybdenum as its main component element.

15. The semiconductor device according to claim 1, The second layer is a molybdenum layer, or Mo layer.

16. The semiconductor device according to claim 1, The atomic concentration of hydrogen in the second layer is higher than that in the second insulating film.

17. The semiconductor device according to claim 1, The first layer is a barrier metal layer, and the second layer is an electrode material layer.

18. The semiconductor device according to claim 1, The first electrode layer is disposed between the lower insulating film and the upper insulating film in the plurality of first insulating films. The first layer is disposed on the upper surface of the lower insulating film, the lower surface of the upper insulating film, and the side surface of the second insulating film. The second layer is disposed on the upper surface, lower surface and side surface of the first layer.

19. The semiconductor device according to claim 18, The first layer is disposed on the upper surface of the lower insulating film, the lower surface of the upper insulating film, and the side surface of the second insulating film, separated by the fourth insulating film.

20. A method for manufacturing a semiconductor device, comprising: A laminated film is formed, the laminated film comprising a plurality of third layers and a plurality of first insulating films alternately disposed in a first direction; A first recess is formed within the laminated film, extending along the first direction; A charge storage layer is formed on the side of the laminated film in the first recess, separated by a second insulating film, and a semiconductor layer is formed on the side of the charge storage layer in the first recess, separated by a third insulating film, thereby forming a columnar portion extending in the first direction within the laminated film. as well as The plurality of third layers are replaced with a plurality of electrode layers. The first electrode layer among the plurality of electrode layers is formed to include: The first layer contains molybdenum, nitrogen, and Group 14 elements; and The second layer contains molybdenum.

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